Encryption acceleration for network communication packets

Abstract

The invention relates to encryption acceleration for network communication packets. An apparatus includes an interface to a memory; and a processor to execute the one or more instructions. The instructions cause the processor to receive a plurality of packets via an application programming interface (API), a respective packet of the plurality of packets including a respective header and a respective payload. Further, the instructions cause the processor to determine to encrypt the plurality of packets in parallel through the QUIC protocol stack. Further, the instructions cause the processor to encrypt payloads of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt headers of the plurality of packets in parallel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to previously filed International Application No. PCT / CN2023 / 107286, filed on July 13, 2023, entitled “ENCRYPTION ACCELERATION FOR NETWORK COMMUNICATION PACKETS,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to cryptographic acceleration for network communication packets. Background Art

[0004] Modern computing devices may include general-purpose processor cores as well as various hardware accelerators for performing specialized tasks. Certain computing devices may include one or more accelerators implemented as field programmable gate arrays (FPGAs), which may include programmable digital logic resources that may be configured by an end user or system integrator. Summary of the invention

[0005] According to one aspect of the present disclosure, a device is provided, comprising: an interface to a memory; and a processor for executing one or more instructions so that the processor performs the following operations: receiving an indication about a plurality of packets via an application programming interface (API), corresponding packets in the plurality of packets comprising corresponding headers and corresponding payloads; determining, through a QUIC protocol stack, to encrypt the plurality of packets in parallel; encrypting the payloads of the plurality of packets in parallel; and encrypting the headers of the plurality of packets in parallel.

[0006] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, comprising one or more instructions, which when executed by one or more processors cause the one or more processors to perform the following operations: receiving an indication about a plurality of packets via an application programming interface (API), corresponding packets in the plurality of packets comprising corresponding headers and corresponding payloads; determining, through a QUIC protocol stack, to encrypt the plurality of packets in parallel; encrypting the payloads of the plurality of packets in parallel; and encrypting the headers of the plurality of packets in parallel.

[0007] According to one aspect of the present disclosure, a computer-implemented method is provided, comprising: receiving, by a processor, an indication of a plurality of packets to be sent, a corresponding packet of the plurality of packets comprising a header and a payload; and causing, by the processor, encryption of the plurality of packets, the encryption comprising: encrypting the payloads of the plurality of packets in parallel; and encrypting the headers of the plurality of packets in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To easily identify the discussion of any particular element or act, the most significant digit(s) in the reference number refers to the figure number in which the element is first introduced.

[0009] Figure 1 Aspects of the subject matter according to one embodiment are illustrated.

[0010] Figure 2 Aspects of the subject matter according to one embodiment are illustrated.

[0011] Figure 3 Aspects of the subject matter according to one embodiment are illustrated.

[0012] Figure 4 Aspects of the subject matter according to one embodiment are illustrated.

[0013] Figure 5 Aspects of the subject matter according to one embodiment are illustrated.

[0014] Figure 6 Aspects of the subject matter according to one embodiment are illustrated.

[0015] Figure 7 Aspects of the subject matter according to one embodiment are illustrated.

[0016] Figure 8 Aspects of the subject matter according to one embodiment are illustrated. DETAILED DESCRIPTION

[0017] The disclosed embodiments address technical challenges regarding communication networks ("networks"). Communication protocols such as the Transmission Control Protocol (TCP) define requirements for end-to-end connections across networks. QUIC is a recently developed transport layer networking protocol as an alternative to TCP. QUIC supports a set of multiplexed connections over the User Datagram Protocol (UDP). QUIC connections can provide performance improvements over TCP for connection-oriented applications (e.g., network applications). Improvements can include a reduction in the number of exchanges when establishing a new connection, such as for handshakes, encryption setup, and initial data requests, thereby reducing latency. The QUIC protocol can facilitate several other improvements to the network, such as stream multiplexing.

[0018] Embodiments described herein offload one or more processes to hardware when communicating using the QUIC transport layer protocol. In some examples, receive side scaling (RSS), large send offload (LSO), receive segment coalescing (RSC), and cryptographic (encryption / decryption) offloads are performed in hardware for QUIC communications. As a result of offloading tasks (including offloading to different processors), software control complexity and processing burden (such as for a separate processor) are reduced. In some embodiments, bulk encryption / decryption can be performed using AVX512 and VAES, VPCLMULQDQ instruction extensions.

[0019] Although the concept of the present disclosure allows for various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the concept of the present disclosure is not intended to be limited to the specific form disclosed, but on the contrary, it is intended to cover all modifications, equivalents and alternatives consistent with the present disclosure and the appended claims.

[0020] References in the specification to "one embodiment," "an embodiment," "an illustrative embodiment," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not necessarily include the particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described). In addition, it should be understood that an item included in a list in the form of "at least one of A, B, and C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, an item listed in the form of "at least one of A, B, or C" may mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0021] Reference is now made to the accompanying drawings, in which the same reference numerals are used to refer to the same elements throughout. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding thereof. However, novel embodiments may be practiced without these specific details. In other cases, known structures and devices are shown in block diagram form for ease of description thereof. The present invention is intended to cover all modifications, equivalents, and substitutions consistent with the claimed subject matter.

[0022] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transient or non-transient machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be specifically implemented as any storage device, mechanism, or other physical structure (e.g., volatile or non-volatile memory, media disk, or other media device) for storing or transmitting information in a machine-readable form.

[0023] In the drawings and accompanying description, the designations "a", "b", and "c" (and similar designators) are intended to be variables representing any positive integer. Thus, for example, if an embodiment sets a value a=5, a complete set of components 121, illustrated as components 121-1 through 121-a, may include components 121-1, 121-2, 121-3, 121-4, and 121-5. The embodiments are not limited in this context.

[0024] The operation of the disclosed embodiments may be further described with reference to the following figures. Some figures may include logic flows. Although the figures presented herein may include specific logic flows, it is understood that the logic flows only provide examples of how the general functions described herein may be implemented. Further, unless otherwise indicated, a given logic flow does not necessarily have to be performed in the order presented. Moreover, in some embodiments, not all actions illustrated in the logic flow may be required. In addition, a given logic flow may be implemented by hardware elements, software elements executed by a processor, or any combination thereof. The embodiments are not limited to this context.

[0025] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Instead, in some embodiments, such features may be arranged in a different manner and / or order than shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not mean that such a feature is required in all embodiments, and in some embodiments, such a feature may not be included or may be combined with other features.

[0026] Figure 1An example communication device 200 is depicted in accordance with one or more embodiments. The communication device 200 includes a link layer 102 that facilitates the communication device 200 to send and receive data over a network 118 using the Open Systems Interconnection (OSI) model. The OSI model is a conceptual model that describes how different network protocols can communicate with each other. The model divides the communication process into several layers, each with its own functions and responsibilities. For example, these layers include: a) a physical layer that handles the sending and receiving of raw data bits over a physical medium; b) a data link layer that provides reliable data transfer between two devices on the same network; c) a network layer that handles the routing and forwarding of packets across different networks; d) a transport layer that ensures end-to-end data integrity and reliability; e) a session layer that establishes, maintains, and terminates sessions between applications; f) a presentation layer that transforms data into a format that the application layer can understand; and g) an application layer that provides services to users, such as email, web browsing, file transfer, etc.

[0027] Although not all OSI layers are depicted, Figure 1 , the communication device 200 illustrates a link layer 102 (the lowest layer), a network layer 104 (sometimes also referred to as an Internet Protocol (IP) layer) above the link layer 102, a transport layer 106 above the network layer 104, and an application layer 108 above the transport layer 106. The application layer 108 is sometimes referred to as a hypertext transfer protocol (HTTP) layer.

[0028] The transport layer 106 can facilitate the use of the Transmission Control Protocol / Internet Protocol (TCP 110), which is a set of communication protocols for interconnecting communication devices 200 on a network 118 such as the Internet. TCP 110 is also used as a communication protocol in a dedicated computer network (intranet or extranet). The TCP 110 protocol suite is used as an abstraction layer between Internet applications and routing and switching structures. TCP 110 specifies how data is exchanged through the Internet by providing end-to-end communication, which identifies how data should be divided into packets, addressed, sent, routed, and received at the destination. The two main protocols in the suite provide specific functions. TCP 110 defines how applications on the communication device 200 can create a communication channel across the network 118. It also manages how to assemble messages into smaller packets before the smaller packets are transmitted through the Internet and reassembled in the correct order at the destination address. TCP 110 uses the Internet Protocol (IP) to define how to address and route each packet to ensure that the packet reaches the correct destination. Each gateway computer on the network checks the IP address to determine where to forward the packet. For example, the subnet mask indicates to the communication device 200 or other network device what portion of the IP address is used to represent the network 118 and what portion is used to represent the host or other communication device 200 on the network 118. Common protocols handled by TCP 110 may include: Hypertext Transfer Protocol (HTTP), which handles communications between web servers and web browsers; HTTP Security, which handles secure communications between web servers and web browsers; and File Transfer Protocol, which handles file transfers between communication devices 200. Embodiments herein are not limited to the above-mentioned protocols.

[0029] In some embodiments, the transport layer 106 includes a transport layer security (TLS 112) protocol that adds a security layer on top of the TCP / IP transport protocol. TLS 112 uses both symmetric encryption and public key encryption to securely send private data, and adds additional security features such as authentication and message tampering detection. When sending data using TCP / IP, TLS adds more processing, so it increases latency in network communications.

[0030] In some embodiments, the transport layer 106 uses the QUIC 116 layer instead of the TCP 110 protocol suite. QUIC 116 provides a protocol based on the User Datagram Protocol (UDP), which is used as the "transport" and "session" layers of the network OSI model. QUIC 116 replaces the TCP 110 and TLS 112 portions of the network stack (in the transport layer 106). The reliable components of TCP (such as loss recovery, congestion control, connection establishment, etc.) are included in QUIC 116 together with the security provided by TLS 112. Connection establishment is significantly improved in QUIC 116, where TLS handshake establishment and TCP handshake establishment are completed by QUIC 116 itself in the transport layer 106, thereby saving the delay increased by multiple round trips. Therefore, QUIC 116 provides an improvement to TCP 110-based communications.

[0031] In one embodiment, the network layer is provided according to the UDP 114 suite utilizing the QUIC 116 transport layer protocol. The application layer 108 provides process-to-process communication between processes running on different hosts (e.g., general purpose computing devices, servers, etc.) connected to the network 118, the host being, for example, the communication device 200. The transport layer 106 provides end-to-end communication between different hosts, including providing (one or more) end-to-end connections between hosts for use by processes. The network layer 104 provides routing (e.g., communication between different individual portions of the network 118) via routers. The link layer 102 provides communication between physical network addresses (such as media access control (MAC) addresses of adjacent nodes in the network 118), such as via network switches and / or hubs operating at the link layer 102 for the same single network.

[0032] In one example, the communication device 200 uses QUIC 116 to establish a channel (application layer channel) at the application layer 108 of the network 118. The channel is established between instances of applications or processes running on different communication devices 200. For example, the channel is a process-to-process channel between client instances on two (or more) communication devices 200.

[0033] In some examples, the (application layer) channel is established via one or more transport layer channels (often referred to as (one or more) end-to-end or host-to-host channels) between the communication devices 200. Each transport layer channel is established via (one or more) network layer channels between one communication device 200 and a router or (one or more) network layer channels between pairs of routers established via link layer channels within various networks such as the Internet. The channel can be a unidirectional channel or a bidirectional channel.

[0034] Figure 2An embodiment of a communication device 200 is illustrated. The communication device 200 is a computer system having one or more processor cores, such as a distributed computing system, a supercomputer, a high performance computing system, a computing cluster, a mainframe computer, a minicomputer, a client-server system, a personal computer (PC), a workstation, a server, a portable computer, a laptop computer, a tablet computer, a handheld device such as a personal digital assistant (PDA), an infrastructure processing unit (IPU), a data processing unit (DPU), or other devices for processing, displaying, or transmitting information. Similar embodiments may include, for example, entertainment devices (such as portable music players or portable video players), smart phones or other cellular phones, telephones, digital cameras, digital still cameras, external storage devices, etc. Additional embodiments implement larger-scale server configurations. Examples of IPUs include IPU and Pensando IPU. Examples of DPUs include Intel DPU, Fungible DPU, OCTEON and ARMADA DPU, NVIDIA DPU and Pensando DPU. In other embodiments, the communication device 200 may have a single processor with one core or more than one processor. It should be noted that the term "processor" refers to a processor with a single core or a processor package with multiple processor cores. In at least one embodiment, the communication device 200 represents a component of a system for encrypting network packets for the QUIC protocol. More generally, the computing communication device 200 is configured to implement all logic, systems, logic flows, methods, devices, and functions described herein with reference to the accompanying drawings.

[0035] As used in this application, the terms "system", "component" and "module" are intended to refer to computer-related entities, either hardware, a combination of hardware and software, software, or software in execution, examples of which are provided by the exemplary communication device 200. For example, a component can be, but is not limited to, a process running on a processor, a processor, a hard drive, multiple storage drives (optical and / or magnetic storage media), an object, an executable file, a thread of execution, a program and / or a computer. By way of illustration, both an application running on a server and a server can be a component. One or more components can reside in a process and / or a thread of execution, and a component can be located on one computer and / or distributed between two or more computers. Further, components can be communicatively coupled to each other through various types of communication media to coordinate operations. Coordination can involve unidirectional or bidirectional information exchange. For example, a component can transmit information in the form of a signal transmitted on a communication medium. The information can be implemented as a signal assigned to various signal lines. In such an assignment, each message is a signal. However, other embodiments can alternatively adopt data messages. Such data messages can be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

[0036] like Figure 2 As shown, the communication device 200 includes a system on chip (SoC) 202 for mounting platform components. The system on chip (SoC) 202 is a point-to-point (P2P) interconnect platform, which includes a first processor 204 and a second processor 206 coupled via a point-to-point interconnect 270 such as a super channel interconnect (UPI). In other embodiments, the communication device 200 can be another bus architecture, such as a multi-point bus. In addition, each of the processor 204 and the processor 206 can be a processor package with multiple processor cores, and the multiple processor cores include (one or more) cores 208 and (one or more) cores 210 respectively. Although the communication device 200 is an example of a dual-socket (2S) platform, other embodiments may include more than two sockets or one socket. For example, some embodiments may include a four-socket (4S) platform or an eight-socket (8S) platform. Each socket is a mounting member for a processor and may have a socket identifier. It should be noted that the term platform may refer to a motherboard on which certain components such as a processor 204 and a chipset 232 are mounted. Some platforms may include additional components, while some platforms may only include a socket to mount a processor and / or chipset. In addition, some platforms may not have a socket (e.g., SoC, etc.). Although depicted as SoC 202, one or more of the components of SoC 202 may also be included in a single die package, a multi-chip module (MCM), a multi-die package, a chipset, a bridge, and / or an interposer. Therefore, embodiments are not limited to SoCs.

[0037] Processor 204 and processor 206 may be any of a variety of commercially available processors, including but not limited to Core(2) and processor; and processor; Application, embedded and security processors; and and Processors; IBM and Cell processor; and similar processors. Dual microprocessors, multi-core processors, and other multi-processor architectures may also be used as processor 204 and / or processor 206. In addition, processor 204 need not be the same as processor 206.

[0038] Processor 204 includes an integrated memory controller (IMC) 220 and a point-to-point (P2P) interface 224 and a P2P interface 228. Similarly, processor 206 includes an IMC 222 and a P2P interface 226 and a P2P interface 230. IMC 220 and IMC 222 couple processor 204 and processor 206 to corresponding memories (e.g., memory 216 and memory 218), respectively. Memory 216 and memory 218 may be part of a main memory (e.g., dynamic random access memory (DRAM)) for a platform (such as double data rate type 4 (DDR4) or type 5 (DDR5) synchronous DRAM (SDRAM)). In the present embodiment, memory 216 and memory 218 are locally attached to the corresponding processor (e.g., processor 204 and processor 206). In other embodiments, the main memory may be coupled to the processor via a bus and a shared memory hub. Processor 204 includes register 212, and processor 206 includes register 214.

[0039] Communication device 200 includes a chipset 232 coupled to processor 204 and processor 206. In addition, chipset 232 can be coupled to storage device 250, for example, via interface (I / F) 238. I / F 238 can be, for example, a peripheral component interconnect enhanced (PCIe) interface, a Compute Express The storage device 250 may store instructions that may be executed by circuits (e.g., the processor 204, the processor 206, the GPU 248, the accelerator 254, the visual processing unit 256, etc.) of the communication device 200. For example, the storage device 250 may store instructions for encrypting network packets in batch mode, etc.

[0040] Processor 204 is coupled to chipset 232 via P2P interface 228 and P2P 234, and processor 206 is coupled to chipset 232 via P2P interface 230 and P2P 236. Direct media interface (DMI) 276 and DMI 278 may couple P2P interface 228 and P2P 234 and P2P interface 230 and P2P 236, respectively. DMI 276 and DMI 278 may be high-speed interconnects that facilitate, for example, eight gigabit transfers per second (GT / s), such as DMI 3.0. In other embodiments, processor 204 and processor 206 may be interconnected via a bus.

[0041] Chipset 232 may include a controller hub, such as a platform controller hub (PCH). Chipset 232 may include a system clock that performs clock functions, and include interfaces for I / O buses (such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), CXL Interconnect, UCIe Interconnect, Interface Serial Peripheral Interconnect (SPI), Integrated Circuit (I2C), etc.) to facilitate the connection of peripheral devices on the platform. In other embodiments, chipset 232 may include more than one controller hub, such as a chipset with a memory controller hub, a graphics controller hub, and an input / output (I / O) controller hub.

[0042] In the depicted example, chipset 232 is coupled via I / F 242 to a trusted platform module (TPM) 244 and UEFI, BIOS, and FLASH circuitry 246. TPM 244 is a specialized microcontroller designed to protect hardware by integrating cryptographic keys into the device. UEFI, BIOS, and FLASH circuitry 246 may provide pre-boot code.

[0043] In addition, the chipset 232 includes an I / F 238 that couples the chipset 232 with a high-performance graphics engine, such as a graphics processing circuit or graphics processing unit (GPU) 248. In other embodiments, the communication device 200 may include a flexible display interface (FDI) (not shown) between the processor 204 and / or the processor 206 and the chipset 232. The FDI interconnects a graphics processor core in one or more of the processors 204 and / or the processors 206 with the chipset 232.

[0044] The communication device 200 is operable to communicate with wired and wireless devices or entities via a network interface controller (NIC) 280 using the IEEE 802 family of standards, such as wireless devices operatively arranged for wireless communication (e.g., IEEE 802.11 over-the-air modulation techniques). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth. TMWireless technology, 3G, 4G, LTE wireless technology, etc. Thus, the communication can be a predefined structure like a conventional network, or just an ad hoc communication between at least two devices. Wi-Fi networks use radio technology known as IEEE 802.11x (a, b, g, n, ac, ax, etc.) to provide secure, reliable, and fast wireless connections. Wi-Fi networks can be used to connect computers to each other, to the Internet, and to wired networks (which use IEEE 802.3 related media and functions).

[0045] Additionally, accelerator 254 and / or visual processing unit 256 may be coupled to chipset 232 via I / F 238. Accelerator 254 represents any type of accelerator device (e.g., data flow accelerator, cryptographic accelerator, cryptographic coprocessor, offload engine, etc.). An example of accelerator 254 is Data Stream Accelerator (DSA). Another example of accelerator 254 is AMD Accelerator. The accelerator 254 may be a device including circuits for accelerating the following items: copy operations, data encryption, hash value calculations, data comparison operations (including comparisons of data in the memory 216 and / or the memory 218), network communication operations, and / or data compression. For example, the accelerator 254 may be a USB device, a PCI device, a PCIe device, a CXL device, a UCIe device, and / or an SPI device. The accelerator 254 may also include a circuit arranged to perform ML-related operations (e.g., training, reasoning, etc.) for a machine learning (ML) model. Typically, the accelerator 254 may be specifically designed to perform computationally intensive operations such as hash value calculations, comparison operations, cryptographic operations, and / or compression operations in a more efficient manner than when executed by the processor 204 or the processor 206. Because the load of the communication device 200 may include hash value calculations, comparison operations, cryptographic operations, and / or compression operations, the accelerator 254 may greatly improve the performance of the communication device 200 for these operations.

[0046] The accelerator 254 may be embodied as any type of device, such as a coprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a function block, an IP core, a graphics processing unit (GPU), a processor with a specific instruction set for accelerating one or more operations, or other hardware accelerator of the computing device 200 capable of performing the functions described herein. In some embodiments, the accelerator 254 may be packaged in a discrete package, an add-in card, a chipset, a multi-chip module (e.g., a chiplet, a dielet, etc.), and / or a SoC. The embodiments are not limited to these contexts.

[0047] The accelerator 254 may include one or more dedicated work queues and one or more shared work queues (each not shown). Typically, the shared work queue is configured to store descriptors submitted by multiple software entities. The software can be any type of executable code that shares the accelerator 254, such as a process, thread, application, virtual machine, container, microservice, etc. For example, the accelerator 254 can be shared according to a single root I / O virtualization (SR-IOV) architecture and / or a scalable I / O virtualization (S-IOV) architecture. The embodiments are not limited to these contexts. In some embodiments, the software uses instructions that atomically submit descriptors to the accelerator 254 via non-posted writes (e.g., delayed memory writes (DMWr)). An example of an instruction that atomically submits a work descriptor to the shared work queue of the accelerator 254 is The ENQCMD command or instruction (which may be referred to herein as "ENQCMD") supported by the instruction set architecture (ISA). However, any instruction having a descriptor including an indication of an operation to be performed, a source virtual address for the descriptor, a destination virtual address of a device-specific register for a shared work queue, a virtual address of parameters, a virtual address of a completion record, and an identifier of the address space of the submitting process represents an instruction to atomically submit a work descriptor to the shared work queue of the accelerator 254. A dedicated work queue may accept job submissions via a command such as a movdir64b instruction.

[0048] Various I / O devices 260 and display 252 are coupled to bus 272 along with bus bridge 258 coupling bus 272 to second bus 274 and I / F 240 connecting bus 272 to chipset 232. In one embodiment, second bus 274 may be a low pin count (LPC) bus. Various devices may be coupled to second bus 274 including, for example, keyboard 262, mouse 264, and communication devices 266.

[0049] In addition, an audio I / O 268 may be coupled to the second bus 274. Many of the I / O devices 260 and the communication devices 266 may reside on the system on a chip (SoC) 202, while the keyboard 262 and the mouse 264 may be additional peripheral devices. In other embodiments, some or all of the I / O devices 260 and the communication devices 266 are additional peripheral devices and do not reside on the system on a chip (SoC) 202.

[0050] refer to Figure 2In one example, the communication device 200 includes one or more hardware components configured to perform networking operations offloaded from software, such as RSS, LSO, RSC, and cryptographic offload for QUIC communications. The communication device 200 can be any type of computing device connected to a network. One or more examples improve the efficiency of processing packets transmitted over a network using QUIC. Therefore, in some examples, the communication device 200 is used in applications that require the communication device 200 to send or receive a large number of packets, including packets of larger size (greater than a predetermined size), over a network. For example, the communication device 200 can be a network server.

[0051] In some examples, the communication device 200 is connected to other computers through a physical network link. The physical network link can be any suitable transmission medium, such as copper wire, optical fiber, or in the case of a wireless network, air.

[0052] In the illustrated example, the communication device 200 includes a network interface controller 280 (NIC) that is configured to send and receive packets over the physical network 118. The specific construction of the network interface controller 280 depends on the characteristics of the physical network 118. However, in one example, the network interface controller 280 is implemented using circuitry as used in data transmission technology to send and receive packets over a physical network link.

[0053] In one example, the network interface controller 280 is a modular unit implemented on a printed circuit board coupled to (e.g., plugged into) the communication device 200. However, in some examples, the network interface controller 280 is a logic device implemented in circuitry residing on a module that performs functions in addition to the functions of the network interface controller 280. Thus, the network interface controller 280 may be implemented in hardware, software, or a combination of hardware and software.

[0054] In the illustrated example, the network interface controller 280 additionally includes logic to perform processing on network packets to be sent or received over the physical network 118. In one example, the logic is embodied in electronic circuitry on the network interface controller 280 to perform some or all of the offloaded software operations. In some examples, a different hardware configuration of the network interface controller 280 is provided separately from the network interface controller 280 to perform the offload functionality.

[0055] The network interface controller 280 includes an integrated circuit 282 and / or other hardware that contains circuitry for performing offload processing. Additionally or alternatively, the present disclosure contemplates offloading software functionality to other hardware, such as one or more processors 204, accelerators 254, and the like. For example, in one example, traffic is traversed across the processor 204 and accelerator 254 using a hashing process that utilizes a connection identifier (CID) from the QUIC data and, optionally, a value from an IP address, as described in more detail herein. In some examples, the processor 204 and accelerator 254 form part of the network interface controller 280.

[0056] In some examples, integrated circuit 282 is a programmable logic device (such as one or more field programmable gate arrays), or may be one or more application specific integrated circuits or other suitable integrated circuits configured to perform specific offload functions. It should be understood that the processors may be hardware components, each of which is configured to perform one or more of the offload functions from software. It should be understood that in some examples, in addition to performing processing on network packets for send and / or receive operations, integrated circuit 282 and processors also perform other functions, which may or may not be related to the send and / or receive operations.

[0057] Once the network interface controller 280 receives a packet (and / or an indication about a packet, such as a memory address, location, identifier, etc.) and performs processing on the packet, the packet can be further processed by the communication device 200, for example, using hardware and / or software components. The processing of the network packet depends on the information within the packet or the information applicable to certain packets. For example, the data from the network packet is analyzed to determine one or more fields. Based on the characteristics of the field, it is further determined whether the network packet includes a header, such as Ethernet (ETH), IP, and UDP. Based on the determined characteristics, the payload in the network packet can be further processed. Once the network interface controller 280 or the logic within the processor completes the processing of the received packet, the packet can be transmitted to other components of the communication device, such as an operating system, an application, a driver, etc., for further processing.

[0058] In some embodiments, the network packets are stored in a data buffer (e.g., in memory 216), or in a memory allocated to the network interface controller 280. Each successive layer within the network stack then processes the network packets by reading and / or modifying the buffer. As each layer completes processing, the layer signals the next layer to begin processing. In the illustrated embodiment, the link layer 102 module processes packets to determine compliance with the requirements of the link layer, the network layer 104 module processes packets to determine compliance with the requirements of the network protocol layer, the UDP 114 processing module processes packets to determine compliance with the requirements of UDP, and the QUIC 116 processing module processes packets to determine compliance with the requirements of QUIC. It should be understood that other checks may be performed, such as checking the packet to determine whether the packet has a header indicating that the packet is sent from an IP address that is an allowed source of the packet and / or determining whether the network packet is sent using the QUIC transport protocol. Other similar checks may be performed to determine whether the received packet complies with the requirements of the layered protocol.

[0059] In one example, at each stage in the process, it is determined whether the packet complies with the requirements of a particular protocol in the layered protocol. If the process determines that the packet does not comply with the requirements of the protocol, the packet can be discarded. Alternatively, error detection or error recovery steps can be performed. However, if compliance with all protocol layers is verified, the data from the packet can be passed to an application within the communication device 200 or otherwise utilized.

[0060] Figure 3 An example of a network packet 300 that may be received and stored in accordance with one or more embodiments is illustrated. The network packet 300 includes fields that store information for processing the network packet 300. In this example, the network packet 300 includes an Ethernet header 302, an IP header 304, a UDP header 306, and a body defined by a QUIC payload 308. The QUIC payload 308 is encrypted.

[0061] In addition, as shown in the illustrated example, the network packet 300 includes an authentication data portion illustrated as QUIC plaintext 310 (unencrypted portion) and a QUIC header 312. The QUIC plaintext 310 portion is the portion of the QUIC header 312 that is visible to the network 118, while the QUIC payload 308 is not visible to the network. In various embodiments, the QUIC header 312 is unencrypted. The remainder of the network packet 300 is the encrypted QUIC payload 308. Within the packet QUIC payload 308, there are one or more frames, each having a header and an optional payload. In various examples, the key used for encryption depends on the type of packet header (a static version dedicated to a "plaintext" long header, TLS determined for a short header, and 0-RTT for a long header, etc.).

[0062] In some embodiments, the information within network packet 300 is used to perform hardware offload, which includes having a single call for performing the offload function. In QUIC, encryption is performed at the transport layer and Figure 1 An example protocol stack including several layers is illustrated in . In some embodiments, the QUIC 116 layer also includes a TLS 112 layer. It should be understood that QUIC 116 makes the application layer 108 smaller and includes some functions of TLS 112 within the application layer 108 (e.g., HTTP, HTTP2), TCP 110, and the QUIC 116 layer. Some functions may include stream multiplexing and prioritization. Moreover, because encryption is performed at the transport layer, the QUIC header 312 is encrypted when the network packet is transmitted across the network 118 using UDP. The QUIC transport protocol thus provides an end-to-end security protocol.

[0063] Therefore, in some embodiments, the QUIC protocol runs on top of a UDP socket and, in many examples, uses TLS 1.3 to encrypt data. QUIC also uses specific headers and contains parts of HTTP 1 and HTTP 2. The embodiments described herein facilitate improved implementations of QUIC to provide TCP-like reliability while supporting 0-RTT and stream multiplexing in a tamper-proof and secure manner.

[0064] Unlike some of the other network protocols, the QUIC protocol makes the exchange of setting keys and supported protocols part of the initial handshake process. When a client (e.g., communication device 200) opens a connection, the response packet includes the data required for future packets to use encryption. This eliminates the need to set up a TCP connection and then negotiate security protocols via additional packets. Other protocols can be served in the same way, combining multiple steps into a single request-response. This data can then be used both for subsequent requests in the initial setup and for future requests that would otherwise be negotiated as separate connections.

[0065] During or after the handshake, in order to make QUIC tamper-proof by middleboxes, there are two types of protection operations performed in QUIC, packet protection and header protection from the perspective of QUIC-level encryption. Unlike other protocols such as TCP, in QUIC, network packets 300 are encrypted individually so that they do not cause encrypted data to wait for partial packets. Further, the QUIC protocol aims to perform encryption in a single handshake process.

[0066] Figure 4QUIC network packet 300 encryption logic 400 is depicted in accordance with one or more embodiments. Packet encryption logic 400 includes collecting packet IDs (destination ID (DCID) and / or source ID (SCID)) from QUIC header 312 and passing them to SHA-256 module 402 along with an initial salt value (salt) that is publicly available and specific to each QUIC version. The packet number is used to determine a cryptographic nonce for packet encryption. Each endpoint maintains a separate packet number for sending and receiving.

[0067] The SHA-256 module 402 gives a value called the "initial secret" as an output. The initial secret is passed to the HMAC-based key derivation function (HKDF) module 404 along with the client / server in the QUIC key, QUIC IV, and QUIC HP. The HKDF module 404 uses the initial key to generate different keys used in successive stages. The QUIC key, QUIC IV, and QUIC HP are keys used by the HKDF module 404. HKDF is a component of a cryptographic system whose goal is to obtain a certain source of initial keying material and derive one or more cryptographically strong keys from it. The temporary number is generated from the client_iv and the packet number. AEAD uses an initialization vector (IV) as one of the factors (or keys) for encryption. The IV has a predetermined length, such as 16 bytes. In some embodiments, the IV generated by the HKDF module 404 is XORed with the packet number retrieved from the unprotected QUIC header 312 and used with the key from the HKDF module 404 to protect the QUIC payload 308 portion of the network packet 300.

[0068] The QUIC plaintext 310 is padded to make it a fixed length payload (e.g., 1162 bytes). Finally, the fixed length padded payload is encrypted using an AEAD module 406 (e.g., Advanced Encryption Standard (AES), such as AES-128-GCM). Thus, AEAD-based encryption is used to protect the QUIC payload 308 and generate a protected payload 410.

[0069] Payload protection is followed by header protection, which is the process of protecting a portion of the QUIC header 312 using a key derived from the protected packet and can only be applied after the payload is protected. The specific portion of the QUIC header 312 protected in this process includes the packet number and the initial flag byte. The key used in this process is generated by sampling the protected packet based on the packet number length (pn_length) and the HP key generated by the HKDF module 404 in the previous stage. Both keys are passed to the AES-ECB module 408 to generate a mask that will be used to mask a specific portion of the QUIC header 312.

[0070] In some embodiments, generating the mask includes calculating the packet number length based on the flag byte (e.g., the last two bits of the flag byte represent the packet number length). Further, generating the mask includes calculating a sample from the protected packet payload based on the calculated pn_length. Further, based on the sample, the mask is calculated with the aid of the hp_key previously calculated from the HKDF module 404.

[0071] As part of the QUIC protocol processing, performing packet and header protection (e.g., AES-ECB encryption) may cost considerable latency and computing resources. As described herein, unlike the traditional transport layer based on TCP, the QUIC stack is based on the UDP protocol, which uses datagram payloads in packets (L2), and the L2 packet size is limited by the maximum transmission unit (MTU), so that the unit QUIC sent is usually smaller than one MTU. Typically, the MTU is set to 1500 bytes; however, other values ​​can be configured in one or more embodiments. In computer networking, the MTU is the size of the largest protocol data unit that can be transmitted in a single network layer transaction. The QUIC protocol requires two rounds of encryption for each network packet 300, namely, one total packet-level encryption and one header protection encryption, so when QUIC needs to send a portion of data (e.g., a file, stream, etc.) (e.g., a 1M file) to a peer, the normal working process of QUIC is to divide the file into multiple L2 packets and perform 2 rounds of encryption for each packet, and the cipher size is lower than the MTU. Further, in some examples, due to limitations of the encryption application programming interface (API) in OpenSSL and BoringSSL, the QUIC 116 layer must call the encryption API one by one for multiple network packets 300 belonging to the same session (same key). For example, a separate API call can be used for each buffer to be encrypted. An example of an API call is encryption (buffer, buffer_length, key, iv, password). In this example, the contents of the "buffer" can be encrypted and stored in the "password". It will be understood that other forms of APIs can be used in other embodiments, and the example API calls should not be considered limitations of the present disclosure. This leads to inefficiencies due to (1) encryption context switching, which is most visible for short packet sizes; and (2) lack of parallelization in encryption operations. For example, encryption context switching may be caused by crossing shared library boundaries multiple times or using a common encryption API without QUIC-specific encryption parameters (same IV size for all packets, same additional authentication data (AAD) size, etc.).

[0072] In this scenario, the technical challenge of performing two rounds of encryption for each of the multiple packets is further exacerbated because such encryption results in frequent cryptographic context switching and inefficient cryptographic performance due to the relatively small encryption size (limited by the MTU). The embodiments described herein may address such technical challenges by facilitating the acceleration of QUIC protocol encryption using batch mode encryption operations. Batch mode encryption may perform multiple encryption operations simultaneously and accelerate overall QUIC performance. Additionally, the embodiments herein may be further enhanced by using features such as AVX512 and vector AES instructions, which are provided by features such as from The embodiments described herein can achieve significant improvements in QUIC performance.

[0073] For example, assume that the QUIC protocol is used to send a record (e.g., a file, a stream, or any type of data) to a peer or host (e.g., communication device 200). The QUIC protocol divides the record into multiple smaller pieces and performs encryption one by one using different IVs but the same key. This process is due to the limitation of the MTU size. Instead, embodiments of the present invention use vector-based AES (e.g., using The cipher architecture performs batch mode encryption operations, which allows multiple smaller plaintext pieces and IV pieces to be provided in batches and encrypted in a single run using the same key. This single-run encryption operation is accomplished by utilizing a specific instruction set (such as The VAES instruction set) reduces the overhead of context switching and power conversion (for example, when using Advanced Vector Extensions (AVX)). Therefore, the embodiments of the present invention enable smaller cryptographic operations to work in parallel and improve QUIC performance.

[0074] Therefore, the embodiments of the present invention can facilitate solving the pain point of QUIC deployment that has degraded performance compared to TLS. The embodiments of the present invention can improve the performance of the UDP-based QUIC protocol by utilizing encryption instructions that can offload QUIC protocol operations and / or execute in parallel. In some embodiments, an API is provided to use batch mode encryption functions. The API can facilitate offloading batch mode encryption functions. Further, the API can be used when completing operations in current encryption libraries such as OpenSSL. Further, the API can be used to support segmentation offloading. For example, it may be necessary to group data into multiple packets via segmentation offloading. Segmentation offloading can include generating a packet including a header, which can be encrypted using an API for batch mode encryption functions. In one example, segmentation offloading is TCP segmentation offloading, in which smaller TCP segments are generated from larger portions of data.

[0075] Figure 5 A flow chart of batch mode protection 500 is illustrated according to one or more embodiments. Although the example batch mode protection 500 depicts a particular order of operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of the batch mode protection 500. In other examples, different components of the example device or system implementing the batch mode protection 500 may perform functions substantially simultaneously or in a particular order. Reference Figure 6 A description of one or more operations of batch mode protection 500 is provided.

[0076] According to some examples, the method includes determining a plurality of network packets to be encrypted in a single session at block 502. As described elsewhere herein, a single session may include using the QUIC protocol to transmit a data buffer greater than a predetermined length (e.g., 1 megabyte, 2 megabytes, etc.), which requires dividing the transmission into a plurality of network packets 300 to be sent by a communication device 200 to another communication device 200.

[0077] According to some examples, the method includes performing payload protection on a set of multiple network packets in parallel using a single API call at block 504. The set of network packets 300 may include two or more network packets 300. In some embodiments, N network packets 300 are encrypted in a single batch, where N ≥ 2. N may be a predetermined number that may be configurable in some embodiments. The value of N may be based on the size of the data buffer used to store the network packets 300 (e.g., 64 kilobytes, 128 kilobytes, etc.).

[0078] Figure 6 A comparison between prior art using per-packet payload protection 602 and payload protection logic 600 performed by batch mode protection 500 according to one or more embodiments herein is depicted. Batch mode protection 500 processes multiple QUIC network packets 300 (e.g., N network packets, N ≥ 2) under a single API call or function, which results in a reduction in processor cycles required to cross shared library boundaries. The single API call also incorporates QUIC-specific encryption parameters (IV and AAD size).

[0079] The QUIC payload 308 and / or an indication about the payload (such as a memory address, location, identifier, etc.) from each network packet 300 in the set of N network packets 300 that are encrypted together (as a batch) is passed as input to a single API call. In addition, a QUIC key common to the N network packets 300 is passed to the API call. Further, a count N of IV values ​​corresponding to the N network packets 300 is also passed as input to the API call. In some embodiments, the input parameter can be passed as a pointer (e.g., the address of a memory location where the value of the input parameter is stored).

[0080] The QUIC payloads 308 of the N network packets 300 are encrypted in parallel using the AEAD module 406 shown in the logic 400. In other words, N protected payloads 410 corresponding to the input N network packets 300 are generated in parallel (e.g., in batch mode) by the AEAD module 406. It should be noted that at this stage, the QUIC headers 312 of the N network packets 300 are not encrypted.

[0081] As shown, in contrast, per-packet payload protection 602 requires N separate API calls to encrypt each of the N network packets 300. Each separate API call is input with a corresponding QUIC payload 308 from each of the N network packets 300. In addition, each separate API call is input with a QUIC key and a corresponding IV for encryption to be performed by AEAD module 406.

[0082] Using batch mode protection 500 allows the application of additional optimization techniques that are not possible in traditional per-packet payload protection 602. Batch mode protection 500 facilitates multi-buffer processing, wherein certain elements of AEAD encryption (e.g., AES-GCM) processing can be completed in parallel on multiple network packets 300 at the same time. This includes but is not limited to the last block encryption in AAD (additional authentication data) processing or AES-GMAC calculation (a part of the AES-GCM AEAD algorithm construction). In other words, the AEAD module 406 calculates a single instance of AAD for all N network packets 300 input. Therefore, the AAD calculation cycle is reduced. In addition, the AEAD module 406 can perform only one AES-GCM calculation across all N network packets 300 (rather than performing N times in per-packet payload protection 602 mode). Therefore, compared with per-packet payload protection 602, batch mode protection 500 promotes performance improvements. During batch mode protection 500, multi-buffer processing can be used in several other operations.

[0083] Alternatively or in addition, batch mode protection 500 facilitates "function stitching," where computational elements of an AEAD algorithm performed on a first network packet 300A can be combined or interleaved with different computational elements performed on a second network packet 300B. If the computational functions utilize different processor computational resources, the functions can be interleaved, thereby improving performance. As an example, in Figure 6 In the illustration of , the AAD calculation for network packet 2 can be interleaved with the final block encryption of packet 1 which is a predecessor of packet 2.

[0084] According to some examples, the method for batch mode protection 500 also includes performing header protection on a set of N network packets 300 in parallel using a single API call at block 506. The header protection uses the corresponding protected payload 410 generated earlier in the process (block 504). As described elsewhere herein, the header protection generates a mask of a predetermined length for each network packet 300 using sampled data 704 from the protected payload 410 of each corresponding network packet 300. In the example herein, a 5-byte mask is generated for the network packet 300 using 16 bytes of sampled data 704 from the protected payload 410 corresponding to the network packet 300.

[0085] Figure 7 A comparison between the prior art using per-packet header protection 702 and header protection logic 700 performed by batch mode protection 500 according to one or more embodiments herein is depicted. Batch mode protection 500 processes multiple QUIC network packets 300 (e.g., N network packets, N ≥ 2) under a single API call or function, which results in a reduction in processor cycles required to cross shared library boundaries. Batch mode protection 500 uses a single AES-ECB encryption call to generate protected headers 412 (masked headers) for N network packets 300, rather than N separate AES-ECB encryption calls for each network packet 300.

[0086] Batch mode protection 500 includes using corresponding 16-byte sample data 704 to calculate the mask of multiple network packets 300 at the same time, rather than calculating the protected header 412 for each network packet 300 one by one. This batch mode processing can reduce the computational cost across the shared library boundary by calling the API only once per batch of N network packets 300 (rather than once per packet), and can also achieve higher throughput by utilizing parallel processing of multiple blocks rather than one by one. Sampling of the protected payload 410 can be performed using known techniques for randomly generating sample data 704 of a predetermined length (e.g., 16 bytes). N sample data 704 are input as a single data buffer to a single AES-ECB encryption call to generate a mask for protecting the header 412 (masked header) of the N network packets 300. For example, a 5-byte mask is generated, which is XORed against the message header 412 to hide / mask the header 412. The AES-ECB module 408 generates N 5-byte masked headers (412) as output.

[0087] In some embodiments, at block 508, the network interface controller 280 sends the encrypted network packet 300 using the QUIC protocol.

[0088] Figure 8 An operational flow for batch encryption of packets 800 according to one or more embodiments is illustrated. In the illustration, N network packets 300 are to be sent using the QUIC protocol. The N network packets 300 may include portions of data (e.g., files, streams, etc.) that are partitioned into N (or more) network packets 300. The N network packets 300 are encrypted in batches using the techniques described herein. Each of the N network packets 300 includes a QUIC payload 308 and a QUIC header 312. The QUIC payloads 308 are first encrypted in parallel using a single function call (see Figure 6) to generate corresponding N protected payloads 410. Encryption of the payload can be performed using the public QUIC key using the AEAD module 406. In some embodiments, a separate IV value is provided for each of the N QUIC payloads 308.

[0089] Further, each of the N protected payloads 410 is sampled to obtain N blocks of sampled data 704; the sampled data 704 blocks correspond to each network packet 300. The sampled data 704 blocks are used to generate corresponding header masks 802, one for each network packet 300.

[0090] The QUIC headers 312 of the N network packets 300 are then encrypted in a batch. The encryption may be performed using the AES-ECB module 408. The QUIC header 312 is protected by the AES-ECB module 408 using a corresponding header mask 802 generated using the protected payload 410. In some embodiments, the QUIC header 312 is XORed using the corresponding header mask 802. Thus, the QUIC header 312 of packet 1 is masked using the header mask 802 generated using the QUIC payload 308 of packet 1; the QUIC header 312 of packet 2 is masked using the header mask 802 generated using the QUIC payload 308 of packet 2; and so on, until the QUIC header 312 of packet N is masked using the header mask 802 generated using the QUIC payload 308 of packet N.

[0091] Thus, N network packets 300 are encrypted, including QUIC header 312 and QUIC payload 308. The encrypted N network packets 300 are then sent via network 118 in accordance with the QUIC protocol.

[0092] Embodiments herein facilitate a processor circuit comprising a memory interface and one or more processors coupled to the memory interface, wherein the one or more processors are configured to encrypt multiple network packets transmitted using the QUIC protocol. The network packet comprises a header portion and a payload portion. Encryption comprises executing a first instruction to encrypt the payload of the multiple network packets using a first key. The first key is used across multiple network packets (e.g., is public). Further, encryption comprises a second instruction to encrypt the headers of the multiple network packets using a second key. The second key is used across multiple network packets (e.g., is public).

[0093] In some embodiments, a second key for encrypting a header of a first packet from a plurality of network packets is generated using a sampled subset of data from an encrypted payload of the first packet. In some embodiments, encrypting the header of the first packet is masking the header using the second key. Masking may include an exclusive-or operation.

[0094] In some embodiments, the first instructions to encrypt payloads of a plurality of network packets independently encrypt each payload in parallel.

[0095] In some embodiments, first instructions to encrypt payloads of a plurality of network packets encrypt each payload by interleaving an operation to encrypt a first packet with an operation to encrypt a second packet.

[0096] In some embodiments, encryption of the payload and / or encryption of the header is offloaded to the accelerator 254. The accelerator 254 may be an accelerator device, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), a smart NIC, one or more processors, or a combination thereof.

[0097] The components and features of the above-described devices may be implemented using any combination of discrete circuits, application specific integrated circuits (ASICs), logic gates, and / or single chip architectures. Further, where appropriate, features of the devices may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing. Note that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic" or "circuitry."

[0098] It should be understood that the exemplary devices shown in the above block diagrams can represent a functional descriptive example of many potential implementations. Therefore, the division, omission or inclusion of block functions depicted in the drawings does not imply that the hardware components, circuits, software and / or elements used to implement these functions must be divided, omitted or included in the embodiments.

[0099] At least one computer-readable storage medium may include instructions that, when executed, cause a system to perform any of the computer-implemented methods described herein.

[0100] Some embodiments may be described using the expression "one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily all refer to the same embodiment. Moreover, unless otherwise indicated, the above-mentioned features are considered to be usable together in any combination. Thus, unless it is indicated that the features are incompatible with each other, any features discussed separately may be employed in combination with each other.

[0101] The detailed description herein may be presented in terms of program processes executed on a computer or computer network with general reference to the symbols and nomenclature used herein. These process descriptions and representations are used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art.

[0102] A process is generally considered here to be a self-consistent sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. Usually, although not necessarily, these quantities take the form of electrical, magnetic or optical signals capable of being stored, transferred, combined, compared and otherwise manipulated. It proves convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be noted, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to those quantities.

[0103] Further, the manipulations performed are often referred to by terms such as adding or comparing, which are often associated with mental operations performed by a human operator. In any of the operations described herein that form a part of one or more embodiments, in most cases, such capabilities of a human operator are not required or desired. Rather, the operations are machine operations. Useful machines for performing the operations of the various embodiments include general purpose digital computers or similar devices.

[0104] Some embodiments may be described using the expressions "coupled" and "connected" and their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, some embodiments may be described using the terms "connected" and / or "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0105] Various embodiments also relate to apparatus or systems for performing these operations. The apparatus may be specially constructed for the desired purpose, or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. The processes presented herein are not inherently related to a particular computer or other apparatus. Various general-purpose machines may be used with programs written according to the teachings of this article, or it may prove convenient to construct a more specialized apparatus to perform the desired method. The required structure of various such machines will be apparent from the description given.

[0106] What has been described above includes examples of the disclosed architecture. Of course, it is not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art will recognize that many additional combinations and permutations are possible. Therefore, the novel architecture is intended to embrace all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.

[0107] As previously referenced Figures 1 to 8 The various elements of the described devices may include various hardware elements, software elements, or a combination of the two. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processors, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, applications, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. However, determining whether to use hardware elements and / or software elements to implement an embodiment may vary depending on any number of factors, such as desired computing rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation.

[0108] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logics within a processor, which, when read by a machine, cause the machine to manufacture logic to perform the techniques described herein. Such representations, referred to as "IP cores," may be stored on tangible machine-readable media and provided to various customers or manufacturing facilities to be loaded into manufacturing machines that manufacture logic or processors. For example, some embodiments may be implemented using a machine-readable medium or article that may store instructions or instruction sets, which, when executed by a machine, may cause the machine to perform methods and / or operations according to the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, etc., and may be implemented using any suitable combination of hardware and / or software. The machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and / or storage unit, such as memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disk, floppy disk, compact disk read only memory (CD-ROM), compact disk recordable (CD-R), compact disk rewritable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of digital versatile disks (DVDs), magnetic tapes, cassettes, etc. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc., implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

[0109] It should be understood that the exemplary devices shown in the above block diagrams can represent a functional descriptive example of many potential implementations. Therefore, the division, omission or inclusion of block functions depicted in the drawings does not imply that the hardware components, circuits, software and / or elements used to implement these functions must be divided, omitted or included in the embodiments.

[0110] At least one computer-readable storage medium may include instructions that, when executed, cause a system to perform any of the computer-implemented methods described herein.

[0111] Some embodiments may be described using the expression "one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily all refer to the same embodiment. Moreover, unless otherwise indicated, the above-mentioned features are considered to be usable together in any combination. Thus, unless it is indicated that the features are incompatible with each other, any features discussed separately may be employed in combination with each other.

[0112] The following examples relate to further embodiments, from which numerous permutations and configurations will be apparent.

[0113] Example 1 includes an apparatus comprising: an interface to a memory; and a processor that executes one or more instructions. The instructions cause the processor to receive an indication of a plurality of packets via an application programming interface (API), a corresponding packet in the plurality of packets including a corresponding header and a corresponding payload. Further, the instructions cause the processor to determine, through a QUIC protocol stack, to encrypt the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the payload of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.

[0114] In Example 2, the apparatus further comprises an accelerator device, wherein the processor causes the payload to be encrypted using the accelerator device.

[0115] In Example 3, the processor causes the header to be encrypted using the accelerator device.

[0116] In Example 4, the accelerator device is a hardware accelerator, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), or a network interface controller (NIC).

[0117] In Example 5, the payloads of multiple packets are encrypted in parallel using a common key.

[0118] In Example 6, headers of multiple packets are encrypted in parallel using corresponding masks.

[0119] In Example 7, a corresponding mask for an encrypted header is generated based on the encrypted payloads of the corresponding plurality of packets.

[0120] Example 8 includes a non-transitory computer-readable storage medium, including one or more instructions that, when executed by one or more processors, cause the one or more processors to perform one or more operations. The one or more processors receive an indication of a plurality of packets via an application programming interface (API), wherein a corresponding packet in the plurality of packets includes a corresponding header and a corresponding payload. The one or more processors determine, through the QUIC protocol stack, to encrypt the plurality of packets in parallel. The one or more processors encrypt the payload of the plurality of packets in parallel. The one or more processors encrypt the headers of the plurality of packets in parallel.

[0121] In Example 9, the one or more processors cause the payload to be encrypted using the accelerator device.

[0122] In example 10, the one or more processors cause encryption of the header using the accelerator device.

[0123] In Example 11, the accelerator device is a hardware accelerator, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), or a network interface controller (NIC).

[0124] In Example 12, the payloads of multiple packets are encrypted in parallel using a common key.

[0125] In Example 13, headers of multiple packets are encrypted in parallel using corresponding masks.

[0126] In Example 14, a corresponding mask for an encrypted header is generated based on the encrypted payloads of the corresponding plurality of packets.

[0127] Example 15 includes a computer-implemented method. The method includes receiving, by a processor, an indication of a plurality of packets to be sent, a corresponding packet in the plurality of packets including a header and a payload. The method also includes causing, by the processor, encryption of the plurality of packets. The encryption includes encrypting the payloads of the plurality of packets in parallel and encrypting the headers of the plurality of packets in parallel.

[0128] In Example 16, encrypting payloads of multiple packets in parallel includes a single function call.

[0129] In Example 17, encrypting headers of multiple packets in parallel includes a single function call.

[0130] In Example 18, the payloads of multiple packets are encrypted in parallel using a common key.

[0131] In Example 19, headers of multiple packets are encrypted in parallel using corresponding masks.

[0132] In Example 20, a corresponding mask for the encrypted header is generated based on the encrypted payloads of the corresponding plurality of packets.

[0133] It should be emphasized that the abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. The abstract is submitted with the following understanding: it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the aforementioned detailed description, it can be seen that in order to make the present disclosure smooth, various features are grouped together in a single embodiment. This disclosure method should not be interpreted as reflecting the intention that the claimed embodiment requires more features than the features explicitly stated in each claim. Instead, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Thus, the following claims are thus incorporated into the detailed description, wherein each claim is independently a separate embodiment. In the attached claims, the terms "including" and "wherein" are used as the plain English equivalents of the corresponding terms "including" and "wherein", respectively. Moreover, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0134] The above description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. It is contemplated that the scope of the present disclosure is not limited by this specific embodiment, but rather by the appended claims. Future applications claiming priority to the present application may claim the disclosed subject matter in different ways, and may generally include any set of one or more limitations as variously disclosed or otherwise presented herein.

Claims

1. A device comprising: Interface to memory; as well as A processor, configured to execute one or more instructions so that the processor performs the following operations: receiving, via an application programming interface (API), an indication of a plurality of packets, a respective packet of the plurality of packets comprising a respective header and a respective payload; Determining, by the QUIC protocol stack, to encrypt the plurality of packets in parallel; encrypting the payloads of the plurality of packets in parallel; and The headers of the plurality of packets are encrypted in parallel.

2. The apparatus according to claim 1, further comprising an accelerator device, wherein: The processor causes encryption of the payload using the accelerator device.

3. The device according to claim 2, wherein: The processor causes encryption of the header using the accelerator device.

4. The device according to claim 2, wherein: The accelerator device is a hardware accelerator, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), or a network interface controller (NIC).

5. The device according to claim 1 or 2, wherein: The payloads of the plurality of packets are encrypted in parallel using a common key.

6. The device according to claim 5, wherein: The headers of the plurality of packets are encrypted in parallel using corresponding masks.

7. The device according to claim 6, wherein: The respective masks used to encrypt the headers are generated based on the encrypted payloads of the respective plurality of packets.

8. The device according to claim 1 or 2, wherein: The instructions for encrypting the payloads of the plurality of packets in parallel comprise a single function call.

9. A non-transitory computer-readable storage medium comprising one or more instructions that, when executed by one or more processors, cause the one or more processors to: receiving, via an application programming interface (API), an indication of a plurality of packets, a respective packet of the plurality of packets comprising a respective header and a respective payload; Determining, by the QUIC protocol stack, to encrypt the plurality of packets in parallel; encrypting payloads of the plurality of packets in parallel; and The headers of the plurality of packets are encrypted in parallel.

10. The non-transitory computer-readable storage medium of claim 9, wherein: The one or more processors cause encryption of the payload using an accelerator device.

11. The non-transitory computer-readable storage medium of claim 10, wherein: The one or more processors cause encryption of the header using the accelerator device.

12. The non-transitory computer-readable storage medium of claim 10, wherein: The accelerator device is a hardware accelerator, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), or a network interface controller (NIC).

13. The non-transitory computer-readable storage medium according to claim 9 or 10, wherein: The payloads of the plurality of packets are encrypted in parallel using a common key.

14. The non-transitory computer-readable storage medium of claim 13, wherein: The headers of the plurality of packets are encrypted in parallel using corresponding masks.

15. The non-transitory computer-readable storage medium of claim 14, wherein: The respective masks used to encrypt the headers are generated based on the encrypted payloads of the respective plurality of packets.

16. The non-transitory computer-readable storage medium of claim 9, wherein: The instructions for encrypting the payloads of the plurality of packets in parallel comprise a single function call.

17. A computer-implemented method comprising: receiving, by a processor, an indication of a plurality of packets to be sent, a respective packet of the plurality of packets comprising a header and a payload; as well as causing, by the processor, encrypting the plurality of packets, the encrypting comprising: encrypting payloads of the plurality of packets in parallel; as well as The headers of the plurality of packets are encrypted in parallel.

18. The computer-implemented method of claim 17, wherein: The processor causes encryption of the payload using an accelerator device.

19. The computer-implemented method of claim 18, wherein: The processor causes encryption of the header using the accelerator device.

20. The computer-implemented method of claim 18, wherein: The accelerator device is a hardware accelerator, a graphics processing unit (GPU), a data processing unit (DPU), an infrastructure processing unit (IPU), or a network interface controller (NIC).

21. The computer-implemented method of claim 17 or 18, wherein: The encrypting the headers of the plurality of packets in parallel comprises a single function call.

22. The computer-implemented method of claim 17, wherein: The payloads of the plurality of packets are encrypted in parallel using a common key.

23. The computer-implemented method of claim 17, wherein: The headers of the plurality of packets are encrypted in parallel using corresponding masks.

24. The computer-implemented method of claim 23, wherein: The respective masks used to encrypt the headers are generated based on the encrypted payloads of the respective plurality of packets.

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