Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure comprises the following steps: providing a substrate; forming a stacked layer on the top surface of the substrate, wherein the stacked layer comprises a conductive layer and an active layer located above the conductive layer; etching the stacked layer to form a plurality of first grooves that penetrate the stacked layer along a first direction and are arranged at intervals along a second direction, wherein the plurality of first grooves separate the conductive layer into a plurality of first conductive lines; etching the active layer to form a plurality of second grooves that penetrate the stacked layer along the first direction and are arranged at intervals along a third direction, wherein the plurality of first grooves and the plurality of second grooves separate the active layer into a plurality of active pillars arranged at intervals. The present disclosure reduces the difficulty of the semiconductor structure manufacturing process and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, multiple second conductive lines electrically connected to the memory cells, and multiple bit lines. Each memory cell typically includes a switching element and a storage element electrically connected to the switching element. The second conductive line voltage on the second conductive line can control the switching element to turn on and off, thereby allowing data stored in the storage element to be read or written to the storage element via the bit lines.

[0003] In the manufacturing process of semiconductor structures such as DRAM, buried signal line structures (such as buried bit lines) are often used to reduce the size of the semiconductor structure. However, buried bit lines are typically formed using processes such as metal deposition, ion implantation, and silicide formation. However, the metal deposition method for forming buried bit lines requires lateral etching, which is difficult to perform; the ion implantation method is prone to damage to the active pillars and the ion implantation process is relatively complex; and the silicide formation process requires lateral etching and annealing, which is not only complex but also easily affects the morphology of the active pillars.

[0004] Therefore, how to simplify the manufacturing process of embedded signal lines and improve the performance of semiconductor structures is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to simplify the manufacturing process of buried signal lines and improve the performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0007] providing a substrate;

[0008] forming a stacked layer on the top surface of the substrate, the stacked layer comprising a conductive layer and an active layer located above the conductive layer;

[0009] Etching the stacked layer to form a plurality of first trenches penetrating the stacked layer along a first direction and spaced apart along a second direction, wherein the plurality of first trenches separate the conductive layer into a plurality of first conductive lines, wherein the first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate;

[0010] The active layer is etched to form a plurality of second grooves that penetrate the stacked layer along the first direction and are arranged at intervals along a third direction, wherein the plurality of first grooves and the plurality of second grooves separate the active layer into a plurality of active pillars arranged at intervals, the third direction is parallel to the top surface of the substrate, and the second direction intersects with the third direction.

[0011] In some embodiments, the specific steps of forming the stacked layer on the top surface of the substrate include:

[0012] forming the conductive layer on the top surface of the substrate;

[0013] forming a first source / drain layer on the conductive layer;

[0014] forming a channel layer on the first source and drain layer;

[0015] A second source-drain layer is formed on the channel layer, wherein the active layer includes the first source-drain layer, the channel layer and the second source-drain layer.

[0016] In some embodiments, the conductive material is any one of a metal material, a metal compound material, a polymer material, and a doped silicon material, or a combination of two or more thereof.

[0017] In some embodiments, the material of the first source / drain layer and the material of the second source / drain layer are both silicon materials doped with first type ions;

[0018] The material of the channel layer is a silicon material doped with first type ions or second type ions, and the conductivity types of the first type ions and the second type ions are opposite.

[0019] In some embodiments, the specific step of forming a stacked layer on the top surface of the substrate further includes:

[0020] A contact layer electrically connected to the second source / drain layer is formed on the second source / drain layer, and the stacked layer includes the conductive layer, the active layer, and the contact layer.

[0021] In some embodiments, the material of the contact layer is any one of a metal material, a metal compound material, a polymer material, and a doped silicon material, or a combination of two or more thereof.

[0022] In some embodiments, the substrate includes an array region and a peripheral region outside the array region, the height of the substrate in the peripheral region is higher than the height of the substrate in the array region, and the stacked layer covers the array region and the peripheral region; before forming the plurality of first trenches that penetrate the stacked layer along the first direction and are spaced apart along the second direction, the following steps are further included:

[0023] The stacked layer in the peripheral area and part of the contact layer in the array area are removed to expose the substrate in the peripheral area, and the top surface of the remaining contact layer in the array area is flush with the top surface of the substrate in the peripheral area.

[0024] In some embodiments, the specific steps of forming a plurality of first trenches penetrating the stacked layer along the first direction and spaced apart along the second direction include:

[0025] The stacked layer and a portion of the substrate are etched to form a plurality of first trenches that penetrate the stacked layer along the first direction and extend into the interior of the substrate.

[0026] In some embodiments, the specific steps of etching the active layer include:

[0027] forming a first filling layer that completely fills the first trench;

[0028] The active layer and the first filling layer are etched to form a plurality of second grooves that penetrate the active layer and the first filling layer along the first direction and are arranged at intervals along the third direction. The plurality of first grooves and the plurality of second grooves separate the first source and drain layer into a plurality of first source and drain regions arranged at intervals, separate the channel layer into a plurality of channel regions arranged at intervals, and separate the second source and drain layer into a plurality of second source and drain regions arranged at intervals. The active pillar includes the first source and drain regions, the channel regions, and the second source and drain regions.

[0029] In some embodiments, after forming a plurality of second trenches penetrating the stacked layer along the first direction and spaced apart along the third direction, the method further includes the following steps:

[0030] forming a gate dielectric layer covering the channel region in the active pillar;

[0031] A plurality of second conductive lines extending along the second direction and arranged at intervals along the third direction are formed, wherein the second conductive lines continuously cover the gate dielectric layer in the plurality of active pillars arranged at intervals along the second direction.

[0032] In some embodiments, the specific steps of forming a gate dielectric layer covering the channel region in the active pillar include:

[0033] forming a second filling layer that completely fills the second trench;

[0034] Etching back a portion of the second filling layer to expose the channel region, with the top surface of the remaining second filling layer being flush with the top surface of the first source and drain region;

[0035] The gate dielectric layer is formed along the second trench, covering the channel region and located above the second filling layer.

[0036] According to some other embodiments, the present disclosure further provides a semiconductor structure, including:

[0037] substrate;

[0038] A stacked structure is located on the top surface of the substrate, the stacked structure includes a conductive epitaxial structure and an active epitaxial structure stacked on the conductive epitaxial structure along a first direction, an epitaxial contact interface is provided between the conductive epitaxial structure and the active epitaxial structure, the conductive epitaxial structure includes a plurality of first conductive lines extending along a third direction and arranged at intervals along a second direction, the active epitaxial structure includes a plurality of active pillars arranged at intervals along the second direction and the third direction, the first direction is perpendicular to the top surface of the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects with the third direction.

[0039] In some embodiments, the conductive epitaxial structure is made of doped silicon.

[0040] In some embodiments, the active epitaxial structure comprises:

[0041] a first source / drain layer stacked on the conductive epitaxial structure along the first direction, wherein an epitaxial contact interface is formed between the first source / drain layer and the conductive epitaxial structure;

[0042] a channel layer, stacked on the first source and drain layer along the first direction, with an epitaxial contact interface between the channel layer and the first source and drain layer;

[0043] A second source-drain layer is stacked on the channel layer along the first direction, and an epitaxial contact interface is formed between the second source-drain layer and the channel layer.

[0044] In some embodiments, the material of the first source / drain layer and the material of the second source / drain layer are both silicon materials doped with first type ions;

[0045] The material of the channel layer is a silicon material doped with first type ions or second type ions, and the conductivity types of the first type ions and the second type ions are opposite.

[0046] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. A stacked layer is formed on a substrate, and the stacked layer includes a conductive layer and an active layer located above the conductive layer. The conductive layer is directly etched to form a first conductive line, and the active layer is etched to form an active pillar. In this way, in the process of forming the first conductive line, no lateral etching is required, no ion implantation along the gap between adjacent active pillars is required, and no annealing treatment is required. This not only simplifies the formation process of the first conductive line, reduces the difficulty of the semiconductor structure process, and improves the manufacturing yield of the semiconductor structure, but also avoids damage to the active pillar, reduces or even avoids leakage problems between the first conductive line and other conductive structures, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Attachment Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0048] Attachment Figure 2 -Attached Figure 8 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0050] This embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 -Attached Figure 8 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. Figures 1-8 As shown, the method for forming the semiconductor structure includes the following steps:

[0051] Step S11, providing a substrate 13;

[0052] Step S12, forming a stacked layer 46 on the top surface of the substrate 13, wherein the stacked layer 46 includes a conductive layer 40 and an active layer 45 located above the conductive layer;

[0053] Step S13: etching the stacked layer 46 to form a plurality of first trenches extending through the stacked layer 46 along a first direction and spaced apart along a second direction D2. The plurality of first trenches separate the conductive layer 40 into a plurality of first conductive lines 11. The first direction is perpendicular to the top surface of the substrate 13, and the second direction D2 is parallel to the top surface of the substrate 13.

[0054] In step S14, the active layer 45 is etched to form a plurality of second grooves that penetrate the stacked layer 46 along the first direction and are arranged at intervals along the third direction D3. The plurality of first grooves and the plurality of second grooves separate the active layer 45 into a plurality of active pillars 10 that are arranged at intervals. The third direction D3 is parallel to the top surface of the substrate 13, and the second direction D2 intersects with the third direction D3.

[0055] In some embodiments, the specific steps of forming the stacked layer 46 on the top surface of the substrate 13 include:

[0056] forming the conductive layer 40 on the top surface of the substrate 13;

[0057] forming a first source / drain layer 41 on the conductive layer 40;

[0058] forming a channel layer 42 on the first source and drain layer 41;

[0059] A second source / drain layer 43 is formed on the channel layer 42 . The active layer 45 includes the first source / drain layer 41 , the channel layer 42 , and the second source / drain layer 43 .

[0060] The semiconductor structure described in this embodiment may be, but is not limited to, a DRAM. This embodiment is described using a DRAM as an example. The substrate 13 may be, but is not limited to, a silicon substrate. This embodiment is described using a silicon substrate as an example. In other embodiments, the substrate 13 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 13 is used to support the device structure above it. Figure 2 is a schematic top view of the semiconductor structure formed in this specific embodiment, Figure 3 Shown Figure 2 A schematic cross-sectional view of the aa position, bb position, cc position, dd position and ee position after the substrate 13 is formed. The substrate 13 may include an array area AA and a peripheral area PA located outside the array area AA, wherein the aa position, bb position, cc position and dd position are all located in the array area AA, and the ee position is located in the peripheral area PA. The array area AA is used to form a memory array, and the peripheral area PA is used to form a control circuit, and the control circuit is used to transmit a control signal to the memory array. The height of the substrate 13 in the array area AA is lower than the height of the substrate 13 in the peripheral area PA, that is, along the first direction, the top surface of the array area AA is located below the top surface of the peripheral area PA, as shown in FIG. Figure 3As shown. For example, the steps of forming the substrate 13 may be: providing an initial substrate, and defining the array area AA and the peripheral area PA located outside the array area AA in the initial substrate; removing part of the initial substrate in the array area AA by a dry etching process, so that the thickness of the initial substrate in the array area AA is lower than the thickness of the initial substrate in the peripheral area PA, and using the remaining initial substrate as the substrate 13, as shown. Figure 3 After the substrate 13 is formed, dopant ions may be implanted into the substrate 13 to reduce leakage between the first conductive line 11 formed subsequently and the substrate 13 .

[0061] After forming the substrate 13, a deposition process or an epitaxial process may be used to form the conductive layer 40 covering the top surface of the substrate 13. The thickness of the conductive layer 40 may be determined according to the thickness of the first conductive line 11 to be formed subsequently. Next, a deposition process or an epitaxial process may be used to form the first source-drain layer 41 covering the conductive layer 40 on the conductive layer 40; a deposition process or an epitaxial process may be used to form the channel layer 42 covering the first source-drain layer 41 on the first source-drain layer 41; a deposition process or an epitaxial process may be used to form the second source-drain layer 43 covering the channel layer 42 on the channel layer 42, as shown in FIG. Figure 4 As shown. Among them, Figure 4 Shown Figure 2 Schematic cross-sectional view of the positions aa, bb, cc, dd, and ee in the figure after forming the stacked layer 46. In this specific embodiment, the conductive layer 40, the first source / drain layer 41, the channel layer 42, and the second source / drain layer 43 are sequentially formed on the substrate 13 through a deposition process or an epitaxial process. On the one hand, in the subsequent process of forming the first conductive line 11, only the conductive layer 40 needs to be etched along the first direction, eliminating the need for lateral bowl-shaped structure etching, ion implantation along the narrow gaps between adjacent active pillars, and annealing. This reduces the manufacturing difficulty and cost of the first conductive line 11, avoids damage to the subsequently formed active pillars, improves the manufacturing yield of the semiconductor structure, and improves the performance of the semiconductor structure. On the other hand, the positions of the first source / drain region, the channel region, and the second source / drain region in the subsequently formed active pillars can be controlled, eliminating the need for subsequent ion implantation, thereby further improving the yield of the semiconductor structure.

[0062] In some embodiments, the conductive material is any one of a metal material, a metal compound material, a polymer material, and a doped silicon material, or a combination of two or more thereof. In one example, the conductive material is a silicon material doped with a first type of ions, so that the conductive layer 40 can be grown on the top surface of the substrate 13 through an epitaxial process. For example, a silicon material can be first epitaxially grown on the top surface of the substrate 13, and then the first type of ions (e.g., N-type ions) can be implanted into the epitaxially grown silicon material through an ion implantation process to form the conductive layer 40.

[0063] In some embodiments, the material of the first source / drain layer 41 and the material of the second source / drain layer 43 are both silicon materials doped with first type ions;

[0064] The channel layer 42 is made of silicon doped with first-type ions or second-type ions. The first-type ions and the second-type ions have opposite conductivity types.

[0065] In one example, the first type of ions are N-type ions, and the second type of ions are P-type ions. For example, the material of the conductive layer 40, the material of the first source / drain layer 41, and the material of the second source / drain layer 43 are all silicon materials doped with N-type ions, and the doping concentration of the N-type ions in the conductive layer 40 is greater than the doping concentration of the N-type ions in the first source / drain layer 41, and greater than the doping concentration of the N-type ions in the second source / drain layer 43. The material of the channel layer 42 can be silicon material doped with N-type ions or silicon material doped with P-type ions.

[0066] In some embodiments, the specific steps of forming the stacked layer 46 on the top surface of the substrate 13 further include:

[0067] A contact layer 44 electrically connected to the second source / drain layer 43 is formed on the second source / drain layer 43 . The stacked layer 46 includes the conductive layer 40 , the active layer 45 and the contact layer 44 .

[0068] In some embodiments, the material of the contact layer 44 is any one of metal materials, metal compound materials, polymer materials, and doped silicon materials, or a combination of two or more thereof.

[0069] In some embodiments, the substrate 13 includes an array area AA and a peripheral area PA located outside the array area AA. The height of the substrate 13 in the peripheral area PA is higher than the height of the substrate 13 in the array area AA. The stacked layer 46 covers the array area AA and the peripheral area PA. Before forming a plurality of first trenches that penetrate the stacked layer 46 along the first direction and are spaced apart along the second direction D2, the following steps are further included:

[0070] The stacking layer 46 located in the peripheral area PA is removed, and part of the contact layer 44 located in the array area AA is removed to expose the substrate 13 of the peripheral area PA, and the top surface of the remaining contact layer 44 in the array area AA is made flush with the top surface of the substrate 13 of the peripheral area PA.

[0071] In one example, Figure 3 In the structure shown, along the first direction, the distance between the top surface of the substrate 13 of the array area AA and the top surface of the substrate 13 of the peripheral area PA is 100nm to 200nm (for example, 160nm). For example, in the process of forming the stacked layer 46, the conductive layer 40 and the active layer 45 both cover the array area AA and the peripheral area PA. After the active layer 45 is formed, an epitaxial growth process can be used to epitaxially grow a silicon material layer on the surface of the second source and drain layer 43, and the first type of ions (for example, N-type ions) can be in situ implanted to form the contact layer 44 located above the array area AA and above the peripheral area PA. After the stacked layer 46 including the contact layer 44, the active layer 45 and the conductive layer 40 is formed, the height of the peripheral area PA is higher than the height of the array area AA, as shown in FIG. Figure 4 Then, a planarization process such as chemical mechanical polishing (CMP) can be used to planarize the stacked layer 46, remove all the stacked layers 46 in the peripheral area PA, and remove part of the stacked layers 46 in the array area AA, so that the substrate 13 in the peripheral area PA is exposed, and the top surface of the remaining stacked layer 46 in the array area AA is flush with the top surface of the exposed substrate 13 in the peripheral area PA along the first direction, so as to facilitate the implementation of subsequent processing, as shown in FIG. Figure 5 As shown. Among them, Figure 5 Shown Figure 2 Schematic cross-sectional view of the aa position, bb position, cc position, dd position and ee position after the stack layer 46 is planarized.

[0072] In some embodiments, the specific steps of forming a plurality of first trenches penetrating the stacked layer 46 along the first direction and spaced apart along the second direction D2 include:

[0073] The stacked layer 46 and a portion of the substrate 13 are etched to form a plurality of first trenches that penetrate the stacked layer 46 along the first direction and extend to the interior of the substrate 13 .

[0074] In some embodiments, the specific steps of etching the active layer 45 include:

[0075] A first filling layer 60 is formed to fill the first trench, such as Figure 6 As shown, Figure 6 Shown Figure 2 A schematic cross-sectional view of the aa position, the bb position, the cc position, the dd position, and the ee position after the first filling layer 60 is formed;

[0076] The active layer 45 and the first filling layer 60 are etched to form a plurality of second grooves that penetrate the active layer 45 and the first filling layer 60 along the first direction and are arranged at intervals along the third direction D3. The plurality of first grooves and the plurality of second grooves separate the first source and drain layer 41 into a plurality of first source and drain regions 72 arranged at intervals, separate the channel layer 42 into a plurality of channel regions 73 arranged at intervals, and separate the second source and drain layer 43 into a plurality of second source and drain regions 74 arranged at intervals. The active pillar 10 includes the first source and drain regions 72, the channel regions 73 and the second source and drain regions 74.

[0077] For example, after the stacked layer 46 is planarized and formed as follows Figure 5 After the structure shown, a SADP (Self-aligned Double Patterning) etching process can be used to etch the stacked layer 46 and over-etch the substrate 13 in the array area AA, forming a plurality of first trenches that penetrate the stacked layer 46 along the first direction and extend into the interior of the substrate 13. Next, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process is used to deposit an oxide material (e.g., silicon dioxide) into the first trenches to form a first filling layer 60 that fills the first trenches and covers the top surface of the stacked layer 46, as shown in FIG. Figure 6 As shown. By over-etching the substrate 13, the first filling layer 60 is extended to the inside of the substrate 13. On the one hand, the conductive layer 40 can be fully cut off to ensure that the adjacent first conductive lines 11 are isolated from each other; on the other hand, the leakage problem between adjacent first conductive lines 11 can be reduced, thereby further improving the performance of the semiconductor structure. Before forming the first trench, the substrate 13 in the peripheral area PA can also be etched to form a peripheral active column 61, and the peripheral active column 61 is subsequently used to form a peripheral transistor. In order to isolate the peripheral active column 61 from other structures, a first peripheral isolation layer 62 and a second peripheral isolation layer 63 covering the peripheral active column 61 can also be formed. In one example, the material of the first peripheral isolation layer 62 can be an oxide material (such as silicon dioxide), and the material of the second peripheral isolation layer 63 can be a nitride material (such as silicon nitride).

[0078] After forming the first filling layer 60, the SADP etching process can be used again to etch the contact layer 44 and the active layer 45 in the stacked layer 46, as well as the first filling layer 60, to form a plurality of second trenches that penetrate the active layer 45 and the first filling layer 60 along the first direction and are arranged at intervals along the third direction D3. The plurality of first trenches and the plurality of second trenches together separate the active layer 45 into a plurality of active pillars 10 arranged in a two-dimensional array along the second direction D2 and the third direction D3, as shown in FIG. Figure 2 and Figure 7 As shown. Among them, Figure 7 Shown Figure 2 Schematic cross-sectional view of the positions aa, bb, cc, dd, and ee in the figure after the active pillars 10 are formed. Each active pillar 10 includes a first source / drain region 72 located above the conductive line 11, a channel region 73 located above the first source / drain region 72, and a second source / drain region 74 located above the channel region 73, to form a vertically structured transistor. In this embodiment, the active pillars 10 are directly formed by epitaxially growing the active layer 25 and etching the epitaxially grown active layer 25, thereby ensuring the uniformity of the morphology of the multiple active pillars 10 formed, as well as the uniformity of the positions and doping concentrations of the first source / drain regions 72, the channel regions 73, and the second source / drain regions 74 in the multiple active pillars 10, thereby further improving the performance of the semiconductor structure. The multiple first trenches and the multiple second trenches also jointly separate the contact layer 44 into a plurality of contact regions 75 electrically connected to the multiple active pillars 10 in a one-to-one correspondence. The contact region 75 is used to reduce the contact resistance between the subsequently formed charge storage structure and the second source / drain region 74. In one example, the charge storage structure may be a capacitor.

[0079] In some embodiments, after forming a plurality of second trenches penetrating the stacked layer 46 along the first direction and spaced apart along the third direction D3, the following steps are further included:

[0080] forming a gate dielectric layer 82 covering the channel region 73 in the active pillar 10;

[0081] A plurality of second conductive lines 12 extending along the second direction D2 and arranged at intervals along the third direction D3 are formed, and the second conductive lines 12 continuously cover the gate dielectric layer 82 in the plurality of active pillars 10 arranged at intervals along the second direction D2.

[0082] In some embodiments, the specific steps of forming the gate dielectric layer 82 covering the channel region 73 in the active pillar 10 include:

[0083] forming a second filling layer that completely fills the second trench;

[0084] Etch back a portion of the second filling layer to expose the channel region 73 , and ensure that the top surface of the remaining second filling layer is flush with the top surface of the first source and drain region 72 ;

[0085] The gate dielectric layer 82 is formed along the second trench, covering the channel region 73 and located above the second filling layer.

[0086] For example, after forming a plurality of second trenches, an oxide material (such as silicon dioxide) may be deposited along the second trenches to form a first dielectric layer 70 covering the inner walls of the second trenches; and a nitride material (such as silicon nitride) may be deposited along the second trenches to form a second dielectric layer 71 filling the second trenches and covering the first dielectric layer 70. The first dielectric layer 70 and the second dielectric layer 71 together constitute the second filling layer. Figure 7 As shown. Then, part of the second filling layer is etched back to lower the height of the second filling layer (for example, the top surface of the remaining second filling layer is flush with the top surface of the first source and drain region 72), so that the channel region 73 in the active column 10 is exposed. The remaining second filling layer after the back etching serves as the first isolation layer between the first conductive line 11 and the second conductive line 12. Afterwards, the gate dielectric layer 82 covering the channel region 73 can be formed by an ISSG (In-Situ Steam Generation) process or a deposition process. Then, an atomic layer deposition process can be used to deposit a conductive material such as TiN or metal tungsten on the gate dielectric layer 82 to form a plurality of second conductive lines 12 extending along the second direction D2 and spaced apart along the third direction D3. Then, an isolation material is deposited in the second trench to form a second isolation layer 80 that fills the second trench and covers the second conductive line 12, as shown. Figure 8 As shown. Among them, Figure 8 Shown Figure 2 Schematic cross-sectional view of aa, bb, cc, dd, and ee positions after forming the second isolation layer 80. In one example, the first conductive line 11 may be a bit line, and the second conductive line 12 may be a word line.

[0087] This embodiment also provides a semiconductor structure. The semiconductor structure in this embodiment can be used as follows: Figures 1-8 The semiconductor structure is formed by the method shown in FIG. 1 . The schematic diagram of the semiconductor structure formed in this embodiment can be seen in FIG. Figure 2 and Figure 8 .like Figure 2-Figure 8As shown, the semiconductor structure includes:

[0088] substrate 13;

[0089] A stacked structure is located on the top surface of the substrate 13, and the stacked structure includes a conductive epitaxial structure and an active epitaxial structure stacked on the conductive epitaxial structure along a first direction. An epitaxial contact interface is provided between the conductive epitaxial structure and the active epitaxial structure. The conductive epitaxial structure includes a plurality of first conductive lines 11 extending along a third direction D3 and arranged at intervals along a second direction D2. The active epitaxial structure includes a plurality of active pillars 10 arranged at intervals along the second direction D2 and the third direction D3. The first direction is perpendicular to the top surface of the substrate 13, and the second direction D2 and the third direction D3 are both parallel to the top surface of the substrate 13, and the second direction D2 intersects with the third direction D3.

[0090] For example, if Figure 2 and Figure 8 As shown, the conductive epitaxial structure includes the plurality of first conductive lines 11 extending along the third direction D3 and arranged at intervals along the second direction D2, and the conductive epitaxial structure is formed by epitaxially growing the conductive layer 40 on the substrate 13 and etching the conductive layer 40. The active epitaxial structure includes a plurality of active pillars 10 arranged at intervals along the second direction D2 and the third direction D3, and the active epitaxial structure is formed by epitaxially growing the active layer 45 on the conductive layer 40 and etching the active layer 45. In this specific embodiment, the conductive layer 40 and the active layer 45 are sequentially formed on the substrate 13 through an epitaxial process, so that an epitaxial contact interface is formed between the active epitaxial structure and the conductive epitaxial structure. On the one hand, in the subsequent process of forming the first conductive line 11, it is only necessary to etch the conductive layer 40 along the first direction, without the need for horizontal bowl-shaped structure etching, and no ion implantation along the narrow gap between adjacent active pillars, and no annealing treatment is required, which reduces the manufacturing difficulty and manufacturing cost of the first conductive line 11, avoids damage to the subsequently formed active pillars, improves the manufacturing yield of the semiconductor structure, and improves the performance of the semiconductor structure; on the other hand, it can control the morphology of the subsequently formed active pillars, and no ion implantation process is required subsequently, thereby further improving the yield of the semiconductor structure. The epitaxial contact interface described in this specific embodiment refers to the contact interface between two epitaxial layers grown separately through two epitaxial processes.

[0091] In some embodiments, the conductive epitaxial structure is made of a doped silicon material. In one example, the conductive epitaxial structure is made of a silicon material doped with N-type ions.

[0092] In some embodiments, the active epitaxial structure comprises:

[0093] a first source / drain layer 41 stacked on the conductive epitaxial structure along the first direction, with an epitaxial contact interface between the first source / drain layer 41 and the conductive epitaxial structure;

[0094] a channel layer 42 stacked on the first source / drain layer 41 along the first direction, with an epitaxial contact interface between the channel layer and the first source / drain layer 41;

[0095] The second source / drain layer 43 is stacked on the channel layer 42 along the first direction, and an epitaxial contact interface is formed between the second source / drain layer 43 and the channel layer 42 .

[0096] In some embodiments, the material of the first source / drain layer 41 and the material of the second source / drain layer 43 are both silicon materials doped with first type ions;

[0097] The channel layer 42 is made of silicon doped with first-type ions or second-type ions. The first-type ions and the second-type ions have opposite conductivity types.

[0098] Some embodiments of the present specific implementation manner provide a semiconductor structure and a method for forming the same. A stacked layer is formed on a substrate, and the stacked layer includes a conductive layer and an active layer located above the conductive layer. The first conductive line is formed by directly etching the conductive layer, and the active column is formed by etching the active layer. In this way, in the process of forming the first conductive line, no lateral etching is required, no ion implantation is required along the gap between adjacent active columns, and no annealing treatment is required. This not only simplifies the formation process of the first conductive line, reduces the difficulty of the semiconductor structure process, and improves the manufacturing yield of the semiconductor structure, but also avoids damage to the active column, reduces or even avoids the leakage problem between the first conductive line and other conductive structures, thereby improving the performance of the semiconductor structure.

[0099] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: providing a substrate; forming a stacked layer on the top surface of the substrate, the stacked layer comprising a conductive layer and an active layer located above the conductive layer; Etching the stacked layer to form a plurality of first trenches penetrating the stacked layer along a first direction and spaced apart along a second direction, wherein the plurality of first trenches separate the conductive layer into a plurality of first conductive lines, wherein the first direction is perpendicular to the top surface of the substrate, and the second direction is parallel to the top surface of the substrate; Etching the active layer to form a plurality of second trenches extending along the first direction through the stacked layer and spaced apart along a third direction, wherein the plurality of first trenches and the plurality of second trenches separate the active layer into a plurality of spaced apart active pillars, wherein the third direction is parallel to the top surface of the substrate, and the second direction intersects the third direction; The specific steps of forming a stacked layer on the top surface of the substrate include: forming the conductive layer on the top surface of the substrate; forming a first source / drain layer on the conductive layer; forming a channel layer on the first source and drain layer; forming a second source-drain layer on the channel layer, wherein the active layer includes the first source-drain layer, the channel layer and the second source-drain layer; The specific steps of forming a stacked layer on the top surface of the substrate also include: A contact layer electrically connected to the second source / drain layer is formed on the second source / drain layer, and the stacked layer includes the conductive layer, the active layer, and the contact layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The conductive layer is made of any one of metal materials, metal compound materials, polymer materials, and doped silicon materials, or a combination of two or more thereof.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first source / drain layer and the material of the second source / drain layer are both silicon materials doped with first type ions; the material of the channel layer is silicon material doped with first type ions or second type ions, and the conductivity types of the first type ions and the second type ions are opposite.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the contact layer is any one of metal materials, metal compound materials, polymer materials, and doped silicon materials, or a combination of two or more thereof.

5. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes an array region and a peripheral region outside the array region, the height of the substrate in the peripheral region is higher than the height of the substrate in the array region, and the stacked layer covers the array region and the peripheral region. Before forming a plurality of first trenches that penetrate the stacked layer along a first direction and are spaced apart along a second direction, the method further includes the following steps: The stacked layer in the peripheral area and part of the contact layer in the array area are removed to expose the substrate in the peripheral area, and the top surface of the remaining contact layer in the array area is flush with the top surface of the substrate in the peripheral area.

6. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a plurality of first grooves penetrating the stacked layer along the first direction and spaced apart along the second direction include: The stacked layer and a portion of the substrate are etched to form a plurality of first trenches that penetrate the stacked layer along the first direction and extend into the interior of the substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of etching the active layer include: forming a first filling layer that completely fills the first trench; The active layer and the first filling layer are etched to form a plurality of second grooves that penetrate the active layer and the first filling layer along the first direction and are arranged at intervals along the third direction. The plurality of first grooves and the plurality of second grooves separate the first source and drain layer into a plurality of first source and drain regions arranged at intervals, separate the channel layer into a plurality of channel regions arranged at intervals, and separate the second source and drain layer into a plurality of second source and drain regions arranged at intervals. The active pillar includes the first source and drain regions, the channel regions, and the second source and drain regions.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming a plurality of second grooves penetrating the stacked layer along the first direction and spaced apart along the third direction, the method further includes the following steps: forming a gate dielectric layer covering the channel region in the active pillar; A plurality of second conductive lines extending along the second direction and arranged at intervals along the third direction are formed, wherein the second conductive lines continuously cover the gate dielectric layer in the plurality of active pillars arranged at intervals along the second direction.

9. The method for forming a semiconductor structure according to claim 8, wherein: The specific steps of forming a gate dielectric layer covering the channel region in the active pillar include: forming a second filling layer that completely fills the second trench; Etching back a portion of the second filling layer to expose the channel region, with the top surface of the remaining second filling layer being flush with the top surface of the first source and drain region; The gate dielectric layer is formed along the second trench, covering the channel region and located above the second filling layer.

10. A semiconductor structure, wherein the semiconductor structure is prepared by the forming method according to any one of claims 1 to 9, wherein: include: substrate; A stacked structure is located on the top surface of the substrate, the stacked structure includes a conductive epitaxial structure and an active epitaxial structure stacked on the conductive epitaxial structure along a first direction, an epitaxial contact interface is provided between the conductive epitaxial structure and the active epitaxial structure, the conductive epitaxial structure includes a plurality of first conductive lines extending along a third direction and arranged at intervals along a second direction, the active epitaxial structure includes a plurality of active pillars arranged at intervals along the second direction and the third direction, the first direction is perpendicular to the top surface of the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects with the third direction.

11. The semiconductor structure according to claim 10, wherein: The conductive epitaxial structure is made of doped silicon.

12. The semiconductor structure according to claim 10, wherein: The active epitaxial structure comprises: a first source / drain layer stacked on the conductive epitaxial structure along the first direction, wherein an epitaxial contact interface is formed between the first source / drain layer and the conductive epitaxial structure; a channel layer, stacked on the first source and drain layer along the first direction, with an epitaxial contact interface between the channel layer and the first source and drain layer; A second source-drain layer is stacked on the channel layer along the first direction, and an epitaxial contact interface is formed between the second source-drain layer and the channel layer.

13. The semiconductor structure according to claim 12, wherein: The material of the first source / drain layer and the material of the second source / drain layer are both silicon materials doped with first type ions; The material of the channel layer is a silicon material doped with first type ions or second type ions, and the conductivity types of the first type ions and the second type ions are opposite.

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