Semiconductor memory device

Abstract

There is provided a semiconductor memory device having improved integration and electrical characteristics, including: a bit line extending in a first direction on a substrate; a channel structure on the bit line and including a first vertical portion extending in the second direction and a second vertical portion spaced apart from the first vertical portion in the first direction and extending in the second direction; a back gate electrode on the bit line on at least one side of the channel structure and extending in a second direction; a back gate insulating film between the back gate electrode and the channel structure; a back gate cover film on the back gate electrode and the back gate insulating film; a first word line between the first vertical portion and the second vertical portion and extending in the second direction; a second word line between the first vertical portion and the second vertical portion, extending in the second direction and spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor connected to the first vertical portion and the second vertical portion on the first vertical portion and the second vertical portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0002] There is a need to increase the integration of semiconductor memory devices to meet the excellent performance and low price required by consumers. In the case of semiconductor memory devices, since the integration is an important factor determining the price of the product, it is particularly necessary to increase the integration.

[0003] In the case of a two-dimensional or planar semiconductor memory device, the integration level is mainly determined by the area occupied by the unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required to miniaturize the pattern, the integration level of two-dimensional semiconductor memory devices is increasing, but is still limited. Therefore, a semiconductor memory device including a vertical channel transistor having a channel extending in a vertical direction is proposed. Summary of the invention

[0004] Aspects of the present invention provide a semiconductor memory device having improved integration and electrical characteristics.

[0005] However, aspects of the present invention are not limited to the aspects set forth herein. The above and other aspects of the present invention will become more apparent to those skilled in the art to which the present invention pertains by referring to the detailed description of the present invention given below.

[0006] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a bit line extending in a first direction on a substrate; a channel structure on the bit line, the channel structure comprising a first vertical portion extending in a second direction and a second vertical portion spaced apart from the first vertical portion in the first direction and extending in the second direction; a back gate electrode on at least one side of the channel structure on the bit line and extending in the second direction; a back gate insulating film between the back gate electrode and the channel structure; a back gate covering film on the back gate electrode and the back gate insulating film; a first word line between the first vertical portion and the second vertical portion and extending in the second direction; a second word line between the first vertical portion and the second vertical portion, extending in the second direction, and spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor connected to the first vertical portion and the second vertical portion on the first vertical portion and the second vertical portion.

[0007] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a bit line extending in a first direction on a substrate; a back gate structure defining a channel groove exposing the bit line on the substrate and extending in a second direction intersecting the first direction; an etch stop film between the back gate structure and the bit line; a channel structure extending along a lower surface and sidewalls of the channel groove and comprising a first channel pattern and a second channel pattern spaced apart from the first channel pattern in the first direction; a first word line and a second word line spaced apart from each other in the first direction on the channel structure and extending in the second direction; a gate insulating film between the first channel pattern and the first word line and between the second channel pattern and the second word line; and a first capacitor and a second capacitor connected to the first channel pattern and the second channel pattern on the first channel pattern and the second channel pattern, the back gate structure comprising a back gate electrode and a back gate insulating film between the back gate electrode and the channel structure, based on the upper surface of the bit line, a height up to the upper surface of the back gate structure is equal to or less than a height up to the upper surface of the first word line.

[0008] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a bit line extending in a first direction on a substrate; a channel structure on the bit line and including a first vertical portion extending in a second direction and a second vertical portion spaced apart from the first vertical portion in the first direction and extending in the second direction; a back gate structure on the bit line on at least one side of the channel structure and including a back gate electrode extending in the second direction and a back gate insulating film between the back gate electrode and the channel structure; an etch stop film between the bit line and the back gate structure; a back gate covering film on the back gate electrode and the back gate insulating film; a first word line between the first vertical portion and the second vertical portion and extending in the second direction; a second word line between the first vertical portion and the second vertical portion, extending in the second direction and spaced apart from the first word line in the first direction; a gate insulating film between the first vertical portion and the first word line and between the second vertical portion and the second word line; and a first capacitor and a second capacitor connected to the first vertical portion and the second vertical portion on the first vertical portion and the second vertical portion, based on the upper surface of the bit line, until the height of the upper surface of the back gate structure is equal to or less than the height until the upper surface of the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 are layout diagrams for explaining a semiconductor memory device according to some example embodiments.

[0011] Figure 2 is along Figure 1Cross-sectional view taken along lines AA and BB.

[0012] Figure 3 is along Figure 1 Cross-sectional view taken at CC and DD.

[0013] Figure 4 yes Figure 2 A magnified view of part Q.

[0014] Figure 5 yes Figure 2 An enlarged view of part P.

[0015] Figures 6 to 10 yes Figure 2 An enlarged view of part P.

[0016] Fig.11 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0017] Figures 12 to 15 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0018] Figures 16 to 18 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0019] Figures 19 to 22 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0020] Figures 23 to 38 are diagrams for explaining a method for manufacturing a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0021] Figure 1 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Figure 2 is along Figure 1 Cross-sectional view taken along lines AA and BB. Figure 3 is along Figure 1 Cross-sectional view taken at CC and DD. Figure 4 yes Figure 2 A magnified view of part Q. Figure 5 yes Figure 2 An enlarged view of part P. Figures 6 to 10 yes Figure 2 An enlarged view of part P.

[0022] A semiconductor memory device according to some example embodiments of the present invention may include a memory cell including a vertical channel transistor (VCT).

[0023] Reference Figures 1 to 10, a semiconductor memory device according to some example embodiments may include a peripheral gate structure PG, a bit line BL, word lines WL1 and WL2 , a channel structure AP_ST, a back gate structure 175ST, and a data storage pattern DSP.

[0024] The substrate 100 may be a silicon substrate, or may include other materials such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0025] The peripheral gate structure PG may be disposed on the substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG may be disposed above the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG is disposed in the cell array region of the substrate 100, and the remaining portion of the peripheral gate structure PG may be disposed in the peripheral circuit region of the substrate 100.

[0026] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. However, example embodiments are not limited thereto, and types of transistors disposed in the cell array region and the peripheral circuit region may vary depending on the design and / or purpose of the semiconductor memory device.

[0027] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride.

[0028] The peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 each include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material (2D material), a metal, and a metal alloy. Although the peripheral gate structure PG is shown as including a plurality of conductive patterns, example embodiments are not limited thereto.

[0029] In a semiconductor device according to some example embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, and may include, for example, but not limited to, graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2) and tungsten disulfide (WS 2 That is, since the above-mentioned 2D materials are listed only as examples, the 2D materials that can be included in the semiconductor memory device of the present invention are not limited to the above-mentioned materials.

[0030] The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 are disposed on the substrate 100. The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 may each be made of an insulating material.

[0031] The first peripheral wiring line 241a and the peripheral contact plug 241b may be disposed inside the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. Although the first peripheral wiring line 241a and the peripheral contact plug 241b are shown as films different from each other, example embodiments are not limited thereto. The boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b may not be distinguished, that is, the first peripheral wiring line 241a and the peripheral contact plug 241b may be integral. The first peripheral wiring line 241a and the peripheral contact plug 241b each include a conductive material.

[0032] The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 may be disposed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 may each be made of an insulating material.

[0033] The second peripheral wiring line 243 and the peripheral via plug 242 may be disposed on the first peripheral wiring line 241 a. The peripheral via plug 242 may be disposed in the first peripheral upper insulating film 261. The second peripheral wiring line 243 may be disposed in the second peripheral upper insulating film 262.

[0034] The second peripheral wiring line 243 and the peripheral via plug 242 can be connected to the first peripheral wiring line 241a. The peripheral via plug 242 can connect the first peripheral wiring line 241a and the second peripheral wiring line 243. The second peripheral wiring line 243 and the peripheral via plug 242 each include a conductive material. Although the second peripheral wiring line 243 and the peripheral via plug 242 are shown as different films from each other, example embodiments are not limited thereto. The boundary between the second peripheral wiring line 243 and the peripheral via plug 242 may not be distinguished, that is, the second peripheral wiring line 243 and the peripheral via plug 242 may be integrated.

[0035] The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may be sequentially disposed on the second peripheral wiring line 243. The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may each be made of an insulating material.

[0036] The fourth peripheral upper insulating film 264 may be made of an insulating material different from the insulating materials of the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265. For example, the fourth peripheral upper insulating film 264 may be made of an oxide-based insulating material, and the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265 may be made of a nitride-based insulating material, but example embodiments are not limited thereto.

[0037] The cell connection plug 244 may be disposed in the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265. The cell connection plug 244 may be connected to the second peripheral wiring line 243. The cell connection plug 244 includes a conductive material. In some example embodiments, the cell connection plug 244 may be disposed in a peripheral upper insulating film made of a single layer, which is not shown.

[0038] The bit line BL is disposed on the peripheral gate structure PG. In some example embodiments, the bit line BL may be disposed on the fifth peripheral upper insulating film 265. For example, the bit line BL may contact the fifth peripheral upper insulating film 265.

[0039] The bit lines BL may extend long in the second direction D2. Adjacent bit lines BL may be spaced apart in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.

[0040] Although not shown, each bit line BL may extend from the cell array region to the peripheral circuit region. An end portion of each bit line BL may be disposed on the peripheral circuit region of the substrate 100.

[0041] Each bit line BL may be disposed on the cell connection plug 244. Each bit line BL may be connected to the cell connection plug 244. Each bit line BL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and a metal alloy. Although each bit line BL is illustrated as a single film, example embodiments are not limited thereto.

[0042] The cell lower insulating film 171 may be disposed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 is disposed between the bit lines BL spaced apart in the first direction D1. The cell lower insulating film 171 may be made of an insulating material.

[0043] The etch stop film 173 may be disposed between the back gate structure 175ST and the cell lower insulating film 171 , which will be described later. The etch stop film 173 may be disposed between the back gate structure 175ST and the bit line BL. The etch stop film 173 may include a material having an etch selectivity with respect to the back gate electrode 175 .

[0044] The sidewall of the etch stop film 173 may also be in contact with the channel structure AP_ST, which will be described below. The back gate structure 175ST may not be disposed between the etch stop film 173 and the channel structure AP_ST.

[0045] The back gate structure 175ST may be disposed on the bit line BL and the cell lower insulating film 171. The back gate structure 175ST may be disposed on the etching stop film 173. The back gate structure 175ST may include a plurality of channel trenches CH_T. Each channel trench CH_T may extend long in the first direction D1. Adjacent channel trenches CH_T may be spaced apart in the second direction D2.

[0046] Each channel trench CH_T crosses the bit line BL. One channel trench CH_T may expose a plurality of bit lines BL adjacent in the first direction D1.

[0047] The lower surface of each channel trench CH_T may be defined by the bit line BL and the cell lower insulating film 171. The sidewall of each channel trench CH_T may be defined by the etch stop film 173, the back gate structure 175ST, and the back gate capping film 174. At least a portion of the sidewall of the channel trench CH_T may be a sidewall of the back gate insulating film 176. If the etch stop film 173 is not provided, the sidewall of each channel trench CH_T may be defined by the back gate structure 175ST and the back gate capping film 174.

[0048] The back gate structure 175ST may include a back gate electrode 175 and a back gate insulating film 176 .

[0049] The back gate electrode 175 may be disposed on the etch stop film 173. The back gate electrode 175 may be in contact with an upper surface of the etch stop film 173. The back gate electrode 175 may extend in the third direction D3.

[0050] As an example, the back gate electrode 175 may include polysilicon containing impurities. The impurities may include, for example, at least one of N-type and P-type impurities. As another example, the back gate electrode 175 may include a conductive metal. However, example embodiments are not limited thereto.

[0051] The back gate insulating film 176 may be disposed on the upper surface of the etch stop film 173 and the sidewalls of the back gate electrode 175. The back gate insulating film 176 may extend along the sidewalls of the back gate electrode 175. The back gate insulating film 176 may be in contact with the upper surface of the etch stop film 173. One sidewall of the back gate insulating film 176 may be disposed on the back gate electrode 175. The other sidewall of the back gate insulating film 176 may be disposed on the channel structure AP_ST.

[0052] The back gate electrode 175 and the back gate insulating film 176 may completely cover the upper surface of the etch stop film 173 .

[0053] The back gate insulating film 176 may include an insulating material. As an example, if the back gate electrode 175 includes polysilicon, the back gate insulating film 176 may include silicon oxide. As another example, if the back gate electrode 175 includes a conductive metal, the back gate insulating film 176 may include an oxide of the metal included in the back gate electrode 175.

[0054] The back gate structure 175ST may have a first height H1 up to the upper surface 175ST_US of the back gate structure 175ST based on the upper surface BL_US of the bit line BL. The upper surface of the back gate electrode 175 and the upper surface of the back gate insulating film 176 may be disposed on the same plane. In other words, the height up to the upper surface of the back gate electrode 175 and the height up to the upper surface of the back gate insulating film 176 may be equal to the first height H1 based on the upper surface BL_US of the bit line BL.

[0055] The back gate capping film 174 may be disposed on the back gate structure 175ST. The back gate capping film 174 may extend along the upper surface 175ST_US of the back gate structure 175ST. The back gate capping film 174 may cover the upper surface of the back gate electrode 175 and the upper surface of the back gate insulating film 176.

[0056] In some example embodiments, a portion of the back gate capping film 174 may overlap a portion of a first vertical portion AP_STV1 of a channel structure AP_ST to be described later in the first direction D1. However, example embodiments are not limited thereto.

[0057] The back gate capping film 174 may include an insulating material. The back gate capping film 174 may include, for example, a silicon nitride-based insulating material. However, example embodiments are not limited thereto.

[0058] The channel structure AP_ST may be disposed on each bit line BL. A plurality of channel structures AP_ST may be connected to one bit line BL. The plurality of channel structures AP_ST disposed on one bit line BL are spaced apart in the second direction D2.

[0059] The channel structure AP_ST may be disposed in a channel trench CH_T extending in the first direction D1. A plurality of channel structures AP_ST may be disposed in one channel trench CH_T. The plurality of channel structures AP_ST disposed in the channel trench CH_T are spaced apart in the first direction D1.

[0060] For example, the channel structures AP_ST may be two-dimensionally arranged along first and second directions D1 and D2 crossing each other.

[0061] The channel structure AP_ST may extend along the sidewall and the lower surface of the channel trench CH_T. In a cross section taken along the second direction D2, the channel structure AP_ST may have a 'U' shape.

[0062] The channel structure AP_ST may include a horizontal portion AP_STH, a first vertical portion AP_STV1, and a second vertical portion AP_STV2. The first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST may protrude from the horizontal portion AP_STH of the channel structure AP_ST in the third direction D3.

[0063] The horizontal portion AP_STH of the channel structure AP_ST may extend along the lower surface of the channel trench CH_T. In a cross section taken along the second direction D2, the horizontal portion AP_STH of the channel structure AP_ST may extend along the upper surface of the bit line BL. The horizontal portion AP_STH of the channel structure AP_ST is connected to the bit line BL. For example, the horizontal portion AP_STH of the channel structure AP_ST may contact the upper surface BL_US of the bit line BL.

[0064] The first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST may extend along the sidewalls of the channel trench CH_T. In a cross section taken along the second direction D2, the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST may each extend along the sidewalls 175ST_SW of the back gate structure 175ST.

[0065] The channel structure AP_ST may also include an oxide semiconductor material. The channel structure AP_ST may include, for example, a metal oxide. As an example, the channel structure AP_ST may be an amorphous metal oxide film. As another example, the channel structure AP_ST may be a polycrystalline metal oxide film. As yet another example, the channel structure AP_ST may be in a state where an amorphous metal oxide film and a polycrystalline metal oxide film are combined. As another example, the channel structure AP_ST may be a CAAC (c-axis aligned crystallization) metal oxide film.

[0066] The channel structure AP_ST may include, for example but not limited to, at least one of the following: indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr -Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, and In-Hf-Al-Zn-based oxide.

[0067] Here, In-Ga-Zn-based oxide refers to an oxide with In, Ga and Zn as main components, but does not refer to the singular ratio of In, Ga and Zn. That is, taking IGZO (indium gallium zinc oxide) as an example, the channel structure AP_ST may include IGZO (indium gallium zinc oxide, InxGayZnzO). IGZO (In:Ga:Zn=1:1:1) containing the same ratio of indium, gallium and zinc may be an In-Ga-Zn-based oxide. Ga-rich IGZO may have a higher gallium ratio (In:Ga:Zn=1:1:1) than IGZO and a lower indium ratio than IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO may also be an In-Ga-Zn-based oxide. In-rich IGZO may also have a higher indium ratio than IGZO (In:Ga:Zn=1:1:1) and a lower gallium ratio than IGZO (In:Ga:Zn=1:1:1). In-rich IGZO may also be an In-Ga-Zn-based oxide.

[0068] Although the above description has been made using IGZO, the present invention is not limited thereto. Needless to say, the above description can be applied when the channel structures AP_ST each include ternary or more metal oxides. In addition, when the channel structure AP_ST includes an In-Ga-Zn-based oxide, the channel structure AP_ST may further include doped metal elements other than In, Ga, and Zn.

[0069] The channel structure AP_ST may include a first channel pattern AP1, a second channel pattern AP2, and a connection channel pattern AP_CP. The connection channel pattern AP_CP connects the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 and the second channel pattern AP2 are spaced apart in the second direction D2.

[0070] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP are disposed on the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 are connected to the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 may contact an upper surface of the bit line BL.

[0071] The first channel pattern AP1 may include a portion of the horizontal portion AP_STH of the channel structure AP_ST and a first vertical portion AP_STV1 of the channel structure. A portion of the horizontal portion AP_STH of the channel structure AP_ST may be a horizontal portion of the first channel pattern AP1. The first vertical portion AP_STV1 of the channel structure AP_ST may be a vertical portion of the first channel pattern AP1.

[0072] The second channel pattern AP2 may include another portion of the horizontal portion AP_STH of the channel structure AP_ST and a second vertical portion AP_STV2 of the channel structure AP_ST. Another portion of the horizontal portion AP_STH of the channel structure AP_ST may be a horizontal portion of the second channel pattern AP2. The second vertical portion AP_STV2 of the channel structure AP_ST may be a vertical portion of the second channel pattern AP2.

[0073] The connection channel pattern AP_CP includes the remaining portion of the horizontal portion AP_STH of the channel structure AP_ST.

[0074] The horizontal portion AP_STH of the channel structure AP_ST may have a fourth height H4. Here, the fourth height H4 may be the thickness of the horizontal portion AP_STH of the channel structure AP_ST in the third direction D3. The etching stop film 173 may have a fifth height H5. Here, the fifth height H5 may be the thickness of the etching stop film 173 in the third direction D3. In other words, the fifth height H5 may be a height from the upper surface BL_US of the bit line BL to the upper surface of the etching stop film 173. In some example embodiments, the fifth height H5 may be greater than the fourth height H4. However, example embodiments are not limited thereto. For example, the fifth height H5 may be the same as the fourth height H4.

[0075] The uppermost portion of the vertical portion AP_STV1 and the uppermost portion of the vertical portion AP_STV2 of the channel structure AP_ST may have a second height H2 based on the upper surface BL_US of the bit line BL. The uppermost portions of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST may be disposed to be higher than the upper surface 175ST_US of the back gate structure 175ST. That is, the first height H1 of the back gate structure 175ST may be less than the second height H2 of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST.

[0076] In a semiconductor memory device according to some example embodiments, as Figure 6 As shown, the first height H1 of the back gate structure 175ST may be the same as the second height H2 of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST.

[0077] In a semiconductor memory device according to some example embodiments, a portion of the back gate insulating film 176 may protrude toward the channel structure AP_ST, as shown in FIG. Figure 8 shown.

[0078] The sidewall of the back gate capping film 174 and the sidewall of the back gate insulating film 176 may not be arranged on the same line. For example, the back gate insulating film 176 may protrude beyond the sidewall of the back gate capping film 174 in the second direction D2. The sidewall of the etching stop film 173 and the sidewall of the back gate insulating film 176 may not be arranged on the same line. For example, the back gate insulating film 176 may protrude beyond the sidewall of the etching stop film 173 in the second direction D2.

[0079] and Figure 5 Differently, each of the first vertical portion AP_STV1 of the channel structure AP_ST and the second vertical portion AP_STV2 of the channel structure AP_ST may include a recessed portion. The back gate insulating film 176 may fill the recessed portion.

[0080] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may be distinguished based on the first word line WL1 and the second word line WL2, which will be described later. Figure 4 , the first word line WL1 will be described as an example. The first word line WL1 may include an inner sidewall facing the sidewall 175ST_SW of the back gate structure 175ST and an outer sidewall opposite to the inner sidewall in the second direction D2. The boundary between the first channel pattern AP1 and the connection channel pattern AP_CP may be an extension line of the outer sidewall of the first word line WL1 extending in the third direction D3.

[0081] The first word line WL1 and the second word line WL2 may be disposed on the channel structure AP_ST. The first word line WL1 and the second word line WL2 may be disposed in the channel trench CH_T.

[0082] Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2. The first word line WL1 is spaced apart from the second word line WL2 in the second direction D2.

[0083] The first word line WL1 and the second word line WL2 are spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 cross the bit line BL.

[0084] The first word line WL1 and the second word line WL2 are disposed on the horizontal portion AP_STH of the channel structure. The first word line WL1 and the second word line WL2 are disposed between the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST.

[0085] The first word line WL1 is disposed on the first channel pattern AP1. The second word line WL2 is disposed on the second channel pattern AP2. The first word line WL1 and the second word line WL2 are disposed between the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 is closer to the first word line WL1 than to the second word line WL2. The second channel pattern AP2 is closer to the second word line WL2 than to the first word line WL1.

[0086] Each of the first word line WL1 and the second word line WL2 may have a width in the second direction D2. The width of the first word line WL1 in a portion overlapping the channel structure AP_ST along the third direction D3 may be different from the width of the first word line WL1 in a portion not overlapping the channel structure AP_ST. The width of the second word line WL2 in a portion overlapping the channel structure AP_ST along the third direction D3 may be different from the width of the second word line WL2 in a portion not overlapping the channel structure AP_ST.

[0087] For example, each of the first word line WL1 and the second word line WL2 may include a first portion WLa of the word line and a second portion WLb of the word line. The width of the first portion WLa of the word line in the second direction D2 may be smaller than the width of the second portion WLb of the word line in the second direction D2. As an example, the first portion WLa of the word line may be disposed on the channel structure AP_ST. The first portion WLa of the word line may be disposed on the first channel pattern AP1 and the second channel pattern AP2.

[0088] Each of the first word line WL1 and the second word line WL2 may include first portions WLa of the word line and second portions WLb of the word line alternately disposed along the first direction D1. Each channel structure AP_ST may be disposed between second portions WLb of the word line adjacent in the first direction D1. In the first word line WL1, each first active pattern AP1 may be disposed between second portions WLb of the word line adjacent in the first direction D1. In the second word line WL2, each second active pattern AP2 may be disposed between second portions WLb of the word line adjacent in the first direction D1.

[0089] The channel structure AP_ST is not disposed under the second portion WLb of the word line. A height of the first portion WLa of the word line is less than a height of the second portion WLb of the word line.

[0090] The first word line WL1 and the second word line WL2 include a conductive material, and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbon nitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.

[0091] The first word line WL1 and the second word line WL2 may include an upper surface WL_US and a lower surface opposite to each other in the third direction D3. The lower surfaces of the first word line WL1 and the second word line WL2 face the bit line BL.

[0092] exist Figure 5 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be plane. Fig. 9 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be convexly rounded. Fig.10 , upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be concavely rounded.

[0093] Based on the upper surface BL_US of the bit line BL, the upper surface WL_US of the first word line WL1 and the second word line WL2 may be higher than the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST. The uppermost portions of the channel patterns AP1 and AP2 may be the uppermost portions of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST. The first word line WL1 and the second word line WL2 may have a third height H3 from the upper surface BL_US of the bit line BL to the upper surface WL_US of the first word line WL1 and the second word line WL2. The second height H2 up to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST may be less than the third height H3 up to the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0094] In a semiconductor memory device according to some example embodiments, a second height H2 up to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST may be equal to a third height H3 up to the upper surface WL_US of the first and second word lines WL1 and WL2. In a semiconductor memory device according to some example embodiments, a first height H1 up to the upper surface 175ST_US of the back gate structure 175ST may be equal to or less than a third height H3 up to the upper surface WL_US of the first and second word lines WL1 and WL2.

[0095] The gate insulating film GOX may be disposed between the first word line WL1 and the channel structure AP_ST and between the second word line WL2 and the channel structure AP_ST. The gate insulating film GOX may be disposed between the first word line WL1 and the first active pattern AP1 and between the second word line WL2 and the second active pattern AP2. The gate insulating film GOX may extend in the first direction D1 together with the first word line WL1 and the second word line WL2.

[0096] The gate insulating film GOX may extend along the first vertical portion AP_STV1 of the channel structure. The gate insulating film GOX may extend along the second vertical portion AP_STV2 of the channel structure. In the semiconductor memory device according to some example embodiments, the gate insulating film GOX may not be provided on the horizontal portion AP_STH of the channel structure AP_ST that does not overlap with the first word line WL1 and the second word line WL2 in the third direction D3. From the perspective of the cross-sectional view, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0097] The gate insulating film GOX may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than that of the silicon oxide film, or a combination thereof.

[0098] A portion of the gate insulating film GOX may protrude beyond the upper surfaces WL_US of the first and second word lines WL1 and WL2 in the third direction D3. A portion of the gate insulating film GOX may protrude beyond the uppermost portions of the vertical portions AP_STV1 and AP_STV2 of the channel structures in the third direction D3.

[0099] The height from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film may be greater than a second height H2 from the upper surface BL_US of the bit line BL to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST. The height from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film may be greater than a third height H3 from the upper surface BL_US of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0100] The gate separation pattern GSS may be disposed on the bit line BL and the cell lower insulating film 171. The gate separation pattern GSS may be disposed inside the channel trench CH_T. The gate separation pattern GSS may be disposed on the channel structure AP_ST, the first word line WL1, and the second word line WL2.

[0101] In a semiconductor memory device according to some example embodiments, a gate separation pattern GSS may be in contact with a channel structure AP_ST. The gate separation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate separation pattern GSS may be in contact with a horizontal portion AP_STH of the channel structure. The gate separation pattern GSS may be spaced apart from a bit line BL in a third direction D3.

[0102] The gate separation pattern GSS may be disposed between the first and second word lines WL1 and WL2 adjacent in the second direction D2. The first and second word lines WL1 and WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend in the first direction D1 between the first and second word lines WL1 and WL2.

[0103] The first word line WL1 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The second word line WL2 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The first word line WL1 may be disposed between the gate separation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second channel pattern AP2.

[0104] The gate separation pattern GSS may include a horizontal portion and a protruding portion. The protruding portion of the gate separation pattern GSS may protrude from the horizontal portion of the gate separation pattern GSS toward the bit line BL in the third direction D3. The protruding portion of the gate separation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate separation pattern GSS. The horizontal portion of the gate separation pattern GSS may be disposed on the upper surface WL_US of the first word line WL1 and the second word line WL2. In a cross-sectional view, the gate separation pattern GSS may have a "T" shape.

[0105] The gate separation pattern GSS may include a gate separation pad 151, a gate separation filling film 153, and a gate separation capping film 155. The gate separation pad 151 may extend along the upper surface WL_US of the first word line WL1 and the second word line WL2 and the outer sidewalls of the first word line WL1 and the second word line WL2. The gate separation pad 151 may extend along the horizontal portion AP_STH of the channel structure. The gate separation pad 151 may be in contact with the connection channel pattern AP_CP. The gate separation pad 151 may extend along the gate insulation film GOX protruding beyond the upper surface WL_US of the first word line WL1 and the second word line WL2. Unlike the example shown, the gate separation pad 151 may not extend along the gate insulation film GOX protruding beyond the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0106] The gate separation filling film 153 may be disposed on the gate separation liner 151. The gate separation capping film 155 may be disposed on the gate separation filling film 153. The gate separation liner 151, the gate separation filling film 153, and the gate separation capping film 155 may each be made of an insulating material. Unlike the illustrated example, the gate separation pattern GSS may be a single film.

[0107] Unlike the illustrated example, the upper surface GSS_US of the gate separation pattern may be disposed at the same height as the upper surface 175ST_US of the back gate structure 175ST based on the upper surface BL_US of the bit line BL, but is not limited thereto.

[0108] A height from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern may be greater than a second height H2 from the upper surface BL_US of the bit line BL to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST. A height from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern GSS may be greater than a third height H3 from the upper surface BL_US of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0109] A height from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern may be the same as a height from the upper surface BL_US of the bit line BL to the upper surface 174_US of the back gate cover film 174 .

[0110] Although the height from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern GSS is illustrated as being the same as the height from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film GOX, example embodiments are not limited thereto.

[0111] The landing pad LP may be disposed on the channel structure AP_ST. The landing pad LP is connected to the first vertical portion AP_STV1 of the channel structure and the second vertical portion AP_STV2 of the channel structure.

[0112] The landing pad LP may be disposed on the first and second channel patterns AP1 and AP2. The landing pad LP is connected to the first and second channel patterns AP1 and AP2.

[0113] From a planar perspective, the landing pad LP may have various shapes such as a circular shape, an oval shape, a rectangular shape, a square shape, a diamond shape, and / or a hexagonal shape.

[0114] The landing pad LP may include a horizontal portion LP_H and a protruding portion LP_P. The horizontal portion LP_H of the landing pad may be disposed on the upper surface of the back gate cover film 174 and the upper surface GSS_US of the gate separation pattern. The protruding portion LP_P of the landing pad may protrude from the horizontal portion LP_H of the landing pad toward the bit line BL in the third direction D3.

[0115] Based on the upper surface BL_US of the bit line BL, the lowermost portion of the landing pad LP may be lower than the upper surface GSS_US of the gate separation pattern. In other words, the protruding portion LP_P of the landing pad is disposed between the back gate cover film 174 and the gate separation pattern GSS. The height from the upper surface BL_US of the bit line BL to the lowermost portion of the landing pad LP may be less than the height from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film.

[0116] The pad separation insulating pattern 235 may be disposed between the landing pads LP. From a planar perspective, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the landing pad LP may be coplanar with the upper surface of the pad separation insulating pattern 235, but is not limited thereto.

[0117] The landing pad LP includes a conductive material. The landing pad LP may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, a metal, and a metal alloy.

[0118] Data storage patterns DSP may be disposed on the landing pads LP, respectively. The data storage pattern DSP may be connected to the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST. The data storage pattern DSP may be connected to each of the first channel pattern AP1 and the second channel pattern AP2.

[0119] The data storage patterns DSP may be arranged in a matrix form along the first direction D1 and the second direction D2. Figure 1 The data storage pattern DSP may completely or partially overlap the landing pad LP in the third direction D3. The data storage pattern DSP may contact all or part of the upper surface of the landing pad LP.

[0120] As an example, the data storage pattern DSP may be a capacitor. The first channel pattern AP1 may be connected to the first capacitor. The second channel pattern AP2 may be connected to the second capacitor.

[0121] The data storage pattern DSP may include a capacitor dielectric film 253 interposed between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 may be in contact with the landing pad LP. From a planar perspective, the storage electrode 251 may have various shapes such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, and a hexagonal shape. The data storage pattern DSP may completely or partially overlap the landing pad LP. The data storage pattern DSP may be in contact with all or part of the upper surface of the landing pad LP. The storage electrode 251 may penetrate the cell upper etch stop film 247. The cell upper etch stop film 247 may be made of an insulating material.

[0122] Differently, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material, in which a crystalline state changes according to the amount of current.

[0123] Fig.11 is a diagram for explaining a semiconductor memory device according to some example embodiments. Figures 1 to 10 For reference, Fig.11 yes Figure 2 An enlarged view of part P.

[0124] Reference Fig.11 , in the semiconductor memory device according to some example embodiments, the gate separation pattern GSS does not contact the channel structure AP_ST.

[0125] A portion of the gate insulating film GOX may be disposed between the gate separation pattern GSS and the channel structure AP_ST. From a cross-sectional view perspective, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be connected to the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0126] Figures 12 to 15 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 Explain the different points.

[0127] For reference, Fig.12 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Fig.13 is along Fig.12 Cross-sectional view taken along lines AA and BB. Fig.14 is along Fig.12Cross-sectional view taken at CC and DD. Fig.15 yes Fig.13 An enlarged view of part P.

[0128] Reference Figures 12 to 15 , in the semiconductor memory device according to some example embodiments, the first channel pattern AP1 and the second channel pattern AP2 spaced apart in the second direction D2 are not connected to each other within the channel trench CH_T.

[0129] The first channel pattern AP1 may include a horizontal portion AP1_H extending along an upper surface of the bit line BL and a vertical portion AP1_V extending along a sidewall of the back gate structure 175ST. The vertical portion AP1_V of the first channel pattern may protrude from the horizontal portion AP1_H of the first channel pattern in the third direction D3.

[0130] The second channel pattern AP2 may include a horizontal portion AP2_H extending along an upper surface of the bit line BL and a vertical portion AP2_V extending along a sidewall of the back gate structure 175ST. The vertical portion AP2_V of the second channel pattern may protrude from the horizontal portion AP2_H of the second channel pattern in the third direction D3.

[0131] The gate separation pattern GSS may contact the upper surface BL_US of the bit line BL. The horizontal portion AP2_H of the second channel pattern and the horizontal portion AP1_H of the first channel pattern may be spatially separated by the gate separation pattern GSS. The gate separation liner 151 may contact the upper surface BL_US of the bit line BL.

[0132] Figures 16 to 18 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 Explain the different points.

[0133] For reference, Fig.16 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Fig.17 is along Fig.16 Cross-sectional view taken along lines AA and BB. Fig.18 is along Fig.16 Cross-sectional view taken at CC and DD.

[0134] Reference Figures 16 to 18 , the semiconductor memory device according to some example embodiments may further include a shielding structure 180 .

[0135] The shielding structure 180 may extend in the second direction D2. The shielding structure 180 may be spaced apart from the bit lines BL in the first direction D1. The shielding structure 180 may be alternately arranged with the bit lines BL in the first direction D1.

[0136] The shielding structure 180 may be disposed inside the cell lower insulating film 171. An upper surface of the shielding structure 180 may be lower than an upper surface BL_US of the bit line BL.

[0137] As an example, the shielding structure 180 may include a conductive material.As another example, the shielding structure 180 may include a conductive material and may include an air gap or void within the conductive material.

[0138] Figures 19 to 22 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 Explain the different points.

[0139] Reference Fig.19 In a semiconductor memory device according to some example embodiments, the first channel pattern AP1 and the second channel pattern AP2 may be alternately arranged in a diagonal direction relative to the first direction D1 and the second direction D2. Here, the diagonal direction may be parallel to the upper surface of the substrate 100.

[0140] The channel structure AP_ST may be formed to be twisted in a diagonal direction. From a planar perspective, the first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may each have a parallelogram shape or a diamond shape. The WLb portion of the word line may be twisted to match or substantially match the diagonal direction.

[0141] Reference Fig. 20 , in the semiconductor memory device according to some example embodiments, the landing pads LP and the data storage patterns DSP may be arranged in a zigzag or honeycomb form from a planar perspective.

[0142] Reference Fig.21 , in the semiconductor memory device according to some example embodiments, the data storage pattern DSP may be disposed to be misaligned with the landing pad LP from a planar perspective.

[0143] Each of the data storage patterns DSP may make contact with a portion of the landing pad LP.

[0144] Reference Fig. 22 In a semiconductor memory device according to some example embodiments, each of the landing pads LP disposed on the first and second channel patterns AP1 and AP2 may have a semicircular form or a semi-elliptical form from a planar perspective.

[0145] From a planar perspective, the landing pads LP may be disposed symmetrically to each other.

[0146] Figures 23 to 38 are diagrams for explaining a method for manufacturing a semiconductor memory device according to some example embodiments.

[0147] Reference Figure 23 to Figure 25 , a peripheral gate structure PG may be formed on the substrate 100 .

[0148] A first peripheral wiring line 241 a and a peripheral contact plug 241 b may be formed on the substrate 100 .

[0149] The peripheral upper insulating films 261, 262, 263, 264 and 265 may be sequentially formed on the first peripheral wiring line 241a and the peripheral contact plug 241b. The second peripheral wiring line 243, the peripheral via plug 242 and the cell connection plug 244 may be formed inside the peripheral upper insulating films 261, 262, 263, 264 and 265.

[0150] Then, a bit line BL may be formed on the fifth peripheral upper insulating film 265. The bit line BL may extend long in the second direction D2 on the substrate 100. A cell lower insulating film 171 may be formed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 may expose an upper surface of the bit line BL.

[0151] Reference Fig.26 and Fig. 27 , a pre-etching stopper film 173P, a pre-back gate electrode 175P, and a pre-back gate capping film 174P may be formed on the bit line BL and the cell lower insulating film 171 .

[0152] In some example embodiments, a pre-etch stopper film 173P may be formed on an upper surface BL_US of the bit line BL and an upper surface of the cell lower insulating film 171. The pre-etch stopper film 173P may include a material having an etch selectivity with the pre-back gate electrode 175P.

[0153] The pre-back gate electrode 175P may be formed on an upper surface of the pre-etching stopper film 173P. The pre-back gate capping film 174P may be formed on an upper surface of the pre-back gate electrode 175P.

[0154] Reference Fig.28 and Fig.29 , an etching stopper film 173 , a back gate electrode 175 , and a back gate capping film 174 may be formed on the substrate 100 .

[0155] In some example embodiments, a mask layer may be formed on the pre-back gate cover film 174P. Subsequently, the pre-back gate cover film 174P may be patterned using the mask layer. The mask layer and / or the back gate cover film 174P may be used as an etching mask to form a back gate electrode 175 and an etching stop film 173. Each of the etching stop film 173, the back gate electrode 175, and the back gate cover film 174 may extend in the first direction D1.

[0156] The etch stop film 173 , the back gate electrode 175 , and the back gate capping film 174 may include a plurality of channel trenches CH_T extending in the first direction D1 . The channel trenches CH_T may cross the bit lines BL . The channel trenches CH_T may expose the bit lines BL .

[0157] Reference Fig.30 and Fig.31 , a back gate structure 175ST may be formed on the etch stop film 173 .

[0158] In some example embodiments, the back gate insulating film 176 may be formed on the sidewalls of the back gate electrode 175 by an oxidation process. The back gate insulating film 176 may be formed on both sidewalls of the back gate electrode 175. The formation thickness of the back gate insulating film 176 may vary according to the conditions of the oxidation process. The back gate insulating film 176 may not be formed between the etch stop film 173 and the back gate electrode 175.

[0159] As semiconductor memory devices become smaller, the difficulty of gap filling increases. For example, it may be difficult to deposit a conductive material in a narrow trench. When a back gate insulating film is deposited on the trench and a back gate electrode is deposited, the conductive material may not completely fill the trench. As a result, the reliability of the semiconductor memory device may be reduced.

[0160] In the semiconductor memory device according to some example embodiments, the back gate electrode 175 is formed by etching the pre-back gate electrode 175P. Subsequently, a back gate insulating film 176 is formed on the sidewall of the back gate electrode 175 using an oxidation process. Therefore, the back gate structure 175ST can be uniformly formed on one side of the channel structure AP_ST. As a result, the reliability of the semiconductor memory device can be improved.

[0161] The etch stop film 173 , the back gate structure 175ST, and the back gate capping film 174 may include a plurality of channel trenches CH_T extending in the first direction D1 .

[0162] Reference Fig.32 and Fig.33 , a pre-channel structure AP_P may be formed along the sidewalls and the lower surface of the channel trench CH_T.

[0163] The pre-channel structure AP_P may contact the bit line BL exposed by the channel trench CH_T. The pre-channel structure AP_P is not formed on the upper surface of the back gate capping film 174 .

[0164] Then a sacrificial film 30 may be formed on the pre-channel structure AP_P. The sacrificial film 30 may fill the channel trench CH_T. The sacrificial film 30 may be, but is not limited to, one of an insulating material and a silicon oxide film formed using a SOG (Spin On Glass) technique.

[0165] Reference Fig.34 and Fig.35 , the pre-channel structure AP_P may be patterned to form a channel structure AP_ST extending along the sidewalls and the lower surface of the channel trench CH_T.

[0166] In some example embodiments, a channel separation mask may be formed on the sacrificial layer 30 and the back gate capping film 174. A portion of the sacrificial film 30 may be removed using the channel separation mask. By removing a portion of the sacrificial film 30, a portion of the pre-channel structure AP_P may be exposed.

[0167] A portion of the exposed pre-channel structure AP_P may be removed using an etching process. Thus, a channel structure AP_ST may be formed in the channel trench CH_T.

[0168] The sacrificial film 30 may then be removed in the channel trench CH_T.

[0169] Reference Fig.36 and Fig.37 , a gate insulating film GOX may be formed on the channel structure AP_ST.

[0170] The gate insulating film GOX may be formed along the contour of the channel structure AP_ST. In the portion where the channel structure AP_ST is not formed, the gate insulating film GOX may be formed along the sidewall of the back gate cap film 174 and the sidewall 175ST_SW of the back gate structure 175ST. The gate insulating film GOX may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques, but is not limited thereto.

[0171] Subsequently, a first word line WL1 and a second word line WL2 may be formed on the gate insulating film GOX. The first word line WL1 and the second word line WL2 may be formed along a sidewall of the channel trench CH_T.

[0172] The formation of the first word line WL1 and the second word line WL2 may include an anisotropic etching process of the gate conductive film after depositing the gate conductive film on the gate insulating film GOX.

[0173] When the gate conductive film is subjected to an anisotropic etching process, a portion of the gate insulating film GOX may be etched. Therefore, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST. Unlike the illustrated example, the gate insulating film GOX may be used as an etching stop film when the gate conductive film is subjected to an anisotropic etching process.

[0174] An upper surface of the first word line WL1 and an upper surface of the second word line WL2 may be located at a lower level than an upper surface 174_US of the back gate cap film 174 .

[0175] Reference Fig.37 and Fig.38 , a gate separation pattern GSS may be formed on the first word line WL1 and the second word line WL2. The gate separation pattern GSS may fill the channel trench CH_T.

[0176] In some example embodiments, the gate separation liner 151 may be formed along the outline of the first word line WL1 and the outline of the second word line WL2 . The gate separation liner 151 may also be formed on the upper surface 174_US of the back gate capping film 174 .

[0177] A prefill film may be formed on the gate separation liner 151. The prefill film may also be formed on the upper surface 174_US of the back gate cover film 174. A gate separation filling film 153 may be formed on the gate separation liner 151 by removing a portion of the prefill film.

[0178] A pre-covering film may be formed on the gate separation filling film 153. A pre-covering film may also be formed on the upper surface 174_US of the back gate covering film 174. The gate separation covering film 155 may be formed by removing a portion of the pre-covering film. While the gate separation covering film 155 is formed, the gate separation pad 151 and the pre-covering film formed on the upper surface 174_US of the back gate covering film 174 may be removed.

[0179] A voltage may be applied to the back gate electrode 175 in the semiconductor device according to some example embodiments. The voltage applied to the back gate electrode 175 may change the threshold voltage (Vth) of the first word line WL1 and the second word line WL2. That is, the threshold voltage (Vth) of the semiconductor memory device may be adjusted by adjusting the voltage applied to the back gate electrode 175.

[0180] The oxygen of the channel structure AP_ST may partially disappear in the manufacturing process of the semiconductor memory device. For example, in the heat treatment process, the oxygen of the channel structure AP_ST disappears, and the oxygen composition ratio of the channel structure AP_ST may decrease. In the semiconductor device according to some example embodiments, the back gate insulating film 176 may be in contact with the channel structure AP_ST. The back gate insulating film 176 may provide oxygen to the channel structure AP_ST. As a result, the channel structure AP_ST can compensate for the oxygen loss in the manufacturing process.

[0181] Reference Figure 2 and Figure 3 By removing a portion of the channel structure AP_ST, the uppermost surface of the channel structure AP_ST may become lower than the upper surface 174_US of the back gate cover film 174. A pre-landing pad film may then be formed on the back gate cover film 174, the gate separation pattern GSS, and the channel structure AP_ST. The pre-landing pad film may be patterned to form a landing pad LP on the channel structure AP_ST.

[0182] The data storage pattern DSP may then be formed on the landing pad LP. The data storage pattern DSP may be connected to the channel structure AP_ST and formed on the gate separation pattern GSS.

[0183] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0184] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the inventive concept. Therefore, the exemplary embodiments of the present invention disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

[0185] This application claims the priority of Korean Patent Application No. 10-2023-0089706 filed in the Korean Intellectual Property Office on July 11, 2023, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor storage device, comprising: A bit line extending in a first direction on the substrate; a channel structure on the bit line, the channel structure comprising a first vertical portion extending in a second direction and a second vertical portion spaced apart from the first vertical portion in the first direction and extending in the second direction; a back gate electrode extending on the bit line and in the second direction on at least one side of the channel structure; a back gate insulating film, between the back gate electrode and the channel structure; a back gate covering film on the back gate electrode and the back gate insulating film; a first word line extending between the first vertical portion and the second vertical portion and in the second direction; a second word line extending in the second direction between the first vertical portion and the second vertical portion and spaced apart from the first word line in the first direction; as well as A first capacitor and a second capacitor are connected to the first vertical portion and the second vertical portion on the first vertical portion and the second vertical portion.

2. The semiconductor memory device according to claim 1, in, A height measured from an upper surface of the bit line to an upper surface of the back gate electrode is equal to or smaller than a height to an upper surface of the first vertical portion.

3. The semiconductor memory device according to claim 2, in, The height measured from the upper surface of the bit line to the upper surface of the back gate electrode is smaller than the height to the upper surface of the first word line.

4. The semiconductor memory device according to claim 1, further comprising: An etch stop film between the bit line and the back gate electrode.

5. The semiconductor memory device according to claim 4, The lower surface of the back gate electrode is in contact with the etching stopper film.

6. The semiconductor memory device according to claim 4, wherein The channel structure includes a horizontal portion connecting the first vertical portion and the second vertical portion, and In the second direction, a thickness of the horizontal portion is smaller than a thickness of the etching stopper film.

7. The semiconductor memory device according to claim 1, in, A height up to an upper surface of the first word line measured from an upper surface of the bit line is different from a height up to an upper surface of the first vertical portion.

8. The semiconductor memory device according to claim 1, A portion of the first vertical portion overlaps with the back gate cover film in the first direction.

9. The semiconductor memory device according to claim 1, further comprising: A gate insulating film is between the first word line and the channel structure.

10. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern on the bit line and separating the first word line and the second word line, wherein the channel structure comprises a horizontal portion connecting the first vertical portion and the second vertical portion, and The gate separation pattern contacts the horizontal portion of the channel structure.

11. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern on the bit line and separating the first word line and the second word line, Wherein, measured from the upper surface of the bit line, the height up to the upper surface of the back gate cover film is equal to the height up to the upper surface of the gate separation pattern.

12. A semiconductor storage device comprising: A bit line extending in a first direction on the substrate; a back gate structure defining a channel trench exposing the bit line on the substrate and extending in a second direction intersecting the first direction; an etch stop film between the back gate structure and the bit line; a channel structure extending along a lower surface and sidewalls of the channel trench and comprising a first channel pattern and a second channel pattern spaced apart from the first channel pattern in the first direction; A first word line and a second word line, spaced apart from each other in the first direction on the channel structure, and each extending in the second direction; a gate insulating film between the first channel pattern and the first word line and between the second channel pattern and the second word line; as well as a first capacitor and a second capacitor connected to the first channel pattern and the second channel pattern on the first channel pattern and the second channel pattern, The back gate structure includes a back gate electrode and a back gate insulating film between the back gate electrode and the channel structure, and A height measured from an upper surface of the bit line to an upper surface of the back gate structure is equal to or less than a height to an upper surface of the first word line.

13. The semiconductor memory device according to claim 12, further comprising: A back gate capping film is on the upper surface of the back gate structure.

14. The semiconductor memory device according to claim 12, The back gate electrode is in contact with the etching stopper film.

15. The semiconductor memory device according to claim 12, The back gate electrode includes at least one of polysilicon and conductive metal.

16. The semiconductor memory device according to claim 12, further comprising: a gate separation pattern on the bit line and separating the first word line and the second word line, The gate separation pattern is in contact with the bit line.

17. The semiconductor memory device according to claim 12, The channel structure includes indium gallium zinc oxide.

18. The semiconductor memory device according to claim 12, further comprising: A shielding structure extends in the first direction and is spaced apart from the bit line in a direction perpendicular to the first direction and the second direction.

19. The semiconductor memory device according to claim 12, in, The height measured from the upper surface of the bit line to the upper surface of the first word line is equal to or greater than a height to an upper surface of the first channel pattern.

20. A semiconductor storage device, comprising: A bit line extending in a first direction on the substrate; a channel structure on the bit line and including a first vertical portion extending in a second direction and a second vertical portion spaced apart from the first vertical portion in the first direction and extending in the second direction; a back gate structure on the bit line on at least one side of the channel structure and including a back gate electrode extending in the second direction and a back gate insulating film between the back gate electrode and the channel structure; an etch stop film between the bit line and the back gate structure; a back gate covering film on the back gate electrode and the back gate insulating film; a first word line extending between the first vertical portion and the second vertical portion and in the second direction; a second word line extending in the second direction between the first vertical portion and the second vertical portion and spaced apart from the first word line in the first direction; a gate insulating film between the first vertical portion and the first word line and between the second vertical portion and the second word line; as well as a first capacitor and a second capacitor connected to the first vertical portion and the second vertical portion on the first vertical portion and the second vertical portion, A height measured from an upper surface of the bit line to an upper surface of the back gate structure is equal to or less than a height to an upper surface of the first word line.

Images