Semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a peripheral circuit structure including a peripheral circuit transistor; a bit line on the peripheral circuit structure and extending in a first horizontal direction; a back gate line extending in the second horizontal direction at a vertical height higher than the bit line; word lines extending in the second horizontal direction at a higher vertical height than the bit lines and alternating with the back gate lines; a plurality of vertical channel layers on the bit lines in a matrix form, each of the plurality of vertical channel layers including a first sidewall extending in a vertical direction and facing a corresponding back gate line and a second sidewall opposite the first sidewall and facing a corresponding word line, the part, adjacent to the bit line, of the second side wall is bent; a contact pad on the plurality of vertical channel layers; and a storage node on the contact pad.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a vertical channel transistor and a method of manufacturing the same. Background Art

[0002] Based on the reduction in size of semiconductor devices, the size of dynamic random access memory (DRAM) devices is also reduced. In a DRAM device having a one transistor-one capacitor (1T-1C) structure (in which one capacitor is connected to one transistor), there is a problem that as the device is miniaturized, the leakage current through the channel region increases. In order to reduce the leakage current, a vertical channel transistor including a channel layer extending in a vertical direction has been proposed. Summary of the invention

[0003] One or more embodiments provide a semiconductor device having improved electrical performance.

[0004] One or more embodiments also provide a method of manufacturing a semiconductor device having improved electrical performance.

[0005] According to one aspect of the embodiment, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit transistor; a plurality of bit lines, the plurality of bit lines being located on the peripheral circuit structure and extending along a first horizontal direction; a plurality of back gate lines, the plurality of back gate lines extending along a second horizontal direction at a vertical height higher than that of the plurality of bit lines; a plurality of word lines, the plurality of word lines extending along a second horizontal direction at a vertical height higher than that of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers being located on the plurality of bit lines in a matrix form, each of the plurality of vertical channel layers comprising a first sidewall and a second sidewall, the first sidewall extending along a vertical direction and facing a corresponding back gate line among the plurality of back gate lines, the second sidewall being opposite to the first sidewall and facing a corresponding word line among the plurality of word lines, a portion of the second sidewall adjacent to the bit lines among the plurality of bit lines being in a bent shape; a plurality of contact pads, the plurality of contact pads being located on the plurality of vertical channel layers; and a plurality of storage nodes, the plurality of storage nodes being located on the plurality of contact pads.

[0006] According to another aspect of the embodiment, a semiconductor device is provided, the semiconductor device comprising: a plurality of bit lines, the plurality of bit lines being located on a substrate and extending in a first horizontal direction; a plurality of back gate lines, the plurality of back gate lines extending in a second horizontal direction at a vertical height higher than that of the plurality of bit lines; a plurality of word lines, the plurality of word lines extending in the second horizontal direction at a vertical height higher than that of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, each of the plurality of vertical channel layers comprising a first sidewall, a second sidewall, a first end portion, and a second end portion, the first sidewall of the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, the first sidewall of the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, the second ... first sidewall of the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, the second sidewall of the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, the first sidewall of the plurality of vertical channel layers extending in a vertical direction A side wall extends in a vertical direction and faces a corresponding back gate line among a plurality of back gate lines, a second side wall is opposite to the first side wall and faces a corresponding word line among a plurality of word lines, a first end portion contacts a bit line among a plurality of bit lines, a second end portion is opposite to the first end portion, and the second side wall has a convex curved shape toward a corresponding word line among a plurality of word lines at a position adjacent to the first end portion; a plurality of contact pads, the plurality of contact pads are located on a plurality of vertical channel layers; and a plurality of storage nodes, the plurality of storage nodes are located on the plurality of contact pads, wherein a first width of the first end portion in a first horizontal direction is smaller than a second width of the second end portion in the first horizontal direction.

[0007] According to another aspect of the embodiment, a semiconductor device is provided, the semiconductor device comprising: a peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit transistor; a plurality of bit lines, the plurality of bit lines being located on the peripheral circuit structure and extending along a first horizontal direction; a plurality of back gate lines, the plurality of back gate lines extending along a second horizontal direction at a vertical height higher than a vertical height of the plurality of bit lines; a plurality of word lines, the plurality of word lines extending along the second horizontal direction at a vertical height higher than a vertical height of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers being located on the plurality of bit lines in a matrix form, each vertical channel in the plurality of vertical channel layers The layer includes a first side wall and a second side wall, the first side wall extends in a vertical direction and faces a corresponding back gate line among a plurality of back gate lines, the second side wall is opposite to the first side wall and faces a corresponding word line among a plurality of word lines, and a portion of the second side wall adjacent to the bit line is in a curved shape; a gate insulating layer, the gate insulating layer is located between each vertical channel layer in the plurality of vertical channel layers and the corresponding word line; a spacer, the spacer is located between each vertical channel layer in the plurality of vertical channel layers and the corresponding back gate line; a plurality of contact pads, the plurality of contact pads are located on the plurality of vertical channel layers; and a plurality of storage nodes, the plurality of storage nodes are located on the plurality of contact pads.

[0008] According to another aspect of the embodiment, a method for manufacturing a semiconductor device is provided, the method comprising: forming a plurality of line patterns extending along a first horizontal direction on a substrate, each of the plurality of line patterns comprising a back gate line and spacers located on two side walls of the back gate line; forming a preliminary channel layer on the plurality of line patterns located on the substrate; performing a laser annealing process on the preliminary channel layer to crystallize the preliminary channel layer into a single crystal; removing a portion of the preliminary channel layer on a first surface of each of the plurality of line patterns, and removing a portion of the preliminary channel layer on the substrate, and leaving a portion of the preliminary channel layer on the side walls of the plurality of line patterns; and removing portions of the preliminary channel layer to form a plurality of channel layers spaced apart from each other in the first horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a perspective view schematically illustrating a semiconductor device according to an embodiment;

[0011] Figure 2 yes Figure 1 an enlarged layout diagram of a portion of a cell array region;

[0012] Figure 3 It is along Figure 2 A cross-sectional view taken along line A1-A1';

[0013] Figure 4 yes Figure 3 A magnified view of a portion of CX1;

[0014] Figure 5 yes Figure 3 A schematic plan view at a first vertical height of;

[0015] Figure 6 is a cross-sectional view illustrating a semiconductor device according to an embodiment;

[0016] Figure 7 yes Figure 6 A magnified view of a portion of CX1;

[0017] Figure 8 is a cross-sectional view illustrating a semiconductor device according to an embodiment;

[0018] Fig. 9 yes Figure 8 A magnified view of a portion of CX1;

[0019] Fig.10 is a cross-sectional view illustrating a semiconductor device according to an embodiment;

[0020] Fig.11 yes Fig.10 An enlarged view of a portion of CX1;

[0021] Fig.12 yes Fig.10 A schematic plan view at a first vertical height of;

[0022] Fig.13 is a cross-sectional view illustrating a semiconductor device according to an embodiment;

[0023] Fig.14 yes Fig.13 An enlarged view of a portion of CX1;

[0024] Fig.15 yes Fig.13 A schematic plan view at a first vertical height of;

[0025] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig. 22 , Fig.23 , Fig.24A , Fig. 24B , Fig.25 , Fig.26 , Fig. 27 and Fig.28 is a schematic diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, wherein Figures 16 to 19 , Fig. 20A , Fig.21A , Fig. 22 , Fig.23 , Fig.24A and Figure 25 to Figure 28 It is along Figure 2 A cross-sectional view taken along line A1-A1', and Fig. 20B , Fig. 21B and Fig. 24B yes Fig. 20A , Fig.21A and Fig.24A A plan view at the first vertical height;

[0026] Fig.29 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment; and

[0027] Fig. 30A , Fig. 30B , Fig.31A , Fig.31B and Fig.32 is a schematic diagram illustrating a method of manufacturing a semiconductor device according to an embodiment, wherein Fig. 30A , Fig.31A and Fig.32 It is along Figure 2 A cross-sectional view taken along line A1-A1', and Fig. 30B and Fig.31B yes Fig. 30A and Fig.31A Plan view at the first vertical height. DETAILED DESCRIPTION

[0028] The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto.

[0029] It should be understood that although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and / or parts (collectively referred to as "elements"), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element described in this specification section may be referred to as the second element in the claims section, or vice versa.

[0030] It should be understood that when an element or layer is referred to as being “over,” “on,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly over, over, on, under, under, under, connected to, or coupled to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0031] Figure 1 is a perspective view schematically illustrating a semiconductor device 100 according to an embodiment. Figure 2 yes Figure 1 An enlarged layout diagram of a portion of the cell array area MCA. Figure 3 It is along Figure 2 A cross-sectional view taken along line A1-A1'. Figure 4 yes Figure 3 An enlarged view of a portion of CX1. Figure 5 yes Figure 3 Schematic plan view at a first vertical height LV1.

[0032] refer to Figures 1 to 5 , the semiconductor device 100 may include a cell array region MCA and a peripheral circuit region PCA arranged at different vertical heights. The peripheral circuit region PCA and the cell array region MCA may overlap each other in the vertical direction. For example, the cell array region MCA may be as follows: Figure 1 As shown, the semiconductor device 100 is disposed on the peripheral circuit area PCA, and may have a cell on periphery (COP) structure.

[0033] In some embodiments, the cell array area MCA may be a memory cell area of ​​a DRAM device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of ​​the DRAM device. For example, the peripheral circuit area PCA may include a peripheral circuit transistor 60TR for transmitting signals and / or power to the memory cell array included in the cell array area MCA (see Figure 3 ). In an embodiment, the peripheral circuit transistor 60TR may include various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0034] like Figure 2 As shown, a plurality of word lines WL and a plurality of back gate lines 130 may be alternately arranged in the cell array area MCA to extend in the first horizontal direction X. In addition, a plurality of bit lines BL may extend in the second horizontal direction Y. On the plurality of bit lines BL, a plurality of cell transistors CTR may be arranged between each word line WL in the plurality of word lines WL and each back gate line 130 in the back gate lines 130 adjacent to the plurality of word lines WL. The plurality of cell transistors CTR may be arranged in a matrix form in the first horizontal direction X and the second horizontal direction Y. A plurality of storage nodes 180 may be arranged on the plurality of cell transistors CTR, respectively.

[0035] The peripheral circuit structure PS may include a substrate 50 and a peripheral circuit transistor 60TR disposed on the substrate 50 .

[0036] The substrate 50 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 50 may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). A device isolation layer 52 may be formed on the substrate 50, and the active region AC may be defined by the device isolation layer 52.

[0037] The peripheral circuit transistor 60TR may be arranged on the active region AC of the substrate 50. The peripheral circuit transistor 60TR may include, for example, at least one of a planar transistor, a finFET, a multi-bridge channel transistor, and a buried channel array transistor.

[0038] Peripheral circuit contacts 72 and peripheral circuit wiring layers 74 may be disposed on substrate 50 and may be electrically connected to peripheral circuit transistor 60TR. Interlayer insulating layer 80 covering peripheral circuit transistor 60TR, peripheral circuit contacts 72 and peripheral circuit wiring layers 74 may be disposed on substrate 50.

[0039] The peripheral circuit structure PS can correspond to Figure 1 The peripheral circuit area PCA, and for example, the peripheral circuit transistor 60TR can be configured to apply a driving signal or a driving voltage to at least one of the bit line BL, the word line WL and the back gate line 130 arranged in the cell array area MCA vertically overlapping the peripheral circuit structure PS.

[0040] A plurality of bit lines BL extending in the second horizontal direction Y may be arranged on the interlayer insulating layer 80. In some embodiments, the bit line BL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), polysilicon, or a combination thereof. The bit line isolation layer may be arranged to extend along the second horizontal direction Y between the plurality of bit lines BL. For example, the bit line isolation layer may be formed at the same height as the bit line BL along the vertical direction Z while filling the space between two adjacent bit lines BL.

[0041] The plurality of back gate lines 130 may be arranged to extend along the first horizontal direction X on the plurality of bit lines BL and the bit line isolation layer. The buried insulating layer 132 may be arranged on the bottom surface of the back gate line 130, and the first insulating layer 136 may be arranged on the top surface of the back gate line 130. The buried insulating layer 132 and the first insulating layer 136 may be arranged on the top surface and the bottom surface of the back gate line 130, respectively, and may extend in the extension direction of the back gate line 130 (e.g., the first horizontal direction X). The buried insulating layer 132 may be arranged between the back gate line 130 and each of the plurality of bit lines BL and between the back gate line 130 and the bit line isolation layer, and the plurality of bit lines BL and the plurality of back gate lines 130 may be separated by the buried insulating layer 132 in the vertical direction Z and electrically insulated from each other.

[0042] The spacer 134 may be disposed on both sidewalls of the plurality of back gate lines 130. The spacer 134 may have a top surface disposed at the same height as a top surface of the first insulating layer 136, and may have a bottom surface disposed at a height lower than a bottom surface of the back gate line 130, and a bottom surface of the spacer 134 may contact the buried insulating layer 132. The spacer 134 may cover or contact both sidewalls of the back gate line 130.

[0043] Each of the plurality of back gate lines 130 may include Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, or a combination thereof. In some embodiments, the plurality of back gate lines 130 may include a conductive barrier layer and a metal buried layer, and the conductive barrier layer may be disposed at an interface between the spacer 134 and the back gate line 130 and / or at an interface between the first insulating layer 136 and the back gate line 130, and a top surface and a sidewall of the metal buried layer may be covered by the conductive barrier layer.

[0044] A plurality of vertical channel layers 140 may be arranged on the plurality of bit lines BL to extend in the vertical direction Z on the sidewalls of the buried insulating layer 132 and the spacer 134. The plurality of vertical channel layers 140 may be spaced apart in the first horizontal direction X and the second horizontal direction Y and arranged in a matrix form, and each of the plurality of vertical channel layers 140 may extend in the vertical direction Z on a top surface of each of the plurality of bit lines BL.

[0045] Each vertical channel layer 140 may include a first vertical channel layer 140_L arranged on a first side of each back gate line 130. Each vertical channel layer 140 may also include a second vertical channel layer 140_R arranged on a second side of each back gate line 130 and adjacent to the first vertical channel layer 140_L in the second horizontal direction Y. The first vertical channel layer 140_L and the second vertical channel layer 140_R may be symmetrical with respect to each other. For example, the first vertical channel layer 140_L and the second vertical channel layer 140_R may be symmetrical with respect to each other along a center line of the back gate line 130 arranged between the first vertical channel layer 140_L and the second vertical channel layer 140_R.

[0046] In an embodiment, the plurality of vertical channel layers 140 may include single crystalline silicon. For example, the vertical channel layer 140 may include single crystalline silicon crystallized by performing a laser annealing process on the preliminary channel layer 140P formed of amorphous silicon (see Fig.19). In some embodiments, there may be crystal defects such as stacking faults or dislocations inside the vertical channel layer 140. In some embodiments, the crystal defects observed inside the vertical channel layer 140 may be observed by a measurement device such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For example, the crystal defect may refer to a local area where regularity is lost observed inside the single crystal silicon of the vertical channel layer 140.

[0047] Each vertical channel layer 140 may include a first end portion 140E1 in contact with the bit line BL and a second end portion 140E2 disposed at an opposite side of the first end portion 140E1. The second end portion 140E2 of each of the plurality of vertical channel layers 140 may be a portion disposed farthest from the bit line BL of the vertical channel layer 140. In the second horizontal direction Y, a first width w1 of the first end portion 140E1 of each of the plurality of vertical channel layers 140 may be greater than a second width w2 of the second end portion 140E2.

[0048] Each of the plurality of vertical channel layers 140 may include a first side wall SW1 facing the back gate line 130 and a second side wall SW2 opposite to the first side wall SW1. At a first end 140E1 of each of the plurality of vertical channel layers 140, the first side wall SW1 may extend substantially vertically. At a first end 140E1 of each of the plurality of vertical channel layers 140, the second side wall SW2 may be in a curved shape. For example, the second side wall SW2 may be in a curved shape that bulges outward toward the corresponding word line WL.

[0049] In an embodiment, a preliminary channel layer 140P may be formed on the sidewalls of the spacer 134 and the buried insulating layer 132 (see Figures 17 to 20B ), and an anisotropic etching process may be performed to separate the preliminary channel layer 140P into a plurality of vertical channel layers 140. The convex curved shape of the second sidewall SW2 may be a resultant structure formed by exposing a portion adjacent to the first end portion 140E1 of the vertical channel layer 140 to an etching atmosphere for a relatively long time during the anisotropic etching process.

[0050] The gate insulating layer 150 may be disposed on the second sidewall SW2 of each of the plurality of vertical channel layers 140. The gate insulating layer 150 may conformally extend from the sidewall of the second end portion 140E2 of each of the plurality of vertical channel layers 140 toward the sidewall of the first end portion 140E1, and may extend along the convex curved shape of the second sidewall SW2 of the vertical channel layer 140. In an embodiment, the gate insulating layer 150 may include at least one of silicon oxide, silicon nitride, or a high-k metal oxide.

[0051] In some embodiments, the gate insulating layer 150 may be formed of at least one selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead titanium zirconate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0052] The plurality of word lines WL may extend along the first horizontal direction X on the sidewall of the gate insulating layer 150. The top surface of each of the plurality of word lines WL may be arranged at the same height as the top surface of each of the plurality of gate insulating layers 150, and the second insulating layer 162 may be arranged on the bottom surface of each of the plurality of word lines WL. The second insulating layer 162 may extend in the extension direction (e.g., the first horizontal direction X) of each of the plurality of word lines WL, and may electrically isolate each of the plurality of word lines WL from each of the plurality of bit lines BL. In some embodiments, the word line WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0053] A plurality of word lines WL may be alternately arranged with a plurality of back gate lines 130 and may extend in the first horizontal direction X, and each cell transistor CTR may have a double gate structure including one word line WL and one back gate line 130 as a gate electrode. Figure 3 As shown, a word line WL is arranged on the left side of the first vertical channel layer 140_L, and a gate insulating layer 150 is arranged between the first vertical channel layer 140_L and the word line WL. In addition, a back gate line 130 is arranged on the right side of the first vertical channel layer 140_L, and a spacer 134 is arranged between the first vertical channel layer 140_L and the back gate line 130. The first vertical channel layer 140_L can act as a vertical channel shared by the word line WL arranged on the left side thereof and the back gate line 130 arranged on the right side thereof, and a dual-gate type vertical transistor can be implemented.

[0054] like Figure 5As illustrated, the channel layer separation insulating layers 142 may be disposed between the vertical channel layers 140 adjacent to each other along the first horizontal direction X. For example, the vertical channel layers 140 and the channel layer separation insulating layers 142 may be alternately and repeatedly disposed in the space between the gate insulating layer 150 and the spacer 134 .

[0055] The contact pad 170 may be disposed on each of the plurality of vertical channel layers 140. The interlayer insulating layer 172 may be disposed on top surfaces of the first insulating layer 136, the gate insulating layer 150, and the word line WL, and may be adjacent to and surround the sidewall of the contact pad 170. The storage node 180 may be disposed on the contact pad 170.

[0056] In some embodiments, the contact pad 170 may include Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, polysilicon, or a silicide material thereof. In some embodiments, the storage node 180 may include a metal-insulator-metal (MIM) capacitor. In some other embodiments, the storage node 180 may include a memory component such as a variable resistance memory device, a phase change memory device, and a magnetic memory device.

[0057] In some embodiments, impurities may be further doped on a portion of a first end 140E1 of the vertical channel layer 140 contacting the bit line BL and / or a portion of a second end 140E2 of the vertical channel layer 140 contacting the contact pad 170, and the portion of the first end 140E1 and the portion of the second end 140E2 doped with impurities may serve as source / drain regions of the cell transistor CTR, respectively.

[0058] Generally speaking, in order to improve the integration of memory cells of DRAM devices, 1T-1C type DRAM devices in which vertical channel transistors and storage nodes are connected to each other have been proposed. However, since a silicon layer is patterned using a silicon-on-insulator (SOI) type substrate to form a vertical channel with improved crystal quality, etching damage may occur in the patterning process of the silicon layer, and manufacturing costs may increase.

[0059] However, according to an embodiment, a back gate line and a preliminary channel layer may be formed on a bulk silicon substrate, and a laser annealing process may be performed on the preliminary channel layer to crystallize the preliminary channel layer into a single crystal, thereby forming a vertical channel layer 140. The crystal quality of the vertical channel layer 140 crystallized by the laser annealing process may be improved, so that the semiconductor device 100 may have improved electrical properties. In addition, the manufacturing cost of the semiconductor device 100 may be reduced by using a bulk silicon substrate.

[0060] Figure 6is a cross-sectional view illustrating a semiconductor device 100A according to an embodiment. Figure 7 yes Figure 6 An enlarged view of a portion of CX1. Figure 6 and Figure 7 in Figures 1 to 5 Like reference numerals in the drawings denote like components.

[0061] refer to Figure 6 and Figure 7 , the bottom surface of the buried insulating layer 132 and the bottom surface of the spacer 134 may be arranged at the same height as the bottom surface of the first end portion 140E1 of the vertical channel layer 140A. The bottom surface of the buried insulating layer 132, the bottom surface of the spacer 134, and the bottom surface of the first end portion 140E1 of the vertical channel layer 140A may contact the top surface of the bit line BL.

[0062] According to the embodiment, when compared with the reference Figures 1 to 4 Compared with the described embodiment, a portion of the first end portion 140E1 of the vertical channel layer 140A can be removed by a planarization process, and thus, a portion of the convex curved shape of the second side wall SW2 of the vertical channel layer 140A can be removed together. As the portion of the convex curved shape of the second side wall SW2 of the vertical channel layer 140A is removed, a contact area between the first end portion 140E1 of the vertical channel layer 140A and the bit line BL can be increased.

[0063] Figure 8 is a cross-sectional view illustrating a semiconductor device 100B according to an embodiment. Fig. 9 yes Figure 8 An enlarged view of a portion of CX1. Figure 8 and Fig. 9 in Figures 1 to 7 The same reference numerals in the drawings represent the same components.

[0064] refer to Figure 8 and Fig. 9 , a tail portion 136T may be formed on the top surface of the first insulating layer 136, the tail portion 136T may represent two edge portions adjacent to the top surface of the first insulating layer 136, and the tail portion 136T of the first insulating layer 136 may have a shape that protrudes outward more than a bottom surface of the first insulating layer 136 that contacts the top surface of the back gate line 130. Both the inner and outer sidewalls of the spacer 134 may have curved sidewalls along the shape of the tail portion 136T of the first insulating layer 136.

[0065] The second end portion 140E2 of the outer sidewall of the vertical channel layer 140B contacting the spacer 134 may also have a curved sidewall along the shape of the tail portion 136T of the first insulating layer 136. Figures 1 to 4As described, the first side wall SW1 adjacent to the first end 140E1 of the vertical channel layer 140B has a vertical profile, and the second side wall SW2 adjacent to the first end 140E1 has a convex curved side wall toward the corresponding word line WL. In addition, a portion of the first side wall SW1 adjacent to the second end 140E2 of the vertical channel layer 140B may have a curved shape along the shape of the tail 136T of the first insulating layer 136, and a portion of the second side wall SW2 adjacent to the second end 140E2 of the vertical channel layer 140B may have a curved shape along the shape of the tail 136T of the first insulating layer 136.

[0066] Fig.10 is a cross-sectional view illustrating a semiconductor device 100C according to an embodiment. Fig.11 yes Fig.10 An enlarged view of a portion of CX1. Fig.12 yes Fig.10 Schematic plan view at the first vertical height LV1. Figures 10 to 12 in Figures 1 to 9 Like reference numerals in the drawings denote like components.

[0067] refer to Figures 10 to 12 The vertical channel layer 140C may include a first end portion 140E1 contacting the bit line BL and a second end portion 140E2 contacting the contact pad 170 , and in the second horizontal direction Y, a first width w1 of the first end portion 140E1 may be greater than a second width w2 of the second end portion 140E2 .

[0068] In an embodiment, the substrate 210 (see Fig. 30A ) on the protective layer 220 (see Fig. 30A ) opening 220H (see Fig. 30A ) is formed by an epitaxial growth process using the top surface of the substrate 210 as a seed layer. In some other embodiments, the vertical channel layer 140C may be formed by forming the preliminary channel layer 140P2 using amorphous silicon in the opening 220H of the protection layer 220 and performing a laser annealing process on the preliminary channel layer 140P2, and the vertical channel layer 140C may include single crystal silicon crystallized in the laser annealing process.

[0069] In some embodiments, there may be crystal defects such as stacking faults or dislocations inside the vertical channel layer 140C. In some embodiments, the crystal defects observed inside the vertical channel layer 140C can be observed by a measurement device such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For example, the crystal defect may refer to a local area where regularity is lost observed inside the single crystal silicon of the vertical channel layer 140C.

[0070] Fig.13 is a cross-sectional view illustrating a semiconductor device 100D according to an embodiment. Fig.14 yes Fig.13 An enlarged view of a portion of CX1. Fig.15 yes Fig.13 Schematic plan view at the first vertical height LV1. Figures 13 to 15 in Figures 1 to 12 Like reference numerals in the drawings denote like components.

[0071] refer to Figures 13 to 15 The gate insulating layer 150 may be conformally disposed on the sidewall of the vertical channel layer 140 and may continuously extend to the top surface WLU of the word line WL on the sidewall of the second end portion 140E2 of the vertical channel layer 140. The top surface WLU of the word line WL may be covered by the gate insulating layer 150 and may not be in direct contact with the bottom surface of the interlayer insulating layer 172.

[0072] like Fig.15 As shown, the channel layer separation insulating layer 142 may be omitted between the vertical channel layers 140 adjacent to each other along the first horizontal direction X, the gate insulating layer 150 may be conformally arranged on the sidewalls of the vertical channel layers 140, and a portion of the gate insulating layer 150 may be arranged on the sidewalls of the spacer 134. For example, the word line WL may be arranged to fill the space where the channel layer separation insulating layer 142 is omitted, and for example, the word line WL may be arranged to fill the space between two adjacent vertical channel layers 140 in the first horizontal direction X.

[0073] Figures 16 to 19 , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig. 22 , Fig.23 , Fig.24A , Fig. 24B and Figure 25 to Figure 28 is a schematic diagram illustrating a method of manufacturing a semiconductor device 100 according to an embodiment, wherein Figures 16 to 19 , Fig. 20A , Fig.21A , Fig. 22 , Fig.23 , Fig.24A and Figure 25 to Figure 28 It is along Figure 2 A cross-sectional view taken along line A1-A1', and Fig. 20B , Fig. 21B and Fig. 24B yes Fig. 20A , Fig.21A and Fig.24A The plan view under the first vertical height LV1.

[0074] refer to Fig.16 A stack pattern of a first insulating layer 136 and a back gate line 130 extending in a first horizontal direction X may be formed on a first surface 210F1 of a substrate 210 including a first surface 210F1 and a second surface 210F2. In an embodiment, the substrate 210 may include a single crystalline silicon substrate.

[0075] The spacer 134 may be formed on any one sidewall of the first insulating layer 136 and the back gate line 130, and a buried insulating layer 132 covering the top surface of the back gate line 130 may be formed on the top surface of the back gate line 130. In an embodiment, the buried insulating layer 132 may be formed to a height covering the top surface of the spacer 134 in the vertical direction Z, and may have a T-shaped vertical cross-sectional shape. The first insulating layer 136 may be formed using silicon oxide, and the buried insulating layer 132 may be formed using silicon nitride.

[0076] In an embodiment, the back gate line 130 may be formed using Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, or a combination thereof. In an embodiment, the back gate line 130 may be formed in a double-layer structure of a conductive barrier layer and a metal buried layer, and in this case, the conductive barrier layer may be thinly formed on the inner wall of the spacer 134 and the top surface of the first insulating layer 136, the metal buried layer may be filled on the conductive barrier layer, and the top surface of the metal buried layer may be planarized to form the back gate line 130.

[0077] In some embodiments, a mold layer including polysilicon or amorphous silicon may be formed on the substrate 210, a portion of the mold layer may be removed to form a mold opening, and an oxidation process may be performed on an inner wall of the mold opening to form a spacer 134. Thereafter, a first insulating layer 136, a back gate line 130, and a buried insulating layer 132 may be sequentially formed on the inner wall of the spacer 134 and inside the mold opening, and the mold layer may be removed.

[0078] Therefore, LPs included in the first insulating layer 136 , the back gate line 130 , the spacer 134 , and the buried insulating layer 132 are arranged on the first surface 210F1 of the substrate 210 to extend in the first horizontal direction X, and the first surface 210F1 of the substrate 210 is exposed in a space between adjacent line patterns LP.

[0079] refer to Fig.17 , a preliminary channel layer 140P may be formed on a top surface and both sidewalls of the line pattern LP and on the first surface 210F1 of the substrate 210 .

[0080] In an embodiment, the preliminary channel layer 140P may include amorphous silicon. The preliminary channel layer 140P may be formed with a conformal thickness on the top surface and both sidewalls of the line pattern LP and on the first surface 210F1 of the substrate 210 .

[0081] A portion of the preliminary channel layer 140P disposed on the sidewall of the line pattern LP includes a first sidewall SW1 and a second sidewall SW2. The first sidewall SW1 contacts the spacer 134 and extends in the first horizontal direction X. The second sidewall SW2 is disposed opposite to the first sidewall SW1 and may extend in the first horizontal direction X. In addition, another portion of the preliminary channel layer 140P may be disposed to contact the first surface 210F1 of the substrate 210.

[0082] refer to Fig.18 , a laser annealing process P200 may be performed on the preliminary channel layer 140P. By performing the laser annealing process P200 on the preliminary channel layer 140P, the amorphous silicon of the preliminary channel layer 140P may be melted and annealed to crystallize, thereby crystallizing the preliminary channel layer 140P into single crystalline silicon. In the laser annealing process P200, the first surface 210F1 of the substrate 210 in contact with the bottom surface of the preliminary channel layer 140P serves as a template, and the preliminary channel layer 140P may be crystallized into single crystalline silicon having the same crystal structure as the substrate 210.

[0083] In an embodiment, the laser annealing process P200 may be performed by applying a pulse laser having a wavelength of several hundred nanometers for several nanoseconds to several tens of nanoseconds.

[0084] In embodiments, when the preliminary channel layer 140P is crystallized from amorphous silicon to crystalline silicon through the laser annealing process P200 , crystal defects such as stacking faults or dislocations may be generated in the preliminary channel layer 140P.

[0085] refer to Fig.19 , portions of the preliminary channel layer 140P may be removed so that the preliminary channel layer 140P remains on the sidewalls of the line patterns LP.

[0086] In an embodiment, an anisotropic etching process may be performed on the preliminary channel layer 140P to remove a portion of the preliminary channel layer 140P on the top surface of the line pattern LP and a portion of the preliminary channel layer 140P on the first surface 210F1 of the substrate 210, and the preliminary channel layer 140P may remain on the sidewall of the line pattern LP. After performing the anisotropic etching process, the preliminary channel layer 140P may have a second end portion 140E2 disposed on the first surface 210F1 of the substrate 210, and a first end portion 140E1 disposed opposite to the second end portion 140E2 and disposed at a vertical height higher than the second end portion 140E2. In the anisotropic etching process, a portion of the first end portion 140E1 may be exposed to an etching atmosphere to be removed, and a second sidewall SW2 adjacent to the first end portion 140E1 may be in a curved shape.

[0087] refer to Fig. 20A and Fig. 20B , a protection layer 220 filling a space between the line patterns LP may be formed. The protection layer 220 may be formed using at least one of silicon oxide, a spin-on hard mask, silicon carbide, a low-k dielectric material, and an amorphous carbon layer.

[0088] In embodiments, the top surface of the protection layer 220 may be removed such that the top surface of the protection layer 220 may be arranged coplanar with the top surfaces of the preliminary channel layer 140P and the buried insulation layer 132 .

[0089] refer to Fig.21A and Fig. 21B A mask pattern may be formed on the top surface of the preliminary channel layer 140P, the top surface of the buried insulating layer 132, and the top surface of the protective layer 220, and an opening 142H may be formed by removing a portion of the preliminary channel layer 140P using the mask pattern as an etching mask. Through the formation of the opening 142H, the preliminary channel layer 140P may be divided into a plurality of vertical channel layers 140 spaced apart in the first horizontal direction X.

[0090] Thereafter, a channel layer separation insulating layer 142 may be formed in the opening 142H using an insulating material. For example, the channel layer separation insulating layer 142 may be disposed between two adjacent vertical channel layers 140 in the first horizontal direction X.

[0091] like Fig. 21BAs illustrated, the vertical channel layer 140 may include a first vertical channel layer 140_L arranged on a first side of a back gate line 130 and a second vertical channel layer 140_R arranged on a second side of a back gate line 130, and the first vertical channel layer 140_L and the second vertical channel layer 140_R may have shapes that are mirror-symmetric relative to each other along a center line of the back gate line 130 arranged between the first vertical channel layer 140_L and the second vertical channel layer 140_R.

[0092] refer to Fig. 22 , the protection layer 220 may be removed.

[0093] Thereafter, a gate insulating layer 150 may be formed on the line pattern LP and the vertical channel layer 140 .

[0094] In an embodiment, gate insulating layer 150 may be formed of at least one selected from silicon oxide, a high-k dielectric material having a higher dielectric constant than that of silicon oxide, and a ferroelectric material. In some embodiments, the gate insulating layer 150 may be formed of at least one selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead titanium zirconate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0095] refer to Fig.23 , portions of the gate insulating layer 150 arranged on the top surface of the line pattern LP and the first surface 210F1 of the substrate 210 may be removed, and only portions of the gate insulating layer 150 arranged on the sidewalls of the line pattern LP may remain.

[0096] Thereafter, word lines WL may be formed on sidewalls of the gate insulating layer 150. In some embodiments, the word lines WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0097] A recess process may be performed on a portion of an upper side of the word line WL to lower a top surface of the word line WL to a height lower than a top surface of the gate insulating layer 150 and a top surface of the vertical channel layer 140, and a second insulating layer 162 may be formed on the top surface of the word line WL. The second insulating layer 162 may be formed using silicon nitride.

[0098] In embodiments, the second insulating layer 162 may be formed to cover the top surfaces of the line patterns LP and the vertical channel layers 140 .

[0099] refer to Fig.24A and Fig. 24B , top surfaces of the line pattern LP and the vertical channel layer 140 may be exposed by planarizing the upper side of the second insulating layer 162 .

[0100] Thereafter, impurity ions may be implanted through the top surface of the vertical channel layer 140 to form source / drain regions within the first end portion 140E1 of the vertical channel layer 140 .

[0101] refer to Fig.25 , a plurality of bit lines BL extending in the second horizontal direction Y may be formed on the first end portion 140E1 of the vertical channel layer 140 , and a bit line isolation layer may be formed in a space between the plurality of bit lines BL.

[0102] refer to Fig.26 , a peripheral circuit structure PS can be prepared.

[0103] The peripheral circuit structure PS may be prepared by forming a device separator 52 and an active region AC on a substrate 50 and forming a peripheral circuit transistor 60TR, a peripheral circuit contact 72 , a peripheral circuit wiring layer 74 , and an interlayer insulating layer 80 on the substrate 50 .

[0104] Subsequently, the substrate 210 may be attached to the peripheral circuit structure PS so that a plurality of bit lines BL are arranged on the peripheral circuit structure PS.

[0105] In an embodiment, attachment of the substrate 210 to the peripheral circuit structure PS may be performed by a wafer bonding method such as an oxide bonding method or a metal oxide hybrid bonding method.

[0106] Thereafter, the structure in which the substrate 210 and the peripheral circuit structure PS are attached to each other may be reversed such that the second surface 210F2 of the substrate 210 faces upward.

[0107] refer to Fig. 27 , the substrate 210 may be removed.

[0108] In an embodiment, the removal process of the substrate 210 may be performed by grinding, wet etching, or a combination thereof. The substrate 210 may be removed, and the second end portion 140E2 of the vertical channel layer 140 and the top surface of the word line WL may be exposed.

[0109] refer to Fig.28, an interlayer insulating layer 172 may be formed on the vertical channel layer 140 and the word line WL, and an opening exposing the top surface of the vertical channel layer 140 may be formed by removing a portion of the interlayer insulating layer 172. Thereafter, a contact pad 170 may be formed in the opening. The contact pad 170 may include Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, polysilicon, or silicide materials thereof.

[0110] In an embodiment, before forming the contact pad 170 , source / drain regions may be formed by implanting impurity ions into the upper side of the exposed vertical channel layer 140 .

[0111] Return to reference Figure 3 , a storage node 180 may be formed on the contact pad 170 .

[0112] The semiconductor device 100 may be completely formed by performing the above-mentioned processes.

[0113] Generally speaking, a vertical channel is formed by etching a silicon layer using an SOI type substrate to realize a vertical channel transistor. However, due to etching damage to the silicon layer during the etching process, the crystal quality of the vertical channel may not be high and / or the electrical characteristics of the vertical channel transistor may not be high. In addition, when an SOI type substrate is used, the manufacturing cost may be expensive.

[0114] However, according to an embodiment, the preliminary channel layer 140P may be formed using amorphous silicon on the sidewalls of the line pattern LP, and a laser annealing process P200 may be performed on the preliminary channel layer 140P to crystallize the amorphous silicon into single crystal silicon, thereby forming the vertical channel layer 140. Therefore, since the vertical channel layer 140 is not damaged by etching, the electrical characteristics of the vertical channel transistor may be improved. In addition, the manufacturing cost may be reduced.

[0115] Fig.29 is a cross-sectional view illustrating a method of manufacturing the semiconductor device 100 according to an embodiment.

[0116] refer to Fig.29 , the laser annealing process P200 may not be performed on the preliminary channel layer 140P, but may be performed in a state where the preliminary channel layer 140P remains only on the sidewalls of the line patterns LP and the protection layer 220 is filled in the space between the preliminary channel layers 140P.

[0117] For example, you can reference Fig.16 and Fig.17 The process described, then perform the reference Fig.19The preliminary channel layer 140P is formed by the process described in the previous embodiment. In this case, since the laser annealing process P200 is not performed on the preliminary channel layer 140P, the preliminary channel layer 140P may include amorphous silicon. Thereafter, the preliminary channel layer 140P may be formed by performing the process described in the previous embodiment. Fig. 20A and Fig. 20B The process described is used to form the protection layer 220 on the first surface 210F1 of the substrate 210 .

[0118] Thereafter, a laser annealing process P200 may be performed on the top surface of the preliminary channel layer 140P. The laser annealing process P200 may be performed by applying a pulse laser having a wavelength of, for example, hundreds of nanometers for several nanoseconds to tens of nanoseconds.

[0119] By performing the laser annealing process P200 on the preliminary channel layer 140P, the amorphous silicon of the preliminary channel layer 140P may be melted and annealed to crystallize, thereby crystallizing the preliminary channel layer 140P into single crystal silicon. In the laser annealing process P200, the first surface 210F1 of the substrate 210 in contact with the bottom surface of the preliminary channel layer 140P serves as a template, and the preliminary channel layer 140P may be crystallized into single crystal silicon having the same crystal structure as the substrate 210.

[0120] In some other embodiments, the reference Fig.21A and Fig. 21B The described process divides the preliminary channel layer 140P into a plurality of vertical channel layers 140 spaced apart in the first horizontal direction X before performing the laser annealing process P200 .

[0121] Afterwards, you can reference Figure 22 to Figure 28 The described process completely forms the semiconductor device 100 .

[0122] In some other embodiments, in reference to Fig.23 In the process described above, the upper side of the word line WL can be further removed in the recess process so that the top surface of the word line WL is placed at the same height as the top surface of the back gate line 130. Then, when the reference Fig.24A and Fig. 24B When the planarization process is performed on the upper side of the second insulating layer 162 in the described process, the top surface of the second insulating layer 162 can be planarized to be arranged at the same height as the top surface of the spacer 134. In this case, the curved sidewall portion arranged at the first end portion 140E1 of the vertical channel layer 140 can be removed together in the planarization process, and the top surface area of ​​the vertical channel layer 140 can be relatively large. In this case, the reference Figure 6 and Figure 7 A semiconductor device 100A is described.

[0123] In some other embodiments, when in reference Fig.16 When the first insulating layer 136 and the back gate line 130 are formed in the described process, a mask pattern may be formed on the back gate line 130 after the first insulating layer 136 and the back gate line 130 are sequentially formed, and the mask pattern may be used as an etching mask to pattern the back gate line 130 and the first insulating layer 136. In the patterning process, a tail portion 136T may be formed on a portion of the first insulating layer 136 adjacent to the first surface 210F1 of the substrate 210, and then in the process of forming the spacer 134 and the preliminary channel layer 140P, portions of the spacer 134 and the preliminary channel layer 140P may be formed to have a curved sidewall along the shape of the tail portion 136T of the first insulating layer 136. In this case, the reference 134 may be manufactured. Figure 8 and Fig. 9 A semiconductor device 100B is described.

[0124] In some other embodiments, it is possible not to refer to Fig. 22 The channel layer separation insulating layer 142 is formed in the process described above, and the portion of the gate insulating layer 150 disposed on the first surface 210F1 of the substrate 210 may not be removed, and may be formed in the process described above. Fig.23 In the process described above, the word line WL is formed on a portion of the gate insulating layer 150. In this case, the reference Figures 13 to 15 A semiconductor device 100D is described.

[0125] Fig. 30A , Fig. 30B , Fig.31A , Fig.31B and Fig.32 is a schematic diagram illustrating a method of manufacturing a semiconductor device 100C according to an embodiment, wherein Fig. 30A , Fig.31A and Fig.32 It is along Figure 2 A cross-sectional view taken along line A1-A1', and Fig. 30B and Fig.31B yes Fig. 30A and Fig.31A Plan view at the first vertical height.

[0126] First, you can reference Fig.16 The process is described to form the line pattern LP on the first surface 210F1 of the substrate 210 .

[0127] refer to Fig. 30A and Fig. 30B, a protective layer 220 may be formed in the space between the line patterns LP. Thereafter, a mask pattern may be formed on the protective layer 220, and a portion of the protective layer 220 may be removed using the mask pattern as an etching mask to form an opening 220H. The first surface 210F1 of the substrate 210 may be exposed at the bottom of the opening 220H, and the opening 220H may be arranged to expose the sidewall of the spacer 134 at the inner wall of the opening 220H.

[0128] refer to Fig.31A and Fig.31B , a preliminary channel layer 140P2 may be formed using amorphous silicon on the first surface 210F1 of the substrate 210 in the opening 220H of the protection layer 220 .

[0129] In an embodiment, after the preliminary channel layer 140P2 fills the interior of the opening 220H of the protective layer 220, a planarization process is further performed on the upper side of the preliminary channel layer 140P2 so that the preliminary channel layer 140P2 has a flat top surface, wherein the second end 140E2 of the preliminary channel layer 140P2 is arranged at the same height as the top surface of the protective layer 220.

[0130] refer to Fig.32 , a laser annealing process P200C may be performed on the top surface of the preliminary channel layer 140P2. The laser annealing process P200C may be performed by applying a pulse laser having a wavelength of, for example, several hundred nanometers for several nanoseconds to several tens of nanoseconds.

[0131] By performing the laser annealing process P200C on the preliminary channel layer 140P2, the amorphous silicon of the preliminary channel layer 140P2 may be melted and annealed to crystallize, so that the preliminary channel layer 140P2 is crystallized into single crystal silicon. In the laser annealing process P200C, the first surface 210F1 of the substrate 210 in contact with the bottom surface of the preliminary channel layer 140P2 may serve as a template, and the preliminary channel layer 140P2 may be crystallized into single crystal silicon having the same crystal structure as the substrate 210. The preliminary channel layer 140P2 melted, annealed, and / or crystallized by the laser annealing process P200C may be referred to as a vertical channel layer 140C.

[0132] In some other embodiments, the preliminary channel layer 140P2 may be formed in the opening 220H of the protective layer 220 by an epitaxial growth process using the first surface 210F1 of the substrate 210 as a seed layer. In an embodiment, the epitaxial growth process for forming the preliminary channel layer 140P2 may be performed by supplying a liquid or gaseous silicon precursor as a source material. In this case, the reference numeral 220 may be additionally performed or omitted. Fig.32 Described laser annealing process P200C.

[0133] The protective layer 220 is then removed, and a channel layer separation insulating layer 142 (see FIG. 1 ) may be formed between the plurality of vertical channel layers 140C. Fig.12 ).

[0134] Afterwards, you can reference Figure 22 to Figure 28 The semiconductor device 100C is completely manufactured by the described process.

[0135] Although embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: a peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit transistor; a plurality of bit lines, the plurality of bit lines being located on the peripheral circuit structure and extending along a first horizontal direction; a plurality of back gate lines extending in a second horizontal direction at a vertical height greater than a vertical height of the plurality of bit lines; a plurality of word lines extending along the second horizontal direction at a vertical height greater than the vertical height of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers being arranged on the plurality of bit lines in a matrix form, each of the plurality of vertical channel layers comprising a first sidewall and a second sidewall, the first sidewall extending in a vertical direction and facing a corresponding back gate line among the plurality of back gate lines, the second sidewall being opposite to the first sidewall and facing a corresponding word line among the plurality of word lines, and a portion of the second sidewall adjacent to a bit line among the plurality of bit lines being in a bent shape; a plurality of contact pads, the plurality of contact pads being located on the plurality of vertical channel layers; as well as A plurality of storage nodes are located on the plurality of contact pads.

2. The semiconductor device according to claim 1, wherein Each of the plurality of vertical channel layers includes a first end contacting the bit line and a second end opposite to the first end, and Wherein, a first width of the first end in the first horizontal direction is smaller than a second width of the second end in the first horizontal direction.

3. The semiconductor device according to claim 2, wherein: The second sidewall of each of the plurality of vertical channel layers has a convexly curved shape toward the corresponding word line at a position adjacent to the first end portion.

4. The semiconductor device according to claim 3, further comprising: a gate insulating layer, the gate insulating layer being located between each of the plurality of vertical channel layers and the corresponding word line among the plurality of word lines, The gate insulating layer is located on the convex curved shape of the second side wall of each of the plurality of vertical channel layers.

5. The semiconductor device according to claim 2, further comprising: a spacer, wherein the spacer is located between each of the plurality of vertical channel layers and the corresponding back gate line among the plurality of back gate lines, The spacer extends along the vertical direction on the first sidewall of each vertical channel layer among the plurality of vertical channel layers.

6. The semiconductor device according to claim 1, wherein The plurality of vertical channel layers include single crystalline silicon.

7. The semiconductor device according to claim 1, wherein Stacking faults or dislocations are included in the plurality of vertical channel layers.

8. The semiconductor device according to claim 1, wherein The plurality of vertical channel layers include: a first vertical channel layer, the first vertical channel layer being located at a first side of each of the plurality of back gate lines; and a second vertical channel layer, the second vertical channel layer being located at a second side of each of the plurality of back gate lines and being adjacent to the first vertical channel layer in the first horizontal direction, The first vertical channel layer and the second vertical channel layer are symmetrical with respect to each other.

9. A semiconductor device, comprising: a plurality of bit lines, the plurality of bit lines being located on the substrate and extending along a first horizontal direction; a plurality of back gate lines extending in a second horizontal direction at a vertical height greater than a vertical height of the plurality of bit lines; a plurality of word lines extending along the second horizontal direction at a vertical height greater than the vertical height of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers extending in a vertical direction on the plurality of bit lines, each of the plurality of vertical channel layers comprising a first sidewall, a second sidewall, a first end, and a second end, the first sidewall extending in the vertical direction and facing a corresponding back gate line among the plurality of back gate lines, the second sidewall being opposite to the first sidewall and facing a corresponding word line among the plurality of word lines, the first end being in contact with a bit line among the plurality of bit lines, the second end being opposite to the first end, and the second sidewall having a convex curved shape toward the corresponding word line among the plurality of word lines at a position adjacent to the first end; a plurality of contact pads, the plurality of contact pads being located on the plurality of vertical channel layers; as well as a plurality of storage nodes, the plurality of storage nodes being located on the plurality of contact pads, Wherein, a first width of the first end in the first horizontal direction is smaller than a second width of the second end in the first horizontal direction.

10. The semiconductor device according to claim 9, wherein The plurality of vertical channel layers include: a first vertical channel layer, the first vertical channel layer being located at a first side of each of the plurality of back gate lines; and a second vertical channel layer, the second vertical channel layer being located at a second side of each of the plurality of back gate lines and being adjacent to the first vertical channel layer in the first horizontal direction, The first vertical channel layer and the second vertical channel layer are symmetrical with respect to each other.

11. The semiconductor device according to claim 9, further comprising: a peripheral circuit structure, the peripheral circuit structure being located between the substrate and the plurality of bit lines, The peripheral circuit structure includes peripheral circuit transistors configured to drive the plurality of bit lines or the plurality of word lines.

12. The semiconductor device according to claim 9, further comprising: a gate insulating layer, the gate insulating layer being located between each of the plurality of vertical channel layers and the corresponding word line; as well as A spacer is located between each of the plurality of vertical channel layers and the corresponding back gate line.

13. The semiconductor device according to claim 12, wherein: The gate insulating layer is located on the convex curved shape of the second side wall of each of the plurality of vertical channel layers, and The spacer extends along the vertical direction on the first sidewall of each vertical channel layer among the plurality of vertical channel layers.

14. The semiconductor device according to claim 9, wherein: The plurality of vertical channel layers include single crystalline silicon.

15. The semiconductor device according to claim 9, wherein: Stacking faults or dislocations are included in the plurality of vertical channel layers.

16. A semiconductor device, comprising: a peripheral circuit structure, the peripheral circuit structure comprising a peripheral circuit transistor; a plurality of bit lines, the plurality of bit lines being located on the peripheral circuit structure and extending along a first horizontal direction; a plurality of back gate lines extending in a second horizontal direction at a vertical height greater than a vertical height of the plurality of bit lines; a plurality of word lines extending along the second horizontal direction at a vertical height greater than the vertical height of the plurality of bit lines and alternating with the plurality of back gate lines; a plurality of vertical channel layers, the plurality of vertical channel layers being arranged on the plurality of bit lines in a matrix form, each of the plurality of vertical channel layers comprising a first sidewall and a second sidewall, the first sidewall extending in a vertical direction and facing a corresponding back gate line among the plurality of back gate lines, the second sidewall being opposite to the first sidewall and facing a corresponding word line among the plurality of word lines, and a portion of the second sidewall adjacent to the bit line being in a curved shape; a gate insulating layer, the gate insulating layer being located between each of the plurality of vertical channel layers and the corresponding word line; a spacer, the spacer being located between each of the plurality of vertical channel layers and the corresponding back gate line; a plurality of contact pads, the plurality of contact pads being located on the plurality of vertical channel layers; as well as A plurality of storage nodes are located on the plurality of contact pads.

17. The semiconductor device according to claim 16, wherein: The plurality of vertical channel layers include: a first vertical channel layer, the first vertical channel layer being located at a first side of each of the plurality of back gate lines; and a second vertical channel layer, the second vertical channel layer being located at a second side of each of the plurality of back gate lines and being adjacent to the first vertical channel layer in the first horizontal direction, The first vertical channel layer and the second vertical channel layer are symmetrical with respect to each other.

18. The semiconductor device according to claim 16, wherein: Each of the plurality of vertical channel layers includes a first end contacting the bit line and a second end opposite to the first end, and Wherein, a first width of the first end in the first horizontal direction is smaller than a second width of the second end in the first horizontal direction.

19. The semiconductor device according to claim 18, wherein: The second sidewall of each of the plurality of vertical channel layers has a convex curved shape toward the corresponding word line among the plurality of word lines at a position adjacent to the first end portion.

20. The semiconductor device according to claim 19, wherein The gate insulating layer is located on the convex curved shape of the second side wall of each of the plurality of vertical channel layers, and The spacer extends along the vertical direction on the first sidewall of each vertical channel layer among the plurality of vertical channel layers.

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