Three-dimensional (3D) ferroelectric random access memory (FeRAM)

Abstract

A three-dimensional (3D) ferroelectric random access memory (FeRAM) is provided. The 3DFeRAM comprises the following components: a substrate; bit lines extending in a first horizontal direction, spaced apart from each other in a second horizontal direction; word lines disposed above the bit lines, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction; semiconductor patterns arranged at intervals on respective portions of the word line; and a ferroelectric capacitor (FeCap) structure disposed on the semiconductor pattern, where the FeCap structure includes: a first electrode including a body portion and at least two horizontal extensions; the ferroelectric layer covers the outer wall of the first electrode; and a second electrode covering the ferroelectric layer on the horizontal extension portion.

Description

Technical Field

[0001] The inventive concept relates to semiconductor memory devices, and more particularly, to a three-dimensional (3D) ferroelectric random access memory (FeRAM) and a method of manufacturing the same. Background Art

[0002] Due to the expectation of miniaturization, versatility and high performance of electronic devices, people seek high-capacity semiconductor memory devices, and need to improve the integration to provide high-capacity semiconductor memory devices. Because the integration of conventional two-dimensional (2D) semiconductor memory devices is mainly determined by the area occupied by the unit memory cell, the integration of 2D semiconductor memory devices is constantly improving, but still limited. Therefore, a three-dimensional (3D) semiconductor memory device with increased storage capacity achieved by stacking a plurality of memory cells in a vertical direction on a substrate has been proposed. Summary of the invention

[0003] The inventive concept provides a three-dimensional (3D) ferroelectric random access memory (FeRAM) having an increased memory window per unit area and reduced process difficulty and distribution, and a method of manufacturing the 3D FeRAM.

[0004] According to one aspect of the present invention, a three-dimensional (3D) ferroelectric random access memory (FeRAM) is provided, the 3D FeRAM comprising: bit lines extending along a first horizontal direction on a substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; word lines arranged above the bit lines, extending along the second horizontal direction, and spaced apart from each other in the first horizontal direction; semiconductor patterns arranged at intervals on corresponding portions of the word lines, with a gate dielectric layer located between the semiconductor patterns and corresponding portions of the word lines; and a ferroelectric capacitor (FeCap) structure located above the semiconductor pattern in a vertical direction, wherein the FeCap structure comprises: a first electrode comprising a main body portion extending from a corresponding semiconductor pattern along the vertical direction and at least two horizontal extensions extending from a side surface of the main body portion along the first horizontal direction and located at different levels; a ferroelectric layer covering an outer wall of the main body portion and the at least two horizontal extensions; and a second electrode covering a portion of the ferroelectric layer located on each of the at least two horizontal extensions.

[0005] According to another aspect of the present inventive concept, a three-dimensional (3D) ferroelectric random access memory (FeRAM) is provided, wherein the 3D FeRAM: a substrate; a bit line, the bit line extending along a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a selection transistor (Tr), the one selection transistor including a word line and a semiconductor pattern, the word line being arranged above the bit line in a vertical direction, extending along the second horizontal direction, and spaced apart from each other in the first horizontal direction, the semiconductor pattern being arranged on corresponding portions of the word line at intervals in the second horizontal direction and a gate dielectric layer being located between the semiconductor pattern and corresponding portions of the word line; and a FeCap structure, the FeCap structure having a plurality of capacitors on the one selection Tr, wherein the FeCap structure includes: a first electrode, the first electrode including a main body portion extending from the corresponding semiconductor pattern along the vertical direction and a plurality of horizontal extensions extending from a side surface of the main body portion along the first horizontal direction; a ferroelectric layer covering an outer wall of the main body portion and an outer wall of the plurality of horizontal extensions; a plurality of second electrodes, the plurality of second electrodes covering a portion of the ferroelectric layer located on each of the plurality of horizontal extensions, wherein the 3D FeRAM has a structure in which the plurality of capacitors are electrically connected to the one selection Tr.

[0006] According to another aspect of the present invention, a three-dimensional (3D) ferroelectric random access memory (FeRAM) is provided, the 3D FeRAM comprising: a substrate; a bit line extending along a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; at least one transistor (TR), the at least one TR being located on the bit line; and a FeCap structure, the FeCap structure being located on the at least one TR, wherein the FeCap structure comprises: a first electrode, the first electrode comprising a main body portion extending from the at least one TR in a vertical direction and a plurality of horizontal extension portions extending from a side surface of the main body portion along the first horizontal direction and being located at different horizontal heights; a ferroelectric layer covering an outer wall of the main body portion and an outer wall of the plurality of horizontal extension portions; and a plurality of second electrodes, the plurality of second electrodes covering a portion of the ferroelectric layer located on each of the plurality of horizontal extension portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1is an equivalent circuit diagram of a three-dimensional (3D) ferroelectric random access memory (FeRAM) according to an embodiment;

[0009] Figure 2A and Figure 2B are a perspective view and a top view of a 3D FeRAM according to an embodiment, respectively;

[0010] FIG. 3A to FIG. 3C yes Figure 2B An enlarged plan view and a cross-sectional view of a portion A of a 3D FeRAM;

[0011] Figure 4A and Figure 4B are an equivalent circuit diagram and a cross-sectional diagram of a 3D FeRAM according to an embodiment, respectively; and

[0012] FIG. 5A to FIG. 15C is a schematic diagram showing the manufacturing Figure 2B Plan and cross-sectional views of the 3D FeRAM process. DETAILED DESCRIPTION

[0013] Figure 1 is an equivalent circuit diagram of a three-dimensional (3D) ferroelectric random access memory (FeRAM) according to an embodiment.

[0014] refer to Figure 1 The 3D FeRAM 100 according to the present embodiment may include bit lines BL1 and BL2, a selection transistor S-Tr, and a ferroelectric capacitor (FeCap) C FE The bit lines BL1 and BL2 and the word lines WL1 and WL2 connected to the gate of the selection transistor S-Tr may each be arranged in a two-dimensional manner. For example, the bit lines BL1 and BL2 may each extend in the x-direction and be spaced apart from each other in the y-direction. In addition, the word lines WL1 and WL2 may each extend in the y-direction and be spaced apart from each other along the x-direction.

[0015] In various embodiments, a plurality of selection transistors S-Tr may be connected in parallel to each of the bit lines BL1 and BL2. For example, the first bit line BL1 may be commonly connected to the first ends of the sources / drains of the selection transistors S-Tr arranged in the first row along the x direction, and the second bit line BL2 may be commonly connected to the first ends of the sources / drains of the selection transistors S-Tr arranged in the second row along the x direction. Moreover, the gates of the selection transistors S-Tr arranged in the first column along the y direction may be commonly connected to the first word line WL1, and the gates of the selection transistors S-Tr arranged in the second column along the y direction may be commonly connected to the second word line WL2.

[0016] In various embodiments, FeCap C FEThe second end may be connected to the source / drain of the selection transistor S-Tr. Figure 1 As shown in the circuit diagram, multiple FeCap C FE The FeCap C can be connected to the source / drain of a selection transistor S-Tr in the vertical direction, i.e., the z direction, wherein multiple FeCap C connected to the same source / drain FE For example, multiple FeCap C arranged in the z direction FE The FeCap electrodes C and C can be connected together to a common electrode CE and can be connected to corresponding plate line electrodes PL, wherein the common electrode CE is connected to the same source / drain of the selection transistor S-Tr. FE It can be connected to the plate line electrode PL in the y direction.

[0017] In various embodiments, four FeCap Cs spaced apart from each other in the z direction FE It can be regarded as a group of independent capacitors (Cap), where the group of Caps can be arranged at the position where the selection transistor S-Tr is located on the xy plane. In addition, the group of plate line electrodes PL connected to the group of Caps 1 and PL 2 The FeCaps C may extend in the y direction and be spaced apart from each other in the x direction. Because the set of Caps includes four FeCaps C spaced apart from each other in the z direction FE , so the first set of plate line electrodes PL in the first column 1 may include first to fourth plate line electrodes PL spaced apart from each other in the z direction 11 To PL 14 , and the second set of plate line electrodes PL in the second column 2 may include first to fourth plate line electrodes PL spaced apart from each other in the z direction 21 To PL 24 Although the FeRAM embodiment is described as having four FeCaps, this is for illustration purposes only, and other numbers of FeCaps may be employed in the device without departing from the scope of the present disclosure and claims.

[0018] In various embodiments, the 3D FeRAM 100 may have the above connection relationship and may have a plurality of FeCap C FE (For example, four FeCap C FE ) is connected to a select transistor S-Tr. Therefore, the 3D FeRAM 100 can be described as a 1TnC structure, which means that n (n is an integer greater than or equal to 2) capacitors (Cap) are connected to a common transistor (Tr). For reference, Figure 1In the circuit diagram of FIG. 1 , as indicated by the thick dashed line and the thick double-dashed line, when the first bit line BL1 and the first word line WL1 are selected, the selection transistor S-Tr located on the left side in the x direction may be turned on, and the first bit line BL1 and the first group plate line electrode PL 1 The first plate line electrode PL 11 When selected, the information can be stored in the corresponding FeCap C FE or from the corresponding FeCap C FE In the case of reading, a sense amplifier (SA) connected to the first bit line BL1 can be used. Figure 1 In the circuit diagram of , (sel) may represent a selected line, and (N-sel) may represent a non-selected line.

[0019] In various embodiments of the 3D FeRAM 100, a plurality of FeCap C connected to the source / drain of the select transistor S-Tr FE In the z direction, they are spaced apart and can form a quadrilateral columnar shape facing one direction, such as the x direction. FE The capacitors are formed on five surfaces including the four side surfaces and the bottom surface of the quadrilateral pillar, so the capacitance per unit area can be significantly increased, where the capacitance can be increased in proportion to the number of capacitors (e.g., each FeCap C connected to the source / drain FE have substantially the same capacitance). Moreover, compared with a typical vertical stack (VS)-DRAM structure, since unit transistors may not be used, the process difficulty / distribution may be significantly reduced.

[0020] Figure 2A and Figure 2B are respectively a perspective view and a top view of a 3D FeRAM according to an embodiment, and Figure 2A is with Figure 2B A perspective view of the portion corresponding to a word line in a 3D FeRAM. FIG. 3A to FIG. 3C yes Figure 2B An enlarged plan view and cross-sectional view of a portion A of a 3D FeRAM, where Figure 3B is along Figure 3A A cross-sectional view taken along line XX', and Figure 3C is along Figure 3A The cross-sectional view taken along the line Y-Y' is shown below. Figure 1 Given the Figure 2A and Figure 2B Description of the above reference Figure 1 The description that has been given may be briefly given or may be omitted.

[0021] refer to Figures 2A to 3C According to the present embodiment, the 3D FeRAM 100 includes a substrate 101, a bit line 110, a word line 120, a semiconductor pattern 130, and a FeCap 140, for example, Figure 3B The 3D FeRAM 100 according to the present embodiment may have a horizontally symmetrical structure around a first center line C1 between the second electrodes 145 of two FeCaps 140 adjacent to each other in the x direction or a second center line C2 between the first electrodes 141 of two FeCaps 140 adjacent to each other in the x direction, for example, Figure 2B shown.

[0022] In various embodiments, the substrate 101 may include silicon (Si), such as single crystal silicon, polycrystalline silicon, or amorphous silicon. However, the material of the substrate 101 is not limited to Si. For example, according to some embodiments, the substrate 101 may include a Group IV semiconductor including but not limited to germanium (Ge), a Group IV-IV compound semiconductor such as silicon germanium (SiGe) or silicon carbide (SiC), or a Group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0023] In various embodiments, the substrate 101 may be a Si bulk substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate. The substrate 101 is not limited to a bulk substrate, an SOI substrate, or a GeOI substrate, and may also be a substrate based on an epitaxial wafer, a polished wafer, or an annealed wafer. The substrate 101 may include a conductive region, such as a well doped with impurities or various structures doped with impurities. Moreover, depending on the type of impurity ions doped into the substrate 101, the substrate 101 may be configured as a P-type substrate or an N-type substrate. Peripheral circuits and wiring layers connected to the peripheral circuits may be arranged on a portion of the substrate 101.

[0024] In various embodiments, the bit lines 110 extend along the x-direction on the substrate 101 and may be arranged to be spaced apart from each other in the y-direction. The bit lines 110 may be arranged to be connected to the selection transistor S-Tr, and more specifically, to the impurity region 135 of the selection transistor S-Tr. The impurity region 135 may correspond to the source / drain region of the selection transistor S-Tr. The bit lines 110 may include a conductive material, wherein the bit lines 110 may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a metal semiconductor compound, or a combination thereof.

[0025] In various embodiments, the word lines 120 may be disposed above the bit lines 110 in a vertical direction (eg, z-direction) on the substrate 101 and spaced apart from the bit lines 110. The word lines 120 may extend in a y-direction on the bit lines 110 and may be arranged to be spaced apart from each other in an x-direction. Figure 3B As shown, the word lines 120 may be arranged on both sides of the semiconductor patterns 130 in the x direction, wherein the semiconductor patterns 130 are located between the word lines 120. For example, the word lines 120 may include a left word line 1201 and a right word line 120r with the semiconductor pattern 130 therebetween, for example, as shown in FIG. Figure 2A For example, Figure 3B As shown, the gate dielectric layer 122 may be disposed between the semiconductor pattern 130 and the word line 120. According to various embodiments, the word line 120 may be located only on one side of the semiconductor pattern 130 in the x-direction. The word line 120 may include a conductive material, wherein the word line 120 may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a metal semiconductor compound, or a combination thereof.

[0026] In various embodiments, the semiconductor patterns 130 may be arranged at specific predetermined intervals in the x-direction and the y-direction. For example, the semiconductor patterns 130 may be arranged at positions where the bit lines 110 are located along the x-direction. Moreover, the semiconductor patterns 130 may be arranged to be spaced apart from each other in the y-direction on the corresponding word lines 120 through the gate dielectric layer 122 therebetween. In other words, the semiconductor patterns 130 may be disposed at intersections where the word lines 120 intersect the bit lines 110.

[0027] In various embodiments, the semiconductor pattern 130 may include a channel region 132 located at a central portion thereof in the z direction and impurity regions 135 corresponding to sources / drains located at both sides of the channel region 132 in the z direction. The word line 120 may be located on the channel region 132 and the gate dielectric layer 122 may be located between the word line 120 and the channel region 132. The semiconductor pattern 130 and the word line 120 may constitute a selection transistor S-Tr, and the bit line 110 may be electrically connected to the first impurity region 135 located at one side of the semiconductor pattern 130, and the FeCap 140 may be connected to the second impurity region 135 located at a side of the semiconductor pattern 130 opposite to the first impurity region 135.

[0028] In various embodiments, the semiconductor pattern 130 may include an undoped semiconductor material or a doped semiconductor material. According to various embodiments, the semiconductor pattern 130 may include a semiconductor material such as single crystal Si, polycrystalline Si, SiGe, or SiC. According to various embodiments, the semiconductor pattern 130 may include a 2D semiconductor material including a transition metal dichalcogenide (TMD), including but not limited to CuS 2 ,CuSe 2 ,WSe 2 、MoS 2 、MoSe 2 and WS 2, hexagonal boron nitride (h-BN), graphene, carbon nanotubes (CNT), and combinations thereof. According to various embodiments, the semiconductor pattern 130 may include an amorphous metal oxide semiconductor material, a polycrystalline metal oxide semiconductor material, or a combination thereof. For example, the metal oxide semiconductor material may include, but is not limited to, indium zinc-based oxide (IZO), zinc tin-based oxide (ZTO), indium gallium-based oxide (IGO), yttrium zinc-based oxide (YZO), and indium gallium zinc-based oxide (IGZO). However, the materials constituting the semiconductor pattern 130 are not limited to the above materials.

[0029] In various embodiments, the semiconductor pattern 130 may have a quadrilateral columnar structure corresponding to the quadrilateral columnar structure of the main body portion 141b of the first electrode 141 of the FeCap 140. For example, the semiconductor pattern 130 may have a quadrilateral columnar shape extending in the z direction, such as Figure 2A The semiconductor pattern 130 may include a channel region 132 located at a central portion thereof in the z direction and impurity regions 135 located at both sides of the channel region 132 in the z direction, for example, Figure 3B The lower impurity region 135 may be connected to the bit line 110 , and the upper impurity region 135 may be connected to the first electrode 141 of the FeCap 140 , wherein the upper impurity region 135 and the lower impurity region 135 are located on opposite sides of the channel region 132 .

[0030] The impurity region 135 may be formed by implanting dopant ions into both sides of the semiconductor pattern 130 in the z direction, wherein the implanted dopant may be an n-type dopant or a p-type dopant. The impurity region 135 may form the source junction and drain junction of the selection transistor S-Tr. As described above, the semiconductor pattern 130 and the word line 120 corresponding to the portion thereof may constitute the selection transistor S-Tr. Moreover, the semiconductor pattern 130 may include a channel region 132 disposed adjacent to the word line 120 and passing through the gate dielectric layer 122 between the semiconductor pattern 130 and the word line 120, and may include an impurity region 135 corresponding to the source / drain located on both sides of the channel region 132 in the z direction. A silicide layer may be formed between the impurity region 135 and the bit line 110 and between the impurity region 135 and the first electrode 141 as an ohmic contact with a metal. The silicide film may include, for example, at least one of titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide.

[0031] In various embodiments, the FeCap 140 may include a first electrode 141, a ferroelectric layer 143, and a second electrode 145. The FeCaps 140 may be each disposed on the semiconductor pattern 130 or the selection transistor S-Tr and electrically connected to the semiconductor pattern 130 or the selection transistor S-Tr, wherein the FeCaps 140 may be disposed at a cross-point position where the word line 120 crosses the bit line 110 with respect to the xy plane and close to each other.

[0032] In various embodiments, the first electrode 141 may include a main body portion 141b extending in a vertical direction (e.g., z-direction) on the substrate 101 and a plurality of horizontal extensions 141he extending from a side surface of the main body portion 141b in an x-direction. The plurality of horizontal extensions 141he may be located at different levels along the z-direction (e.g., at different vertical distances from the substrate 101). Figure 3B As shown, the first electrodes 141 are commonly connected to the FeCap C formed by the horizontal extension 141he. FE , and thus the first electrode 141 may be referred to as a common electrode. Also, the first electrode 141 connected to one semiconductor pattern 130 may have a structure in which the entire first electrode 141 is integrally connected to the semiconductor pattern 130 .

[0033] In various embodiments, the main body portion 141b may have a quadrilateral columnar shape. Figure 3B As shown, the horizontal cross-section of the body portion 141b may have a quadrilateral shape. The body portion 141b may extend through the etch stop layer 150 and be electrically connected to the semiconductor pattern 130 at the bottom surface of the body portion 141b. The etch stop layer 150 may be disposed on the first insulating layer 103a, the surface of the substrate 101 and located above the bit line 110, the word line 120 and the semiconductor pattern 130.

[0034] In various embodiments, the horizontal extension portion 141he may extend from the side surface of the main body portion 141b in the x-direction, wherein the horizontal extension portion 141he may have a quadrilateral column shape (e.g., a strip shape) extending in the x-direction. In other words, the horizontal extension portion 141he may have a quadrilateral column shape lying flat in the x-direction (i.e., oriented in the x-direction). Figure 3C As shown, the vertical cross section of the horizontal extension portion 141he perpendicular to the x direction may have a quadrilateral shape. Also, the vertical cross section of the horizontal extension portion 141he perpendicular to the y direction may have a quadrilateral shape elongated in the x direction.

[0035] exist Figure 3B, three horizontal extensions 141he are shown to be arranged on the main body portion 141b, wherein the three horizontal extensions 141he and the main body portion 141b are connected to form an "E" shape. However, the number of horizontal extensions 141he arranged along one main body portion 141b is not limited to three. For example, in the 3D FeRAM 100 according to the present embodiment, one, two, four or more horizontal extensions 141he may be arranged along the main body portion 141b.

[0036] In various embodiments, such as Figure 3B As shown, the horizontal extensions 141he of two main body portions 141b adjacent to each other in the x-direction may extend in opposite directions to each other in the x-direction. For example, in the x-direction, the main body portion 141b and the horizontal extension 141he of the first first electrode 141, the horizontal extension 141he and the main body portion 141b of the second first electrode 141, and the main body portion 141b and the horizontal extension 141he of the third first electrode 141 may be arranged in the stated order. Therefore, the horizontal extension 141he of the first first electrode 141 and the horizontal extension 141he of the second first electrode 141 are adjacent to each other, and the main body portion 141b of the second first electrode 141 and the main body portion 141b of the third first electrode 141 may be adjacent to each other.

[0037] In various embodiments, the first electrode 141 may be a conductive material, including but not limited to doped semiconductor materials, metals, conductive metal nitrides, and conductive metal oxides. The metal may include, for example, ruthenium, iridium, titanium, tantalum, etc. The conductive metal nitride may include, for example, titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc. The conductive metal oxide may include, for example, iridium oxide, niobium oxide, etc. However, the materials constituting the first electrode 141 are not limited to the above materials.

[0038] In various embodiments, the ferroelectric layer 143 may have a structure covering the outer side surface of the first electrode 141, wherein the ferroelectric layer 143 may surround at least a portion of the main body portion 141b. The ferroelectric layer 143 may cover the four side surfaces of the main body portion 141b of the first electrode 141, wherein the ferroelectric layer 143 is located between the horizontal extensions 141he. For example, the portion of the ferroelectric layer 143 covering the main body portion 141b may have a ring shape of a quadrilateral tube extending in the z direction. Thus, for example, Figure 3A As shown, at a level where there is no horizontal extension 141he, a horizontal cross-section perpendicular to the z-direction of a portion of the ferroelectric layer 143 covering the main body portion 141b may have a quadrilateral ring shape.

[0039] In various embodiments, the ferroelectric layer 143 may cover the outer side surface, the top surface, the bottom surface, and the end surface of the horizontal extension portion 141he of the first electrode 141, for example, Figure 3B As shown. The ferroelectric layer 143 may cover the four side surfaces and the bottom surface of the horizontal extension portion 141he. For example, the portion of the ferroelectric layer 143 covering the horizontal extension portion 141he may have a ring shape of a quadrilateral tube extending in the x direction, with a closed distal end and connected to the main body portion 141b at a proximal end. Figure 3C As shown, the vertical cross section perpendicular to the x-direction of the portion of the ferroelectric layer 143 covering the horizontal extension 141he may have a quadrilateral ring shape. Figure 3B As shown, a vertical cross section perpendicular to the y direction of a portion of the ferroelectric layer 143 covering the horizontal extension 141he may have shape (e.g., a square-cornered "C" shape).

[0040] As for the overall structure of the ferroelectric layer 143, the ferroelectric layer 143 has a vertical quadrilateral tubular portion extending along the z direction corresponding to the main part 141b and a horizontal quadrilateral tubular portion extending along the x direction corresponding to the horizontal extension 141he. The vertical quadrilateral tubular portion can make both ends (such as the top and the bottom) open in the z direction, and the horizontal quadrilateral tubular portion can make one end closed in the x direction. In addition, on one side of the vertical quadrilateral tubular portion, the portion corresponding to the horizontal extension 141he can be open, and the horizontal quadrilateral tubular portion can be connected thereto. At the same time, corresponding to the first electrode 141, the ferroelectric layer 143 can also have a structure in which the entire ferroelectric layer 143 is connected as a whole, thereby forming a continuous layer on the main part 141b and the horizontal extension 141he.

[0041] In various embodiments, the ferroelectric layer 143 may include a ferroelectric material, wherein for example, the ferroelectric layer 143 may include a hafnium (Hf)-based oxide. The Hf-based oxide may include hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), and hafnium silicon oxynitride (HfSiON). When the ferroelectric layer 143 includes an Hf-based oxide, the ferroelectric layer 143 may include at least one dopant among Zr, Si, Al, Y, Gd, La, Sc, and Sr. However, the materials constituting the ferroelectric layer 143 are not limited to the above materials.

[0042] In various embodiments, the ferroelectric layer 143 may include a single film or multiple layers. When the ferroelectric layer 143 includes multiple layers, the outermost layers located on both sides may include ferroelectric thin films, for example, the ferroelectric layer 143 may have a three-layer structure including a first ferroelectric thin film, an AlO thin film, and a second ferroelectric thin film. In various embodiments, the ferroelectric layer 143 may have a five-layer structure including a first ferroelectric thin film, a first AlO thin film, a second ferroelectric thin film, a second AlO thin film, and a third ferroelectric thin film. However, the multilayer structure of the ferroelectric layer 143 is not limited to a three-layer or five-layer structure.

[0043] In various embodiments, the second electrode 145 may include, for example, Fig. 13B The cover portion 145c shown and the Figure 2A The cover portion 145c of the second electrode 145 may cover the horizontal quadrilateral tubular portion of the ferroelectric layer 143, wherein the cover portion 145c may surround the ferroelectric layer 143 on the horizontal extension portion 141he. For example, the cover portion 145c may have a quadrilateral tube shape extending in the x direction and having one end closed. Fig. 13C As shown, the vertical cross section of the cover portion 145c perpendicular to the x direction may have a quadrilateral ring shape. Fig. 13B As shown, the vertical cross section of the cover portion 145c perpendicular to the y direction may have shape (e.g., a square-cornered "C" shape).

[0044] In various embodiments, in the closed quadrilateral tubular shape of the cover portion 145c, the closed end can be thicker than the other four sides, such as Fig. 13B For example, in In the shape, the vertical portion may be thicker than the upper horizontal portion and the lower horizontal portion. This is because, as indicated by the dotted line, during the process of forming the second electrode 145, a portion of the initial second electrode (in Figure 8B 145i) merges with the closed distal end of the cover portion 145c. FIG. 5A to FIG. 15C The thickness of the closed end of the cover portion 145c is described in more detail.

[0045] In various embodiments, for example, Figure 3A and Figure 3BAs shown, the extension 145e may extend from the closed end of the cover portion 145c in the y direction. For example, the extension 145e may correspond to a portion of the initial second electrode 145i, which does not include the portion of the initial second electrode 145i that meets the closed end of the cover portion 145c. The extension 145e may connect the second electrodes 145 located at the same level in the z direction to each other along the y direction. Therefore, the closed end of the cover portion 145c of the second electrode 145 and the extension 145e may form a plate line shape extending in the y direction at the same level in the z direction. Therefore, the second electrode 145 may be referred to as a plate line electrode. The second electrode 145 may include a conductive material substantially the same as the first electrode 141. However, according to various embodiments, the conductive material included in the second electrode 145 may be different from the conductive material of the first electrode 141.

[0046] Furthermore, a portion of the substrate 101 (excluding the portion of the substrate 101 corresponding to the bit line 110, the word line 120, the semiconductor pattern 130, the FeCap 140, and the etch stop layer 150) may be covered by the insulating layer 103, for example, as shown in FIG. Figure 3B The insulating layer 103 may include, for example, an oxide layer, such as a silicon oxide layer (SiO 2 ). However, the material constituting the insulating layer 103 is not limited to the oxide layer. FIG. 3A to FIG. 3C The insulating layer 103 is shown to be separated into a first insulating layer 103a and a second insulating layer 103b. However, the difference between the first insulating layer 103a and the second insulating layer 103b is the formation time, wherein the first insulating layer 103a is formed before the second insulating layer 103b, and the first insulating layer 103a and the second insulating layer 103b may both include the same material, such as an oxide layer.

[0047] As described above, the first electrode 141, the ferroelectric layer 143, and the second electrode 145 may constitute the FeCap 140. Due to the hysteresis characteristics of the ferroelectric layer 143 relative to the polarization of the dielectric, this FeCap 140 may store information values, such as "0" or "1". Each second electrode 145 may constitute a capacitor. In other words, in the FeCap 140, the horizontal extension 141he of the first electrode 141, the horizontal quadrilateral tubular portion of the ferroelectric layer 143, and the cap portion 145c of the second electrode 145 may constitute a capacitor. As a result, as Figure 3B As shown, one first electrode 141 and one ferroelectric layer 143 may meet three separated second electrodes 145 to form three FeCaps 140 , wherein the three FeCaps 140 may be connected to one semiconductor pattern 130 or one selection transistor S-Tr.

[0048] For reference, FeRAM can be distinguished into a 1Tr1Cap (i.e., 1T1C) type device in which one FeCap is set in one transistor Tr and a 1Tr type device in which the gate dielectric layer of the field effect transistor (FET) is replaced with a ferroelectric layer (similar to FET). For example, the 3D FeRAM 100 according to the present embodiment may belong to the 1Tr1Cap type. The 3D FeRAM 100 according to the present embodiment may have n FeCaps arranged at one selection transistor S-Tr. Therefore, the 3D FeRAM 100 may have a 1TrnCap structure, i.e., a 1TnC structure having a plurality of separate capacitors FeCap.

[0049] In various embodiments, the 3D FeRAM 100 has a 1TnC structure, and may also have a columnar structure in which the FeCap 140 is oriented in a lateral direction (e.g., an x ​​direction), wherein the columnar structure is substantially parallel to the plane of the substrate 101. The flat columnar shape portion of the FeCap 140 is a portion constituting a capacitor, and the flat columnar portion may have, for example, a quadrilateral columnar shape. Therefore, the memory window (MW) per unit area of ​​the 3D FeRAM 100 may be significantly increased. Moreover, compared to the VS-DRAM structure, in the 3D FeRAM 100, a selection transistor S-Tr is provided, and there is no cell transistor for each layer, so it is very advantageous in terms of process difficulty / distribution.

[0050] Moreover, the 1T1C structure and the 1TnC structure can solve the durability problem of FeRAM (e.g., FeFET) having a 1Tr structure, and can also solve the problem of VS-DRAM requiring a stacked single crystal Si channel due to a leakage problem. Therefore, due to the 1TnC structure of the 3D FeRAM 100, leakage problems do not occur even when polysilicon is used in the semiconductor pattern 130 constituting the channel. Moreover, in the 3D FeRAM 100, the second electrodes 145 can be separated from each other in the z direction. In this regard, since the second electrodes 145 are separated from each other in the z direction, the read interference problem caused by the structure in which all the second electrodes 145 are combined with each other can be solved, and thus the reliability of the FeRAM can be significantly improved.

[0051] Figure 4A and Figure 4B is an equivalent circuit diagram and a cross-sectional diagram of a 3D FeRAM according to an embodiment, wherein Figure 4B The cross-sectional view corresponds to Figure 3B The above reference will be briefly given or omitted. Figures 1 to 3C Description already given.

[0052] refer to Figure 4A and Figure 4B , the 3D FeRAM 100a may be different from the gate line 120a, the structure of the semiconductor pattern 130a corresponding thereto, and the additionally provided source line 160. Figure 3B According to the present embodiment, in the 3DFeRAM 100a, the bit line 110, the FeCap 140 and the etch stop layer 150 are the same as those in the above embodiment. Figure 3B However, when the FeCap 140 is connected to the floating gate FG 120-2 of the storage transistor Sto-Tr, the FeCap C FE The floating gate FG may be additionally arranged in the y direction, such as Figure 4A As indicated by the thin solid and dotted lines in FIG. FE can be included together in the unit pixel Unit-Cell. In addition, Figure 4A shows word lines WL0 to WL3 connected to FeCap C FE , and the word lines WL0 to WL3 may correspond in terms of circuit connection to Figure 1 3D FeRAM 100 of the circuit diagram of the plate line electrode PL. Therefore, the word lines WL0 to WL3 may correspond to Figure 4B The second electrode 145 is provided.

[0053] In various embodiments, the gate line 120a may include a lower gate line 120-1 and an upper gate electrode 120-2, wherein the upper gate electrode 120-2 may be separated from the lower gate line 120-1 by the second impurity region ImA2. The lower gate lines 120-1 may extend in the y direction and may be arranged to be spaced apart from each other in the x direction. For example, the lower gate lines 120-1 may be spaced apart from each other in the x direction. Figure 3B The word line 120 in the 3D FeRAM 100 is arranged in substantially the same structure. The lower gate line 120-1 may constitute a control transistor Con-Tr together with the lower semiconductor pattern 130-1. Therefore, the lower gate line 120-1 may be referred to as a control gate line.

[0054] In various embodiments, the upper gate electrode 120-2 may be disposed on the lower gate line 120-1 and may be located at the intersection position where the lower gate line 120-1 overlaps the bit line 110. The upper gate electrode 120-2 has a substantially quadrilateral columnar shape and may be electrically connected to the first electrode 141 of the FeCap 140 through the top surface of the upper gate electrode 120-2. The upper gate electrode 120-2 may constitute a storage transistor Sto-Tr together with the upper semiconductor pattern 130-2. Moreover, since the power supply will not be connected to the upper gate electrode 120-2, the upper gate electrode 120-2 may be in a floating state. Therefore, the upper gate electrode 120-2 may be referred to as a floating gate FG.

[0055] In various embodiments, the semiconductor pattern 130a may include a lower semiconductor pattern 130-1 and an upper semiconductor pattern 130-2. The lower semiconductor pattern 130-1 may include a lower channel region 132-1 and a lower impurity region 135-1. The upper semiconductor pattern 130-2 may include an upper channel region 132-2 and an upper impurity region 135-2.

[0056] In various embodiments, the lower channel region 132-1 may be disposed on both sides of the lower gate line 120-1 in the x-direction, and the lower gate dielectric layer 122-1 is located between the lower channel regions 132-1. The lower impurity region 135-1 may be disposed on both sides of the lower channel region 132-1 in the z-direction. For example, the lower impurity region 135-1 may include a first impurity region ImA1 disposed below the lower channel region 132-1 in the z-direction and a second impurity region ImA2 disposed above the lower channel region 132-1 in the z-direction.

[0057] In various embodiments, the upper channel region 132-2 may surround four side surfaces of the upper gate electrode 120-2, and the upper gate dielectric layer 122-2 is located between the upper channel regions 132-2. The upper impurity region 135-2 may be disposed on both sides of the upper channel region 132-2 in the z direction. For example, the upper impurity region 135-2 may include a second impurity region ImA2 disposed below the upper channel region 132-2 in the z direction and a third impurity region ImA3 disposed above the upper channel region 132-2 in the z direction. The second impurity region ImA2 may correspond to a shared impurity region commonly used by the lower impurity region 135-1 and the upper impurity region 135-2.

[0058] In various embodiments, the source line 160 may extend in parallel with the bit line 110 in the x direction and may be arranged to be spaced apart in the y direction, wherein the source line 160 may be above the bit line 110 and separated from the bit line 110 by the first insulating layer 103a. The source line 160 may be electrically connected to the upper semiconductor pattern 130-2. The source line 160 may be electrically connected to the third impurity region ImA3 of the upper semiconductor pattern 130-2. The source line 160 may be located above the upper gate electrode 120-2 and immediately below the etch stop layer 150 in the z direction.

[0059] In various embodiments, the 3D FeRAM 100a has a 2TnC structure, and the FeCap 140 may have a shape of a column laid in a lateral direction (e.g., x direction). Therefore, the MW per unit area of ​​the 3D FeRAM 100a may be significantly increased. Moreover, compared to the VS-DRAM structure, in the 3D FeRAM 100a, a control transistor Con-Tr and a storage transistor Sto-Tr are arranged, and there is no unit transistor for each layer, so it is very advantageous in terms of process difficulty / distribution.

[0060] FIG. 5A to FIG. 15C is a schematic diagram showing the manufacturing Figure 2B Plan and cross-sectional views of the 3D FeRAM process. Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A Corresponds to Figure 3A , Figure 5A , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B Corresponds to Figure 3B ,as well as Figure 5B , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C Corresponds to Figure 3C In addition, for ease of understanding, Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A In the example, the portion Y-Y' moves slightly toward the wire-cut region LC. FIG. 3A to FIG. 3C Given FIG. 5A to FIG. 15C The description above will be briefly given or omitted. Figures 1 to 3C Description already given.

[0061] refer to Figure 5A and Figure 5B According to the method of manufacturing the 3D FeRAM 100, a bit line 110, a word line 120, a semiconductor pattern 130, and an etch stop layer 150a are formed on a substrate 101. As described above, the bit line 110 may extend in the x direction on the substrate 101, and may be arranged to be spaced apart from each other in the y direction. The word line 120 may be arranged in the z direction on the substrate 101 and located above the bit line 110, extending in the y direction, and spaced apart from each other in the x direction. The semiconductor pattern 130 may be arranged at a specific predetermined interval in the x direction and the y direction, wherein the semiconductor pattern 130 may form an array. For example, the semiconductor pattern 130 is arranged in the x direction where the bit line 110 is arranged, and the semiconductor pattern 130 may also be arranged to be spaced apart from each other in the y direction on the corresponding word line 120, and the gate dielectric layer 122 is located between the semiconductor pattern 130 and the corresponding word line 120. The etch stop layer 150a may be provided on the entire surface of the substrate and located above the bit line 110, the word line 120, and the semiconductor pattern 130. A first insulating layer 103 a may be located on the bit line 110 and the substrate 101 , and an etch stop layer 150 a is formed on the first insulating layer 103 a , wherein the first insulating layer 103 a may separate the bit line 110 from the etch stop layer 150 a .

[0062] In various embodiments, (multiple) first insulating layers 103a and (multiple) sacrificial layers 105 are alternately stacked on the etch stop layer 150a. The first insulating layer 103a and the sacrificial layer 105 may include materials having an etching selectivity relative to each other, wherein, for example, the first insulating layer 103a may include materials such as silicon oxide (SiO 2 ) layer, and the sacrificial layer 105 may include a nitride layer such as a silicon nitride (SiNx) layer. However, the materials constituting the first insulating layer 103a and the sacrificial layer 105 are not limited to the above materials. The etch stop layer 150a may include a material having an etching selectivity with respect to the first insulating layer 103a and the sacrificial layer 105. However, because the first insulating layer 103a is directly formed on the etch stop layer 150a, according to some embodiments, the etch stop layer 150a may include a material having an etching selectivity with respect to the first insulating layer 103a, such as a nitride layer.

[0063] refer to FIG. 6A to FIG. 6C After forming the first insulating layer 103a and the sacrificial layer 105, a first trench T1 corresponding to the wire cutting region LC is formed. The first trench T1 extends in the y direction and may pass through the first insulating layer 103a and the sacrificial layer 105 and expose the etch stop layer 150a. Therefore, the wire cutting region LC may have a shape extending in the y direction on the xy plane and having a certain width in the x direction.

[0064] In various embodiments, the first insulating layer 103a and the sacrificial layer 105 may be exposed to the inner wall of the first trench T1. After the first trench T1 is formed, the exposed portion of the sacrificial layer 105 is removed by a partial pull-back process. Since a portion of the sacrificial layer 105 is removed by the partial pull-back process, a first horizontal recess HR1 may be formed at the location where the sacrificial layer 105 is located in the first trench T1.

[0065] Afterwards, refer to 7A to 7C , the first trench T1 and the first horizontal recess HR1 are filled with the second electrode material layer 145l. For example, the second electrode material layer 145l may include, but is not limited to, doped semiconductor materials, metals, conductive metal nitrides, and conductive metal oxides. Fig. 7A , a dotted line outside the wire cut region LC in the x direction indicates a region where a space formed by removing a portion of the sacrificial layer 105 thereunder is filled with the second electrode material layer 145 l .

[0066] refer to FIG. 8A to FIG. 8C , the first trench T1 corresponding to the wire cutting area LC is formed again. The first trench T1 extends in the y direction, can penetrate the second electrode material layer 145l and the first insulating layer 103a, and expose the etch stop layer 150a. When the first trench T1 is formed again, the second electrode material layers 145l located at different horizontal heights in the z direction can be separated from each other, and a portion of the first insulating layer 103a can be vertically located between the separated second electrode material layers 145l. The interlayer separation process of the electrode layer is called a node separation process. (Multiple) initial second electrodes 145i can be formed by the node separation process. Fig. 8A , a dotted line outside the wire cut region LC in the x direction indicates a region where a space formed by removing a portion of the sacrificial layer 105 thereunder is filled with the preliminary second electrode 145i.

[0067] refer to 9A to 9C Then, the first trench T1 is filled with a material substantially the same as the first insulating layer 103a. Fig.9A, a dotted line located outside the wire cut region LC in the x direction indicates a region where a preliminary second electrode 145i is formed in a space formed by removing a portion of the sacrificial layer 105 therebelow.

[0068] refer to FIG. 10A to FIG. 10C After forming the initial second electrode 145i, a second trench T2 is formed to separate the nodes of the FeCap 140. The second trench T2 can be formed as follows. First, a layer having a thickness corresponding to the thickness of the FeCap 140 is formed on the uppermost first insulating layer 103a. Fig. 10A A mask of the shape of the solid line shown in FIG. Thereafter, the first insulating layer 103 a and the sacrificial layer 105 thereunder are removed by an etching process using the mask, thereby forming a second trench T2. The etching stop layer 150 a may be exposed through the bottom surface of the second trench T2, wherein the removal of the first insulating layer 103 a and the sacrificial layer 105 stops at the etching stop layer 150 a.

[0069] refer to FIG. 11A to FIG. 11C , after forming the second trench T2, the second trench T2 is filled with a second insulating layer 103b. The second insulating layer 103b may include a material substantially the same as the first insulating layer 103a, such as an oxide layer. As described above, the difference between the first insulating layer 103a and the second insulating layer 103b may be only the formation time. For example, the insulating layer 103 formed before forming the second trench T2 may be the first insulating layer 103a, and the insulating layer 103 formed after forming the second trench T2 may be the second insulating layer 103b.

[0070] refer to FIG. 12A to FIG. 12C After forming the second insulating layer 103b, a third trench T3 is formed to form the FeCap 140. The third trench T3 may be formed at a location where the semiconductor pattern 130 or the selection transistor S-Tr is disposed on the xy plane. Fig. 12A As shown, the horizontal cross-section of the third trench T3 may have a quadrilateral shape. The insulating layer 103 and the sacrificial layer 105 may be exposed along the sidewalls of the third trench T3, and the etch stop layer 150a may be exposed at the bottom of the third trench T3.

[0071] After forming the third trench T3, the exposed portion of the sacrificial layer 105 is removed by a pull-back process. When the sacrificial layer 105 is completely removed by the pull-back process, a second horizontal recess HR2 may be formed on one side surface of the third trench T3 in the x-direction, wherein the range (e.g., depth) of the pull-back process may determine the length of the horizontal extension 141he.

[0072] Afterwards, refer to FIG. 13A to FIG. 13C The second electrode material layer filling the third trench T3 and the second horizontal recess HR2 is formed to a certain thickness. 7A to 7CThe second electrode material layer 1451 shown in FIG. is substantially the same. After that, the third trench T3 is formed again. By forming the third trench T3, the second electrode material layers of different levels are separated from each other. In other words, the node separation of the second electrode material layer is performed by forming the third trench T3. The second electrode 145 can be completed by node separation.

[0073] like Fig. 13B As indicated by the dotted line in FIG. 1 , the closed portion of the cover portion 145c of the second electrode 145 is a combined result of the initial second electrode 145i and the second electrode material layer filling the second horizontal recess HR2. Therefore, the closed portion of the cover portion 145c may be thicker than the four sides of the cover portion 145c.

[0074] refer to FIG. 14A to FIG. 14C After forming the second electrode 145, the ferroelectric layer 143a filling the third trench T3 and the second horizontal recess HR2 is formed to a certain thickness. The ferroelectric layer 143a may be formed on the side surface and the bottom surface of the third trench T3 and on the second electrode 145 in the second horizontal recess HR2. FIG. 3A to FIG. 3C The materials are the same as those described in the description of the 3D FeRAM 100 .

[0075] Afterwards, refer to FIG. 15A to FIG. 15C , remove the ferroelectric layer 143a on the bottom surface of the third trench T3. The ferroelectric layer 143 may be completed by removing the ferroelectric layer 143a on the bottom surface of the third trench T3. Moreover, the etch stop layer 150a may be exposed through the bottom of the third trench T3. Subsequently, the portion of the etch stop layer 150a exposed at the bottom surface of the third trench T3 is removed to expose the semiconductor pattern 130.

[0076] Afterwards, the first electrode 141 filling the third trench T3 and the second horizontal recess HR2 is formed. Figure 3B The 3D FeRAM 100 may be completed by forming the first electrode 141. Before the first electrode 141 is formed in the third trench T3, an impurity doping process may be performed on the semiconductor pattern 130 through the third trench T3.

[0077] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A 3D FeRAM, namely a three-dimensional ferroelectric random access memory, the 3D FeRAM comprising: Bit lines that extend along a first horizontal direction on a substrate and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; Word lines that are disposed above the bit lines, extend along the second horizontal direction, and are spaced apart from each other in the first horizontal direction; Semiconductor patterns that are disposed at corresponding portions of the word lines at intervals, and a gate dielectric layer is located between the semiconductor patterns and the corresponding portions of the word lines; And A FeCap structure, namely a ferroelectric capacitor structure, the FeCap structure being located above the semiconductor patterns in the vertical direction, Wherein, the FeCap structure comprises: A first electrode, the first electrode comprising a main body portion extending along the vertical direction from a corresponding one of the semiconductor patterns and at least two horizontal extension portions extending along the first horizontal direction from side surfaces of the main body portion and located at different horizontal heights; A ferroelectric layer that covers outer walls of the main body portion and the at least two horizontal extension portions; and A second electrode that covers portions of the ferroelectric layer located on each of the at least two horizontal extension portions.

2. The 3D FeRAM according to claim 1, wherein: Between the horizontal extension portions, the main body portion has a quadrilateral shape, and a portion of the ferroelectric layer covering the outer wall of the main body portion has a quadrilateral ring shape.

3. The 3D FeRAM according to claim 1, wherein: Each of the at least two horizontal extension portions has a shape of a quadrilateral column oriented in the first horizontal direction.

4. The 3D FeRAM according to claim 3, wherein: Each portion of the ferroelectric layer located on each of the at least two horizontal extension portions has a shape of a quadrilateral tube oriented in the first horizontal direction and having a closed distal end, A cross-section of each portion of the ferroelectric layer located on each of the at least two horizontal extension portions perpendicular to the first horizontal direction is a quadrilateral ring shape, and A cross-section of each portion of the ferroelectric layer located on each of the at least two horizontal extension portions perpendicular to the second horizontal direction is an "匸" shape.

5. The 3D FeRAM according to claim 3, wherein: Each of the second electrodes has a shape of a quadrilateral tube oriented in the first horizontal direction and having a closed distal end, A cross-section of each of the second electrodes perpendicular to the first horizontal direction is a quadrilateral ring shape, and A cross-section of each of the second electrodes perpendicular to the second horizontal direction is an "匸" shape.

6. The 3D FeRAM according to claim 5, wherein: The closed distal end of the quadrilateral tube of each of the second electrodes is thicker than four side portions of the quadrilateral tube of each of the second electrodes, and each of the second electrodes includes an extension portion extending along the second horizontal direction from the closed distal end of the quadrilateral tube, and Portions of the second electrodes located at the same horizontal height in the vertical direction are connected to each other through the extension portions.

7. The 3D FeRAM according to claim 1, wherein: An etch stop layer is located on a surface of the substrate and above the bit lines, word lines, and semiconductor patterns, and The main body portion penetrates through the etch stop layer and is electrically connected to a corresponding one of the semiconductor patterns.

8. The 3D FeRAM according to claim 1, wherein: The word lines are arranged at both sides of the semiconductor pattern in the first horizontal direction, and The semiconductor patterns each include a channel region located at a central portion of the semiconductor pattern in the vertical direction and an impurity region located between the channel region and the bit line and between the channel region and the body portion in the vertical direction.

9. The 3D FeRAM according to claim 1, wherein: The semiconductor patterns are arranged on both side surfaces of the word line in the first horizontal direction, and The 3D FeRAM further includes: a gate electrode located on the word line and electrically connected to the body portion, an upper semiconductor pattern surrounding four side surfaces of the gate electrode and an upper gate dielectric layer being located between the upper semiconductor patterns, and A source line is connected to the upper semiconductor pattern and extends along the first horizontal direction.

10. The 3D FeRAM according to claim 9, wherein: The semiconductor patterns each include: a channel region located at a central portion of the semiconductor pattern in the vertical direction; a first impurity region located below the channel region; and a second impurity region located above the channel region, and The upper semiconductor pattern includes an upper channel region located at a central portion of the upper semiconductor pattern, a second impurity region located below the upper channel region, and a third impurity region located above the upper channel region.

11. The 3D FeRAM according to claim 9, wherein: An etch stop layer is located on the surface of the substrate and over the gate electrode and the source line, and The body portion penetrates the etch stop layer and is electrically connected to the gate electrode.

12. A 3D FeRAM, i.e. a three-dimensional ferroelectric random access memory, wherein: substrate; bit lines extending along a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a selection transistor, the one selection transistor comprising a word line and a semiconductor pattern, the word line being arranged above the bit line in a vertical direction, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction, the semiconductor patterns being spaced apart in the second horizontal direction on corresponding portions of the word line and having a gate dielectric layer between the semiconductor pattern and the corresponding portion of the word line; as well as FeCap structure, i.e., ferroelectric capacitor structure, the FeCap structure having a plurality of capacitors on the one selection transistor, Wherein, the FeCap structure comprises: a first electrode including a main body portion extending from the corresponding semiconductor pattern along the vertical direction and n horizontal extensions extending from a side surface of the main body portion along the first horizontal direction; a ferroelectric layer covering an outer wall of the main body portion and outer walls of the n horizontal extensions; and a plurality of second electrodes, the plurality of second electrodes covering a portion of the ferroelectric layer located on each of the n horizontal extensions, Among them, the 3D FeRAM has a structure in which the plurality of capacitors are electrically connected to the one select transistor.

13. The 3D FeRAM according to claim 12, wherein: Each of the n horizontal extension portions has the shape of a quadrangular pillar oriented in the first horizontal direction. The portion of the ferroelectric layer on each of the n horizontal extension portions has the shape of a quadrangular tube with a closed distal end in the first horizontal direction. The cross-section of the portion of the ferroelectric layer on each of the n horizontal extension portions perpendicular to the first horizontal direction is a quadrangular ring shape, and The cross section of the portion of the ferroelectric layer located on each of the n horizontal extensions and perpendicular to the second horizontal direction is shape.

14. The 3D FeRAM according to claim 12, wherein: Each of the plurality of second electrodes has the shape of a quadrangular tube with a closed distal end in the first horizontal direction. The cross-section of each of the plurality of second electrodes perpendicular to the first horizontal direction is a quadrangular ring shape. The cross-section of each of the plurality of second electrodes perpendicular to the second horizontal direction is an "匸" shape. Each of the plurality of second electrodes includes an extension portion extending along the second horizontal direction from the closed end of the quadrangular tube, and Some of the second electrodes among the plurality of second electrodes located at the same horizontal height in the vertical direction are connected to each other through the extension portion.

15. The 3D FeRAM according to claim 12, wherein: The etch stop layer is located on the entire surface of the substrate and above the bit line, the word line, and the semiconductor pattern. The word line is arranged on both sides of the semiconductor pattern in the first horizontal direction. Each of the semiconductor patterns includes a channel region and an impurity region. The channel region is located at the central portion of the semiconductor pattern in the vertical direction. The impurity region is located between the channel region and the bit line and between the channel region and the main body portion in the vertical direction, and The main body portion penetrates the etch stop layer and is connected to the impurity region.

16. A 3D FeRAM, namely a three-dimensional ferroelectric random access memory, the 3D FeRAM includes: A substrate; A bit line, the bit line extending along a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; At least one transistor, the at least one transistor being located on the bit line; And A FeCap structure, namely a ferroelectric capacitor structure, the FeCap structure being located on the at least one transistor, Wherein, the FeCap structure includes: A first electrode, the first electrode includes a main body portion extending along the vertical direction from the at least one transistor and a plurality of horizontal extension portions extending along the first horizontal direction from the side surface of the main body portion and located at different horizontal heights; A ferroelectric layer, the ferroelectric layer covering the outer wall of the main body portion and the outer walls of the plurality of horizontal extension portions; and A plurality of second electrodes, the plurality of second electrodes covering the portion of the ferroelectric layer on each of the plurality of horizontal extension portions.

17. The 3D FeRAM according to claim 16, wherein: The at least one transistor includes one select transistor, and The one select transistor includes: word lines, the word lines being disposed above the bit lines in the vertical direction, extending along the second horizontal direction, and spaced apart from each other in the first horizontal direction; channel regions, the channel regions being arranged on corresponding portions of the word lines at intervals in the second horizontal direction and having a gate dielectric layer between the channel regions and the corresponding portions of the word lines; and Impurity regions are arranged on both sides of the channel region in the vertical direction.

18. The 3D FeRAM according to claim 17, wherein: The plurality of horizontal extensions are all in the shape of quadrilateral columns laid in the first horizontal direction, and When the first electrode, the portion of the ferroelectric layer located on each of the plurality of horizontal extensions, and the plurality of second electrodes constitute one FeCap, the 3DFeRAM has a structure in which a plurality of FeCaps are connected to the one selection transistor.

19. The 3D FeRAM according to claim 16, wherein: The at least one transistor includes a first transistor and a second transistor, the first transistor is a lower transistor, the second transistor is an upper transistor, and The first transistor comprises: gate lines, the gate lines being located above the bit lines in the vertical direction, extending along the second horizontal direction, and spaced apart from each other in the first horizontal direction; channel regions arranged at intervals on corresponding portions of the gate lines in the second horizontal direction and on both side surfaces of the gate lines in the first horizontal direction, and a gate dielectric layer is located between the channel regions; and a first impurity region and a second impurity region, wherein in the vertical direction, the first impurity region is located below the channel region, and the second impurity region is disposed above the channel region.

20. The 3D FeRAM according to claim 19, wherein: The second transistor comprises: a gate electrode, the gate electrode being located above the corresponding gate line and connected to the main body portion, an upper channel region, the upper channel region surrounding four side surfaces of the gate electrode and an upper gate dielectric layer being located between the upper channel regions; and a second impurity region and a third impurity region, wherein in the vertical direction, the second impurity region is located below the upper channel region, and the third impurity region is located above the upper channel region, and The 3D FeRAM further includes a source line extending along the first horizontal direction and connected to the third impurity region.

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