Memory chip and semiconductor package including same

Abstract

A memory chip and a semiconductor package including the same are provided. The memory chip includes a cell chip and a core-peripheral chip that are vertically stacked and electrically connected to each other. The cell chip includes cell regions, each of which includes a memory cell layer. The core-peripheral chip includes a core group region and a peripheral region adjacent to each other in a first direction. The core group region includes core regions arranged in rows in a second direction intersecting the first direction. Each core region comprises a core memory bank, and the core memory bank comprises a core circuit; and a neural processing unit (NPU) block, the NPU block including an NPU.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory chip and a semiconductor package including the memory chip. Background Art

[0002] A memory chip may include a plurality of circuit regions therein. For example, a memory chip may have a cell region that performs a storage function, and a core region and a peripheral region formed with circuits for driving the cell region and inputting / outputting data. At the same time, more circuits should be formed on a limited chip area to increase the integration density of the memory chip. Therefore, various studies are being conducted to develop a memory chip that can reduce the form factor and improve performance and a semiconductor package including the memory chip. Summary of the invention

[0003] Embodiments of the present disclosure may provide a memory chip having improved integration density and a semiconductor package including the memory chip.

[0004] Embodiments of the present disclosure may also provide a memory chip with improved performance and a semiconductor package including the memory chip.

[0005] According to an embodiment of the present disclosure, a memory chip is provided, and the memory chip includes: a unit chip; and a core-peripheral chip, wherein the unit chip and the core-peripheral chip are vertically stacked and electrically connected to each other, wherein the unit chip includes a unit area, each of the unit area includes a memory cell layer, wherein the core-peripheral chip includes at least one core group area and a peripheral area adjacent to each other in a first direction, wherein the at least one core group area includes core areas arranged in rows along a second direction intersecting the first direction, and wherein each of the core areas includes: a core memory body, the core memory body includes a core circuit; and a neural processing unit (NPU) block, the NPU block includes an NPU.

[0006] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a unit chip; a core-peripheral chip; and a through-silicon via (TSV), wherein the TSV electrically connects the unit chip and the core-peripheral chip to each other, wherein the unit chip and the core-peripheral chip are alternately stacked, wherein each of the unit chips includes a unit area for storing data, and wherein each of the core-peripheral chips includes a neural processing unit (NPU) block configured to perform data operations.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a plurality of memory chips, the plurality of memory chips are stacked vertically; and a through silicon via (TSV), the TSV electrically connecting the plurality of memory chips, wherein each of the plurality of memory chips includes a unit chip and a core-peripheral chip stacked vertically, wherein the unit chip includes: a unit area, each of the unit areas includes a memory cell layer, wherein the core-peripheral chip includes at least one core group area and a peripheral area adjacent to each other in a first direction, wherein the at least one core group area includes core areas arranged in rows along a second direction intersecting the first direction, and wherein each of the core areas includes: a core memory body, the core memory body having a core circuit; and a neural processing unit (NPU) block, the NPU block including an NPU.

[0008] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a packaging substrate; a host structure, the host structure being located on the packaging substrate; and a storage structure, the storage structure being horizontally spaced apart from the host structure on the packaging substrate and electrically connected to the host structure, wherein the storage structure includes a plurality of memory chips stacked vertically, wherein each of the plurality of memory chips includes a unit chip and a core-peripheral chip that are vertically stacked and electrically connected to each other, wherein the unit chip includes a unit area, each of the unit areas includes a storage unit layer, wherein the core-peripheral chip includes at least one core group area and a peripheral area adjacent to each other in a first direction, wherein the at least one core group area includes core areas arranged in rows along a second direction intersecting the first direction, and wherein each of the core areas includes: a core storage body, the core storage body including a core circuit; and a neural processing unit (NPU) block, the NPU block including an NPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 and Figure 2 is a perspective view illustrating a memory chip according to some embodiments of the present disclosure.

[0010] Figures 3 to 10 is a top view illustrating a core-periphery chip of a memory chip according to some embodiments of the present disclosure.

[0011] Figures 11 to 14 is a top view illustrating a unit chip of a memory chip according to some embodiments of the present disclosure.

[0012] FIG. 15A to FIG. 17B is a cross-sectional view illustrating a memory chip according to some embodiments of the present disclosure.

[0013] Fig.18 is a cross-sectional view illustrating a plurality of memory chips according to some embodiments of the present disclosure.

[0014] Fig.19 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present disclosure.

[0015] Fig. 20 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings.

[0017] It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected to or coupled to another element or layer, or there may be intermediate elements or layers. In contrast, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. As used herein, the expression "at least one of..." preceding a list of elements modifies the entire list of elements, without modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0018] Figure 1 and Figure 2 is a perspective view illustrating a memory chip according to some embodiments of the present disclosure.

[0019] refer to Figure 1 and Figure 2 , the memory chip 1000 may include a core-periphery chip 10 and a unit chip 20 stacked along a vertical direction VD. The core-periphery chip 10 and the unit chip 20 may overlap each other vertically. In some embodiments, as Figure 1 As shown, the unit chip 20 can be stacked on the core-periphery chip 10. In some embodiments, as shown in FIG. Figure 2 As shown, the core-periphery chip 10 may be stacked on the unit chip 20 .

[0020] When viewed in a top view, the core-periphery chip 10 may include a core region COR and a peripheral region PR. The core region COR and the peripheral region PR may be adjacent to each other in a horizontal direction. Each core region COR may include a core memory body COB (refer to Figure 3-Figure 9), and the core memory body COB may include core circuits such as sub-word line drivers, sense amplifiers, row decoders, column decoders, and read / write (R / W) circuits. The peripheral region PR may include peripheral circuits such as timing registers, address registers, data input registers, data output registers, and data input / output terminals.

[0021] When viewed in a top view, the unit chip 20 may include a unit region CR. The unit regions CR may be adjacent to each other in a horizontal direction. Each unit region CR may vertically overlap at least a portion of each core region COR. Each unit region CR may include a memory cell layer 210 (refer to Figures 15A-17B ), and the memory cell layer 210 can store data.

[0022] Hereinafter, the planar arrangement of components in the core-periphery chip 10 and the unit chip 20 will be described in more detail.

[0023] Figures 3 to 10 is a top view illustrating a core-periphery chip of a memory chip according to some embodiments of the present disclosure.

[0024] refer to Figures 3 to 10 The core-periphery chip 10 may have a first side surface 10a facing a first direction D1, a second side surface 10b opposite to the first side surface 10a, a third side surface 10c facing a second direction D2, and a fourth side surface 10d opposite to the third side surface 10c. The first direction D1 and the second direction D2 may be parallel to the bottom surface of the core-periphery chip 10 and may intersect each other.

[0025] Each core region COR may include a core memory body COB and a neural processing unit (NPU) block NB. The NPU block NB may include a neural processing unit (NPU) that performs data operations. For example, a core region COR may include a core memory body COB and an NPU block NB, and a core memory body COB and an NPU block NB may be adjacent to each other in the first direction D1 or the second direction D2. Since the core region COR includes the NPU block NB, the memory chip 1000 can be used as a processing in memory (PIM) that can perform data operations.

[0026] The peripheral region PR may be located on the central portion of the core-periphery chip 10. The central portion of the core-periphery chip 10 may be defined as a region of the core-periphery chip 10 disposed at equal distances from the first side surface 10a and the second side surface 10b of the core-periphery chip 10 and disposed at equal distances from the third side surface 10c and the fourth side surface 10d of the core-periphery chip 10. The peripheral region PR may be a region extending long along the second direction D2 on the central portion of the core-periphery chip 10.

[0027] The core region COR may include core regions COR arranged in a row along the second direction D2. The core regions COR arranged in a row may constitute a core group region COG. The core group region COG may be adjacent to the peripheral region PR in the first direction D1 or a direction opposite to the first direction D1.

[0028] The core group region COG may be provided in plurality. The plurality of core group regions COG may be sequentially arranged along the first direction D1. In other words, the core regions COR arranged in a row may be provided, and the core regions COR arranged in another row may be provided to be spaced apart from the core regions COR arranged in a row in the first direction D1.

[0029] For example, the core group region COG may include a first group COG1 adjacent to the peripheral region PR in a first direction D1, and a second group COG2 adjacent to the peripheral region PR in a direction opposite to the first direction D1. The first group COG1 and the second group COG2 may be spaced apart from each other in the first direction D1, with the peripheral region PR interposed between the first group COG1 and the second group COG2. The first group COG1 may be located between the peripheral region PR and the first side surface 10a of the core-periphery chip 10. The second group COG2 may be located between the peripheral region PR and the second side surface 10b of the core-periphery chip 10.

[0030] refer to Figure 3 , the core memory COB and the NPU block NB can be symmetrically arranged relative to the peripheral area PR (i.e., a line perpendicular to the first direction D1). For example, the NPU block NB and the core memory COB of the first group COG1 can be arranged sequentially along the first direction D1 from the peripheral area PR. The NPU block NB and the core memory COB of the second group COG2 can be arranged sequentially from the peripheral area PR in a direction opposite to the first direction D1. In other words, the core memory COB and the NPU block NB of the first group COG1 and the core memory COB and the NPU block NB of the second group COG2 can be symmetrically arranged relative to the peripheral area PR.

[0031] refer to Figure 4, the core memory COB and the NPU block NB may be arranged asymmetrically relative to the peripheral region PR (i.e., a line perpendicular to the first direction D1). For example, the NPU block NB and the core memory COB of the first group COG1 may be arranged sequentially from the peripheral region PR along the first direction D1. The core memory COB and the NPU block NB of the second group COG2 may be arranged sequentially from the peripheral region PR in a direction opposite to the first direction D1. In other words, the NPU block NB and the core memory COB of each of the first group COG1 and the second group COG2 may be arranged sequentially along the first direction D1. For example, the arrangement order of the NPU block NB and the core memory COB in the first group COG1 may be the same as the arrangement order of the NPU block NB and the core memory COB in the second group COG2.

[0032] refer to Figure 5 and Figure 6 , the core memory bodies COB and the NPU blocks NB in ​​each core region COR may be adjacent to each other in the second direction D2.

[0033] In some embodiments, Figure 5 As shown, the paired core regions COR may be adjacent to each other in the second direction D2, and the core memory bank COB and the NPU block NB of each of the paired core regions COR may be arranged sequentially along the second direction D2. In other words, the core memory bank COB and the NPU block NB of the paired core regions COR may be arranged asymmetrically with respect to a line perpendicular to the second direction D2. For example, the arrangement order of the core memory bank COB and the NPU block NB of the paired core regions COR may be the same.

[0034] In certain embodiments, such as Figure 6 As shown, the core memory COB and the NPU block NB of one of the paired core regions COR can be arranged sequentially along the second direction D2, and the core memory COB and the NPU block NB of the other of the paired core regions COR can be arranged sequentially in a direction opposite to the second direction D2. In other words, the core memory COB and the NPU block NB of the paired core regions COR can be arranged symmetrically with respect to a line perpendicular to the second direction D2. For example, the arrangement order of the core memory COB and the NPU block NB in ​​one of the paired core regions COR can be opposite to the arrangement order of the core memory COB and the NPU block NB in ​​the other of the paired core regions COR.

[0035] refer to Figures 7 to 9, a plurality of core group regions COG may be located between the peripheral region PR and the first side surface 10a of the core-periphery chip 10, and another plurality of core group regions COG may be located between the peripheral region PR and the second side surface 10b of the core-periphery chip 10. For example, Figures 7 to 9 As shown, the core group area COG may include a first group COG1, a second group COG2, a third group COG3, and a fourth group COG4. The first group COG1 may be located between the peripheral region PR and the first side surface 10a of the core-peripheral chip 10. The second group COG2 may be located between the peripheral region PR and the second side surface 10b of the core-peripheral chip 10. The third group COG3 may be located between the first group COG1 and the first side surface 10a of the core-peripheral chip 10, and may be adjacent to the first group COG1 in the first direction D1. The fourth group COG4 may be located between the second group COG2 and the second side surface 10b of the core-peripheral chip 10, and may be adjacent to the second group COG2 in the first direction D1. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the core group area COG may also include additional groups such as the fifth group and the sixth group.

[0036] refer to Figure 7 , the core memory COB and the NPU block NB may be symmetrically arranged relative to the peripheral region PR (i.e., a line perpendicular to the first direction D1 and passing through the peripheral region PR). The core memory COB and the NPU block NB of the first group COG1 may be arranged sequentially along the first direction D1. The core memory COB and the NPU block NB of the second group COG2 may be arranged sequentially in a direction opposite to the first direction D1. Therefore, the second group COG2 and the first group COG1 may be symmetrical relative to the peripheral region PR.

[0037] The NPU blocks NB and core banks COB of the third group COG3 may be sequentially arranged along the first direction D1. Therefore, the first and third groups COG1 and COG3 may be symmetrically disposed with respect to a line perpendicular to the first direction D1 and passing through the center between the first and third groups COG1 and COG3.

[0038] The NPU blocks NB and the core memory bodies COB of the fourth group COG4 may be sequentially arranged in a direction opposite to the first direction D1. Therefore, the second group COG2 and the fourth group COG4 may be symmetrically arranged with respect to a line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4. In addition, the fourth group COG4 and the third group COG3 may be symmetrical with respect to the peripheral region PR.

[0039] refer to Figure 8 ,picture Figure 7Similarly, the core memory body COB and the NPU block NB may be symmetrically arranged with respect to the peripheral region PR (ie, a line perpendicular to the first direction D1 and passing through the peripheral region PR). Figure 7 Differently, the NPU blocks NB and the core memory COB of the first group COG1 can be arranged sequentially along the first direction D1, and the NPU blocks NB and the core memory COB of the second group COG2 can be arranged sequentially in a direction opposite to the first direction D1. Therefore, the first group COG1 and the third group COG3 can be asymmetrically arranged relative to a line perpendicular to the first direction D1 and passing through the center between the first group COG1 and the third group COG3, and the second group COG2 and the fourth group COG4 can be asymmetrically arranged relative to a line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4. For example, the arrangement order of the NPU blocks NB and the core memory COB of the first group COG1 and the third group COG3 can be the same. For example, the arrangement order of the NPU blocks NB and the core memory COB of the second group COG2 and the fourth group COG can be the same.

[0040] refer to Fig. 9 , the core memory COB and the NPU block NB may be asymmetrically arranged relative to the peripheral region PR (i.e., a line perpendicular to the first direction D1 and passing through the peripheral region PR). For example, the NPU block NB and the core memory COB of each of the first group COG1, the second group COG2, the third group COG3, and the fourth group COG4 may be arranged sequentially along the first direction D1. In other words, the arrangement order of the NPU blocks NB and the core memory COB of the first group COG1, the second group COG2, the third group COG3, and the fourth group COG4 may be the same. The first group COG1 and the third group COG3 may be asymmetrically arranged relative to a line perpendicular to the first direction D1 and passing through the center between the first group COG1 and the third group COG3, and the second group COG2 and the fourth group COG4 may be asymmetrically arranged relative to a line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4.

[0041] refer to Fig.10, the core-periphery chip 10 may further include a through silicon via (TSV) 30 located in a central portion thereof. The TSV 30 may be located in the peripheral region PR. The TSV 30 may be located between the first group COG1 and the second group COG2. The TSV 30 may be distributed in a region extending in a second direction D2 on a central portion of the core-periphery chip 10. Each TSV 30 may extend vertically in the core-periphery chip 10, and, for example, each TSV 30 may penetrate at least a portion of the core-periphery chip 10. The TSV 30 of the core-periphery chip 10 may be electrically connected to the TSV 30 of the unit chip 20 (refer to Fig.14 ). In other words, the core-periphery chip 10 and the unit chip 20 of the memory chip 1000 may be electrically connected to each other.

[0042] Figures 11 to 14 is a top view illustrating a unit chip of a memory chip according to some embodiments of the present disclosure.

[0043] refer to Figures 11 to 14 The unit chip 20 may have a first side surface 20a facing the first direction D1, a second side surface 20b opposite to the first side surface 20a, a third side surface 20c facing the second direction D2, and a fourth side surface 20d opposite to the third side surface 20c.

[0044] Each cell region CR may include a cell memory cell CB. The cell memory cell CB may include a memory cell layer 210 (refer to Figures 15A-17B ), and the memory cell layer 210 can store data. For example, each cell region CR can vertically overlap at least a portion of each NPU block NB of the core-peripheral chip 10. Therefore, compared with the case where the cell region and the NPU block do not overlap each other, the distance between the cell region CR and the NPU block NB can be reduced. As a result, the data processing speed of the memory chip 1000 can be increased. In addition, the memory chip 1000 can be driven by low power, and problems such as noise and / or heat generation can be reduced or minimized.

[0045] The cell regions CR may be arranged along the first direction D1 and the second direction D2. For example, the cell regions CR may include cell regions CR arranged in rows along the second direction D2. The cell regions CR arranged in rows may constitute a cell group region CG. The cell group region CG may be provided in plurality, and the cell group regions CG may be adjacent to each other in the first direction D1.

[0046] For example, the unit group region CG may include a first group CG1 adjacent to the central portion of the unit chip 20 in the first direction D1, and a second group CG2 adjacent to the central portion of the unit chip 20 in a direction opposite to the first direction D1. The central portion of the unit chip 20 may be defined as a region of the unit chip 20 disposed at an equal distance from the first side surface 20a and the second side surface 20b of the unit chip 20 and disposed at an equal distance from the third side surface 20c and the fourth side surface 20d of the unit chip 20. The first group CG1 and the second group CG2 may be spaced apart from each other in the first direction D1, with the central portion of the unit chip 20 interposed between the first group CG1 and the second group CG2. The first group CG1 may be located between the first side surface 20a and the central portion of the unit chip 20. The second group CG2 may be located between the second side surface 20b and the central portion of the unit chip 20. In some embodiments, the unit group region CG may also include other groups such as the third group and the fourth group. The third group may be located between the first group CG1 and the first side surface 20 a of the unit chip 20 , and the fourth group may be located between the second group CG2 and the second side surface 20 b of the unit chip 20 .

[0047] refer to Fig.12 and Fig.13 Each unit region CR may further include an NPU buffer NBF. The NPU buffer NBF may include an NPU buffer memory for driving the NPU. The NPU buffer memory may include at least one of a new memory (e.g., a phase change random access memory (RAM) (PRAM) device, a spin-transfer torque magnetic RAM (STT-MRAM) device, and a ferroelectric RAM (FeRAM) device) and a static RAM (SRAM) device.

[0048] For example, one unit region CR may include one unit memory bank CB and one NPU buffer NBF. The unit memory bank CB and the NPU buffer NBF may be adjacent to each other in a horizontal direction (e.g., a first direction D1 or a second direction D2). Since the NPU buffer NBF is located on the unit region CR, the area of ​​the NPU block NB in ​​the core-peripheral chip 10 may be reduced. Therefore, the integration density in the core-peripheral chip 10 and the unit chip 20 may be appropriately adjusted by the NPU buffer NBF, thereby improving or maximizing the integration density of the memory chip 1000.

[0049] refer to Fig.12 , the unit memory banks CB and the NPU buffers NBF may be asymmetrically arranged with respect to the central portion of the unit chip 20 (i.e., a line perpendicular to the first direction D1 and passing through the central portion of the unit chip 20). For example, the arrangement order of the unit memory banks CB and the NPU buffers NBF of all the unit regions CR may be the same.

[0050] refer to Fig.13 , the unit memory bank CB and the NPU buffer NBF may be symmetrically arranged with respect to the central portion of the unit chip 20 (i.e., a line perpendicular to the first direction D1 and passing through the central portion of the unit chip 20). For example, the NPU buffer NBF and the unit memory bank CB of the first group CG1 may be sequentially arranged along the first direction D1 from the central portion of the unit chip 20, and the NPU buffer NBF and the unit memory bank CB of the second group CG2 may be sequentially arranged along the direction opposite to the first direction D1 from the central portion of the unit chip 20. In other words, the NPU buffer NBF and the unit memory bank CB of the first group CG1 and the NPU buffer NBF and the unit memory bank CB of the second group CG2 may be symmetrically arranged with respect to the central portion of the unit chip 20.

[0051] refer to Fig.14 , the unit chip 20 may further include a TSV 30 located in a central portion thereof. The TSV 30 may be located between the first group CG1 and the second group CG2. The TSV 30 may be distributed in a region extending in a second direction D2 on a central portion of the unit chip 20. Each TSV 30 may extend vertically in the unit chip 20, and, for example, each TSV 30 may penetrate at least a portion of the unit chip 20. The TSV 30 of the unit chip 20 may be electrically connected to the TSV 30 of the core-peripheral chip 10. The TSV 30 of the core-peripheral chip 10 and the unit chip 20 may be electrically connected to an external device, and may be used to send an electrical signal from the external device to the chip.

[0052] FIG. 15A to FIG. 17B is a cross-sectional view illustrating a memory chip according to some embodiments of the present disclosure.

[0053] refer to FIG. 15A to FIG. 17B The core-periphery chip 10 may include a driving layer 11 and a core-periphery interconnection layer 12. The core-periphery interconnection layer 12 may be disposed on the driving layer 11.

[0054] The driving layer 11 may include a core-peripheral semiconductor layer 100 and a core-peripheral transistor 110 located on the core-peripheral semiconductor layer 100. The core-peripheral semiconductor layer 100 may include a semiconductor material. For some examples, the core-peripheral semiconductor layer 100 may be a semiconductor substrate including a semiconductor material, such as a single crystal silicon substrate, a silicon germanium substrate, or an SOI substrate. For some examples, the core-peripheral semiconductor layer 100 may be a semiconductor epitaxial layer including a semiconductor material. The core-peripheral transistor 110 may be a transistor disposed in a core circuit, a peripheral circuit, and an NPU. The core-peripheral transistor 110 is illustrated as a planar transistor, but in some embodiments, transistors of other shapes may be suitable for the core-peripheral transistor 110.

[0055] The core-periphery interconnection layer 12 may include a core-periphery circuit line 12 a and a core-periphery contact plug 12 b electrically connecting the core-periphery transistor 110 to the core-periphery circuit line 12 a .

[0056] The unit chip 20 may include a data storage layer 21 and a unit interconnection layer 22. The data storage layer 21 may include a unit semiconductor layer 200 and a memory cell layer 210. The unit semiconductor layer 200 may include a first surface 201 and a second surface 202 opposite to each other in a vertical direction VD. The first surface 201 of the unit semiconductor layer 200 may be a front surface of the unit semiconductor layer 200, and the memory cell layer 210 may be formed on the front surface of the unit semiconductor layer 200. The second surface 202 of the unit semiconductor layer 200 may be a rear surface of the unit semiconductor layer 200.

[0057] The unit semiconductor layer 200 may include a semiconductor material. For some examples, the unit semiconductor layer 200 may be a semiconductor substrate including a semiconductor material, such as a single crystal silicon substrate, a silicon germanium substrate, or an SOI substrate. For some examples, the unit semiconductor layer 200 may be a semiconductor epitaxial layer including a semiconductor material. The memory cell layer 210 may include at least one of a variety of semiconductor memories. In some embodiments, the memory cell layer 210 may include a two-dimensional (2D) memory, such as a DRAM having a buried channel array transistor (BCAT) structure or a vertical channel transistor (VCT) structure. In some embodiments, the memory cell layer 210 may include a three-dimensional (3D) memory, such as a vertically stacked DRAM (VSDRAM), a 3D ferroelectric FET (3D FeFET), or a 3D monolithic memory.

[0058] In some embodiments, Fig.15A , Fig.16A and Fig.17AAs shown, the memory cell layer 210 may include a DRAM having a BCAT structure including an active region ACT, a bit line node contact DC, a bit line BL, a storage node contact BC, and a capacitor CAP. Here, a word line may be disposed below the top surface of the active region ACT and may intersect the active region ACT.

[0059] In certain embodiments, such as Fig. 15B , Fig. 16B and Fig. 17B As shown, the memory cell layer 210 may include a DRAM having a VCT structure including a bit line BL, a channel pattern CH, a word line WL, and a capacitor CAP. Here, the channel pattern CH may include at least one of single crystal silicon, polycrystalline silicon, an oxide semiconductor material (e.g., InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, etc.), and a two-dimensional material (e.g., graphene, a transition metal element (e.g., Mo, W, V, Nb, Ta, Ti, etc.) and a chalcogen element (e.g., S, Se, Te, etc.)).

[0060] The cell interconnection layer 22 may include a cell circuit line 22 a and a cell contact plug 22 b electrically connecting the memory cell layer 210 to the cell circuit line 22 a .

[0061] refer to Fig.15A and Fig. 15B , the data storage layer 21 may be disposed on the core-periphery chip 10, and the cell interconnection layer 22 may be disposed on the data storage layer 21. The data storage layer 21 may be disposed between the core-periphery chip 10 and the cell interconnection layer 22.

[0062] The memory cell layer 210 and the cell interconnection layer 22 may be sequentially disposed on the first surface 201 of the unit semiconductor layer 200. The core-periphery chip 10 may be disposed on the second surface 202 of the unit semiconductor layer 200. In other words, the unit semiconductor layer 200, the memory cell layer 210, and the cell interconnection layer 22 may be sequentially stacked on the core-periphery chip 10. The chip insulating layer 60 may be disposed between the second surface 202 of the unit semiconductor layer 200 and the core-periphery chip 10.

[0063] The through conductive pattern 50 may electrically connect the core-periphery chip 10 to the unit chip 20. The through conductive pattern 50 may penetrate the unit chip 20 and the chip insulating layer 60 in the vertical direction VD, and may extend to the core-periphery chip 10. For example, the through conductive pattern 50 may be electrically connected to the unit interconnect layer 22 through the data storage layer 21, and may be electrically connected to the driving layer 11 through the core-periphery interconnect layer 12.

[0064] In some embodiments, when manufacturing the memory chip 1000, the components of the unit chip 20 may be sequentially formed on the core-peripheral chip 10. In other words, the unit semiconductor layer 200, the memory cell layer 210, and the unit interconnect layer 22 may be sequentially formed on the core-peripheral chip 10. In this case, for example, the unit semiconductor layer 200 may be a semiconductor epitaxial layer. In some embodiments, when manufacturing the memory chip 1000, the data storage layer 21 may be formed using a separate manufacturing process and then may be bonded to the core-peripheral chip 10. In this case, for example, the unit semiconductor layer 200 may be a semiconductor substrate. However, the embodiments of the present disclosure are not limited to the description of the method for manufacturing the memory chip 1000.

[0065] refer to Fig.16A and Fig. 16B ,picture Fig.15A and Fig. 15B Likewise, the data storage layer 21 may be disposed on the core-periphery chip 10, and the cell interconnection layer 22 may be disposed on the data storage layer 21. The data storage layer 21 may be disposed between the core-periphery chip 10 and the cell interconnection layer 22.

[0066] However, with Fig.15A and Fig. 15B In contrast, the memory cell layer 210 may be disposed between the first surface 201 of the unit semiconductor layer 200 and the core-periphery chip 10, and the cell interconnection layer 22 may be disposed on the second surface 202 of the unit semiconductor layer 200. In other words, the memory cell layer 210, the unit semiconductor layer 200, and the cell interconnection layer 22 may be sequentially stacked on the core-periphery chip 10. The chip insulating layer 60 may be located on the first surface 201 of the unit semiconductor layer 200, and may be disposed between the memory cell layer 210 and the core-periphery chip 10. The through conductive pattern 50 may electrically connect the core-periphery chip 10 to the unit chip 20.

[0067] In some embodiments, when manufacturing the memory chip 1000, the data storage layer 21 may be formed using a manufacturing process different from the process of manufacturing the core-periphery chip 10, and then may be bonded to the core-periphery chip 10. In this case, for example, the unit semiconductor layer 200 may be a semiconductor substrate. For example, the data storage layer 21 may be turned over and may be bonded to the core-periphery chip 10. However, the embodiments of the present disclosure are not limited to the description of the method of manufacturing the memory chip 1000.

[0068] refer to Fig.17A and Fig. 17B ,and FIG. 15A to FIG. 16B Differently, the cell interconnection layer 22 may be disposed on the core-periphery chip 10, and the data storage layer 21 may be disposed on the cell interconnection layer 22. The cell interconnection layer 22 may be disposed between the data storage layer 21 and the core-periphery chip 10.

[0069] The memory cell layer 210 may be disposed between the first surface 201 of the unit semiconductor layer 200 and the core-periphery chip 10, and the unit interconnection layer 22 may be disposed between the memory cell layer 210 and the core-periphery chip 10. The unit interconnection layer 22, the memory cell layer 210, and the unit semiconductor layer 200 may be sequentially stacked on the core-periphery chip 10.

[0070] The core-periphery interconnect layer 12 may include a core-periphery bonding pad 15. The cell interconnect layer 22 may include a cell bonding pad 25. The core-periphery bonding pad 15 and the cell bonding pad 25 may be coupled to each other, and thus the core-periphery chip 10 and the cell chip 20 may be electrically connected to each other. For example, the core-periphery bonding pad 15 and the cell bonding pad 25 may each include copper (Cu), but the embodiments of the present disclosure are not limited thereto.

[0071] In some embodiments, when manufacturing the memory chip 1000, the unit chip 20 can be formed using a manufacturing process different from the process for manufacturing the core-peripheral chip 10, and can then be bonded to the core-peripheral chip 10. When manufacturing the core-peripheral chip 10, the surface of the core-peripheral bonding pad 15 can be exposed to the outside. When manufacturing the unit chip 20, the surface of the unit bonding pad 25 can be exposed to the outside. Through the bonding process, the exposed surface of the core-peripheral bonding pad 15 can contact the exposed surface of the unit bonding pad 25, and the core-peripheral bonding pad 15 and the unit bonding pad 25 can be coupled to each other. For example, the unit chip 20 can be turned over and can be bonded to the core-peripheral chip 10. However, the embodiments of the present disclosure are not limited to the description of the method for manufacturing the memory chip 1000.

[0072] Fig.18is a cross-sectional view illustrating a plurality of memory chips according to some embodiments of the present disclosure.

[0073] refer to Fig.18 , a plurality of memory chips 1000 may be stacked vertically. Each memory chip 1000 may be one of the above-mentioned memory chips 1000. Each memory chip 1000 may include a core-peripheral chip 10 and a unit chip 20 stacked vertically. The core-peripheral chip 10 and the unit chip 20 may include TSVs 30. The core-peripheral chip 10 and the unit chip 20 may be stacked alternately. Fig.18 Two memory chips 1000 are illustrated in FIG. 1 , but in some embodiments, three or more memory chips 1000 may be stacked.

[0074] The memory chips 1000 may be electrically connected to each other through the TSVs 30. The TSVs 30 of each memory chip 1000 may include the TSVs 30 of the core-periphery chip 10 and the TSVs 30 of the unit chip 20. Fig.18 The TSVs 30 of the core-periphery chip 10 are physically connected to the TSVs 30 of the unit chip 20 , but in some embodiments, the TSVs 30 of the core-periphery chip 10 and the TSVs 30 of the unit chip 20 may be connected to each other through an additional contact provided therebetween.

[0075] The TSVs 30 of the vertically stacked pairs of memory chips 1000 may be electrically connected to each other through the first contact pad CP1 and the second contact pad CP2. The first contact pad CP1 and the second contact pad CP2 may contact each other. The first contact pad CP1 and the second contact pad CP2 may each independently be a conductive pad or a conductive bump.

[0076] Fig.19 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present disclosure.

[0077] refer to Fig.19 , the semiconductor package 2000 may include a substrate chip 1100 and a plurality of memory chips 1000 and 1000' located on the substrate chip 1100. The substrate chip 1100 may be electrically connected to the plurality of memory chips 1000 and 1000', and may include a host core or a buffer die. The host core may include a processor that performs various operations. The buffer die may receive commands, data, and / or signals sent from the outside, and may send the received commands, data, and / or signals to the plurality of memory chips 1000 and 1000'. In other words, the plurality of memory chips 1000 and 1000' may be connected to the substrate chip 1100, and may be used to perform various operations in response to signals received from the substrate chip 1100.

[0078] The plurality of memory chips 1000 and 1000′ may be electrically connected to the substrate chip 1100 through the TSVs 30. For example, the substrate chip 1100 may include a substrate contact pad CPh disposed at an upper end thereof, and the TSVs 30 may be connected to the substrate chip 1100 through the substrate contact pad CPh. For example, the TSVs 30 may not be disposed in the uppermost memory chip 1000′, but the embodiments of the present disclosure are not limited thereto.

[0079] Fig. 20 is a cross-sectional view illustrating a semiconductor package including a memory chip according to some embodiments of the present disclosure.

[0080] refer to Fig. 20 , the semiconductor package 1 may include a package substrate, a storage structure 3000 and a host structure 800. The storage structure 3000 and the host structure 800 may be disposed on the package substrate and may be horizontally spaced apart from each other. The storage structure 3000 and the host structure 800 may be electrically connected to each other through the package substrate.

[0081] In some embodiments, the package substrate may include a first package substrate 400 and a second package substrate 500. The first package substrate 400 may be located on the second package substrate 500, and the storage structure 3000 and the host structure 800 may be located on the first package substrate 400. The first package substrate 400 may be an interposer, and the second package substrate 500 may be a printed circuit board (PCB). The first connection terminal 440 may electrically connect the first package substrate 400 to the second package substrate 500. The second connection terminal 540 may electrically connect the semiconductor package 1 to an external device (e.g., a mainboard).

[0082] The memory structure 3000 may include a substrate chip 300, a plurality of memory chips 1000 and 1000′ on the substrate chip 300, a first mold layer MD1 surrounding the plurality of memory chips 1000 and 1000′, and a memory connection terminal 340 between the substrate chip 300 and a package substrate (e.g., a first package substrate 400 and a second package substrate 500). The substrate chip 300 may correspond to Fig.19 A substrate chip 1100 is provided.

[0083] The substrate chip 300 may include a substrate layer 310, an upper interconnection layer 330 formed on one surface (e.g., the top surface) of the substrate layer 310, and a lower substrate pad 320 exposed at another surface (e.g., the bottom surface) of the substrate layer 310. The upper interconnection layer 330 may include an upper substrate pad 332 and a substrate protection layer 334 surrounding the upper substrate pad 332.

[0084] The substrate chip 300 may redistribute a plurality of memory chips 1000 and 1000'. The upper substrate pad 332 and the lower substrate pad 320 may be electrically connected to each other through a circuit line in the substrate layer 310, and together with the circuit line, may constitute a redistribution circuit. The memory connection terminal 340 may be located between the lower substrate pad 320 and the package substrate (e.g., the first package substrate 400 and the second package substrate 500). The memory connection terminal 340 may include a solder ball or a solder bump. The first mold layer MD1 may include an insulating material. For example, the first mold layer MD1 may include an epoxy mold compound (EMC).

[0085] The host structure 800 may be a data processing unit. The host connection terminal 840 may be disposed between the host structure 800 and the package substrate (e.g., the first package substrate 400 and the second package substrate 500). The host connection terminal 840 may electrically connect the host structure 800 to the package substrate (e.g., the first package substrate 400 and the second package substrate 500). The second mold layer MD2 may surround the storage structure 3000 and the host structure 800 on the package substrate (e.g., the first package substrate 400 and the second package substrate 500).

[0086] According to the present disclosure, the core-periphery chip 10 and the unit chip 20 can be stacked vertically, so the core region COR and the peripheral region PR can be defined on a plane located at a height different from that of the unit region CR. As a result, compared with the case where the unit region CR, the core region COR, and the peripheral region PR are defined on the same plane, the integration density per unit area of ​​the memory chip 1000 can be improved.

[0087] In addition, since the core-peripheral chip 10 includes the NPU block NB, the NPU block NB can be disposed adjacent to the cell region CR. Therefore, the data transmission distance between the NPU block NB and the cell region CR can be minimized, and the data processing speed of the memory chip 1000 can be increased. In addition, the memory chip 1000 can be driven by low power, and problems such as noise and / or heat generation can be reduced or minimized. As a result, the performance of the memory chip 1000 can be improved.

[0088] According to an embodiment of the present disclosure, a core-periphery chip and a unit chip can be vertically stacked, and thus, the integration density per unit area of ​​a memory chip and a semiconductor package including the memory chip can be improved.

[0089] In addition, since the core-peripheral chip includes an NPU block, the NPU block can be disposed adjacent to the cell area. Therefore, the data transmission distance between the NPU block and the cell area can be minimized, and the data processing speed of the memory chip can be increased. Therefore, the performance of the memory chip and the semiconductor package including the memory chip can be improved.

[0090] While non-limiting example embodiments of the present disclosure have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory chip, comprising: Unit chip; as well as Core-peripheral chips, wherein the unit chip and the core-periphery chip are vertically stacked and electrically connected to each other, The unit chip includes unit regions, each of which includes a storage unit layer. The core-periphery chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein the at least one core group region comprises core regions arranged in rows along a second direction intersecting the first direction, and Wherein, each of the core areas includes: a core memory bank, the core memory bank comprising a core circuit; and A neural processing unit block includes a neural processing unit.

2. The memory chip according to claim 1, wherein: The at least one core group region includes a pair of core group regions spaced apart from each other by the peripheral region in the first direction, and Wherein, the core memory bank and the neural processing unit block of the paired core group area are symmetrical with respect to the peripheral area.

3. The memory chip according to claim 1, wherein: The at least one core group region includes a pair of core group regions spaced apart from each other in the first direction, the peripheral region is interposed between the pair of core group regions, and Wherein, the core memory bank and the neural processing unit block of the paired core group area are asymmetric relative to the peripheral area.

4. The memory chip according to claim 1, wherein: The core-periphery chip includes a side surface facing the first direction, and The at least one core group region includes core group regions located between the side surface of the core-periphery chip and the peripheral region and adjacent to each other in the first direction.

5. The memory chip according to claim 1, wherein: Each of the unit regions also includes a neural processing unit buffer.

6. The memory chip according to claim 5, wherein: The neural processing unit buffer includes at least one of a phase change random access memory device, a spin transfer torque magnetic random access memory device, a ferroelectric random access memory device, and a static random access memory device.

7. The memory chip according to claim 1, wherein: The memory cell layer includes at least one of a two-dimensional memory and a three-dimensional memory.

8. The memory chip according to claim 1, wherein: Each of the unit regions vertically overlaps at least a portion of one of the neural processing unit blocks.

9. The memory chip according to claim 1, wherein: Each of the unit chip and the core-periphery chip further includes a through-silicon via, and Wherein, the through silicon via of the unit chip is electrically connected to the through silicon via of the core-periphery chip.

10. The memory chip according to claim 1, wherein: The unit chip and the core-periphery chip are electrically connected to each other through a through conductive pattern penetrating the unit chip and the core-periphery chip.

11. The memory chip according to claim 1, wherein: The unit chip further includes a unit bonding pad, Wherein, the core-periphery chip further comprises a core-periphery bonding pad, and The unit bonding pads and the core-periphery bonding pads are coupled to each other so that the unit chip and the core-periphery chip are electrically connected.

12. The memory chip according to claim 1, wherein: The unit chip further includes a unit semiconductor layer having a semiconductor material, and Wherein, the unit semiconductor layer is located between the core-periphery chip and the memory unit layer.

13. The memory chip according to claim 1, wherein: The unit chip further includes a unit semiconductor layer having a semiconductor material, and Wherein, the memory unit layer is located between the core-periphery chip and the unit semiconductor layer.

14. A semiconductor package, comprising: a plurality of memory chips, the plurality of memory chips being stacked vertically; as well as a through silicon via, wherein the through silicon via electrically connects the plurality of memory chips, Each of the plurality of memory chips includes a unit chip and a core-periphery chip stacked vertically, The unit chip includes: unit regions, each of which includes a storage unit layer, The core-periphery chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein the at least one core group region comprises core regions arranged in rows along a second direction intersecting the first direction, and Wherein, each of the core areas includes: a core memory bank, the core memory bank comprising a core circuit; and A neural processing unit block includes a neural processing unit.

15. The semiconductor package according to claim 14, further comprising: A substrate chip, the substrate chip comprising a host core or a buffer die, Wherein, the plurality of memory chips are located on the base chip.

16. The semiconductor package according to claim 14, wherein: The through silicon via penetrates central portions of the plurality of memory chips.

17. A semiconductor package, comprising: Package substrate; A host structure, the host structure is located on the packaging substrate; as well as a storage structure horizontally spaced apart from the host structure on the packaging substrate and electrically connected to the host structure, Wherein, the storage structure includes a plurality of storage chips stacked vertically, Each of the plurality of memory chips includes a unit chip and a core-periphery chip which are vertically stacked and electrically connected to each other, The unit chip includes unit regions, each of which includes a storage unit layer. wherein the core-periphery chip comprises at least one core unit region and a peripheral region adjacent to each other in a first direction, wherein the at least one core group region comprises core regions arranged in rows along a second direction intersecting the first direction, and Wherein, each of the core areas includes: a core memory bank, the core memory bank comprising a core circuit; and A neural processing unit block includes a neural processing unit.

18. The semiconductor package according to claim 17, wherein: The memory structure also includes a through silicon via that electrically connects the plurality of memory chips.

19. The semiconductor package according to claim 17, wherein: The storage structure includes a plurality of storage structures horizontally spaced apart from each other.

20. The semiconductor package according to claim 17, wherein The memory cell layer includes at least one of a two-dimensional memory and a three-dimensional memory.

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