Semiconductor package

Abstract

The invention relates to a semiconductor package and a method of manufacturing the same. An exemplary semiconductor package includes a first semiconductor die including a first substrate and a first bonding layer on the first substrate; a second semiconductor die disposed on the first semiconductor die, the second semiconductor die including a second substrate and a second bonding layer under the second substrate; and a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, in which at least one hole is provided in the silicon oxide layer, and the height of the at least one hole is # imgabs0 # to 2 nm.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package including a semiconductor package having improved reliability and a method of manufacturing a semiconductor package including a method of manufacturing a semiconductor package capable of improving yield. Background Art

[0002] A semiconductor package is provided to implement an integrated circuit chip to meet the conditions for use in electronic products. Generally, the semiconductor package is configured so that the semiconductor chip is mounted on a printed circuit board (PCB) and the semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and miniaturization of semiconductor packages. Summary of the invention

[0003] The scope of the technology described herein is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0004] In some embodiments, a semiconductor package includes: a first semiconductor die, the first semiconductor die including a first substrate and a first bonding layer located on the first substrate; a second semiconductor die, the second semiconductor die is disposed on the first semiconductor die, the second semiconductor die includes a second substrate and a second bonding layer located below the second substrate; and a silicon oxide layer, the silicon oxide layer is inserted between the first semiconductor die and the second semiconductor die, wherein at least one hole is provided in the silicon oxide layer, and the height of the at least one hole is To 2nm.

[0005] In some embodiments, a semiconductor package includes: a first semiconductor die, the first semiconductor die including a first substrate and a first bonding layer located on the first substrate; a second semiconductor die, the second semiconductor die is arranged on the first semiconductor die, the second semiconductor die includes a second substrate and a second bonding layer located below the second substrate; and a silicon oxide layer, the silicon oxide layer is inserted between the first semiconductor die and the second semiconductor die, wherein at least one hole is provided in the silicon oxide layer, the first bonding layer and the second bonding layer include a plurality of SiCN grains, and a height of the at least one hole is less than an average size of the plurality of SiCN grains.

[0006] In some embodiments, a semiconductor package includes: a first semiconductor die, the first semiconductor die including a first substrate, a first bonding layer located on the first substrate, and a first conductive pattern passing through the first bonding layer; a second semiconductor die, the second semiconductor die is arranged on the first semiconductor die and partially exposes the upper surface of the first semiconductor die, the second semiconductor die includes a second substrate, a second bonding layer located below the second substrate, and a second conductive pattern layer passing through the second bonding layer; a silicon oxide layer, the silicon oxide layer is inserted between the first bonding layer and the second bonding layer, the silicon oxide layer is in contact with the side surfaces of the first conductive pattern and the second conductive pattern; a molding layer, the molding layer covers the side surface of the second semiconductor die and the upper surface of the first semiconductor die; and an external connection terminal, the external connection terminal is bonded to the lower surface of the first semiconductor die, wherein the first bonding layer and the second bonding layer are formed of SiCN, the first bonding layer or the second bonding layer has a first thickness, the silicon oxide layer has a second thickness less than the first thickness, at least one hole is provided in the silicon oxide layer, and the at least one hole is spaced apart from the first conductive pattern and the second conductive pattern.

[0007] In some embodiments, a method for manufacturing a semiconductor package includes: preparing a first wafer including a first bonding layer, the first bonding layer being formed of SiCN and disposed on the uppermost surface of the first wafer; grinding the first bonding layer; removing CN from the surface of the first bonding layer to form dangling bonds with silicon atoms; preparing a second semiconductor die including a second bonding layer, the second bonding layer being formed of SiCN and disposed on the uppermost surface of the second semiconductor die; removing CN from the surface of the second bonding layer to form dangling bonds with silicon atoms; combining OH groups with the dangling bonds of silicon atoms on the surface of the first bonding layer; combining OH groups with the dangling bonds of silicon atoms on the surface of the second bonding layer; inverting the second semiconductor die to place the second semiconductor die on the first wafer so that the second bonding layer contacts the first bonding layer; and performing a first bonding process to form a silicon oxide layer between the second bonding layer and the first bonding layer, and to bond the second bonding layer and the first bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments described herein.

[0009] Figure 1 is a cross-sectional view of an example of a semiconductor package.

[0010] Figure 2 yes Figure 1 An exemplary enlarged view of portion “P1” of FIG.

[0011] Figure 3A and Figure 3B yes Figure 2 An exemplary enlarged view of portion “P2” of FIG.

[0012] Figure 4 yes Figure 3A or Figure 3B An exemplary enlarged view of portion “P3” of FIG.

[0013] Figure 5 is a cross-sectional view of an example of a semiconductor package.

[0014] Figure 6 yes Figure 5 An exemplary enlarged view of portion “P4” in FIG.

[0015] Figure 7 is a flowchart illustrating an example of a method of manufacturing a semiconductor package.

[0016] FIG. 8A to FIG. 8I It shows the manufacturing Figure 1 A cross-sectional view of an example of a method of manufacturing a semiconductor package.

[0017] Fig. 9A yes Figure 8B Or an exemplary enlarged view of portion "P5" of 8D.

[0018] Fig. 9B yes Fig. 9A An exemplary enlarged view of portion "P9" of FIG.

[0019] Fig.10 yes Figure 8C or Fig. 8E An exemplary enlarged view of portion “P6” of FIG.

[0020] Fig.11A yes Figure 8F An exemplary enlarged view of portion “P7” of FIG.

[0021] Fig. 11B yes Fig.11A An exemplary enlarged view of portion “P10” of FIG.

[0022] Fig. 12A yes Figure 8G An exemplary enlarged view of portion “P8” of FIG.

[0023] Fig. 12B yes Fig. 12A An exemplary enlarged view of portion “P11” of FIG.

[0024] Fig.13 yes Figure 8G An exemplary enlarged view of portion “P8” of FIG. DETAILED DESCRIPTION

[0025] Hereinafter, in order to explain these concepts in more detail, implementations according to these concepts will be described with reference to the accompanying drawings.

[0026] Figure 1 is a cross-sectional view of an example of a semiconductor package. Figure 2 yes Figure 1 An exemplary enlarged view of portion “P1” of FIG. Figure 3A and Figure 3B yes Figure 2 An exemplary enlarged view of portion “P2” of FIG. Figure 4 yes Figure 3A or Figure 3B An exemplary enlarged view of portion “P3” of FIG.

[0027] Reference Figure 1 and Figure 2 , the semiconductor package 1000 includes a first semiconductor die 10, a second semiconductor die 100 and a molding layer MD. In this specification, a "semiconductor die" may also be referred to as a "semiconductor chip". The first semiconductor die 10 may be a logic circuit chip or a memory chip, such as a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip or a ReRAM chip. The first semiconductor die 10 includes a first substrate 1, a first interlayer insulating layer IL1 and a first bonding layer BNL1 stacked sequentially. The first substrate 1 may be a semiconductor substrate formed of a semiconductor such as silicon, a silicon-on-insulator (SOI) substrate and / or an insulating substrate. The first substrate 1 includes a first surface 1a and a second surface 1b opposite to each other. Although not shown, a plurality of transistors may be provided on the first surface 1a of the first substrate 1.

[0028] A first interlayer insulating layer IL1 is provided on the first surface 1a of the first substrate 1. The first interlayer insulating layer IL1 may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A multilayer first wiring 25 may be provided in the first interlayer insulating layer IL1. The first wiring 25 may be formed of polysilicon doped with impurities or a metal such as aluminum, tungsten, titanium, or copper. The first wiring 25 and the transistor may configure various circuits.

[0029] A plurality of first conductive pads 7 may be provided on the second surface 1b of the first substrate 1. Although not shown, an insulating layer may be interposed between the second surface 1b of the first substrate 1 and the first conductive pads 7. External connection terminals SB may be bonded to the first conductive pads 7, respectively. The external connection terminals SB may include at least one of a conductive bump and a solder ball. The external connection terminals SB may include at least one metal of copper, nickel, tin, and silver.

[0030] The first via 11 may pass through the first substrate 1 and a portion of the first interlayer insulating layer IL1 to connect the first conductive pad 7 to the first wiring 25. The first via 11 may include a metal material such as copper, tungsten, or titanium. A first through insulating layer 13 may be interposed between the first via 11 and the first substrate 1. The first through insulating layer 13 may be formed of, for example, silicon oxide.

[0031] The first bonding layer BNL1 may be formed of silicon carbon nitride (SiCN). The first bonding layer BNL1 may also be referred to as a “first SiCN layer.” The first conductive pattern CP1 may pass through the first bonding layer BNL1 and a portion of the first interlayer insulating layer IL1. The first conductive pattern CP1 may include, for example, copper.

[0032] The second semiconductor die 100 may be a chip different from the first semiconductor die 10. The second semiconductor die 100 may be a logic circuit chip or a memory chip, for example, a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, or a ReRAM chip. The second semiconductor die 100 includes a second substrate 21, a second interlayer insulating layer IL2, and a second bonding layer BNL2 stacked sequentially. The second substrate 21 may be a semiconductor substrate formed of a semiconductor such as silicon, a silicon-on-insulator (SOI) substrate, and / or an insulating substrate. The second substrate 21 includes a first surface 21a and a second surface 21b opposite to each other. Although not shown, a plurality of transistors may be provided on the first surface 21a of the second substrate 21. The first surface 21a of the second substrate 21 faces the first semiconductor die 10.

[0033] The second interlayer insulating layer IL2 is disposed on the first surface 21a of the second substrate 21. The second interlayer insulating layer IL2 may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A multilayer second wiring 35 may be disposed in the second interlayer insulating layer IL2. The second wiring 35 may be formed of polysilicon doped with impurities or a metal such as aluminum, tungsten, titanium, or copper. The first wiring 25 and the transistor may configure various circuits.

[0034] The second bonding layer BNL2 may be formed of silicon carbon nitride (SiCN). The second bonding layer BNL2 may also be referred to as a “second SiCN layer.” The second conductive pattern CP2 may pass through a portion of the second interlayer insulating layer IL2 and the second bonding layer BNL2. The second conductive pattern CP2 may include, for example, copper.

[0035] The first conductive pattern CP1 and the second conductive pattern CP2 may contact each other. The first conductive pattern CP1 may have a first width WT1. The second conductive pattern CP2 may have a second width WT2 different from the first width WT1. For example, the second width WT2 may be greater than the first width WT1. Conversely, the second width WT2 may be less than the first width WT1. Such a width difference may improve the misalignment margin. An interface exists between the first conductive pattern CP1 and the second conductive pattern CP2 formed integrally with each other.

[0036] Reference Figure 2 , a silicon oxide layer 31 is inserted between the first semiconductor die 10 and the second semiconductor die 100. The silicon oxide layer 31 may be inserted between the first bonding layer BNL1 and the second bonding layer BNL2 and may be in direct contact with the first bonding layer BNL1 and the second bonding layer BNL2. The silicon oxide layer 31 may also be referred to as an "insulating layer" or a "bonding interface layer". The silicon oxide layer 31 may be in contact with the side surface of the first conductive pattern CP1. The silicon oxide layer 31 may be in contact with the side surface of the second conductive pattern CP2. The silicon oxide layer 31 may have a first thickness T1. The first bonding layer BNL1 may have a second thickness T2. The second bonding layer BNL2 may have a third thickness T3. The first thickness T1 may be less than the second thickness T2 and / or the third thickness T3. The second thickness T2 and the third thickness T3 may have the same or different thicknesses.

[0037] At least one hole PO may be provided in the silicon oxide layer 31. The hole PO may be spaced apart from the first bonding layer BNL1 and the second bonding layer BNL2. The hole PO may be spaced apart from the first conductive pattern CP1 and the second conductive pattern CP2. The hole PO may have a first height HT1. The first height HT1 may be The hole PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. The hole PO may also be referred to as a "gap" or a "vacancy".

[0038] Reference Figure 3A and Figure 3B Each of the first conductive pattern CP1 and the second conductive pattern CP2 may have a SiCN grain GRN. The bonding relationship between the silicon atoms, carbon atoms, and nitrogen atoms in each SiCN grain GRN may have, for example, Figure 4t-SiCN crystal structure shown. Alternatively, the crystal structure of each SiCN grain (GRN) may be c-SiCN, o-SiCN or h-SiCN. The SiCN grains GRN may have an average size SZ (here, the size may refer to a diameter, a width or a height). The first height HT1 of the hole PO may be smaller than the average size SZ of the SiCN grains GRN. A gap VC may exist at the interface between the SiCN grains GRN. H as a water molecule WM 2 O may exist (or be trapped) at the interface or in the gap VC between SiCN grains GRN.

[0039] The width of the second semiconductor die 100 may be smaller than the width of the first semiconductor die 10, and the upper surface of the first semiconductor die 10 may be partially exposed. The mold layer MD may cover the upper surface and side surfaces of the second semiconductor die 100 and the upper surface of the first semiconductor die 10. The mold layer MD may include an insulating resin such as an epoxy molding compound (EMC). The mold layer MD may also include a filler, and the filler may be dispersed in the insulating resin. The filler may include, for example, silicon oxide (SiO 2 ).

[0040] In the semiconductor package 1000, ultrafine pores PO are formed in the silicon oxide layer 31. When the pores PO are formed, water molecules WM may induce compressive stress toward the silicon oxide layer 31 in the first bonding layer BNL1 and the second bonding layer BNL2, and thus the bonding strength and bonding area between the first bonding layer BNL1 and the second bonding layer BNL2 may be improved. Figure 4 As shown, the silicon oxide layer 31 may improve the bonding strength between the first bonding layer BNL1 and the second bonding layer BNL2. Therefore, a semiconductor package 1000 having improved reliability may be provided.

[0041] Figure 5 is a cross-sectional view of an example of a semiconductor package. Figure 6 yes Figure 5 An exemplary enlarged view of portion “P4” in FIG.

[0042] Reference Figure 5 and Figure 6, the semiconductor package 1001 according to this example may include second to fifth semiconductor dies 300a, 300b, 300c, and 300d sequentially stacked on the first semiconductor die 200. The first semiconductor die 10 may be a chip of a different type from the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. The first semiconductor die 200 may be, for example, a logic circuit chip or a buffer die. The second to fifth semiconductor dies 300a, 300b, 300c, and 300d may be memory chips that are identical to each other. The memory chip may be, for example, a DRAM, a NAND flash memory, an SRAM, an MRAM, a PRAM, or an RRAM. Although a structure in which one logic circuit chip and four memory chips are stacked is disclosed in this example, the number of stacked logic circuit chips and memory chips is not limited thereto and may be diverse. The first semiconductor die 10 may have a wider width than the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. The semiconductor package 1001 may be a high bandwidth memory (HBM) chip.

[0043] The mold layer MD may cover the upper surface of the first semiconductor die 200 and side surfaces of the second to fifth semiconductor dies 300a, 300b, 300c, and 300d. The upper surface of the mold layer MD may be coplanar with the upper surface of the fifth semiconductor die 300d.

[0044] The first semiconductor die 200 may include a first substrate 1. The first substrate 1 may include a first surface 1a and a second surface 1b opposite to each other. A first interlayer insulating layer IL1 may be provided on the first surface 1a. A first transistor and a multi-layer first wiring 25 may be provided in the first interlayer insulating layer IL1. A first conductive pad 7 may be provided on the first interlayer insulating layer IL1. First conductive bumps 27 may be bonded to the first conductive pads 7, respectively. The first conductive bumps 27 may include, for example, copper. The solder layer 43 may be bonded under the first conductive bumps 27. The solder layer 43 may include, for example, SnAg. The first interlayer insulating layer IL1 may be covered by a first passivation layer 39. The first passivation layer 39 may include, for example, SiN. The second surface 1b of the first substrate 1 may be covered by a first bonding layer BNL1. As Figure 6 As shown, a back insulating layer 115 may be inserted between the first bonding layer BNL1 and the second surface 1b of the first substrate 1. The back insulating layer 115 may be formed of, for example, silicon oxide. A portion of the first substrate 1 and the first interlayer insulating layer IL1 may be penetrated by the first via 11. A first through insulating layer 13 may be inserted between the first via 11 and the first substrate 1. A first conductive pattern CP1 may be provided in the first bonding layer BNL1.

[0045] Each of the second to fifth semiconductor dies 300a, 300b, 300c and 300d may include a second substrate 21. The second substrate 21 may include a first surface 21a and a second surface 21b opposite to each other. A second interlayer insulating layer IL2 may be provided on the first surface 21a of the second substrate 21. A second transistor and a multi-layer second wiring 35 may be provided in the second interlayer insulating layer IL2. A second conductive pattern CP2 may be provided on the second interlayer insulating layer IL2. The second interlayer insulating layer IL2 may be covered by a second bonding layer BNL2. A first bonding layer BNL1 and a first conductive pattern CP1 are provided on the second surface 21b of the second substrate 21. The first conductive pattern CP1 may pass through the first bonding layer BNL1. Figure 6 As shown, a back insulating layer 115 may be inserted between the first bonding layer BNL1 and the second surface 1b of the second substrate 21. Portions of the back insulating layer 115, the second substrate 21, and the second interlayer insulating layer IL2 may all be penetrated by the second through via 111 in the second to fourth semiconductor dies 300a, 300b, and 300c. A second through insulating layer 113 may be inserted between the second through via 111 and the second substrate 21. The fifth semiconductor die 300d may not include the second through via 111 and the second through insulating layer 113, and may be excluded. The first to fifth semiconductor dies 10, 300a, 300b, 300c, and 300d may contact each other. The first conductive pattern CP1 and the second conductive pattern CP2 may contact each other. The widths of the first conductive pattern CP1 and the second conductive pattern CP2 may be the same.

[0046] Reference Figure 5 and Figure 6 , a silicon oxide layer 31 is inserted between the first to fifth semiconductor dies 200, 300a, 300b, 300c, and 300d. At least one hole PO is provided in the silicon oxide layer 31. The hole PO may be spaced apart from the first bonding layer BNL1 and the second bonding layer BNL2. The hole PO may be spaced apart from the first conductive pattern CP1 and the second conductive pattern CP2. Figure 2 As described, the hole PO may have a first height HT1. The first height HT1 may be The hole PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. Other configurations may be similar to those of reference Figures 1 to 4 The configuration described is the same / similar.

[0047] Figure 7 is a flowchart illustrating an example of a method of manufacturing a semiconductor package. FIG. 8A to FIG. 8I It shows the manufacturing Figure 1 A cross-sectional view of an example of a method of manufacturing a semiconductor package.

[0048] Reference Figure 7 and Fig. 8A In the first step S10, a first wafer WF1 including a first bonding layer BNL1 disposed on its uppermost surface is prepared. The first wafer WF1 may include a plurality of device regions DR and separation regions SR therebetween. In each device region DR, the first wafer WF1 may have a Figure 1 and Figure 2 The first semiconductor die 10 described above has the same / similar structure. The first wafer WF1 may include a first interlayer insulating layer IL1 and a first bonding layer BNL1 sequentially stacked on a first substrate 1. The first bonding layer BNL1 is formed of SiCN. Figure 3A As shown, the first bonding layer BNL1 may include a plurality of SiCN grains GRN. The first conductive pad 7 and the external connection terminal SB may be bonded to the lower surface of the first substrate 1. The first wafer WF1 may be attached to the first carrier substrate CR1 through a sacrificial adhesive layer AL1. The sacrificial adhesive layer AL1 may include a thermosetting resin or a photocurable resin. A trench TRC for forming a first conductive pattern CP1 is formed in a portion of the first bonding layer BNL1 and the first interlayer insulating layer IL1. An electroplating process is performed on the first bonding layer BNL1 to form a first conductive layer CPL to fill the trench TRC. The first conductive layer CPL may include, for example, copper.

[0049] Reference Figure 7 and Figure 8B , a grinding process is performed on the first conductive layer CPL to form the first conductive pattern CP1 and expose the upper surface of the first bonding layer BNL1. In this case, the first bonding layer BNL1 is also ground in the second step S20.

[0050] Fig. 9A yes Figure 8B Or an exemplary enlarged view of portion "P5" of 8D. Fig. 9B yes Fig. 9A An exemplary enlarged view of portion "P9" of FIG.

[0051] Reference Figure 7 and Figure 8B as well as Fig. 9A and Fig. 9B , when the upper surface of the first bonding layer BNL1 is ground, the upper surface of the first bonding layer BNL1 appears flat macroscopically, as shown in FIG. Figure 8B However, Fig. 9A As shown, the upper surface of the first bonding layer BNL1 has several The CN groups may be bonded to silicon (Si) atoms on the surface UEP of the first bonding layer BNL1, such as Fig. 9B shown.

[0052] Fig.10 yes Figure 8C or Fig. 8E An exemplary enlarged view of portion “P6” of FIG.

[0053] Reference Figure 7 , Figure 8C and Fig.10 In the third step S30, Fig. 9B The surface UEP of the first bonding layer BNL1 removes CN groups and forms dangling bonds DB with silicon (Si) atoms. Figure 8B The first plasma process PL1 is performed on the first bonding layer BNL1 in a state of being oxidized. The first plasma process PL1 may be performed using at least one of oxygen, nitrogen, and argon. The third step S30 may also be referred to as “activating the surface of the first bonding layer BNL1”.

[0054] Reference Figure 7 and Fig.8D In the fourth step S40, a second semiconductor die 100 including a second bonding layer BNL2 disposed on its uppermost surface is prepared. The second semiconductor die 100 may have the same Figure 1 and Figure 2 The second semiconductor die 100 may include a second interlayer insulating layer IL2 and a second bonding layer BNL2 sequentially stacked on the second substrate 21. The second bonding layer BNL2 is formed of SiCN. Figure 3A As shown, the second bonding layer BNL2 may include a plurality of SiCN grains GRN. A second conductive pattern CP2 is provided in the second bonding layer BNL2. The second semiconductor die 100 may be provided in plurality and may be attached to the second carrier substrate CR2 through a second sacrificial adhesive layer AL2.

[0055] In the grinding process for manufacturing the second conductive pattern CP2, the upper surface of the second bonding layer BNL2 may also be ground. Fig.8D As shown, the upper surface of the second bonding layer BNL2 appears flat macroscopically, but has some or surface roughness of a few nm, such as Fig. 9A The CN group can be bonded to the silicon (Si) atom on the surface UEP of the second bonding layer BNL2, as shown in FIG. Fig. 9B shown.

[0056] Reference Figure 7 and Fig. 8E ,like Fig.10As shown, in the fifth step S50, CN is removed from the surface of the second bonding layer BNL2 and dangling bonds are formed with silicon (Si) atoms. To this end, a second plasma process PL2 is performed on the second bonding layer BNL2. The second plasma process PL2 may be performed using at least one of oxygen, nitrogen, and argon. The fifth step S50 may also be referred to as "activating the surface of the second bonding layer BNL2".

[0057] Fig.11A yes Figure 8F An exemplary enlarged view of portion “P7” of FIG. Fig. 11B yes Fig.11A An exemplary enlarged view of portion “P10” of FIG.

[0058] Reference Figure 7 , Figure 8F , Fig.11A and Fig. 11B , in the sixth step S60, the OH group is bonded to the dangling bond DB of the silicon atom on the surface of the first bonding layer BNL1. In the seventh step S70, the OH group is bonded to the dangling bond DB of the silicon atom on the surface of the second bonding layer BNL2. The sixth step S60 may include performing a cleaning process on the upper surface of the first bonding layer BNL1 using deionized water. In the cleaning process, the deionized water WL1 may remove particles on the first bonding layer BNL1, and at the same time, the OH group of the water molecule of the deionized water WL1 may be bonded to the dangling bond DB of the silicon atom. Step S70 may include performing a cleaning process on the upper surface of the second bonding layer BNL2 using deionized water. In the cleaning process, the deionized water WL1 may remove particles on the second bonding layer BNL2, and at the same time, the OH group of the water molecule of the deionized water WL1 may be bonded to the dangling bond DB of the silicon atom.

[0059] Fig. 12A yes Figure 8G An exemplary enlarged view of portion “P8” of FIG. Fig. 12B yes Fig. 12A An exemplary enlarged view of portion “P11” of FIG.

[0060] Reference Figure 7 , Figure 8F , Figure 8G , Fig. 12A and Fig. 12B In the eighth step S80, the second semiconductor die 100 is turned over and placed on the first wafer WF1 so that the second bonding layer BNL2 contacts the first bonding layer BNL1. Fig. 12A As shown, deionized water WL1 or water molecules may exist in the interface IF between the second bonding layer BNL2 and the first bonding layer BNL1. Fig. 12BAs shown, the OH groups may be adjacent to each other at the interface IF between the second bonding layer BNL2 and the first bonding layer BNL1. In the eighth step S80, the first conductive pattern CP1 and the second conductive pattern CP2 may contact each other.

[0061] Fig.13 yes Figure 8G An exemplary enlarged view of portion “P8” of FIG.

[0062] Reference Figure 7 , Figure 8G and Fig.13 In the ninth step S90, a first bonding process is performed to form a silicon oxide layer 31 between the second bonding layer BNL2 and the first bonding layer BNL1, and to bond the second bonding layer BNL2 and the first bonding layer BNL1. The first bonding process may be referred to as a first thermocompression bonding process. The first bonding process may be performed at 100° C. to 150° C. Through the first bonding process, the OH groups on the surface of the second bonding layer BNL2 react with the OH groups on the surface of the first bonding layer BNL1 to generate H as water molecules WM. 2 O, and the remaining oxygen atoms O are covalently bonded to silicon atoms on the surface of the second bonding layer BNL2 and silicon atoms on the surface of the first bonding layer BNL1, thereby forming a silicon oxide layer 31.

[0063] H as water molecules WM formed in the first bonding process 2 O can penetrate into the gap VC along the interface between the SiCN grains GRN (along the first arrow A1) to cause compressive stress toward the interface IF between the first bonding layer BNL1 and the second bonding layer BNL2 (in the direction of the second arrow A2). Therefore, the distance between the first bonding layer BNL1 and the second bonding layer BNL2 can be reduced, the bonding area can be increased, and the bonding strength can be improved. The covalent bonding area between the oxygen atoms and the silicon atoms of the silicon oxide layer 31 will increase due to the compressive stress. As a result, the bonding strength between the first semiconductor die 10 and the second semiconductor die 100 in the finally formed semiconductor package 1000 can be improved. This can reduce process defects and improve yield.

[0064] When water molecules WM are discharged in the first bonding process, at least one hole PO may be formed in the silicon oxide layer 31, such as Figure 3A As shown. Figure 2 As described, the hole PO may have a first height HT1. The first height HT1 may be The hole PO may have a third width WT3. The third width WT3 may be 1 nm to 100 nm. The water molecules WM may move along the interface between the first wafer WF1 and the second semiconductor die 100 and may escape to the edge of the second semiconductor die 100.

[0065] Some water molecules WM may still be trapped in the gaps VC between the SiCN grains GRN in the first bonding layer BNL1 and the second bonding layer BNL2, as shown in FIG. Figure 3B shown.

[0066] Subsequently, despite Figure 7 Not shown, refer to Figure 8G , a second bonding process may be performed after the first bonding process to bond the first conductive pattern CP1 and the second conductive pattern CP2 to each other. The second bonding process may be referred to as a second thermocompression bonding process. The second bonding process may be performed at a temperature at which the metal (e.g., copper) constituting the first conductive pattern CP1 and the second conductive pattern CP2 is diffused or melted. The second bonding process may be performed at a temperature of, for example, 250°C to 350°C.

[0067] Then refer to Figure 8H , a mold layer MD is formed on the first wafer WF1. Then, as Figure 8I As shown in FIG. 1 , a separation process is performed to cut the separation region SR of the first wafer WF1 and the mold layer MD thereon. As a result, Figure 1 A semiconductor package 1000 is provided.

[0068] According to the method of manufacturing a semiconductor package, it is possible to improve the bonding strength between the first semiconductor die 10 and the second semiconductor die 100. This can reduce process defects and improve yield.

[0069] In a semiconductor package, a silicon oxide layer is provided between a first semiconductor die including a first bonding layer and a second semiconductor including a second bonding layer, and ultrafine pores are formed in the silicon oxide layer. When the pores are formed, water molecules can induce compressive stress in the first bonding layer and the second bonding layer, thereby improving the bonding strength between the first bonding layer and the second bonding layer. Therefore, a semiconductor package with improved reliability can be provided.

[0070] The method for manufacturing a semiconductor package can improve the bonding strength between the first semiconductor die and the second semiconductor die, thereby reducing process defects and improving yield.

[0071] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed invention, but should be interpreted as descriptions of features that are unique to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, in some cases, one or more features in the claimed combination may be deleted from the combination, and the claimed combination may point to a sub-combination or a variant of a sub-combination.

[0072] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the concepts defined in the appended claims. Therefore, the exemplary embodiments of these concepts should be considered in all aspects as illustrative rather than restrictive, wherein the spirit and scope of these concepts are indicated by the appended claims.

Claims

1. A semiconductor package, comprising: a first semiconductor die, the first semiconductor die comprising a first substrate and a first bonding layer, the first bonding layer being located on the first substrate; a second semiconductor die, the second semiconductor die being disposed on the first semiconductor die, the second semiconductor die comprising a second substrate and a second bonding layer, the second bonding layer being located below the second substrate; as well as a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, wherein at least one hole is provided in the silicon oxide layer, and Wherein, the height of the at least one hole is To 2nm.

2. The semiconductor package according to claim 1, wherein: The at least one hole has a width of 1 nm to 100 nm.

3. The semiconductor package according to claim 1, wherein: The first bonding layer includes a first plurality of SiCN grains, SiCN being silicon carbonitride, and the second bonding layer includes a second plurality of SiCN grains, and The average size of the first plurality of SiCN grains or the average size of the second plurality of SiCN grains is greater than the height of the at least one hole.

4. The semiconductor package according to claim 3, wherein: At least one of the first bonding layer and the second bonding layer includes a plurality of water molecules respectively trapped between corresponding at least one of the first plurality of SiCN grains and the second plurality of SiCN grains.

5. The semiconductor package according to claim 1, wherein: The first semiconductor die includes a first conductive pattern disposed on the first substrate, the first conductive pattern extending through the first bonding layer, The second semiconductor die includes a second conductive pattern disposed below the second substrate, the second conductive pattern extends through the second bonding layer, the second conductive pattern contacts the first conductive pattern, and Wherein, the at least one hole is spaced apart from the first conductive pattern and the second conductive pattern.

6. The semiconductor package according to claim 5, wherein: A width of the first conductive pattern is different from a width of the second conductive pattern.

7. The semiconductor package according to claim 1, wherein: The silicon oxide layer has a first thickness, and At least one of the first bonding layer and the second bonding layer has a second thickness greater than the first thickness.

8. The semiconductor package according to claim 1, wherein: The at least one hole is spaced apart from the first bonding layer and the second bonding layer.

9. A semiconductor package, comprising: a first semiconductor die, the first semiconductor die comprising a first substrate and a first bonding layer, the first bonding layer being located on the first substrate; a second semiconductor die, the second semiconductor die being disposed on the first semiconductor die, the second semiconductor die comprising a second substrate and a second bonding layer, the second bonding layer being located below the second substrate; as well as a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, Wherein, at least one hole is provided in the silicon oxide layer, The first bonding layer and the second bonding layer include a plurality of SiCN grains, where SiCN is silicon carbonitride, and Wherein, the height of the at least one hole is smaller than the average size of the plurality of SiCN grains.

10. The semiconductor package according to claim 9, wherein: The at least one hole has to a height of 2 nm.

11. The semiconductor package according to claim 9, wherein: The at least one hole has a width of 1 nm to 100 nm.

12. The semiconductor package according to claim 9, wherein: The first semiconductor die includes a first conductive pattern disposed on the first substrate, the first conductive pattern extending through the first bonding layer, The second semiconductor die includes a second conductive pattern disposed below the second substrate, the second conductive pattern extends through the second bonding layer, the second conductive pattern contacts the first conductive pattern, and Wherein, the at least one hole is spaced apart from the first conductive pattern and the second conductive pattern.

13. The semiconductor package according to claim 12, wherein: A width of the first conductive pattern is different from a width of the second conductive pattern.

14. The semiconductor package according to claim 9, wherein: The silicon oxide layer has a first thickness, and At least one of the first bonding layer and the second bonding layer has a second thickness greater than the first thickness.

15. The semiconductor package according to claim 9, wherein: The at least one hole is spaced apart from the first bonding layer and the second bonding layer.

16. A semiconductor package, comprising: A first semiconductor die, the first semiconductor die comprising a first substrate, a first bonding layer on the first substrate, and a first conductive pattern passing through the first bonding layer; a second semiconductor die disposed on the first semiconductor die and partially exposing an upper surface of the first semiconductor die, the second semiconductor die comprising a second substrate, a second bonding layer below the second substrate, and a second conductive pattern layer extending through the second bonding layer; a silicon oxide layer interposed between the first bonding layer and the second bonding layer, the silicon oxide layer contacting a plurality of side surfaces of the first conductive pattern and the second conductive pattern; a molding layer, the molding layer covering the side surface of the second semiconductor die and the upper surface of the first semiconductor die; as well as external connection terminals bonded to a lower surface of the first semiconductor die, Wherein, the first bonding layer and the second bonding layer include SiCN, SiCN is silicon carbonitride, wherein the first bonding layer or the second bonding layer has a first thickness, wherein the silicon oxide layer has a second thickness that is smaller than the first thickness, wherein at least one hole is provided in the silicon oxide layer, and Wherein, the at least one hole is spaced apart from the first conductive pattern and the second conductive pattern.

17. The semiconductor package according to claim 16, wherein: The at least one hole has to a height of 2 nm.

18. The semiconductor package according to claim 16, wherein: The at least one hole has a width of 1 nm to 100 nm.

19. The semiconductor package according to claim 16, wherein: A width of the first conductive pattern is different from a width of the second conductive pattern.

20. The semiconductor package according to claim 16, wherein The at least one hole is spaced apart from the first bonding layer or the second bonding layer.

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