A method for manufacturing a split gate trench schottky contact super barrier rectifier and a device structure thereof

Abstract

The application discloses a manufacturing method of split-gate trench Schottky contact super-barrier rectifier and a device structure thereof. The main steps of the method are as follows: covering a mask layer on the surface of a polysilicon covering layer; forming a through groove in the mask layer; etching the polysilicon covering layer and a gate dielectric thin layer under the through groove of the mask layer; and performing deep implantation of impurities of a second conductive type, so that the impurities of the second conductive type are partially implanted into a lightly-doped first conductive type drift region through the formed through groove, and are blocked in the mask layer. The device structure comprises a lower electrode layer, a heavily-doped first conductive type substrate layer, a lightly-doped first conductive type drift layer, a trench gate dielectric layer, a polysilicon filling layer, a gate dielectric thin layer, a polysilicon covering layer, a second conductive type body region and an upper electrode layer. The application reduces the barrier capacitance of the device and has better reverse recovery performance while maintaining the good forward characteristics of the Schottky contact super-barrier rectifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to a manufacturing method of split-gate trench Schottky contact super barrier rectifier and a device structure thereof. BACKGROUND

[0002] Low and medium voltage power semiconductor diodes are widely used in power supplies and power converters. Schottky barrier diodes (SBD) have the characteristics of low forward voltage and fast reverse recovery, and are usually used as rectifier devices. However, the specific on-resistance and forward voltage will increase sharply with the increase of the breakdown voltage. Similar to the concept of PN junction field blocking in junction barrier Schottky (JBS), as shown in FIG. 1, trench MOS barrier Schottky diode (TMBS) uses deep MOS trenches to block the electric field. This not only reduces the mesa surface electric field, but also changes the electric field distribution of the drift layer, reducing the lateral depletion caused by the PN junction in JBS. Therefore, it has lower reverse leakage current, higher breakdown voltage and smaller forward voltage. However, TMBS still faces the mirror force potential barrier reduction effect and reliability problems caused by direct Schottky contact. Moreover, the junction capacitance of TMBS is still large. Figure 1

[0003] Schottky contact super barrier rectifier (SSBR) has been proved to have a simple manufacturing process, low forward voltage, low reverse leakage current and excellent high-temperature reliability. However, the breakdown voltage of the existing SSBR is only a few tens of volts. And since SSBR is a majority carrier device, increasing the breakdown voltage will quickly deteriorate its forward conduction characteristics. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method of split-gate trench Schottky contact super barrier rectifier, comprising the following steps:

[0005] 1) Covering a lightly doped first-conductivity-type drift region on a heavily doped first-conductivity-type substrate.

[0006] 2) Forming a trench on the lightly doped first-conductivity-type drift region.

[0007] 3) Covering a dielectric layer in the trench formed in step 2) to form a U-shaped trench gate dielectric layer.

[0008] 4) Depositing polysilicon, and then performing heavy doping on the polysilicon, and then removing the excess polysilicon outside the U-shaped trench gate dielectric layer formed in step) by reverse etching to form a polysilicon filling layer.

[0009] 5) Forming a gate dielectric thin layer on the surface of the super barrier rectifier sample formed in step 4) by thermal oxidation growth, and then forming a polysilicon cover layer on the gate dielectric thin layer by deposition. The polysilicon cover layer is heavily doped. ​

[0010] 6) A masking layer II is formed on the surface of the polysilicon cap layer. Trenches are formed in the masking layer II. The polysilicon cap layer and the gate dielectric thin layer under the trenches of the masking layer II are etched.

[0011] 7) A deep implant of the second conductivity type is performed so that the second conductivity type impurities are implanted through the portion of the trenches formed in step 6) into the lightly doped first conductivity type drift region and are blocked in the portion of the cap layer. The masking layer is removed.

[0012] 8) A second conductivity type body region is formed.

[0013] 9) A metal layer is deposited to form an upper electrode layer and the upper electrode layer forms a Schottky contact with the second conductivity type body region and an ohmic contact with the polysilicon cap layer.

[0014] 10) A lower electrode layer is deposited on the heavily doped first conductivity type substrate lower surface and forms an ohmic contact.

[0015] Further, the process of covering the lightly doped first conductivity type drift region includes epitaxial growth.

[0016] Further, the step of forming trenches on the lightly doped first conductivity type drift region includes:

[0017] 1) A masking layer I is formed on the lightly doped first conductivity type drift region.

[0018] 2) Trenches are formed in the masking layer.

[0019] 3) The lightly doped first conductivity type drift region under the trenches of the masking layer is etched so that trenches are formed on the lightly doped first conductivity type drift region.

[0020] 4) The masking layer I is removed.

[0021] Further, the polysilicon fill layer is located in the U-shaped trench gate dielectric layer.

[0022] Further, the method of forming the second conductivity type body region includes rapid thermal processing.

[0023] Further, the second conductivity type body region is not connected to the U-shaped trench gate dielectric layer. The second conductivity type body region is spaced apart from the U-shaped trench gate dielectric layer.

[0024] The split gate trench Schottky contact super barrier rectifier formed based on the manufacturing method includes a lower electrode layer, a heavily doped first conductivity type substrate layer, a lightly doped first conductivity type drift layer, a U-shaped trench gate dielectric layer, a polysilicon fill layer, a gate dielectric thin layer, a polysilicon cap layer, a second conductivity type body region, and an upper electrode layer.

[0025] The heavily doped first conductive type substrate layer is covered on the lower electrode layer. The lightly doped first conductive type drift layer is covered on the heavily doped first conductive type substrate layer.

[0026] The trench gate dielectric layer is a U-shaped groove, covering part of the surface of the lightly doped first conductive type drift layer. The polysilicon filling layer is filled in the trench gate dielectric layer.

[0027] The gate dielectric thin layer completely covers the polysilicon filling layer and the trench gate dielectric layer, and covers part of the surface of the lightly doped first conductive type drift layer.

[0028] The gate dielectric thin layer also covers part of the surface of the second conductive type body region.

[0029] The polysilicon covering layer is covered on the gate dielectric thin layer.

[0030] The second conductive type body region is covered on part of the surface of the lightly doped first conductive type drift layer.

[0031] The second conductive type body region is not connected with the U-shaped trench gate dielectric layer.

[0032] The second conductive type body region is distributed apart from the U-shaped trench gate dielectric layer.

[0033] The upper electrode layer is covered on the polysilicon covering layer, and covers part of the surface of the second conductive type body region.

[0034] An ohmic contact is formed between the upper electrode layer and the polysilicon covering layer. A Schottky contact is formed between the upper electrode layer and the second conductive type body region.

[0035] Further, the lightly doped first conductive type drift layer, the gate dielectric thin layer, the polysilicon covering layer, the second conductive type body region, and the upper electrode layer together form a Schottky contact super barrier rectifier structure.

[0036] Further, the trench gate dielectric layer, the polysilicon filling layer, the gate dielectric thin layer, and the polysilicon covering layer together form a split gate trench structure.

[0037] Further, the gate dielectric thin layer serves as a gate dielectric material in the Schottky contact super barrier rectifier structure.

[0038] The gate dielectric thin layer serves as an isolation dielectric material in the split gate trench structure, isolating the polysilicon filling layer from the polysilicon covering layer, so that the polysilicon filling layer is not in contact with the polysilicon covering layer.

[0039] The technical effect of the present application is self-evident. The present application introduces a new split gate structure by growing a gate dielectric thin layer. In the case of maintaining good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and the reverse recovery performance is better. At the same time, the gate dielectric thin layer makes the device not need to contact the narrow polysilicon in the trench to the anode metal in the manufacturing process, reduces the minimum line width requirement, and effectively reduces the process complexity and difficulty. The split gate also does not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a schematic diagram of a prior art trench gate MOS Schottky barrier rectifier;

[0041] Figures 2-7 is a schematic cross-sectional view corresponding to the manufacturing method of the split gate trench Schottky contact super barrier rectifier described in the embodiment of the present application;

[0042] Figure 8 is a schematic cross-sectional view of the split gate trench Schottky contact super barrier rectifier described in the embodiment of the present application;

[0043] Figure 9 is a comparison effect diagram of different technical junction capacitances;

[0044] In the figure: lower electrode layer 10, heavily doped first conductive type substrate layer 20, lightly doped first conductive type drift layer 30, mask layer 31, mask layer 32, U-shaped trench gate dielectric layer 40, polysilicon filling layer 50, gate dielectric thin layer 60, polysilicon covering layer 70, second conductive type body region 80 and upper electrode layer 90. DETAILED DESCRIPTION

[0045] The present application will be further described below in conjunction with the embodiments, but should not be understood as limiting the above-mentioned subject matter of the present application to the following embodiments. According to ordinary technical knowledge and conventional means in the art, various substitutions and modifications can be made without departing from the above-mentioned technical idea of the present application, and all should be included in the protection scope of the present application.

[0046] Embodiment 1:

[0047] Referring to Figures 2-9 A manufacturing method of a split gate trench Schottky contact super barrier rectifier, comprising the following steps:

[0048] 1) Covering a lightly doped first conductive type drift region 30 on a heavily doped first conductive type substrate 20.

[0049] 2) Forming a trench on the lightly doped first conductive type drift region 30.

[0050] 3) Cover the trench formed in step 2) with a dielectric layer to form a U-shaped trench grid dielectric layer 40.

[0051] 4) Deposit polysilicon and heavily dope the polysilicon, then perform reverse etching to remove excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3, forming a polysilicon filling layer 50.

[0052] 5) A thermal-oxygen growth process is performed on the surface of the super-barrier rectifier sample formed in step 4) to form a gate dielectric thin layer 60. Then, a polycrystalline silicon capping layer 70 is deposited on the gate dielectric thin layer 60. The polycrystalline silicon capping layer 70 is then heavily doped.

[0053] 6) Cover the surface of the polysilicon capping layer 70 with a mask layer II 32. Form a through-hole in the mask layer II 32. Etch the polysilicon capping layer 70 and the gate dielectric thin layer 60 below the through-hole in the mask layer II 32.

[0054] 7) Perform deep implantation of the second conductivity type impurity, so that the second conductivity type impurity is implanted into the lightly doped first conductivity type drift region 30 through the through-groove portion formed in step 6, and is blocked in the portion covering the mask layer II 32. Remove the mask layer II 32.

[0055] 8) Forming a second type of conductive body region 80.

[0056] 9) Deposit a metal layer to form an upper electrode layer 90, and make the upper electrode layer 90 form a Schottky contact with the second conductivity type body region 80, and the upper electrode layer 90 form an ohmic contact with the polysilicon capping layer 70.

[0057] 10) An electrode layer 10 is deposited on the lower surface of a heavily doped first conductivity type substrate 20, and an ohmic contact is formed.

[0058] The process of covering the lightly doped first conductivity type drift region 30 includes epitaxial growth.

[0059] The step of forming a trench on the lightly doped first conductivity type drift region 30 includes:

[0060] s1) Cover the lightly doped first conductivity type drift region 30 with a mask layer I31.

[0061] s2) A through groove is formed in the mask layer I31.

[0062] s3) Etch the lightly doped first conductivity type drift region 30 below the through-groove of the mask layer I31, so that a trench is formed on the lightly doped first conductivity type drift region 30.

[0063] s4) Remove the mask layer I31.

[0064] The polysilicon fill layer 50 is located in the U-shaped trench gate dielectric layer 40.

[0065] The method of forming the second conductivity type body region 80 includes a rapid thermal process.

[0066] The second conductivity type body region 80 is not connected to the U-shaped trench gate dielectric layer 40. The second conductivity type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40.

[0067] Example 2:

[0068] The split gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of Example 1 includes a lower electrode layer 10, a heavily doped first conductivity type substrate layer 20, a lightly doped first conductivity type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon fill layer 50, a gate dielectric thin layer 60, a polysilicon cover layer 70, a second conductivity type body region 80, and an upper electrode layer 90.

[0069] The heavily doped first conductivity type substrate layer 20 is located on the lower electrode layer 10. The lightly doped first conductivity type drift layer 30 is located on the heavily doped first conductivity type substrate layer 20.

[0070] The trench gate dielectric layer 40 is a U-shaped trench and covers part of the surface of the lightly doped first conductivity type drift layer 30. The polysilicon fill layer 50 is filled in the trench gate dielectric layer 40.

[0071] The gate dielectric thin layer 60 completely covers the polysilicon fill layer 50 and the trench gate dielectric layer 40, and covers part of the surface of the lightly doped first conductivity type drift layer 30.

[0072] The gate dielectric thin layer 60 also covers part of the surface of the second conductivity type body region 80.

[0073] The polysilicon cover layer 70 is located on the gate dielectric thin layer 60.

[0074] The second conductivity type body region 80 is located on part of the surface of the lightly doped first conductivity type drift layer 30.

[0075] The second conductivity type body region 80 is not connected to the U-shaped trench gate dielectric layer 40.

[0076] The second conductivity type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40.

[0077] The upper electrode layer 90 covers the polysilicon cover layer 70 and covers part of the surface of the second conductivity type body region 80.

[0078] The upper electrode layer 90 forms an ohmic contact with the polysilicon covering layer 70. The upper electrode layer 90 forms a Schottky contact with the second conductive type body region 80.

[0079] The lightly doped first conductive type drift layer 30, the gate dielectric thin layer 60, the polysilicon covering layer 70, the second conductive type body region 80, and the upper electrode layer 90 together form a Schottky contact super barrier rectifier structure.

[0080] The trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon covering layer 70 together form a split gate trench structure.

[0081] The gate dielectric thin layer 60 serves as a gate dielectric material in the Schottky contact super barrier rectifier structure.

[0082] The gate dielectric thin layer 60 serves as an isolation dielectric material in the split gate trench structure, isolating the polysilicon filling layer 50 from the polysilicon covering layer 70, so that the polysilicon filling layer 50 and the polysilicon covering layer 70 are not in contact.

[0083] Embodiment 3:

[0084] A method for manufacturing a split gate trench Schottky contact super barrier rectifier, comprising the following steps:

[0085] 1) Form a lightly doped first conductive type drift region 30 on a heavily doped first conductive type substrate 20.

[0086] 2) Form a trench on the lightly doped first conductive type drift region 30.

[0087] 3) Form a dielectric layer in the trench formed in step 2), forming a U-shaped trench gate dielectric layer 40.

[0088] 4) Deposit polysilicon, and heavily dope the polysilicon, then perform reverse etching to remove the excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3), forming a polysilicon filling layer 50.

[0089] 5) Perform thermal oxidation growth on the surface of the super barrier rectifier sample formed in step 4), forming a gate dielectric thin layer 60, then deposit a polysilicon covering layer 70 on the gate dielectric thin layer 60. The polysilicon covering layer 70 is heavily doped.

[0090] 6) Form a through slot in a mask layer II 32 on the surface of the polysilicon covering layer 70. Etch the polysilicon covering layer 70 and the gate dielectric thin layer 60 under the through slot of the mask layer II 32.

[0091] 7) performing a deep implant of the second conductivity type impurities, so that the second conductivity type impurities are implanted into the lightly doped first conductivity type drift region 30 through the via formed in step 6) while being blocked at the portion of the cover mask layer II 32. The mask layer II 32 is removed.

[0092] 8) forming the second conductivity type body region 80.

[0093] 9) depositing a metal layer to form the upper electrode layer 90, and forming a Schottky contact between the upper electrode layer 90 and the second conductivity type body region 80, and forming an ohmic contact between the upper electrode layer 90 and the polysilicon cover layer 70.

[0094] 10) depositing a lower electrode layer 10 on the lower surface of the heavily doped first conductivity type substrate 20, and forming an ohmic contact.

[0095] Example 4:

[0096] A method of manufacturing a split-gate trench Schottky contact super barrier rectifier, the technical content of which is the same as that of any one of Examples 3-5, further comprising epitaxial growth for covering the lightly doped first conductivity type drift region 30.

[0097] Example 5:

[0098] A method of manufacturing a split-gate trench Schottky contact super barrier rectifier, the technical content of which is the same as that of any one of Examples 3-4, further comprising the step of forming a trench on the lightly doped first conductivity type drift region 30, which comprises:

[0099] 1) covering the lightly doped first conductivity type drift region 30 with a mask layer I 31.

[0100] 2) forming a via in the mask layer I 31.

[0101] 3) etching the lightly doped first conductivity type drift region 30 under the via of the mask layer I 31, so that a trench is formed on the lightly doped first conductivity type drift region 30.

[0102] 4) removing the mask layer I 31.

[0103] Example 6:

[0104] A method of manufacturing a split-gate trench Schottky contact super barrier rectifier, the technical content of which is the same as that of any one of Examples 3-5, further comprising that the polysilicon fill layer 50 is located in the U-shaped trench gate dielectric layer 40.

[0105] Example 7:

[0106] A method of manufacturing a split-gate trench Schottky contact super barrier rectifier, the technical content of which is the same as that of any one of Examples 3-6, further comprising that the method of forming the second conductivity type body region 80 comprises rapid thermal processing.

[0107] Embodiment 8:

[0108] A method for manufacturing a split gate trench Schottky contact super barrier rectifier, the technical contents are the same as any one of embodiments 3-7, further, the second conductive type body region 80 is not connected with the U-shaped trench gate dielectric layer 40. The second conductive type body region 80 is distributed apart from the U-shaped trench gate dielectric layer 40.

[0109] Embodiment 9:

[0110] A split gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of any one of embodiments 3-8, comprising a lower electrode layer 10, a heavily doped first conductive type substrate layer 20, a lightly doped first conductive type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon covering layer 70, a second conductive type body region 80 and an upper electrode layer 90.

[0111] The heavily doped first conductive type substrate layer 20 is covered on the lower electrode layer 10. The lightly doped first conductive type drift layer 30 is covered on the heavily doped first conductive type substrate layer 20.

[0112] The trench gate dielectric layer 40 is a U-shaped groove, covering part of the surface of the lightly doped first conductive type drift layer 30. The polysilicon filling layer 50 is filled in the trench gate dielectric layer 40.

[0113] The gate dielectric thin layer 60 is completely covered on the polysilicon filling layer 50 and the trench gate dielectric layer 40, and covers part of the surface of the lightly doped first conductive type drift layer 30.

[0114] The gate dielectric thin layer 60 also covers part of the surface of the second conductive type body region 80.

[0115] The polysilicon covering layer 70 is covered on the gate dielectric thin layer 60.

[0116] The second conductive type body region 80 is covered on part of the surface of the lightly doped first conductive type drift layer 30.

[0117] The second conductive type body region 80 is not connected with the U-shaped trench gate dielectric layer 40.

[0118] The second conductive type body region 80 is distributed apart from the U-shaped trench gate dielectric layer 40.

[0119] The upper electrode layer 90 is covered on the polysilicon covering layer 70, and covers part of the surface of the second conductive type body region 80.

[0120] An ohmic contact is formed between the upper electrode layer 90 and the polysilicon cover layer 70. A Schottky contact is formed between the upper electrode layer 90 and the second-conductivity-type body region 80.

[0121] Embodiment 10:

[0122] The split-gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of any one of Embodiments 3-8, the technical content of which is the same as that of Embodiment 9, further, the lightly-doped first-conductivity-type drift layer 30, the gate dielectric thin layer 60, the polysilicon cover layer 70, the second-conductivity-type body region 80, and the upper electrode layer 90 together form a Schottky contact super barrier rectifier structure.

[0123] Embodiment 11:

[0124] The split-gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of any one of Embodiments 3-8, the technical content of which is the same as that of any one of Embodiments 9-10, further, the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon cover layer 70 together form a split-gate trench structure.

[0125] Embodiment 12:

[0126] The split-gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of any one of Embodiments 3-8, the technical content of which is the same as that of any one of Embodiments 9-11, further, the gate dielectric thin layer 60 serves as a gate dielectric material in the Schottky contact super barrier rectifier structure.

[0127] The gate dielectric thin layer 60 serves as an isolation dielectric material in the split-gate trench structure, and separates the polysilicon filling layer 50 from the polysilicon cover layer 70, so that the polysilicon filling layer 50 and the polysilicon cover layer 70 are not in contact.

[0128] Embodiment 13:

[0129] A manufacturing method of a split-gate trench Schottky contact super barrier rectifier, comprising the following main steps:

[0130] 1) As shown in FIG. 1, a lightly-doped first-conductivity-type drift region 30 is covered on a heavily-doped first-conductivity-type substrate 20; the covering is preferably epitaxial growth; Figure 2 2) As shown in FIG. 2, a mask layer I 31 is covered on the lightly-doped first-conductivity-type drift region 30; a through slot is formed in the mask layer I 31; the lightly-doped first-conductivity-type drift region 30 under the mask layer I 31 is etched, so that after a trench is formed on the lightly-doped first-conductivity-type drift region 30, the mask layer I 31 is removed;

[0131] Figure 3 3) As shown in FIG. 3, a trench gate dielectric layer 40 is formed on the trench formed on the lightly-doped first-conductivity-type drift region 30; the trench gate dielectric layer 40 is preferably formed by a thermal oxidation process;

[0132] ​3) such as Figure 4 As shown, a dielectric layer is covered in the trench formed in step 2 to form a U-shaped trench gate dielectric layer 40;

[0133] 4) such as Figure 5 As shown, polysilicon is deposited and heavily doped. Then, reverse etching is performed to remove excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3, finally forming a polysilicon filling layer 50. The polysilicon filling layer 50 is located inside the U-shaped trench gate dielectric layer 40.

[0134] 5) Perform thermal oxidation growth on the surface of the sample formed in step 4 to form a gate dielectric thin layer 60, and then deposit a polycrystalline silicon capping layer 70 on the gate dielectric thin layer 60; then heavily dope the polycrystalline silicon capping layer 70.

[0135] 6) such as Figure 6 As shown, a mask layer II32 is covered on the surface of the polysilicon capping layer 70; a through-hole is formed in the mask layer II32; the polysilicon capping layer 70 and the gate dielectric thin layer 60 below the through-hole of the mask layer II32 are etched.

[0136] 7) Select an appropriate injection energy to perform deep implantation of the second conductivity type impurity, so that the second conductivity type impurity is injected into the lightly doped first conductivity type drift region 30 in the through-groove portion formed in step 6, while being blocked in the portion covering the mask layer II 32; remove the mask layer II 32;

[0137] 8) For example Figure 7 As shown, a second conductive type body region 80 is formed by rapid heat treatment; the second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the second conductive type body region 80 and the U-shaped trench gate dielectric layer 40 are distributed at intervals.

[0138] 9) Deposit a metal layer to form an upper electrode layer 90; and make the upper electrode layer 90 form a Schottky contact with the second conductivity type body region 80, and make the upper electrode layer 90 form an ohmic contact with the polysilicon capping layer 70.

[0139] 10) An electrode layer 10 is deposited on the lower surface of a heavily doped first conductivity type substrate 20, and an ohmic contact is formed.

[0140] like Figure 8As shown, the embodiment of the present application introduces a new split gate structure by growing a gate dielectric thin layer on the basis of the conventional trench structure. In the case of maintaining good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and the reverse recovery performance is better. At the same time, the gate dielectric thin layer makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal in the manufacturing process of the device, reduces the minimum line width requirement, and effectively reduces the process complexity and difficulty. The split gate does not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device.

[0141] Embodiment 14:

[0142] The device structure of the split gate trench Schottky contact super barrier rectifier formed according to the manufacturing method of the split gate trench Schottky contact super barrier rectifier given in Embodiment 13 comprises a lower electrode layer 10, a heavily doped first-conductivity-type substrate layer 20, a lightly doped first-conductivity-type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon covering layer 70, a second-conductivity-type body region 80, and an upper electrode layer 90;

[0143] The heavily doped first-conductivity-type substrate layer 20 is covered on the lower electrode layer 10; and the lightly doped first-conductivity-type drift layer 30 is covered on the heavily doped first-conductivity-type substrate layer 20;

[0144] The trench gate dielectric layer 40 is a U-shaped groove, which covers part of the surface of the lightly doped first-conductivity-type drift layer 30; and the polysilicon filling layer 50 is filled in the trench gate dielectric layer 40;

[0145] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40, and covers part of the surface of the lightly doped first-conductivity-type drift layer 30 and part of the surface of the second-conductivity-type body region 80; and the polysilicon covering layer 70 is covered on the gate dielectric thin layer 60;

[0146] The second-conductivity-type body region 80 is covered on part of the surface of the lightly doped first-conductivity-type drift layer 30; the second-conductivity-type body region 80 is not connected with the U-shaped trench gate dielectric layer 40; and the second-conductivity-type body region 80 is distributed in intervals with the U-shaped trench gate dielectric layer 40;

[0147] The upper electrode layer 90 is covered on the polysilicon covering layer 70 and part of the surface of the second-conductivity-type body region 80; an ohmic contact is formed between the upper electrode layer 90 and the polysilicon covering layer 70; and a Schottky contact is formed between the upper electrode layer 90 and the second-conductivity-type body region 80;

[0148] The lightly doped first-conductivity-type drift layer 30, the gate dielectric thin layer 60, the polysilicon cover layer 70, the second-conductivity-type body region 80, and the upper electrode layer 90 together form a Schottky contact super barrier rectifier structure; and the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon cover layer 70 together form a split gate trench structure.

[0149] The gate dielectric thin layer 60 serves as a gate dielectric material in the Schottky contact super barrier rectifier structure, and simultaneously serves as an isolation dielectric material in the split gate trench structure, so as to isolate the polysilicon filling layer 50 from the polysilicon cover layer 70 and prevent the polysilicon filling layer 50 from contacting the polysilicon cover layer 70.

[0150] The materials of the heavily doped first-conductivity-type substrate layer 20 and the lightly doped first-conductivity-type drift layer 30 are preferably silicon and silicon carbide; the materials of the polysilicon filling layer 50 and the polysilicon cover layer 70 are preferably polysilicon; and the materials of the trench gate dielectric layer 40 and the gate dielectric thin layer 60 are preferably silicon dioxide, silicon oxynitride, or hafnium oxide.

[0151] As shown in Figure 8 On the basis of a conventional trench structure, the embodiment of the present application introduces a newly added split gate structure by growing a gate dielectric thin layer. In the case of maintaining good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and the device has better reverse recovery performance. Meanwhile, the gate dielectric thin layer makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal in the manufacturing process of the device, reduces the required minimum line width requirement, and effectively reduces the process complexity and difficulty. The split gate does not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device.

[0152] Embodiment 15

[0153] The first-conductivity-type is selected as N type, and the second-conductivity-type is selected as P type. The embodiment discloses a manufacturing method of a split gate trench Schottky contact super barrier rectifier and a device structure thereof.

[0154] The manufacturing method of the split gate trench Schottky contact super barrier rectifier comprises the following main steps:

[0155] 1) As shown in Figure 2 A lightly doped N-type drift region 30 is epitaxially grown on a heavily doped N-type substrate 20; the materials of the heavily doped N-type substrate 20 and the lightly doped N-type drift region 30 are selected as silicon; and the thickness of the lightly doped N-type drift region 30 is about 10 microns;

[0156] 2) As shown in Figure 3As shown, a mask layer I31 is covered on the lightly doped N-type drift region 30; a through-groove is formed in the mask layer I31; the lightly doped N-type drift region 30 below the through-groove of the mask layer I31 is etched so that a trench is formed on the lightly doped N-type drift region 30, and then the mask layer I31 is removed; the depth of the trench is about 4 micrometers and the width is about 1.5 micrometers.

[0157] 3) such as Figure 4 As shown, an oxide layer is thermally grown in the trench formed in step 2, with a thickness of approximately 0.5 micrometers; a U-shaped trench gate dielectric layer 40 is formed.

[0158] 4) such as Figure 5 As shown, polysilicon is deposited and heavily doped. Then, reverse etching is performed to remove excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3, finally forming a polysilicon filling layer 50. The polysilicon filling layer 50 is located inside the U-shaped trench gate dielectric layer 40.

[0159] 5) Perform thermal oxidation growth on the surface of the sample formed in step 4 to form a gate dielectric thin layer 60 with a thickness of about 5 nanometers. Then, deposit a polycrystalline silicon capping layer 70 with a thickness of about 0.4 micrometers on the gate dielectric thin layer 60. The polycrystalline silicon capping layer 70 is then heavily doped.

[0160] 6) such as Figure 6 As shown, a mask layer II32 is covered on the surface of the polysilicon capping layer 70; a through-hole is formed in the mask layer II32; the polysilicon capping layer 70 and the gate dielectric thin layer 60 below the through-hole of the mask layer II32 are etched.

[0161] 7) Select an appropriate implantation energy to perform deep implantation of P-type impurities, so that the P-type impurities are implanted into the lightly doped N-type drift region 30 in the through-groove portion formed in step 6, while being blocked in the portion covered by the mask layer II 32; remove the mask layer II 32.

[0162] 8) For example Figure 7 As shown, a rapid heat treatment forms a P-type body region 80; the P-type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the P-type body region 80 and the U-shaped trench gate dielectric layer 40 are distributed at intervals.

[0163] 9) Deposit a metal layer to form an upper electrode layer 90; and make the upper electrode layer 90 form a Schottky contact with the P-type body region 80, and make the upper electrode layer 90 form an ohmic contact with the polycrystalline silicon capping layer 70; the metal deposited in the upper electrode layer 90 may be Pt, PtNi, Ti or TiN.

[0164] 10) An electrode layer 10 is deposited on the lower surface of a heavily doped N-type substrate 20, and an ohmic contact is formed.

[0165] According to the manufacturing method, the formed split gate trench Schottky contact super barrier rectifier comprises a lower electrode layer 10, a heavily doped N-type substrate 20, a lightly doped N-type drift region 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon covering layer 70, a P-type body region 80 and an upper electrode layer 90.

[0166] The heavily doped N-type substrate 20 is covered on the lower electrode layer 10; the lightly doped N-type drift region 30 is covered on the heavily doped N-type substrate 20.

[0167] The trench gate dielectric layer 40 is a U-shaped groove, covering part of the surface of the lightly doped N-type drift region 30; the polysilicon filling layer 50 is filled in the trench gate dielectric layer 40.

[0168] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40, and covers part of the surface of the lightly doped N-type drift region 30 and part of the surface of the P-type body region 80; the polysilicon covering layer 70 is covered on the gate dielectric thin layer 60.

[0169] The P-type body region 80 is covered on part of the surface of the lightly doped first conductive type drift layer 30; the P-type body region 80 is not connected with the U-shaped trench gate dielectric layer 40; the P-type body region 80 is distributed at intervals with the U-shaped trench gate dielectric layer 40.

[0170] The upper electrode layer 90 is covered on the polysilicon covering layer 70 and part of the surface of the P-type body region 80; the upper electrode layer 90 forms an ohmic contact with the polysilicon covering layer 70; the upper electrode layer 90 forms a Schottky contact with the P-type body region 80.

[0171] The lightly doped N-type drift region 30, the gate dielectric thin layer 60, the polysilicon covering layer 70, the P-type body region 80 and the upper electrode layer 90 together form a Schottky contact super barrier rectifier structure; the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60 and the polysilicon covering layer 70 together form a split gate trench structure.

[0172] The gate dielectric thin layer 60 serves as a gate dielectric material in the Schottky contact super barrier rectifier structure, and simultaneously serves as an isolation dielectric material in the split gate trench structure, so as to isolate the polysilicon filling layer 50 from the polysilicon covering layer 70, and make the polysilicon filling layer 50 not contact with the polysilicon covering layer 70.

[0173] The embodiment of the present application introduces a new split gate structure by growing a gate dielectric thin layer on the basis of the conventional trench structure. In the case of maintaining good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and the device has better reverse recovery performance. Meanwhile, the gate dielectric thin layer makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal in the manufacturing process of the device, reduces the required minimum line width requirement, and effectively reduces the process complexity and difficulty. The split gate does not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device. Figure 9 The size of the junction capacitance is shown in the comparison between the case of using the conventional trench gate MOS structure and the case of using the split gate structure of the present application. It can be seen that the split gate structure of the present application can reduce the rectifier barrier capacitance, thereby improving the reverse recovery characteristics of the device.

Claims

1. A method of manufacturing a split-gate trench Schottky contact super barrier rectifier, characterized by, The method comprises the following steps: 1) covering a lightly doped first-conductivity-type drift region (30) on a heavily doped first-conductivity-type substrate (20); 2) forming a trench on the lightly doped first-conductivity-type drift region (30); 3) covering a dielectric layer in the trench formed in step 2) to form a U-shaped trench gate dielectric layer (40); 4) depositing polysilicon, heavily doping the polysilicon, and then performing reverse etching to remove the polysilicon outside the U-shaped trench gate dielectric layer (40) formed in step 3) to form a polysilicon filling layer (50); 5) performing thermal oxidation growth on the surface of the super barrier rectifier sample formed in step 4) to form a gate dielectric thin layer (60), and then depositing a polysilicon covering layer (70) on the gate dielectric thin layer (60); and heavily doping the polysilicon covering layer (70); 6) covering a mask layer II (32) on the surface of the polysilicon covering layer (70); forming a through slot in the mask layer II (32); and etching the polysilicon covering layer (70) and the gate dielectric thin layer (60) under the through slot of the mask layer II (32); 7) performing deep implantation of a second-conductivity-type impurity, so that the second-conductivity-type impurity is partially implanted into the lightly doped first-conductivity-type drift region (30) through the through slot formed in step 6) and is blocked in the part covered by the mask layer II (32); and removing the mask layer II (32); 8) forming a second-conductivity-type body region (80); 9) depositing a metal layer to form an upper electrode layer (90), and forming a Schottky contact between the upper electrode layer (90) and the second-conductivity-type body region (80), and forming an ohmic contact between the upper electrode layer (90) and the polysilicon covering layer (70); 10) depositing a lower electrode layer (10) on the lower surface of the heavily doped first-conductivity-type substrate (20) to form an ohmic contact.

2. The method of manufacturing a split gate trench Schottky contact super barrier rectifier as recited in claim 1, wherein: The process of covering the lightly doped first-conductivity-type drift region (30) comprises epitaxial growth.

3. The method of manufacturing a split gate trench Schottky contact super barrier rectifier as recited in claim 1, wherein, The step of forming a trench on the lightly doped first-conductivity-type drift region (30) comprises: 1) covering a mask layer I (31) on the lightly doped first-conductivity-type drift region (30); 2) forming a through slot in the mask layer I (31); 3) etching the lightly doped first-conductivity-type drift region (30) under the through slot of the mask layer I (31) to form a trench on the lightly doped first-conductivity-type drift region (30); 4) removing the mask layer I (31).

4. The method of manufacturing a split gate trench Schottky contact super barrier rectifier as recited in claim 1, wherein, The polysilicon filling layer (50) is located in the U-shaped trench gate dielectric layer (40).

5. The method of manufacturing a split gate trench Schottky contact super barrier rectifier as defined in claim 1, wherein, The method of forming the second-conductivity-type body region (80) comprises rapid thermal treatment.

6. The method of manufacturing a split gate trench Schottky contact super barrier rectifier as defined in claim 1, wherein, The second-conductivity-type body region (80) is not connected with the U-shaped trench gate dielectric layer (40); and the second-conductivity-type body region (80) is distributed apart from the U-shaped trench gate dielectric layer (40).

7. The split-gate trench Schottky contact super barrier rectifier formed based on the manufacturing method of any one of claims 1-6, characterized in that, The device comprises a lower electrode layer (10), a heavily doped first-conductivity-type substrate layer (20), a lightly doped first-conductivity-type drift layer (30), a U-shaped trench gate dielectric layer (40), a polysilicon filling layer (50), a gate dielectric thin layer (60), a polysilicon covering layer (70), a second-conductivity-type body region (80), and an upper electrode layer (90). The heavily doped first-conductivity-type substrate layer (20) is covered on the lower electrode layer (10); the lightly doped first-conductivity-type drift layer (30) is covered on the heavily doped first-conductivity-type substrate layer (20); The trench gate dielectric layer (40) is a U-shaped groove, covering part of the surface of the lightly doped first-conductivity-type drift layer (30); the polysilicon filling layer (50) is filled in the trench gate dielectric layer (40); The gate dielectric thin layer (60) completely covers the polysilicon filling layer (50) and the trench gate dielectric layer (40), and covers part of the surface of the lightly doped first-conductivity-type drift layer (30); The gate dielectric thin layer (60) also covers part of the surface of the second-conductivity-type body region (80); The polysilicon covering layer (70) is covered on the gate dielectric thin layer (60); The second-conductivity-type body region (80) is covered on part of the surface of the lightly doped first-conductivity-type drift layer (30); The second-conductivity-type body region (80) is not connected with the U-shaped trench gate dielectric layer (40); The second-conductivity-type body region (80) is distributed apart from the U-shaped trench gate dielectric layer (40); The upper electrode layer (90) is covered on the polysilicon covering layer (70), and covers part of the surface of the second-conductivity-type body region (80); The upper electrode layer (90) and the polysilicon covering layer (70) form an ohmic contact; the upper electrode layer (90) and the second-conductivity-type body region (80) form a Schottky contact.

8. The split-gate trench Schottky contact super barrier rectifier of claim 7, wherein, The lightly doped first-conductivity-type drift layer (30), the gate dielectric thin layer (60), the polysilicon covering layer (70), the second-conductivity-type body region (80), and the upper electrode layer (90) together form a Schottky contact super barrier rectifier structure.

9. The split-gate trench Schottky contact super barrier rectifier of claim 7, wherein, The trench gate dielectric layer (40), the polysilicon filling layer (50), the gate dielectric thin layer (60), and the polysilicon covering layer (70) together form a split gate trench structure.

10. The split-gate trench Schottky contact super barrier rectifier of claim 9, wherein, The gate dielectric thin layer (60) serves as a gate dielectric material in the Schottky contact super barrier rectifier structure; The gate dielectric thin layer (60) serves as an isolation dielectric material in the split gate trench structure, isolating the polysilicon filling layer (50) from the polysilicon covering layer (70), so that the polysilicon filling layer (50) and the polysilicon covering layer (70) are not in contact.

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