Semiconductor structure and preparation method thereof

Abstract

The present invention relates to a semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first device structure, wherein the first device structure includes a first active layer, a first isolation protection layer, a second active layer, a first gate trench, a first gate structure, and a first semiconductor layer. The first active layer is located on the upper surface of the substrate. The first isolation protection layer is located on the upper surface of the substrate and covers the first active layer. The second active layer is located on the upper surface of the first isolation protection layer. The first gate trench penetrates the second active layer and the first isolation protection layer and extends into the first active layer. The first gate structure is located in the first gate trench. The first semiconductor layer is located on the sidewalls and bottom of the first gate trench and surrounds the first gate structure. The material of the first semiconductor layer is the same as that of the first active layer and the second active layer. The semiconductor structure can optimize the on-state characteristics of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, in order to achieve high-density memory, dynamic random access memory (DRAM) based on a capacitor-free indium gallium zinc oxide (IGZO) structure has emerged.

[0003] IGZO semiconductor devices are known for their very low off-state current, which can improve the data retention ability of memory cells and have promising application prospects. However, for IGZO semiconductor devices, the on-state characteristics have a decisive influence on their switching speed, power consumption, and service life. Therefore, how to further optimize the electrical performance of semiconductor devices has become a pressing issue. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problems in the prior art, which can at least optimize the on-state characteristics of the semiconductor device.

[0005] According to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes a substrate and a first device structure; wherein the first device structure includes a first active layer, a first isolation protection layer, a second active layer, a first gate trench, a first gate structure and a first semiconductor layer; the first active layer is located on the upper surface of the substrate; the first isolation protection layer is located on the upper surface of the substrate and covers the first active layer; the second active layer is located on the upper surface of the first isolation protection layer; the first gate trench passes through the second active layer and the first isolation protection layer and extends into the first active layer; the first gate structure is located in the first gate trench; the first semiconductor layer is located on the sidewalls and bottom of the first gate trench and surrounds the first gate structure; the material of the first semiconductor layer is the same as the material of the first active layer and the material of the second active layer.

[0006] In the semiconductor structure of the above embodiment, due to the contact resistance between device structures made of different materials, the resistivity is relatively high. In the first device structure of this embodiment, by providing a first semiconductor layer, a first active layer, and a second active layer made of the same material, the above three are made into a structure using homogeneous materials, thereby avoiding the contact resistance between heterogeneous materials, thereby significantly reducing the resistivity and optimizing the on-state characteristics. In addition, the first isolation protection layer is used to provide isolation protection for the first active layer and the second active layer to avoid external influences. It penetrates the second active layer and the first isolation protection layer and extends to the first gate trench in the first active layer, as well as the first gate structure located in the first gate trench, which is conducive to the vertical stacking of semiconductor structures to increase storage density. Thus, while achieving high-density storage, the on-state characteristics of the semiconductor device are improved.

[0007] In some embodiments, the first semiconductor layer includes an intrinsic indium gallium zinc oxide layer; and the first active layer and the second active layer both include a doped indium gallium zinc oxide layer.

[0008] In some embodiments, the first gate structure includes a first gate and a first gate dielectric layer; the first gate is located in the first gate trench; the first gate dielectric layer is located between the first gate and the first semiconductor layer; the first device structure also includes a first lead-out electrode and a second lead-out electrode; the first lead-out electrode is in contact with the second active layer; and the second lead-out electrode is in contact with the first gate.

[0009] In some embodiments, the semiconductor structure also includes a second device structure, the second device structure includes a third active layer, a second isolation protection layer, a fourth active layer, a second gate trench, a second gate structure and a second semiconductor layer; the third active layer is located on the first device structure; the second isolation protection layer is located on the first device structure and covers the third active layer; the fourth active layer is located on the upper surface of the second isolation protection layer; the second gate trench passes through the fourth active layer and the second isolation protection layer and extends into the third active layer; the second gate structure is located in the second gate trench; the second semiconductor layer is located on the sidewalls and bottom of the second gate trench and surrounds the second gate structure; the material of the second semiconductor layer is the same as the material of the third active layer and the material of the fourth active layer.

[0010] In some embodiments, the material of the first semiconductor layer, the material of the second semiconductor layer, the material of the first active layer, the material of the second active layer, the material of the third active layer, and the material of the fourth active layer are all the same.

[0011] In some embodiments, the second gate structure includes a second gate and a second gate dielectric layer; the second gate is located in the second gate trench; the second gate dielectric layer is located between the second gate and the second semiconductor layer; the second device structure also includes a third lead-out electrode, and the third lead-out electrode is in contact with the fourth active layer.

[0012] In some embodiments, there are multiple second device structures, and the multiple second device structures are stacked sequentially from bottom to top.

[0013] According to some embodiments, another aspect of the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate; forming a first device structure on the upper surface of the substrate; forming the first device structure on the upper surface of the substrate, including: forming a first active layer on the upper surface of the substrate; forming a first isolation protection layer on the upper surface of the substrate, the first isolation protection layer covering the first active layer; forming a second active layer on the upper surface of the first isolation protection layer; forming a first gate trench, the first gate trench passing through the second active layer and the first isolation protection layer, and extending into the first active layer; forming a first gate structure and a first semiconductor layer in the first gate trench; the first semiconductor layer is located on the sidewalls and bottom of the first gate trench, and surrounds the first gate structure; the material of the first semiconductor layer is the same as the material of the first active layer and the material of the second active layer.

[0014] In some embodiments, the first gate structure includes a first gate and a first gate dielectric layer; the first gate is located in the first gate trench; the first gate dielectric layer is located between the first gate and the first semiconductor layer; after the first gate structure and the first semiconductor layer are formed in the first gate trench, it also includes: forming a first lead-out electrode and a second lead-out electrode; the first lead-out electrode is in contact with the second active layer; and the second lead-out electrode is in contact with the first gate.

[0015] In some embodiments, after forming the first device structure on the upper surface of the substrate, it also includes: forming a second device structure on the first device structure; forming the second device structure on the first device structure, including: forming a third active layer and a second isolation protection layer on the first device structure, the second isolation protection layer covering the third active layer; forming a fourth active layer on the upper surface of the second isolation protection layer; forming a second gate trench, the second gate trench passing through the fourth active layer and the second isolation protection layer, and extending into the third active layer; forming a second gate structure and a second semiconductor layer in the second gate trench; the second semiconductor layer is located on the sidewalls and bottom of the second gate trench, and surrounds the second gate structure; the material of the second semiconductor layer is the same as the material of the third active layer and the material of the fourth active layer.

[0016] In some embodiments, the second gate structure includes a second gate and a second gate dielectric layer: the second gate is located in the second gate trench; the second gate dielectric layer is located between the second gate and the second semiconductor layer; after the second gate structure and the second semiconductor layer are formed in the second gate trench, it also includes: forming a third extraction electrode, and the third extraction electrode is in contact with the fourth active layer.

[0017] In some embodiments, after forming the second device structure on the first device structure, the method further includes: repeating the step of forming the second device structure at least once to form a plurality of second device structures stacked sequentially from bottom to top. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 Figure (a) is a schematic three-dimensional diagram of an IGZO semiconductor structure; Figure (b) is a schematic cross-sectional diagram of the structure shown in Figure (a); Figure (c) is a schematic top view of the structure shown in Figure (a);

[0020] Figure 2 Figures (a) to (d) are Figure 1 Schematic cross-sectional views of the structures obtained at different steps in the method for preparing the structure shown;

[0021] Figure 3 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of a curve showing the change of drain current with drain voltage in a semiconductor structure provided in one embodiment of the present disclosure;

[0023] Figure 5 A schematic diagram of a curve showing changes in source current and field-effect mobility with gate voltage in a semiconductor structure provided in one embodiment of the present disclosure;

[0024] Figure 6 is a schematic cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0025] Figure 7 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figure 8 This is a schematic cross-sectional view of a structure obtained in step 21 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0027] Figure 9 This is a schematic cross-sectional view of a structure obtained in step 22 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0028] Figure 10This is a schematic cross-sectional view of a structure obtained in step 23 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0029] Figure 11 This is a schematic cross-sectional view of a structure obtained in step 24 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0030] Figure 12 This is a schematic cross-sectional view of a structure obtained in step 251 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0031] Figure 13 This is a schematic cross-sectional view of a structure obtained in step 252 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0032] Figure 14 This is a schematic cross-sectional view of a structure obtained in step 253 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0033] Figure 15 This is a schematic cross-sectional view of a structure obtained in step 254 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0034] Figure 16 This is a schematic cross-sectional view of a structure obtained in step 261 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0035] Figure 17 This is a schematic cross-sectional view of a structure obtained in step 262 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0036] Figure 18 This is a schematic cross-sectional view of a structure obtained in step 263 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0037] Figure 19 This is a schematic cross-sectional view of a structure obtained in step 311 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0038] Figure 20 This is a schematic cross-sectional view of a structure obtained in step 312 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0039] Figure 21 Schematic cross-sectional view of the structure obtained in step 313 and step 32 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0040] Figure 22This is a schematic cross-sectional view of a structure obtained in step 33 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0041] Figure 23 This is a schematic cross-sectional view of a structure obtained in step 341 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0042] Figure 24 Schematic cross-sectional view of the structure obtained in step 342 and step 35 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0043] Figure 25 Schematic diagram of a cross-section of a structure obtained in step 40 of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0044] Description of reference numerals:

[0045] 10. Substrate; 1A. First device structure; 1B. Second device structure;

[0046] 21. First active layer; 22. Second active layer; 23. Third active layer; 24. Fourth active layer; 31. First isolation protection layer; 311. First dielectric layer; 312. Second dielectric layer; 313. Third dielectric layer; 32. Second isolation protection layer; 321. Fourth dielectric layer; 322. Fifth dielectric layer; 323. Sixth dielectric layer; 324. Seventh dielectric layer; 33. Passivation layer; 41. First gate trench; 42. Second gate trench; 51. First gate structure; 511. First gate; 511′, First gate material layer; 512, first gate dielectric layer; 512', first gate dielectric material layer; 52, second gate structure; 521, second gate; 521', second gate material layer; 522, second gate dielectric layer; 522', second gate dielectric material layer; 61, first semiconductor layer; 61', first semiconductor material layer; 62, second semiconductor layer; 62', second semiconductor material layer; 70, conductive material layer; 71, first lead electrode; 71', electrode contact hole; 72, second lead electrode; 73, third lead electrode; 74, fourth lead electrode. DETAILED DESCRIPTION

[0047] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0050] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0051] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Please refer to Figure 1 and Figure 2 ,In realizing high-density 3D DRAM memory, the memory cell architecture based on IGZO semiconductor ,structure has wide applications. Figure 1 A capacitor-free DRAM cell is shown, which implements a cell architecture with two IGZO thin-film transistors and no capacitors, namely a 2T0C structure. The 2T0C structure can use the parasitic capacitance of the read transistor as a storage element. The 2T0C structure can overcome the key constraints of the traditional DRAM cell structure of one transistor and one capacitor, namely the 1T1C structure, in terms of density improvement. For example, the cut-off current of the small-sized unit silicon transistor is large, which easily leads to charge leakage, and the storage capacitor occupies too large a device area. In addition, IGZO semiconductor devices are known for their very low cut-off current, which can improve the data retention capability of the storage cell and have good application prospects. For IGZO semiconductor devices, the on-state characteristics have a decisive influence on their switching speed, power consumption, service life, etc. Therefore, how to further optimize the electrical performance of semiconductor devices has become a problem that needs to be solved urgently.

[0053] Based on this, the present disclosure aims to provide a semiconductor structure and a method for manufacturing the same, the details of which will be described in subsequent embodiments.

[0054] According to some embodiments, the present disclosure provides a semiconductor structure.

[0055] As an example, the semiconductor structure described above can be used to form a semiconductor device (e.g., a DRAM). The DRAM may include a transistor structure and an equivalent capacitor connected to the transistor structure. The equivalent capacitor is used to store data, and the transistor structure is used to read data from the equivalent capacitor or write data to the equivalent capacitor. It is understood that the semiconductor structure provided in the embodiment of the present application can be used as a component of the transistor structure and the equivalent capacitor in the DRAM, for example, it can be a 2TOC structure, but is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0056] Please refer to Figure 3 The semiconductor structure includes a substrate 10 and a first device structure 1A. The first device structure 1A includes a first active layer 21 , a first isolation protection layer 31 , a second active layer 22 , a first gate trench 41 , a first gate structure 51 and a first semiconductor layer 61 .

[0057] Among them, the first active layer 21 is located on the upper surface of the substrate 10; the first isolation protection layer 31 is located on the upper surface of the substrate 10 and covers the first active layer 21; the second active layer 22 is located on the upper surface of the first isolation protection layer 31; the first gate trench 41 passes through the second active layer 22 and the first isolation protection layer 31, and extends into the first active layer 21; the first gate structure 51 is located in the first gate trench 41; the first semiconductor layer 61 is located on the sidewalls and bottom of the first gate trench 41, and surrounds the first gate structure 51; the material of the first semiconductor layer 61 is the same as the material of the first active layer 21 and the material of the second active layer 22.

[0058] In the semiconductor structure of the above embodiment, due to the contact resistance between device structures made of different materials, the resistivity is relatively high. In the first device structure 1A of this embodiment, by providing a first semiconductor layer 61, a first active layer 21, and a second active layer 22 made of the same material, the above three are made into a structure using homogeneous materials, avoiding the contact resistance between heterogeneous materials, thereby significantly reducing the resistivity and optimizing the on-state characteristics. In addition, the first isolation protection layer 31 is used to provide isolation protection for the first active layer 21 and the second active layer 22 to avoid external influences. It penetrates the second active layer 22 and the first isolation protection layer 31 and extends to the first gate trench 41 in the first active layer 21, as well as the first gate structure 51 located in the first gate trench 41, which is conducive to the vertical stacking of semiconductor structures to increase storage density. Thus, while achieving high-density storage, the on-state characteristics of the semiconductor device are improved.

[0059] Please continue to refer to Figure 3 In some embodiments, the first semiconductor layer 61 includes an intrinsic indium gallium zinc oxide layer; the first active layer 21 and the second active layer 22 both include doped indium gallium zinc oxide layers.

[0060] For example, the doped indium gallium zinc oxide layer is a native indium gallium zinc oxide material that has been plasma-treated; for example, the native indium gallium zinc oxide material is plasma-treated with NF3 to form the doped indium gallium zinc oxide layer. Compared to native indium gallium zinc oxide, the fluorine atoms in the doped indium gallium zinc oxide have similar ionic radii to oxygen atoms. Fluorine atoms can replace oxygen atoms to generate free electrons, thereby disposing of or occupying oxygen vacancies, resulting in good on-state characteristics.

[0061] In some embodiments, the first isolation protection layer 31 includes a stacked first dielectric layer 311, a second dielectric layer 312, and a third dielectric layer 313. The first dielectric layer 311 covers the upper surface and sidewalls of the first active layer 21, as well as the surface of the substrate 10. The third dielectric layer 313 covers the surface of the second active layer 22 adjacent to the substrate 10. The first dielectric layer 311 is used to provide isolation protection for the first active layer 21, and the third dielectric layer 313 is used to provide isolation protection for the second active layer 22, thereby isolating the first active layer 21 and the second active layer 22 from the influence of external oxygen or water vapor.

[0062] For example, the first dielectric layer 311 includes a silicon nitride layer, the second dielectric layer 312 includes a silicon oxide layer, and the third dielectric layer 313 includes a silicon nitride layer. The silicon nitride layer can better isolate the indium gallium zinc oxide layer from external oxygen, water vapor, or other impurities.

[0063] In some embodiments, the first gate structure 51 includes a first gate 511 and a first gate dielectric layer 512 ; the first gate 511 is located in the first gate trench 41 ; and the first gate dielectric layer 512 is located between the first gate 511 and the first semiconductor layer 61 .

[0064] In some embodiments, the first semiconductor layer 61 surrounds the first gate structure 51. The first semiconductor layer 61 can serve as a channel to form a channel-all-around (CAA) structure, which helps save structural size and increase the distribution density of the first device structure 1A, thereby increasing the storage density of the device.

[0065] In some embodiments, the first device structure 1A further includes a first extraction electrode 71 and a second extraction electrode 72. The first extraction electrode 71 contacts the second active layer 22, and the second extraction electrode 72 contacts the first gate 511. The first extraction electrode 71 facilitates connection with peripheral circuits.

[0066] For example, the first extraction electrode 71 penetrates the second active layer 22 until it contacts the first isolation protection layer 31 , thereby increasing the contact area between the first extraction electrode 71 and the second active layer 22 to reduce contact resistance.

[0067] For example, the second extraction electrode 72 at least covers the upper surface of the first gate 511 to facilitate vertical stacking of the semiconductor structure and increase storage density.

[0068] Please refer to Figure 4 It can be understood that the on-state characteristic is an indicator to measure the electrical performance of a semiconductor device. It represents the relationship between the on-state current and on-state voltage of a semiconductor device in a fully on state at a specified junction temperature. Figure 4The middle left figure shows the relationship between the on-state drain current and on-state drain voltage of a semiconductor device in related technology. Figure 4 The middle right figure shows the relationship between the on-state drain current and the on-state drain voltage for the first device structure 1A in the disclosed embodiment. Because the disclosed embodiment utilizes a homogeneous material structure, contact resistance between heterogeneous materials is avoided, significantly reducing resistivity. Consequently, the semiconductor structure in the disclosed embodiment exhibits improved on-state characteristics.

[0069] Please refer to Figure 5 As can be understood, field-effect mobility characterizes the mobility of holes or electrons in a semiconductor under different electric fields, which determines the switching speed of a semiconductor device. It represents the average drift rate of charge carriers under a unit electric field. Compared to related technologies, the semiconductor structure provided by the embodiments of the present disclosure can improve field-effect mobility, reduce power consumption, and increase the current carrying capacity and switching speed of the device.

[0070] Please refer to Figure 6 In some embodiments, the semiconductor structure further includes a second device structure 1B.

[0071] Illustratively, the second device structure 1B includes a third active layer 23 , a second isolation protection layer 32 , a fourth active layer 24 , a second gate trench 42 , a second gate structure 52 , and a second semiconductor layer 62 .

[0072] Among them, the third active layer 23 is located on the first device structure 1A; the second isolation protection layer 32 is located on the first device structure 1A and covers the third active layer 23; the fourth active layer 24 is located on the upper surface of the second isolation protection layer 32; the second gate trench 42 passes through the fourth active layer 24 and the second isolation protection layer 32, and extends into the third active layer 23; the second gate structure 52 is located in the second gate trench 42; the second semiconductor layer 62 is located on the sidewalls and bottom of the second gate trench 42, and surrounds the second gate structure 52; the material of the second semiconductor layer 62 is the same as the material of the third active layer 23 and the material of the fourth active layer 24.

[0073] In this embodiment, since the second device structure 1B is similar to the first device structure 1A in structure, the second device structure 1B also has the technical advantages of the first device structure 1A, which will not be described in detail here.

[0074] In some embodiments, the materials of the first semiconductor layer 61 , the second semiconductor layer 62 , the first active layer 21 , the second active layer 22 , the third active layer 23 and the fourth active layer 24 are all the same.

[0075] In some embodiments, the second isolation protection layer 32 includes a stacked fourth dielectric layer 321, a fifth dielectric layer 322, a sixth dielectric layer 323, and a seventh dielectric layer 324. The fourth dielectric layer 321 completely fills the gap between the first device structure 1A and the third active layer 23, and the top surface of the fourth dielectric layer 321 is flush with the top surface of the third active layer 23. The fifth dielectric layer 322 covers the upper surface of the fourth dielectric layer 321 and the upper surface of the third active layer 23. The seventh dielectric layer 324 covers the surface of the fourth active layer 24 near the substrate 10. The fifth dielectric layer 322 is used to provide isolation protection for the third active layer 23, and the seventh dielectric layer 324 is used to provide isolation protection for the fourth active layer 24, thereby protecting the first active layer 21 and the second active layer 22 from external oxygen or water vapor.

[0076] For example, the fourth dielectric layer 321 includes a silicon oxide layer; the fifth dielectric layer 322 includes a silicon nitride layer; the sixth dielectric layer 323 includes a silicon oxide layer; and the seventh dielectric layer 324 includes a silicon nitride layer. The silicon nitride layer can better isolate the indium gallium zinc oxide layer from external oxygen, water vapor, or other impurities.

[0077] In some embodiments, the second gate structure 52 includes a second gate 521 and a second gate dielectric layer 522 ; the second gate 521 is located in the second gate trench 42 ; and the second gate dielectric layer 522 is located between the second gate 521 and the second semiconductor layer 62 .

[0078] In some embodiments, the second device structure 1B further includes a third extraction electrode 73, which contacts the fourth active layer 24. The third extraction electrode 73 facilitates connection with peripheral circuits.

[0079] For example, the third extraction electrode 73 penetrates the fourth active layer 24 until it contacts the second isolation protection layer 32 , thereby increasing the contact area between the third extraction electrode 73 and the fourth active layer 24 to reduce contact resistance.

[0080] In some embodiments, there are multiple second device structures 1B, and the multiple second device structures 1B are stacked sequentially from bottom to top.

[0081] In an embodiment where there are multiple second device structures 1B, the second device structure 1B further includes a fourth extraction electrode 74 , which is in contact with the second gate 521 .

[0082] For example, the fourth extraction electrode 74 covers at least the upper surface of the second gate 521 , so as to facilitate vertical stacking of multiple second device structures 1B to increase storage density.

[0083] In an embodiment in which there are multiple second device structures 1B, the semiconductor structure further includes a passivation layer 33. The passivation layer 33 covers the upper surface of the fourth active layer 24 and the second gate 521 in the second device structure 1B, and the third extraction electrode 73 also penetrates the passivation layer 33. The passivation layer 33 is used to electrically protect the device structure thereunder.

[0084] Based on the same inventive concept, some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which is used to prepare the semiconductor structures described in some of the above embodiments. The semiconductor preparation method provided in the embodiments of the present disclosure is used to prepare the semiconductor structures described in some of the above embodiments. This preparation method also possesses the technical advantages of the above-described semiconductor structures and will not be described in detail here.

[0085] Please refer to Figure 7 In some embodiments, the method for preparing a semiconductor structure may include the following steps:

[0086] Step S10: providing a substrate;

[0087] Step S20: forming a first device structure on the upper surface of the substrate;

[0088] In step S20, forming a first device structure on the upper surface of the substrate includes:

[0089] Step S21: forming a first active layer on the upper surface of the substrate;

[0090] Step S22: forming a first isolation protection layer on the upper surface of the substrate, wherein the first isolation protection layer covers the first active layer;

[0091] Step S23: forming a second active layer on the upper surface of the first isolation protection layer;

[0092] Step S24: forming a first gate trench, wherein the first gate trench penetrates the second active layer and the first isolation protection layer and extends into the first active layer;

[0093] Step S25: forming a first gate structure and a first semiconductor layer in the first gate trench; the first semiconductor layer is located on the sidewall and bottom of the first gate trench and surrounds the first gate structure; the material of the first semiconductor layer is the same as that of the first active layer and the second active layer.

[0094] In some embodiments, the first gate structure includes a first gate and a first gate dielectric layer; the first gate is located in the first gate trench; the first gate dielectric layer is located between the first gate and the first semiconductor layer;

[0095] After forming the first gate structure and the first semiconductor layer in the first gate trench, that is, after step S25, the method further includes:

[0096] Step S26: forming a first extraction electrode and a second extraction electrode; the first extraction electrode contacts the second active layer; the second extraction electrode contacts the first gate.

[0097] In some embodiments, after forming the first device structure on the upper surface of the substrate, that is, after step S20, the method further includes:

[0098] Step S30: forming a second device structure on the first device structure;

[0099] Step S30, forming a second device structure on the first device structure, includes:

[0100] Step S31: forming a third active layer and a second isolation protection layer on the first device structure, wherein the second isolation protection layer covers the third active layer;

[0101] Step S32: forming a fourth active layer on the upper surface of the second isolation protection layer;

[0102] Step S33: forming a second gate trench, wherein the second gate trench penetrates the fourth active layer and the second isolation protection layer and extends into the third active layer;

[0103] Step S34: forming a second gate structure and a second semiconductor layer in the second gate trench; the second semiconductor layer is located on the sidewalls and bottom of the second gate trench and surrounds the second gate structure; the material of the second semiconductor layer is the same as that of the third active layer and the fourth active layer.

[0104] In some embodiments, the second gate structure includes a second gate and a second gate dielectric layer: the second gate is located in the second gate trench; the second gate dielectric layer is located between the second gate and the second semiconductor layer;

[0105] After forming the second gate structure and the second semiconductor layer in the second gate trench, that is, after step S34, the method further includes:

[0106] Step S35: forming a third extraction electrode, wherein the third extraction electrode contacts the fourth active layer.

[0107] In some embodiments, after forming a second device structure on the first device structure, the method further includes repeating the step of forming the second device structure at least once to form a plurality of second device structures stacked sequentially from bottom to top.

[0108] It should be understood that although Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0109] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, the following Figures 8 to 24 Understand some embodiments of the present application.

[0110] Note that embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, and that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the regions of the device, and do not limit the scope of the invention.

[0111] Please refer to Figure 8 In step S10, the embodiment of the present application does not specifically limit the constituent material of the substrate 10. As an example, the substrate 10 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on insulator.

[0112] Please continue to refer to Figure 8 In step S21 , a first active layer 21 is formed on the upper surface of the substrate 10 .

[0113] Please refer to Figure 9In some embodiments of step S22, the first isolation protection layer 31 includes a stacked first dielectric layer 311, a second dielectric layer 312, and a third dielectric layer 313. The first dielectric layer 311 is used to provide isolation protection for the first active layer 21, and the third dielectric layer 313 is used to provide isolation protection for the second active layer 22, so as to isolate the first active layer 21 and the second active layer 22 from the influence of external oxygen or water vapor.

[0114] For example, step S22 is to form a first isolation protection layer 31 on the upper surface of the substrate 10, wherein the first isolation protection layer 31 covers the first active layer 21, including:

[0115] Step S221 : forming a first dielectric layer 311 , wherein the first dielectric layer 311 covers the upper surface and sidewalls of the first active layer 21 , and covers the surface of the substrate 10 ;

[0116] Step S222 : forming a second dielectric layer 312 on the upper surface of the first dielectric layer 311 ;

[0117] Step S223 : forming a third dielectric layer 313 , where the third dielectric layer 313 covers the surface of the second active layer 22 close to the substrate 10 .

[0118] Please refer to Figure 10 In step S23 , a second active layer 22 is formed on the upper surface of the first isolation protection layer 31 .

[0119] Please refer to Figure 11 In step S24, a first gate trench 41 is formed. The first gate trench 41 penetrates the second active layer 22 and the first isolation protection layer 31 and extends into the first active layer 21, including:

[0120] Step S241: forming a patterned mask layer (not shown) on the upper surface of the second active layer 22;

[0121] Step S242 : etching the second active layer 22 , the first isolation protection layer 31 and the first active layer 21 in sequence based on the patterned mask layer to form a first gate trench 41 penetrating the second active layer 22 and the first isolation protection layer 31 and extending into the first active layer 21 .

[0122] Please refer to Figures 12 to 15 Step S25, forming a first gate structure 51 and a first semiconductor layer 61 in the first gate trench 41, including:

[0123] Step S251: Figure 12 As shown, a first semiconductor material layer 61 ′ is formed to conformally cover the surface of the first gate trench 41 ;

[0124] Step S252: Figure 13As shown, a first gate dielectric material layer 512' is formed to cover the outer surface of the first semiconductor material layer 61';

[0125] Step S253: Figure 14 As shown, a first gate material layer 511 ′ is formed to fill the first gate trench 41 and cover the outer surface of the first gate dielectric material layer 512 ′;

[0126] Step S254: Figures 14 and 15 As shown, the first semiconductor material layer 61', the first gate dielectric material layer 512' and the first gate material layer 511' are etched back until the surface of the second active layer 22 is exposed; the remaining first semiconductor material layer 61' constitutes the first semiconductor layer 61 located on the sidewalls and bottom of the first gate trench 41, the remaining first gate dielectric material layer 512' constitutes the first gate dielectric layer 512, and the remaining first gate material layer 511' constitutes the first gate 511.

[0127] For example, step S254 can be back-etched using anisotropic etching. Anisotropic etching can selectively etch the material in a preset crystal direction or crystal plane direction, leaving only few or almost no etching marks in other directions. Using anisotropic etching for back-etching in this step can make the morphology of the resulting structure more precise and controllable.

[0128] Please refer to Figure 15 In some embodiments, the first gate structure 51 includes a first gate 511 and a first gate dielectric layer 512 ; the first gate 511 is located in the first gate trench 41 ; and the first gate dielectric layer 512 is located between the first gate 511 and the first semiconductor layer 61 .

[0129] For example, the material of the first gate 511 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide or a combination thereof; the material of the first gate dielectric layer 512 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof.

[0130] In some embodiments, the first semiconductor layer 61 surrounds the first gate structure 51. The first semiconductor layer 61 can serve as a channel to form a channel-all-around (CAA) structure, which helps save structural size and increase the distribution density of the first device structure 1A, thereby increasing the storage density of the device.

[0131] In some embodiments, the material of the first semiconductor layer 61 is the same as the material of the first active layer 21 and the material of the second active layer 22 .

[0132] For example, the first semiconductor layer 61 includes an intrinsic indium gallium zinc oxide layer; and the first active layer 21 and the second active layer 22 both include doped indium gallium zinc oxide layers.

[0133] Please refer to Figures 16 to 18 Step S26, forming the first extraction electrode 71 and the second extraction electrode 72, including:

[0134] Step S261: Figure 16 As shown, an electrode contact hole 71 ′ is formed in the second active layer 22 ;

[0135] Step S262: Figure 17 As shown, a conductive material layer 70 is formed to fill the electrode contact hole 71' and cover the second active layer 22;

[0136] For example, the electrode contact hole 71 ′ exposes the surface of the second active layer 22 ;

[0137] Step S263: Figures 17 and 18 As shown, part of the conductive material layer 70 is removed to form a first extraction electrode 71 and a second extraction electrode 72 . The first extraction electrode 71 contacts the second active layer 22 ; the second extraction electrode 72 contacts the first gate 511 .

[0138] For example, the first extraction electrode 71 and the second extraction electrode 72 are made of metal materials, such as copper and tungsten.

[0139] Please refer to Figures 19 to 21 In some embodiments, the second isolation protection layer 32 covers the three active layers, and the second isolation protection layer 32 includes a stacked fourth dielectric layer 321 , a fifth dielectric layer 322 , a sixth dielectric layer 323 and a seventh dielectric layer 324 .

[0140] For example, step S31, forming a third active layer 23 and a second isolation protection layer 32 on the first device structure 1A, includes:

[0141] Step S311: Figure 19 As shown, a third active layer 23 is formed on the upper surface of the first extraction electrode 71; and a fourth dielectric layer 321 is formed in the gap between the third active layer 23 and the first extraction electrode 71 and the second extraction electrode 72;

[0142] Step S312: Figure 20 As shown, a fifth dielectric layer 322 is formed on the upper surface of the fourth dielectric layer 321;

[0143] Step S313: Figure 21 As shown, a sixth dielectric layer 323 and a seventh dielectric layer 324 are sequentially formed on the upper surface of the fifth dielectric layer 322 .

[0144] Please refer to Figure 21 In step S32 , a fourth active layer 24 is formed on the upper surface of the second isolation protection layer 32 .

[0145] Please refer to Figure 22 In step S33 , a second gate trench 42 is formed. The second gate trench 42 penetrates the fourth active layer 24 and the second isolation protection layer 32 and extends into the third active layer 23 .

[0146] Please refer to Figures 23 to 24 Step S34, forming a second gate structure 52 and a second semiconductor layer 62 in the second gate trench 42, including:

[0147] Step S341: Figure 23 As shown, a second semiconductor material layer 62 ′, a second gate dielectric material layer 522 ′ and a second gate material layer 521 ′ are sequentially formed on the surface of the second gate trench 42 ;

[0148] Step S342: Figures 23 to 24 As shown, the second semiconductor material layer 62', the second gate dielectric material layer 522' and the second gate material layer 521' are etched back until the surface of the fourth active layer 24 is exposed; the remaining second semiconductor material layer 62' constitutes the second semiconductor layer 62 located on the sidewalls and bottom of the second gate trench 42, the remaining second gate dielectric material layer 522' constitutes the second gate dielectric layer 522, and the remaining second gate material layer 521' constitutes the second gate 521.

[0149] Please refer to Figure 24 In some embodiments, the second gate structure 52 includes a second gate 521 and a second gate dielectric layer 522 ; the second gate 521 is located in the second gate trench 42 ; and the second gate dielectric layer 522 is located between the second gate 521 and the second semiconductor layer 62 .

[0150] For example, the material of the second gate 521 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide or a combination thereof; the material of the second gate dielectric layer 522 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof.

[0151] In some embodiments, the second semiconductor layer 62 surrounds the second gate structure 52. The second semiconductor layer 62 can serve as a channel to form a channel-all-around (CAA) structure, which helps save structural size and increase the distribution density of the first device structure 1A, thereby increasing the storage density of the device.

[0152] In some embodiments, the material of the second semiconductor layer 62 is the same as the material of the third active layer 23 and the material of the fourth active layer 24 .

[0153] Please refer to Figure 24 In step S35 , a third extraction electrode 73 is formed, and the third extraction electrode 73 contacts the fourth active layer 24 .

[0154] Please refer to Figure 25 In some embodiments, after forming a second device structure 1B on the first device structure 1A, the method further includes:

[0155] Step S40 : repeating the step of forming the second device structure 1B at least once to form a plurality of second device structures 1B stacked sequentially from bottom to top.

[0156] In an embodiment in which a plurality of second device structures 1B are stacked sequentially from bottom to top, the second device structure 1B further includes a fourth extraction electrode 74 , which is in contact with the second gate 521 .

[0157] In some embodiments, the process of repeating the steps of forming the second device structure 1B at least once, when forming the last second device structure 1B, further includes:

[0158] A passivation layer 33 is formed to cover the fourth active layer 24 and the upper surface of the second gate 521 in the second device structure 1B, and the third extraction electrode 73 also penetrates the passivation layer 33. The passivation layer 33 is used to electrically protect the device structure thereunder.

[0159] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate and a first device structure; wherein the first device structure comprises: a first active layer, located on the upper surface of the substrate; a first isolation protection layer, located on the upper surface of the substrate and covering the first active layer; a second active layer, located on an upper surface of the first isolation protection layer; a first gate trench, penetrating the second active layer and the first isolation protection layer, and extending into the first active layer; a first gate structure, located in the first gate trench; a first semiconductor layer located on the sidewalls and bottom of the first gate trench and surrounding the first gate structure; the first semiconductor layer includes an intrinsic indium gallium zinc oxide layer; the first active layer and the second active layer both include a doped indium gallium zinc oxide layer; The semiconductor structure further includes a second device structure, and the second device structure includes: a third active layer, located on the first device structure; a second isolation protection layer, located on the first device structure and covering the third active layer; a fourth active layer, located on an upper surface of the second isolation protection layer; a second gate trench, penetrating the fourth active layer and the second isolation protection layer, and extending into the third active layer; a second gate structure located in the second gate trench; a second semiconductor layer, located on the sidewalls and bottom of the second gate trench and surrounding the second gate structure; the material of the second semiconductor layer is the same as that of the third active layer and the fourth active layer; There are multiple second device structures, and the multiple second device structures are stacked in sequence from bottom to top; The third active layer in the second device structure located on and adjacent to the first device structure is electrically connected to the first gate structure in the first device structure; For two stacked and adjacent second device structures, the third active layer in the upper second device structure is electrically connected to the second gate structure in the lower second device structure.

2. The semiconductor structure according to claim 1, wherein: The first gate structure includes: a first gate located in the first gate trench; a first gate dielectric layer located between the first gate and the first semiconductor layer; The first device structure further includes: a first extraction electrode in contact with the second active layer; and a second extraction electrode in contact with the first gate.

3. The semiconductor structure according to claim 1, wherein: The material of the first semiconductor layer, the material of the second semiconductor layer, the material of the first active layer, the material of the second active layer, the material of the third active layer, and the material of the fourth active layer are all the same.

4. The semiconductor structure according to claim 1, wherein: The second gate structure includes: a second gate located in the second gate trench; a second gate dielectric layer located between the second gate and the second semiconductor layer; The second device structure further includes a third extraction electrode in contact with the fourth active layer.

5. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first device structure on the upper surface of the substrate, comprising: forming a first active layer on the upper surface of the substrate; forming a first isolation protection layer on the upper surface of the substrate, wherein the first isolation protection layer covers the first active layer; forming a second active layer on an upper surface of the first isolation protection layer; forming a first gate trench, wherein the first gate trench penetrates the second active layer and the first isolation protection layer and extends into the first active layer; A first gate structure and a first semiconductor layer are formed in the first gate trench; the first semiconductor layer is located on the sidewalls and bottom of the first gate trench and surrounds the first gate structure; the first semiconductor layer includes an intrinsic indium gallium zinc oxide layer; the first active layer and the second active layer both include a doped indium gallium zinc oxide layer; After forming a first device structure on the upper surface of the substrate, the method further includes: forming a second device structure on the first device structure, including: forming a third active layer and a second isolation protection layer on the first device structure, wherein the second isolation protection layer covers the third active layer; forming a fourth active layer on an upper surface of the second isolation protection layer; forming a second gate trench, wherein the second gate trench penetrates the fourth active layer and the second isolation protection layer and extends into the third active layer; forming a second gate structure and a second semiconductor layer in the second gate trench; the second semiconductor layer is located on the sidewalls and bottom of the second gate trench and surrounds the second gate structure; the material of the second semiconductor layer is the same as that of the third active layer and the fourth active layer; After forming the second device structure on the first device structure, the method further includes: repeating the step of forming the second device structure at least once to form a plurality of second device structures stacked sequentially from bottom to top; The third active layer in the second device structure located on and adjacent to the first device structure is electrically connected to the first gate structure in the first device structure; For two stacked and adjacent second device structures, the third active layer in the upper second device structure is electrically connected to the second gate structure in the lower second device structure.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The first gate structure includes: a first gate located in the first gate trench; a first gate dielectric layer located between the first gate and the first semiconductor layer; after forming the first gate structure and the first semiconductor layer in the first gate trench, further comprising: A first extraction electrode and a second extraction electrode are formed; the first extraction electrode contacts the second active layer; and the second extraction electrode contacts the first gate.

7. The method for preparing a semiconductor structure according to claim 5, wherein: The second gate structure includes: a second gate located in the second gate trench; a second gate dielectric layer located between the second gate and the second semiconductor layer; after forming the second gate structure and the second semiconductor layer in the second gate trench, further comprising: A third extraction electrode is formed, wherein the third extraction electrode contacts the fourth active layer.

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