DC / DC converter

Abstract

The drive circuit (13) controls the operation of the switching elements (Q1, Q2) with a constant on-time. The monitoring circuit generates a first control signal indicating whether the DC / DC converter (1) is in a steady state or an abnormal state. The turn-on timer circuit (14) generates, on the basis of the first control signal, a second control signal that terminates a partial section within each switching cycle of the switching elements (Q1, Q2), said partial section being a section in which energy is stored in the inductor (L1), and transmits the second control signal to the drive circuit (13). When the DC / DC converter (1) is in a steady state, the on-timer circuit (14) generates a second control signal using a first reference voltage (Vref21) that varies in accordance with the duty ratio of the switching elements (Q1, Q2). The turn-on timer circuit (14) generates a second control signal using a fixed second reference voltage (Vref22) when the DC / DC converter (1) is in an abnormal state.

Description

Technical Field

[0001] The present disclosure relates to a DC / DC converter and a control circuit thereof. Background Art

[0002] In recent years, as portable devices have become more functional and smaller, high-efficiency and small-sized, high-frequency hysteresis-controlled switching power supplies are often used as power supply circuits. For example, Patent Document 1 discloses a method of controlling a DC / DC converter to suppress fluctuations in the output voltage by operating so that the magnitude or frequency of the ripple component of the output voltage is constant.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-062942 Summary of the invention

[0006] Problems to be solved by the invention

[0007] As a type of hysteresis control of a DC / DC converter, "constant on-time control" is known. For example, according to the constant on-time control of a buck converter, in each switching cycle of the switching element, when the output voltage is lower than a threshold value, the high-side switching element is turned on for a predetermined length of time, and thereafter, the high-side switching element is turned off. In a buck converter, when the high-side switching element is turned on and the low-side switching element is turned off, energy is stored in the inductor, and when the high-side switching element is turned off and the low-side switching element is turned on, the energy stored in the inductor is released. In this specification, the time interval in which energy is stored in the inductor is referred to as the "on-time interval", and the time interval in which the energy stored in the inductor is released is referred to as the "rectification interval". In addition, if the conditions for ending the on-time interval are fixed, the switching frequency of the switching element may change when the input voltage, output voltage, or output current of the DC / DC converter changes. Therefore, in order to prevent the switching frequency from fluctuating, the condition for ending the conduction period may be changed.

[0008] However, for example, when the operation of the switching element deviates from its stable state (steady state), such as immediately after the DC / DC converter is started or when the ground fault protection circuit is activated, it is difficult to implement constant on-time control without a change in the switching frequency. Therefore, it is required to reduce the change in the switching frequency compared to the past even when the operation of the switching element deviates from its stable state, and preferably implement constant on-time control at a constant switching frequency.

[0009] The present disclosure aims to provide a control circuit that can control a DC / DC converter to implement constant on-time control so that the fluctuation of the switching frequency is reduced compared with the conventional control circuit even when the operation of the switching element deviates from the stable state. Furthermore, the present disclosure aims to provide a DC / DC converter having such a control circuit.

[0010] Means for solving problems

[0011] According to a control circuit of a DC / DC converter according to one embodiment of the present disclosure,

[0012] In a control circuit for controlling a DC / DC converter including an inductor and first and second switching elements for storing and releasing energy in the inductor,

[0013] The control circuit comprises:

[0014] A driving circuit that causes the first and second switching elements to operate through a constant on-time control;

[0015] a monitoring circuit that generates a first control signal indicating whether the DC / DC converter is in a stable state or in an abnormal state; and

[0016] The on-timer circuit generates a second control signal for terminating a portion of each switching cycle of the first and second switching elements based on the first control signal, and sends the second control signal to the drive circuit, wherein the portion of the portion is a portion for storing energy in the inductor.

[0017] The on-timer circuit generates the control signal using a first reference voltage that varies according to a duty ratio of the first and second switching elements when the DC / DC converter is in a stable state,

[0018] The on-timer circuit generates the control signal using a fixed second reference voltage when the DC / DC converter is in an abnormal state.

[0019] Effects of the Invention

[0020] According to one aspect of the present disclosure, even when the operation of the switching element deviates from its stable state, the DC / DC converter can be controlled to perform constant on-time control so that the fluctuation of the switching frequency is reduced compared with the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a block diagram showing the configuration of a DC / DC converter 1 according to the embodiment.

[0022] Figure 2 It is shown Figure 1A circuit diagram of the structure of the conduction timer circuit 14 is shown in FIG.

[0023] Figure 3 It is shown Figure 2 A timing diagram showing changes in various signals of the conduction timer circuit 14.

[0024] Figure 4 1 is a block diagram showing a configuration of a DC / DC converter 1A according to a first modified example of the embodiment.

[0025] Figure 5 1 is a block diagram showing a configuration of a DC / DC converter 1B according to a second modification of the embodiment.

[0026] Figure 6 It is a block diagram showing a configuration of a DC / DC converter 1C according to a third modified example of the embodiment.

[0027] Figure 7 It is a block diagram showing a configuration of a DC / DC converter 1D according to a fourth modified example of the embodiment.

[0028] Figure 8 It is a block diagram showing a configuration of a DC / DC converter 1E according to a fifth modification of the embodiment.

[0029] Fig. 9 It is a block diagram showing a configuration of a DC / DC converter 1F according to a sixth modification of the embodiment.

[0030] Fig.10 1 is a block diagram showing a partial configuration of an on-timer circuit 14A according to a seventh modification of the embodiment.

[0031] Fig.11 It is a block diagram showing a configuration of an on-timer circuit 14B according to an eighth modification of the embodiment.

[0032] Fig.12 14C is a block diagram showing a configuration of an on-timer circuit 14C according to a ninth modification of the embodiment.

[0033] Fig.13 It is a block diagram showing a configuration of a DC / DC converter 1G according to a tenth modification of the embodiment.

[0034] Fig.14 1 is a block diagram showing a configuration of a DC / DC converter 1H according to an eleventh modified example of the embodiment.

[0035] Fig.15 1 is a block diagram showing a configuration of a DC / DC converter 1I according to a comparative example.

[0036] Fig.16 It is shown Fig.15 A circuit diagram of the structure of the conduction timer circuit 14I.

[0037] Fig.17 It is shown Fig.15 14I is a timing chart showing changes in each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 25%.

[0038] Fig.18 It is shown Fig.15 14I is a timing chart showing changes in each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 50%.

[0039] Fig.19 It is shown Fig.15 14I is a timing chart showing changes in each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 75%.

[0040] Fig. 20 It is shown Fig.15 1A is a timing diagram showing changes in various signals of the on-timer circuit 14I immediately after the DC / DC converter 1I is started. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In each of the drawings, the same components are denoted by the same reference numerals.

[0042] [Structure of the embodiment]

[0043] Figure 1 1 is a block diagram showing the structure of the DC / DC converter 1 involved in the embodiment. The DC / DC converter 1 includes switching elements Q1, Q2, an inductor L1, a capacitor C1, and a control circuit 10. The switching elements Q1 and Q2 are connected in series between the input voltage source Vdd and the ground. The switching elements Q1 and Q2 are respectively arranged on the high side and the low side. The switching element Q1 is, for example, a P-channel field effect transistor, and the switching element Q2 is, for example, an N-channel field effect transistor. The inductor L1 is connected between the node between the switching elements Q1 and Q2 and the output terminal Nout of the DC / DC converter 1. The capacitor C1 is connected between the output terminal Nout of the DC / DC converter 1 and the ground. The control circuit 10 generates drive signals S1 and S2 for controlling the on / off of each switching element Q1 and Q2, and applies the drive signals S1 and S2 to the control electrodes (gates) of each switching element Q1 and Q2. Thus, the control circuit 10 controls the switching elements Q1 and Q2 so as to store and release energy in the inductor L1.

[0044] The DC / DC converter 1 receives an input voltage Vin from an input voltage source Vdd, generates an output voltage Vout at its output terminal Nout, and supplies the output voltage Vout to a load device 2. The DC / DC converter 1 is an example of a step-down converter that generates an output voltage Vout lower than the input voltage Vin.

[0045] The control circuit 10 includes resistors R11 and R12, a reference voltage source E11, a comparator 11, a latch circuit 12, a drive circuit 13, an on-timer circuit 14, and a soft start circuit 31. The control circuit 10 may be configured as an integrated circuit having terminals N0 to N4.

[0046] The resistors R11 and R12 are voltage-dividing resistors connected in series with each other. The resistors R11 and R12 divide the output voltage Vout applied via the terminal N0 at a predetermined voltage-dividing ratio, and input the divided voltage Vdiv to the inverting input terminal of the comparator 11 .

[0047] The reference voltage source E11 generates a variable reference voltage Vref11 based on a signal Sss (described later) output from the soft start circuit 31 and inputs the variable reference voltage Vref11 to the non-inverting input terminal of the comparator 11. When the signal Sss is at a low level, the reference voltage Vref11 is set to a first value corresponding to the desired voltage to be supplied from the DC / DC converter 1 to the load device 2. On the other hand, when the signal Sss is at a high level, the reference voltage Vref11 is set to gradually increase from a second value (e.g., 0V) lower than the first value to the first value. Thus, as described later, the DC / DC converter 1 is soft-started at startup.

[0048] The comparator 11 compares the voltage Vdiv with the reference voltage Vref11 , and inputs a signal Scmp indicating the comparison result to the S terminal of the latch circuit 12 .

[0049] The R terminal of the latch circuit 12 is input with a signal Sot (described later) output from the conduction timer circuit 14. The latch circuit 12 generates a signal having a high level or low level value represented by a predetermined truth table based on the signals Scmp and Sot input from the comparator 11 and the conduction timer circuit 14, respectively, and sends the signal to the drive circuit 13.

[0050] The drive circuit 13 generates drive signals S1 and S2, and applies the drive signals S1 and S2 to the control electrodes of the switch elements Q1 and Q2 respectively through the terminals N1 and N2. The drive circuit 13 operates the switch elements Q1 and Q2 by constant on-time control. In each switching cycle of the switch elements Q1 and Q2, when the voltage Vdiv is lower than the reference voltage Vref11, the drive circuit 13 turns on the switch element Q1 and turns off the switch element Q2 for a predetermined time length, thereby accumulating energy in the inductor L1 (on-time interval). After the on-time interval, the drive circuit 13 turns off the switch element Q1 and turns on the switch element Q2, thereby releasing the energy stored in the inductor L1 (rectification interval). In addition, the latch circuit 12 operates according to the signal Sot (described later) output from the on-timer circuit 14, so the drive circuit 13 operates the switch elements Q1 and Q2 according to the signal Sot to end the on-time interval.

[0051] The drive signals S1 and S2 are input to the on-timer circuit 14, and the signal S3 indicating the voltage of the node between the switching elements Q1 and Q2 is input via the terminal N3. In addition, a signal generated by a certain monitoring circuit is input to the on-timer circuit 14, and the signal indicates whether the DC / DC converter 1 is in a stable state or in an abnormal state. The stable state of the DC / DC converter 1 means that when the DC / DC converter 1 is operating, parameters such as the input voltage Vin, the output voltage Vout, and the output current Iout are within the expected range. The abnormal state of the DC / DC converter 1 means that when the DC / DC converter 1 is operating, at least one of the parameters such as the input voltage Vin, the output voltage Vout, and the output current Iout is outside the expected range. Figure 1 In the example of FIG. 1 , the soft start circuit 31 is a monitoring circuit, and the signal Sss generated by the soft start circuit 31 is input to the on-timer circuit 14 as a signal indicating whether the DC / DC converter 1 is in a stable state or in an abnormal state.

[0052] The soft start circuit 31 controls the reference voltage source E11 in a manner that the DC / DC converter 1 is soft started at startup based on the signal Sen input from the outside of the DC / DC converter 1 via the terminal N4. The soft start of the DC / DC converter 1 means that in order to prevent the inrush of the input current and the overshoot of the output voltage, after the DC / DC converter 1 is started, the output voltage Vout is slowly increased from 0V to the desired voltage of the load device 2. In this specification, the time period from when the output voltage Vout slowly increases from 0V to when the desired voltage of the load device 2 is reached after the DC / DC converter 1 is started is referred to as the "soft start period". The soft start circuit 31 generates a signal Sss indicating whether the DC / DC converter 1 is in the soft start period and sends it to the reference voltage source E11. For example, when the signal Sss is at a high level, the DC / DC converter 1 is in the soft start period, and when the signal Sss is at a low level, the DC / DC converter 1 is not in the soft start period. When the DC / DC converter 1 is in the soft start period, the DC / DC converter 1 is in an abnormal state because the output voltage Vout does not meet the expected voltage of the load device 2. On the other hand, it is considered that after the soft start period, the output voltage Vout reaches the expected voltage of the load device 2, and the DC / DC converter 1 is likely to be in a stable state. In other words, the signal Sss indicates whether the DC / DC converter 1 is in a stable state or in an abnormal state. In addition, as mentioned above, the soft start circuit 31 also sends the signal Sss to the conduction timer circuit 14.

[0053] The on-timer circuit 14 generates a signal Sot for terminating the on-interval of each switching cycle of the switching elements Q1 and Q2 based on the signals S1, S2, S3, and Sss, and transmits the signal Sot to the drive circuit 13 via the latch circuit 12. The on-timer circuit 14 generates the signal Sot using a reference voltage that differs according to the signal Sss as described below.

[0054] Figure 2 It is shown Figure 1 The circuit diagram of the structure of the conduction timer circuit 14. The conduction timer circuit 14 includes inverters 21, 24, 25, NOR circuits 22, 23, a comparator 26, capacitors C21, C22, a reference voltage source E21, switching elements Q21, Q22, resistors R21 to R23, and switches SW21 to SW25.

[0055] The drive signals S1 and S2 are input to the on-timer circuit 14, and the signal S3 indicating the voltage of the node between the switching elements Q1 and Q2 is input. In addition, the signal Sss output from the soft start circuit 31 is input to the on-timer circuit 14, and the signal Sss is processed into one of the signals Strog1 to StrgK.

[0056] The switching elements Q21 and Q22 are connected in series with each other between the input voltage source Vdd and the ground. The switching elements Q21 and Q22 are respectively arranged on the high side and the low side. The switching element Q21 is, for example, a P-channel field effect transistor, and the switching element Q22 is, for example, an N-channel field effect transistor. Drive signals S1 and S2 are applied to the control electrodes (gates) of the switching elements Q21 and Q22, respectively. The switching elements Q21 and Q22 are constructed in the same manner as the switching elements Q1 and Q2, and operate in the same manner as the switching elements Q1 and Q2. Therefore, the switching elements Q21 and Q22 generate a voltage at the node between the switching elements Q21 and Q22 that changes in the same manner as the voltage at the node between the switching elements Q1 and Q2.

[0057] Signal S3 is applied to a node between switching elements Q21 and Q22 via switch SW21. Inverter 21 and NOR circuit 22 turn off switch SW21 when one of switching elements Q21 and Q22 is turned on, and turn on switch SW21 when both switching elements Q21 and Q22 are turned off.

[0058] Resistors R21 and R22 are voltage-dividing resistors connected in series with each other. Resistors R21 and R22 divide the node between switching elements Q21 and Q22 at a predetermined voltage-dividing ratio, and capacitor C21 is charged by the voltage after the voltage division. When switching elements Q1 and Q2 operate at a predetermined switching frequency, switching elements Q21 and Q22 also operate at the same switching frequency, and capacitor C21 is charged by the voltage generated by switching elements Q21 and Q22. On the other hand, when both switching elements Q1 and Q2 are turned off (for example, when pulse frequency modulation is used), both switching elements Q21 and Q22 are also turned off, and capacitor C21 is charged by the voltage of signal S3. In either case, the voltage of capacitor C21 varies according to the duty cycle of switching elements Q1 and Q2. The voltage of capacitor C21 is used as a variable reference voltage Vref21. Reference voltage Vref21 is input to the inverting input terminal of comparator 26.

[0059] The switch SW24, the resistor R23, and the capacitor C22 are connected in series between the input voltage source Vdd and the ground. The switch SW24 is turned on / off according to the reverse signal of the signal S1 inverted by the inverter 25. The two ends of the capacitor C22 are short-circuited by the switch SW25 turned on / off according to the signal S1. The voltage Vrmp of the capacitor C22 gradually increases when the switch element Q1 is turned on, and becomes zero when the switch element Q1 is turned off. The voltage Vrmp is input to the non-inverting input terminal of the comparator 26.

[0060] When the DC / DC converter 1 is in an abnormal state, the NOR circuit 23, the inverter 24, the reference voltage source E21, and the switches SW22 and SW23 send a fixed reference voltage Vref22 to the comparator 26 instead of the variable reference voltage Vref21. The reference voltage source E21 generates a fixed reference voltage Vref22. The NOR circuit 23 obtains signals Storg1 to StrgK indicating whether the DC / DC converter 1 is in a stable state or in an abnormal state from one or more monitoring circuits as input. Figure 1 In the example, the soft start circuit 31 is a monitoring circuit, but as an alternative or in addition, the NOR circuit 23 may also be a reference circuit. Figures 4 to 9 The other monitoring circuits described above take signals Strog1 to StrgK as inputs. When all of the signals Strog1 to StrgK are at low levels (i.e., when no abnormal state occurs), the NOR circuit 23 and the inverter 24 control switches SW22 and SW23 to send the reference voltage Vref21 to the comparator 26. When at least one of the signals Strog1 to StrgK is at high levels (i.e., when some abnormal state occurs), the NOR circuit 23 and the inverter 24 control switches SW22 and SW23 to send the reference voltage Vref22 to the comparator 26.

[0061] The comparator 26 generates a signal Sot by comparing the voltage Vrmp with the reference voltage Vref21 or Vref22 and transmits the signal Sot to the latch circuit 12 .

[0062] As described above, the on-timer circuit 14 generates the second control signal Sot for ending the on-interval of each switching cycle of the switching elements Q1 and Q2 based on the first control signal Sss, and sends it to the drive circuit 13. When the DC / DC converter 1 is in a stable state, the on-timer circuit 14 generates the control signal Sot using the first reference voltage Vref21 that changes according to the duty ratio of the switching elements Q1 and Q2. When the DC / DC converter 1 is in an abnormal state, the on-timer circuit 14 generates the control signal Sot using the fixed second reference voltage Vref22.

[0063] According to the control circuit 10 of the DC / DC converter 1 according to the embodiment, Figure 2 The on-timer circuit 14 is provided, so that even when the operation of the switching elements Q1 and Q2 deviates from the stable state, the DC / DC converter 1 can be controlled to implement constant on-time control with a switching frequency variation reduced than before. The operation of the control circuit 10 of the DC / DC converter 1 according to the embodiment will be described in further detail below with reference to the DC / DC converter according to the comparative example.

[0064] [Comparative Example]

[0065] Next, refer to Figures 15 to 20 , the structure and operation of a DC / DC converter according to a comparative example which does not include the on-timer circuit 14 according to the embodiment will be described.

[0066] Fig.15 1 is a block diagram showing the structure of a DC / DC converter 1I according to a comparative example. Figure 1 The on-timer circuit 14 is replaced with an on-timer circuit 14I. The signal Sss generated by the soft start circuit 31 is not input to the on-timer circuit 14I.

[0067] Fig.16 It is shown Fig.15 The circuit diagram of the structure of the conduction timer circuit 14I is shown in FIG. The conduction timer circuit 14I has Figure 2 The on-timer circuit 14I is a structure in which the NOR circuit 23, the inverter 24, the reference voltage source E21, and the switches SW22 and SW23 are removed. The on-timer circuit 14I generates the signal Sot using only the variable reference voltage Vref21.

[0068] Fig.17 It is shown Fig.15 14I is a timing chart showing changes in each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 25%. Fig.18 It is shown Fig.15 14I is a timing chart showing changes in each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 50%. Fig.19 It is shown Fig.15 The timing diagram of the changes of each signal of the conduction timer circuit 14I when the duty ratio of the switching elements Q1 and Q2 is 75%. The signals S1, S2, and Sot transfer between a high level (H) and a low level (L). The voltage Vrmp gradually increases when the switching element Q1 is turned on, and becomes zero when the switching element Q1 is turned off. The reference voltage Vref21 changes according to the duty ratio of the switching elements Q1 and Q2. When the voltage Vrmp reaches the reference voltage Vref21, the signal Sot transfers from a low level to a high level. According to Figure 17 to Figure 19 When the DC / DC converter 1 is in a stable state, the voltage Vrmp can be compared with the variable reference voltage Vref21 to end the conduction period and operate the switching elements Q1 and Q2 at a constant switching frequency.

[0069] Fig. 20 It is shown Fig.151A is a timing diagram showing changes in various signals of the on-timer circuit 14I immediately after the DC / DC converter 1I is started. Fig. 20 The following situation is shown: immediately after the DC / DC converter 1I is started, the output voltage Vout is near 0V, the reference voltage Vref21 becomes significantly lower, and as a result, the cycle of the end conduction interval becomes very short. As described above, the reference voltage Vref21 changes according to the duty ratio of the switching elements Q1 and Q2. Therefore, for example, immediately after the DC / DC converter 1I is started, when the ground protection circuit is activated, etc., when the operation of the switching elements Q1 and Q2 deviates from their stable state, the switching elements Q1 and Q2 cannot be operated at the desired switching frequency.

[0070] [Operation of Implementation Method]

[0071] Figure 3 It is shown Figure 2 The control circuit 10 of the DC / DC converter 1 according to the embodiment includes: Figure 2 The on-timer circuit 14 is used to selectively use the variable reference voltage Vref21 and the fixed reference voltage Vref22. When the DC / DC converter 1 is in the soft start period, that is, when the signal Sss is at a high level, the fixed reference voltage Vref22 is used, and when the signal Sss is at a low level, the variable reference voltage Vref21 is used. When the voltage Vrmp reaches the reference voltage Vref21 or Vref22, the signal Sot is transferred from the low level to the high level. In this way, by selectively using the variable reference voltage Vref21 and the fixed reference voltage Vref22, the switching elements Q1 and Q2 operate at the desired switching frequency. According to the control circuit 10 of the DC / DC converter 1 involved in the embodiment, even if the operation of the switching elements Q1 and Q2 deviates from their stable state, the DC / DC converter 1 can be controlled to implement constant on-time control so that the change of the switching frequency is reduced compared with the past. According to the control circuit 10 of the DC / DC converter 1 according to the embodiment, even when the operation of the switching elements Q1 and Q2 deviates from the stable state, it is preferable to control the DC / DC converter 1 so as to perform constant on-time control at a constant switching frequency.

[0072] [Modification of the monitoring circuit]

[0073] As mentioned above, in Figure 1 In the example, the soft start circuit 31 is a monitoring circuit, but instead of or in addition to it, Figure 2 The NOR circuit 23 can also be referenced from Figures 4 to 9 The other monitoring circuits described take signals Strg1 to StrgK as input.

[0074] Figure 4 This is a block diagram showing the configuration of a DC / DC converter 1A according to a first modification of the embodiment. Figure 1 The control circuit 10 includes a control circuit 10A. The control circuit 10A includes Figure 1 In addition to the various components of the embodiment, a voltage drop detector 32 and a delay circuit 33 are also provided. Figures 4 to 9 , the soft start circuit 31 is omitted. The voltage drop detector 32 is an example of a monitoring circuit. The voltage drop detector 32 obtains the input voltage Vin of the DC / DC converter 1A via the terminal N5 and detects the magnitude of the input voltage Vin. The voltage drop detector 32 generates a signal Suvin indicating whether the input voltage Vin is in a stable state above the threshold or in an abnormal state below the threshold, and sends the signal Suvin to the conduction timer circuit 14 via the delay circuit 33. For example, when the input voltage Vin is above the threshold, the signal Suvin is set to a low level, and when the input voltage Vin is less than the threshold, the signal Suvin is set to a high level. The signal Suvin is processed as one of the signals Strog1 to StrgK input to the NOR circuit 23.

[0075] Figure 5 This is a block diagram showing the configuration of a DC / DC converter 1B according to a second modification of the embodiment. Figure 1 The control circuit 10 is provided with a control circuit 10B. The control circuit 10B includes Figure 1 In addition to the components of the NOR circuit 23, the NOR circuit 23 also includes a voltage drop detector 34. The voltage drop detector 34 is an example of a monitoring circuit. The voltage drop detector 34 generates a signal Suvout indicating whether the output voltage Vout is in a stable state above a threshold value or in an abnormal state below the threshold value, and sends it to the conduction timer circuit 14. For example, when the output voltage Vout is above the threshold value, the signal Suvout is set to a low level, and when the output voltage Vout is less than the threshold value, the signal Suvout is set to a high level. The signal Suvout is processed as one of the signals Strog1 to StrgK input to the NOR circuit 23.

[0076] Figure 6 1C is a block diagram showing a configuration of a DC / DC converter 1C according to a third modification of the embodiment. Figure 1 The control circuit 10 is provided with a control circuit 10C. The control circuit 10C includes Figure 1In addition to the various structural elements of the DC / DC converter 1C, the DC / DC converter 1C also includes a transient response detector 35. The transient response detector 35 is an example of a monitoring circuit. The transient response detector 35 detects whether the DC / DC converter 1 is in a transient response state based on the load device 2 based on the output voltage Vout. The transient response state means that the output voltage Vout varies greatly during a predetermined time period due to the transient response of the load device 2 connected to the output terminal Nout of the DC / DC converter 1C. The transient response detector 35 generates a signal Sus indicating whether the DC / DC converter 1 is in a transient response state, that is, in an abnormal state, or in a stable state that is not the case, and sends it to the conduction timer circuit 14. For example, when the DC / DC converter 1 is in a transient response state, the signal Sus is set to a high level, and when it is not the case, the signal Sus is set to a low level. The signal Sus is processed as one of the signals Strog1 to StrgK input to the NOR circuit 23.

[0077] Figure 7 This is a block diagram showing the structure of a DC / DC converter 1D according to a fourth modification of the embodiment. Figure 1 The control circuit 10 is provided with a control circuit 10D. The control circuit 10D includes Figure 1 In addition to the various structural elements of the present invention, a peak current detector 36 is also provided. The peak current detector 36 is an example of a monitoring circuit. The peak current detector 36 is connected to the input voltage source Vdd via the terminal N6 and is connected to the node between the switching elements Q1 and Q2 via the terminal N3. The peak current detector 36 obtains the output current Iout (or the current flowing through the inductor L1) of the DC / DC converter 1D by monitoring the voltage across the switching element Q1 when the switching element Q1 is turned on, and detects the magnitude of the peak value of the output current Iout. The peak current detector 36 generates a signal Spc indicating whether the peak value of the output current Iout is in a stable state above a threshold value or in an abnormal state below a threshold value, and sends it to the on-timer circuit 14. For example, when the peak value of the output current Iout is above a threshold value, the signal Spc is set to a low level, and when the peak value of the output current Iout is less than the threshold value, the signal Spc is set to a high level. The signal Spc is processed as one of the signals Storg1 to StrgK input to the NOR circuit 23.

[0078] Figure 8 This is a block diagram showing the configuration of a DC / DC converter 1E according to a fifth modification of the embodiment. Figure 1 The control circuit 10 includes a control circuit 10E. The control circuit 10E includes Figure 1In addition to the various structural elements of the DC / DC converter 1E, the DC / DC converter 1E also includes a zero current detector 37. The zero current detector 37 is an example of a monitoring circuit. The zero current detector 37 is connected to the node between the switching elements Q1 and Q2 via the terminal N3 and is grounded via the terminal N7. The zero current detector 37 obtains the output current Iout of the DC / DC converter 1E by monitoring the voltage across the switching element Q2 when the switching element Q2 is turned on, and detects the direction in which the output current Iout flows. The zero current detector 37 generates a signal Szc indicating whether the output current Iout is in a stable state where it flows from the switching element Q2 to the output terminal Nout, or in an abnormal state where it flows in the reverse direction, and sends it to the conduction timer circuit 14. For example, when the output current Iout flows from the switching element Q2 to the output terminal Nout, the signal Szc is set to a low level, and when the output current Iout flows in the reverse direction, the signal Szc is set to a high level. The signal Szc is processed as one of the signals Strog1 to StrgK input to the NOR circuit 23.

[0079] Fig. 9 This is a block diagram showing the structure of a DC / DC converter 1F according to a sixth modification of the embodiment. Figure 1 The control circuit 10 is provided with a control circuit 10F. The control circuit 10F includes Figure 1 In addition to the various structural elements of the DC / DC converter 1F, the reverse current detector 38 is also provided. The reverse current detector 38 is an example of a monitoring circuit. The reverse current detector 38 is connected to the node between the switching elements Q1 and Q2 via the terminal N3 and is grounded via the terminal N7. The reverse current detector 38 obtains the output current Iout of the DC / DC converter 1F by monitoring the voltage across the switching element Q2 when the switching element Q2 is turned on, and detects the direction and magnitude of the output current Iout. The reverse current detector 38 generates a signal Src indicating whether the output current Iout is in a stable state flowing from the switching element Q2 to the output terminal Nout or in an abnormal state flowing in the reverse direction and greater than a threshold, and sends it to the conduction timer circuit 14. For example, when the output current Iout flows from the switching element Q2 to the output terminal Nout, the signal Src is set to a low level, and when the output current Iout flows in the reverse direction and is greater than a threshold, the signal Src is set to a high level. The signal Src is processed as one of the signals Storg1 to StrgK input to the NOR circuit 23.

[0080] According to the control circuits 10A to 10F of the DC / DC converters 1A to 1F according to the modified examples, Figure 1Similarly, the control circuit 10 can selectively use the variable reference voltage Vref21 and the fixed reference voltage Vref22 to generate the control signal Sot that ends the conduction interval. Thus, even when the operation of the switching elements Q1 and Q2 deviates from their stable state, the DC / DC converters 1A to 1F can be controlled to implement constant conduction time control so that the change of the switching frequency is reduced compared to the past.

[0081] You can also combine references Figure 1 , Figures 4 to 9 The structure of the description. Figure 2 The NOR circuit 23 may also receive the signals Strg1 to StrgK from a plurality of monitoring circuits as inputs. Thus, a plurality of events each indicating whether the DC / DC converter is in a stable state or in an abnormal state can be detected.

[0082] [Variation of the On-Timer Circuit]

[0083] Fig.10 1 is a block diagram showing a part of the configuration of the on-timer circuit 14A according to the seventh modification of the embodiment. Figure 2 The inverter 24, the reference voltage source E21, and the switch SW23 are provided. Fig.10 The reference voltage sources E21-1 to E21-K and switches SW23-1 to SW23-K. The reference voltage sources E21-1 to E21-K generate a plurality of reference voltages Vref22-1 to Vref22-K that are different from each other. The on-timer circuit 14A can correspond to a plurality of events respectively, and use a plurality of reference voltages Vref22-1 to Vref22-K that are different from each other to generate the control signal Sot. Thus, when a plurality of events that respectively indicate whether the DC / DC converter is in a stable state or in an abnormal state are detected, an appropriate reference voltage can be used according to the event.

[0084] Fig.11 1 is a block diagram showing a configuration of a conduction timer circuit 14B according to an eighth modification of the embodiment. Figure 2 The switch S21 is provided with a delay circuit 27. The output signal of the NOR circuit 22 is input to the NOR circuit 22 via the delay circuit 27. Thus, when the switch elements Q1 and Q2 start the switching operation from the off state at the same time, the on-timer circuit 14B can generate the control signal Sot using the fixed reference voltage Vref22 during a certain period from the start of the switching operation.

[0085] Fig.12 1 is a block diagram showing a configuration of a conduction timer circuit 14C according to a ninth modification of the embodiment. The conduction timer circuit 14C has Figure 2 The on-timer circuit 14C has an inverter 21, a NOR circuit 22, switch elements Q21, Q22, and a switch SW21. Figure 2 The case of the conduction timer circuit 14 has a simpler circuit structure, which can reduce the size and cost.

[0086] [Modification of DC / DC Converter]

[0087] Figures 1 to 12 An example of a DC / DC converter as a step-down converter is shown. On the other hand, the control of the DC / DC converter according to the embodiment can also be applied to a step-up converter or a step-up / step-down converter.

[0088] Fig.13 10 is a block diagram showing the structure of a DC / DC converter 1G involved in the tenth variation of the embodiment. The DC / DC converter 1G includes switching elements Q11, Q12, an inductor L1, a capacitor C1, and a control circuit 10G. The inductor L1 and the switching element Q11 are connected in series between an input voltage source Vdd and ground. The switching element Q12 is connected between a node between the inductor L1 and the switching element Q11 and an output terminal Nout of the DC / DC converter 1G. The switching elements Q11 and Q12 are respectively arranged on the low side and the high side. The switching element Q11 is, for example, an N-channel field effect transistor, and the switching element Q12 is, for example, a P-channel field effect transistor. The capacitor C1 is connected between the output terminal Nout of the DC / DC converter 1G and ground. The control circuit 10G generates drive signals S11 and S12 for controlling the on / off of the switch elements Q11 and Q12, and applies the drive signals S11 and S12 to the control electrodes (gates) of the switch elements Q11 and Q12. Thus, the control circuit 10G controls the switch elements Q11 and Q12 to store and release energy to the inductor L1.

[0089] The DC / DC converter 1G is an example of a boost converter that generates an output voltage Vout higher than an input voltage Vin.

[0090] Control circuit 10G replacement Figure 1 The drive circuit 13 and the conduction timer circuit 14 are provided with a drive circuit 13G and a conduction timer circuit 14G.

[0091] The drive circuit 13G generates drive signals S11 and S12, and applies the drive signals S11 and S12 to the control electrodes of the switch elements Q11 and Q12 respectively through the terminals N11 and N12. The drive circuit 13G operates the switch elements Q11 and Q12 by constant on-time control. In each switching cycle of the switch elements Q11 and Q12, when the voltage Vdiv is lower than the reference voltage Vref11, the drive circuit 13G turns on the switch element Q11 and turns off the switch element Q12 for a predetermined time length, thereby accumulating energy in the inductor L1 (on-time interval). After the on-time interval, the drive circuit 13G turns off the switch element Q11 and turns on the switch element Q12, thereby releasing the energy stored in the inductor L1 (rectification interval). In addition, since the latch circuit 12 operates according to the signal Sot, the drive circuit 13G operates the switch elements Q11 and Q12 according to the signal Sot to end the on-time interval.

[0092] The on-timer circuit 14G receives the drive signals S11 and S12, and receives the signal S13 indicating the output voltage Vout via the terminal N13. The on-timer circuit 14G receives the signal Sss generated by the soft start circuit 31. The on-timer circuit 14G generates the signal Sot based on the signals S11, S12, S13, and Sss, and transmits the signal Sot to the drive circuit 13G via the latch circuit 12. Figure 1 Similarly, the on-timer circuit 14G selectively uses different reference voltages according to the signal Sss, that is, a variable reference voltage and a fixed reference voltage to generate the signal Sot. In the on-timer circuit 14G, the signals S11, S12, and S13 are substantially the same as Figure 2 The on-timer circuit 14G corresponds to the signals S1, S2, and S3 respectively. Figure 2 Similarly, the conduction timer circuit 14 may also include two switch elements that respectively operate according to the signals S11 and S12, or may be connected to the Fig.12 The on-timer circuit 14C similarly uses the signal S3.

[0093] according to Fig.13 The control circuit 10G, with Figure 1 Similarly, the control circuit 10 can selectively use a variable reference voltage and a fixed reference voltage to generate a control signal Sot that ends the conduction interval. Thus, even when the operation of the switching elements Q11 and Q12 deviates from their stable state, the DC / DC converter 1G can be controlled to implement constant conduction time control so that the change of the switching frequency is reduced compared to the past.

[0094] Fig.13In the example of FIG. 1 , the soft start circuit 31 is a monitoring circuit, but the DC / DC converter 1G as a step-up converter may also have a reference circuit. Figures 4 to 9 Other monitoring circuits described may be used instead or in addition.

[0095] Fig.14 1 is a block diagram showing a configuration of a DC / DC converter 1H according to an eleventh modification of the embodiment. The DC / DC converter 1H includes switching elements Q1 , Q2 , Q11 , and Q12 , an inductor L1 , a capacitor C1 , and a control circuit 10H. Fig.14 The switching elements Q1, Q2 and inductor L1 are Figure 1 The corresponding structural elements of operate similarly as part of a step-down converter. Fig.14 The switching elements Q11, Q12 and the inductor L1 are connected to Fig.13 The corresponding components of the control circuit 10H operate as part of a boost converter. Figure 1 The control circuit 10 and Fig.13 The DC / DC converter 1H is an example of a buck-boost converter that generates both an output voltage Vout lower than the input voltage Vin and an output voltage Vout higher than the input voltage Vin. Fig.14 The control circuit 10H, with Figure 1 The control circuit 10 and Fig.13 Similarly, even when the operation of the switching elements Q1, Q2, Q11, and Q12 deviates from the stable state, the DC / DC converter 1H can be controlled to perform constant on-time control so that the fluctuation of the switching frequency is reduced compared with the related art.

[0096] [Other Modifications]

[0097] exist Figure 1 In the examples such as , the switching elements Q1 and Q2 are provided outside the integrated circuit having the terminals N0 to N8 , etc., but the switching elements Q1 and Q2 may be integrated inside the control circuit 10 .

[0098] The resistor R21 may also be configured to have an adjustable resistance value. The reference voltage source E21 may also be configured to have an adjustable voltage value.

[0099] exist Figure 1 In the above, in order to generate the reference voltage Vref21 that changes according to the duty ratio of the switching elements Q1 and Q2, the signal S3 indicating the voltage of the node between the switching elements Q1 and Q2 is used, but the output voltage Vout may be used instead of the signal S3.

[0100] [Summary of implementation methods]

[0101] The control circuit 10 of the DC / DC converter 1 according to the first embodiment of the present disclosure controls the DC / DC converter 1 including an inductor L1 and first and second switching elements Q1 and Q2 for storing and releasing energy in the inductor L1. The control circuit 10 includes a drive circuit 13, a monitoring circuit, and an on-timer circuit 14. The drive circuit 13 controls the first and second switching elements Q1 and Q2 to operate by a constant on-time control. The monitoring circuit generates a first control signal indicating whether the DC / DC converter 1 is in a stable state or in an abnormal state. Based on the first control signal, the on-timer circuit 14 generates a second control signal that ends a portion of each switching cycle of the first and second switching elements Q1 and Q2, and transmits the second control signal to the drive circuit 13, the portion of which is a portion for storing energy in the inductor L1. When the DC / DC converter 1 is in a stable state, the on-timer circuit 14 generates a second control signal using a first reference voltage that changes according to the duty ratio of the first and second switching elements Q1 and Q2. When the DC / DC converter 1 is in an abnormal state, the on-timer circuit 14 generates a second control signal using a fixed second reference voltage.

[0102] According to the control circuit 10 of the DC / DC converter 1 according to the second aspect of the present disclosure, the control circuit according to the first aspect may be configured as follows: When the DC / DC converter 1 is in the soft start period, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0103] According to the control circuit 10 of the DC / DC converter 1 according to the third aspect of the present disclosure, the control circuit according to the first or second aspect may also be configured as follows: When the input voltage of the DC / DC converter 1 is lower than the first threshold, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0104] According to the control circuit 10 of the DC / DC converter 1 according to the fourth aspect of the present disclosure, the control circuit according to one of the first to third aspects may be configured as follows: When the output voltage of the DC / DC converter 1 is lower than the second threshold, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0105] According to the control circuit 10 of the DC / DC converter 1 according to the fifth aspect of the present disclosure, the control circuit according to one of the first to fourth aspects may be configured as follows: When the DC / DC converter 1 is in a transient response state due to a load, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0106] According to the control circuit 10 of the DC / DC converter 1 involved in the sixth aspect of the present disclosure, the control circuit involved in one of the first to fifth aspects may also be configured as follows: When the peak value of the output current of the DC / DC converter 1 is less than the third threshold value, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0107] According to the control circuit 10 of the DC / DC converter 1 according to the seventh aspect of the present disclosure, the control circuit according to one of the first to sixth aspects may be configured as follows: When the monitoring circuit detects a reverse current in the output current of the DC / DC converter 1, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0108] According to the control circuit 10 of the DC / DC converter 1 involved in the eighth aspect of the present disclosure, the control circuit involved in one of the first to seventh aspects may also be configured as follows: When the output current of the DC / DC converter 1 is a reverse current and is greater than a fourth threshold value, the monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0109] According to the control circuit 10 of the DC / DC converter 1 involved in the ninth aspect of the present disclosure, the control circuit involved in one of the first to eighth aspects can also be configured as follows. The monitoring circuit detects multiple events that respectively indicate that the DC / DC converter 1 is in an abnormal state. The on-timer circuit 14 corresponds to the multiple events respectively and generates a control signal using multiple second reference voltages that are different from each other.

[0110] According to the control circuit 10 of the DC / DC converter 1 according to the tenth aspect of the present disclosure, the control circuit according to one of the first to ninth aspects may be configured as follows: When the first and second switching elements Q1 and Q2 start switching operation simultaneously from the off state, the on-timer circuit 14 generates a control signal using a fixed second reference voltage during a certain period from the start of the switching operation.

[0111] A DC / DC converter 1 according to an eleventh aspect of the present disclosure includes first and second switching elements Q1 and Q2 provided on the high side and the low side, respectively, and a control circuit 10 according to one of the first to tenth aspects.

[0112] Description of the mark

[0113] 1. 1A~1IDC / DC converter; 2. Load device; 10. 10A~10I control circuit; 11. Comparator; 12. Latch circuit; 13. 13G drive circuit; 14. 14A~14C, 14G, 14I conduction timer circuit; 21. 24. 25 inverter; 22. 23 NOR circuit; 26 comparator; 27 delay circuit; 31 soft start circuit; 32 voltage drop detector; 33 delay circuit; 34 voltage drop detector; 3 5 transient response detector; 36 peak current detector; 37 zero current detector; 38 reverse current detector; C1, C21, C22 capacitors; E11, E21, E21-1~E21-K reference voltage sources; L1 inductor; Q1, Q2, Q11, Q12, Q21, Q22 switching elements; R11, R12, R21~R23 resistors; SW21~SW23, SW23-1~SW23-K, SW24, SW25 switches.

Claims

1. A control circuit for a DC / DC converter, In a control circuit for controlling a DC / DC converter including an inductor and first and second switching elements for storing and releasing energy in the inductor, The control circuit comprises: A driving circuit that causes the first and second switching elements to operate through a constant on-time control; a monitoring circuit that generates a first control signal indicating whether the DC / DC converter is in a stable state or in an abnormal state; and The on-timer circuit generates a second control signal for terminating a portion of each switching cycle of the first and second switching elements based on the first control signal, and sends the second control signal to the drive circuit, wherein the portion of the portion is a portion for storing energy in the inductor. The on-timer circuit generates the control signal using a first reference voltage that varies according to a duty ratio of the first and second switching elements when the DC / DC converter is in a stable state, The on-timer circuit generates the control signal using a fixed second reference voltage when the DC / DC converter is in an abnormal state.

2. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the DC / DC converter is in a soft start period.

3. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when an input voltage of the DC / DC converter is lower than a first threshold value.

4. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the output voltage of the DC / DC converter is lower than a second threshold.

5. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the DC / DC converter is in a transient response state due to a load.

6. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when a peak value of an output current of the DC / DC converter is smaller than a third threshold value.

7. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when a reverse current of an output current of the DC / DC converter is detected.

8. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the output current of the DC / DC converter is a reverse current and is greater than a fourth threshold.

9. The control circuit of the DC / DC converter according to claim 1, The monitoring circuit detects a plurality of events respectively indicating that the DC / DC converter is in an abnormal state, The on-timer circuit corresponds to the plurality of events, respectively, and generates the second control signal using a plurality of second reference voltages that are different from each other.

10. The control circuit of the DC / DC converter according to claim 1, When the first and second switching elements simultaneously start switching operations from an off state, the on-timer circuit generates the second control signal using a fixed second reference voltage during a certain period from the start of the switching operations.

11. A DC / DC converter comprising: Inductors; first and second switching elements for storing and releasing energy to the inductor; and The control circuit according to any one of claims 1 to 10.

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