Predicting load values for subsequent load operations

Abstract

The processing circuitry is to perform load operations, each load operation associated with an identification. Prediction circuitry to receive a given load value associated with a given identification and to make a prediction from the given load value indicating a predicted load value for a subsequent load operation to be performed by the processing circuitry and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation. The predicted load value is predicted according to at least one occurrence of each of the given load value and the predicted load value during execution of a sequence of previously performed load operations. The prediction circuit is configured to determine the ID-delta value from a difference between identifications associated with the at least one occurrence of each of the given load value and the predicted load value in the previously performed sequence of load operations.

Description

Background Art

[0001] The present technology relates to the field of data processing.

[0002] A load instruction is an instruction that, when executed, causes a data value to be fetched from a memory system. For example, a load instruction may specify a memory address identifying a particular memory location, and the data value may be fetched from that memory location (or from a cache entry associated with that memory address) and placed in a register. Load operations may sometimes be associated with long delays—for example, if the data value to be loaded is not present in a data cache and must be fetched from memory. Load operations are also quite common. Therefore, load operations and their associated delays may have a significant impact on performance.

[0003] One way to improve the performance of load operations is to implement a prediction scheme. For example, a load value predictor can be used to predict the data values ​​that will be extracted by an upcoming load operation, where the predicted data values ​​are made available in the same manner as the data values ​​are made available at the time of execution of the load operation. This can improve performance by allowing data values ​​to be made available more quickly. Summary of the invention

[0004] From an example, the present technology provides a device, the device comprising:

[0005] processing circuitry for executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations; and

[0006] prediction circuitry for receiving a given load value indicative of a value to be read in response to execution of a given load operation associated with the given identifier,

[0007] wherein the prediction circuitry is configured to make at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed by the processing circuitry and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation; and

[0008] wherein the prediction circuitry is configured to determine the predicted load value based on at least one occurrence of each of the given load value and the predicted load value observed during execution of a previously executed sequence of load operations; and

[0009] Wherein the prediction circuit is configured to determine the ID-increment value based on a difference between an identification associated with the at least one occurrence of each of the given load value and the predicted load value in a previously executed sequence of load operations.

[0010] From another example, the present technology provides a system, which includes: the above-mentioned device implemented in at least one packaged chip;

[0011] at least one system component; and a board,

[0013] The at least one packaged chip and the at least one system component are assembled on the board.

[0014] From another example, the present technology provides a chip-containing product that includes the above system assembled on an additional board with at least one other product component.

[0015] From another example, the present technology provides a method, the method comprising:

[0016] executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations;

[0017] receiving a given load value indicative of a value read in response to execution of a given load operation, the given load operation being associated with the given identification,

[0018] making at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation;

[0019] determining a predicted load value based on at least one occurrence of each of a given load value and a predicted load value observed during execution of a previously executed sequence of load operations; and

[0020] The ID-increment value is determined based on a difference between identifications associated with the at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

[0021] From another example, the present technology provides a computer program, which includes instructions, which when executed by a computer, cause the computer to perform the above method. The computer program can be stored on a computer-readable storage medium, which can be transient or non-transient.

[0022] From another example, the present technology provides a computer program, the computer program comprising a computer readable code for manufacturing an apparatus, the apparatus comprising:

[0023] processing circuitry for executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations; and

[0024] prediction circuitry for receiving a given load value indicative of a value to be read in response to execution of a given load operation associated with the given identifier,

[0025] wherein the prediction circuitry is configured to make at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed by the processing circuitry and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation; and

[0026] wherein the prediction circuitry is configured to determine the predicted load value based on at least one occurrence of each of the given load value and the predicted load value observed during execution of a previously executed sequence of load operations; and

[0027] wherein the prediction circuit is configured to determine the ID-increment value based on a difference between an identification associated with the at least one occurrence of each of the given load value and the predicted load value in a previously executed sequence of load operations. The computer program may be stored on a computer-readable storage medium, which may be transient or non-transitory.

[0028] Further aspects, features and advantages of the present technology will be apparent from the following description of examples read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An example of a processor pipeline is illustrated;

[0030] Figures 2 to 4 illustrates how overlapping execution can lead to performance improvements;

[0031] Figure 5 An example is shown of how the load value forecast can be used to make a forecast of the time series of loads;

[0032] Figure 6 An example of a prediction circuit is illustrated;

[0033] Figure 7 A more detailed example of a prediction circuit is illustrated;

[0034] Figure 8 An example of how a prediction circuit can be trained is illustrated;

[0035] Fig. 9 An example of how prediction circuitry can be used to make predictions is illustrated;

[0036] Fig.10 A more detailed example of how a prediction circuit can be trained is illustrated;

[0037] Fig.11 A more detailed example of how the prediction circuit can be used to make predictions is illustrated;

[0038] Fig.12 is a flow chart illustrating an example method of making a load value prediction;

[0039] Fig.13 is a flow chart illustrating an example method of training a prediction circuit;

[0040] Fig.14 is a flow chart illustrating an example method of using a confidence tracker during training of a prediction circuit; and

[0041] Fig.15 An example of how the present technology may be implemented in a packaged chip that may form part of a chip-containing product is illustrated. DETAILED DESCRIPTION

[0042] The following description of example implementations and associated advantages is provided before discussing example implementations with reference to the accompanying drawings.

[0043] There are several types of load value predictors. For example, one type of load value predictor may rely on the fact that a given load instruction may load the same data value each time it is executed. This means that the data value for a given load instruction may generally be predicted based on load values ​​retrieved in response to previous executions of the same instruction.

[0044] Another type of load value predictor may rely on the addresses of a sequence of load operations that form a regular sequence. For example, if a sequence of load operations is performed where the address for each load operation differs from the previous address by the same amount (e.g., a linearly varying sequence, such as 1, 4, 7, 10 ...), this type of load value predictor may be able to predict the entire sequence of data values ​​before performing the corresponding load operation.

[0045] However, none of these methods will necessarily work for a sequence of load operations whose loaded data values ​​form a time series. A time series includes any sequence of values ​​that repeats periodically; for example, the following sequence of values ​​is a time series with a periodicity of 4 (the dashed line "-" indicates periodicity):

[0046] 9,3,12,19-9,3,12,19-9,3,12,19

[0047] In the above sequence, the first values ​​(9, 3, 12, 19) follow an arbitrary sequence, but the sequence repeats. This type of sequence may also be referred to as a "periodic" sequence.

[0048] Loading time series of data values ​​is quite common in data processing. For example, pointer following algorithms, such as traversing a linked list (e.g., a list where each entry contains a pointer to the next entry), can involve loading time series of values. Therefore, it would be useful to be able to predict such series.

[0049] The difficulty in predicting a time series of load values ​​like this is that the periodicity of the series may be different from the periodicity of any identifier associated with the load instruction (e.g., program counter, instance count, etc.). This means that the same identifier is not necessarily always associated with the same load value. Furthermore, as can be seen from the above example, the series may not be a linearly varying series.

[0050] The present technology is intended to provide a mechanism for predicting a time series of load values. Specifically, the present technology provides an apparatus comprising a processing circuit for performing load operations, each load operation being associated with an identifier indicating the position of the load operation in a sequence of load operations. The identifier associated with each load operation may be any identifier indicating the position of the load operation in the sequence of load operations. For example, it may be a program counter, an instance count, or a loop identifier. For example, each load operation may be performed by the processing circuit in response to a load instruction being decoded.

[0051] The apparatus further comprises a prediction circuit for receiving a given load value indicative of a value to be read in response to execution of a given load operation, and for making at least one prediction indicative of a predicted load value for a subsequent load operation to be performed by the processing circuitry. The prediction made by the prediction circuitry is dependent on the given load value and further indicates an ID-increment value which is a difference between a given identification associated with the given load operation and an identification of a subsequent load operation. It is noted that the predicted load value is not necessarily the next load value in the sequence - the subsequent load operation may be several load operations prior to the given load operation.

[0052] The prediction circuit is configured to determine the predicted load value based on at least one occurrence of each of the given load value and the predicted load value observed during execution of a previously executed sequence of load operations, and to determine the ID-increment value based on a difference between identifications associated with at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

[0053] For example, consider that a load value "A" is observed as a result of a load operation with identification "1", and a load value "B" is observed as a result of a load operation with identification "4". If the prediction circuitry later receives a given load value "A", the prediction may indicate a predicted load value "B" and an ID-increment value "3".

[0054] In this way, by taking into account the "ID-delta" value that indicates the difference between the identifications, the prediction circuit can perform load value prediction for a time series of load values. Furthermore, because the prediction depends on the observed load values, the technique can be used regardless of whether the memory address for a subsequent load operation is known. This makes the technique particularly useful for self-feeding sequences such as pointer chasing algorithms, which typically follow a time series and in which the address for a given load operation is typically not known until a previous load operation has been executed.

[0055] In some examples, performance of the subsequent load operation includes reading a data value from a location identified by the load address, and the predicted load value includes at least one of:

[0056] The predicted data value for subsequent load operations, and

[0057] Predicted load addresses for subsequent load operations.

[0058] Therefore, the above-mentioned "predicted load value" may refer to a data value or an address.

[0059] In some examples, the apparatus includes metadata storage circuitry to store, for a previously executed sequence of load operations, information indicating a corresponding load value for each load operation in the previously executed sequence of load operations, wherein the prediction circuitry is configured to generate the prediction based on the information read from the metadata storage circuitry.

[0060] In this manner, predictions are made based on prediction data corresponding to previously executed sequences of load operations (e.g., information stored in metadata storage circuitry). This is particularly useful for predicting load values ​​in a temporal sequence of load values, since temporal sequences are characterized by repeating patterns of load values ​​(as described above). This means that a previously executed sequence may be part of the same sequence of load operations as a given load operation, in which case the pattern of load values ​​seen in the previously executed sequence may provide an indication of what subsequent load values ​​in the sequence will be.

[0061] In some examples, for at least one trigger load operation in a previously executed sequence of load operations, the metadata storage circuit includes an entry for storing a corresponding additional load value for at least one additional load operation in the previously executed sequence of load operations, wherein for the at least one additional load operation, the entry indicates a corresponding ID-increment value indicating a difference between a trigger identifier associated with the trigger load operation and a corresponding identifier associated with the additional load operation.

[0062] In this example, the at least one additional load operation may include a later load operation in a previously executed sequence. The entry may store a corresponding ID-increment value for each additional load operation, or it may indicate the corresponding ID-increment value in some other way. For example, the entry may store a corresponding identification, where a trigger identification is also stored (e.g., in a trigger entry corresponding to the trigger load operation), so that it is possible to subsequently calculate the ID-increment value from these values. Alternatively, the trigger identification may be stored as described above, but the corresponding ID-increment value for at least one additional load operation may be implicit from the arrangement of the storage metadata circuitry (e.g., each entry in the metadata storage device may be associated with a different ID-increment value). In any case, such an arrangement of the metadata storage circuitry allows a temporal sequence of load values ​​corresponding to a previously executed sequence to be represented, so that predictions can be made for subsequent load operations in the sequence.

[0063] In some examples, the associated flag for each load operation includes a loop flag that is incremented for each backward branch taken.

[0064] There are many different identifiers that can be used as associated identifiers for each load operation. For example, it can be considered to use a program counter (PC) for this purpose, or an instance count (e.g., indicating the number of times a specific load PC has been extracted). Alternatively, a new identifier can be defined for this purpose. However, although any of these identifiers (or one of several other existing identifiers) can be used as an associated identifier, this example utilizes a loop identifier (also known as a loop ID) as an associated identifier. The loop identifier is incremented for each backward branch taken during the execution of the instruction sequence. There are many advantages to using the loop identifier as a corresponding identifier. For example, the loop identifier has been used for other purposes (e.g., in a replay predictor) in a typical processor, so the use of the loop identifier avoids the need to define a new identifier. In addition, there may be a situation where the loop identifier will be better than, for example, the instance count—for example, in a program that sometimes skips some load operations, the instance count will not be incremented for those skipped load operations, while the loop identifier will be incremented because the backward branch will still be taken. This helps to mitigate any impact of the skipped load operation on the accuracy of the prediction made by the prediction circuit. Note that in some data processing systems, the replay predictor provides multiple candidate loop IDs, one of which is incremented for each backward branch taken. In such data processing systems implementing the present example, the loop ID (the one that is incremented for each backward branch taken) is used as the corresponding identification.

[0065] In some examples, the apparatus includes training circuitry, responsive to execution of at least one observed load operation, to store in temporary storage circuitry an observed load value indicative of a value read in response to execution of the observed load operation.

[0066] In this way, by training the prediction circuit based on previously observed load operations, more accurate predictions can be made for a given load operation and any additional load operations. Note that the training circuit may also be referred to as a "recorder."

[0067] In some examples, the training circuitry stores, in response to execution of the at least one observed load operation, an indication of an identification associated with the observed load operation in a temporary storage circuitry.

[0068] Storing the indication of the identity in the temporary storage circuit means that more storage space is required in the temporary storage circuit (or means that the number of load operations that can be represented in the temporary storage circuit is reduced). However, an advantage of storing the indication of the identity (rather than, for example, making the identity implicit from the structure of the temporary storage structure) is that it may provide more freedom as to how the temporary structure is arranged. The indication of the identity stored in the temporary storage circuit may be the identity itself, the corresponding ID-increment value or any other value that may be used to determine the identity.

[0069] In some examples, the training circuitry selects a storage location in the temporary storage circuitry in response to execution of the at least one observed load operation based on an identification associated with the observed load operation and stores the observed load value in the selected storage location, and the training circuitry is configured to select the storage location to provide an indication of the identification associated with the observed load operation.

[0070] In this example, the identification is not explicitly stored in the temporary storage location, but is implicit from the location of the storage location used to store information associated with the observed load operation. As described above, this may place constraints on how the temporary storage circuitry is arranged, but also reduces the amount of storage space required for each observed load operation.

[0071] In some examples, the temporary storage structure is configured to hold a metadata row including a trigger entry for storing information indicating a trigger load operation and one or more additional entries for storing observed load values ​​for each observed load operation. In these examples, the training circuitry is configured to, in response to determining that a predetermined condition has been satisfied, store the metadata row to the metadata storage circuitry, and the prediction circuitry is configured to generate a prediction based on information read from the metadata storage circuitry.

[0072] This describes an example of how to populate the metadata storage circuit based on the result of the observed load operation. Providing a trigger entry and one or more further entries allows indicating the relationship between the observed load operation and the trigger load operation, which may make it easier to retrieve prediction data from the metadata storage circuit when a prediction is requested.

[0073] In some examples, the temporary storage structure is configured to hold a metadata row that includes a trigger entry storing information indicating a trigger load operation and one or more additional entries storing observed load values ​​for each observed load operation. In these examples, the temporary storage circuit includes a trigger queue for holding a plurality of trigger entries, and a recorder array including one or more additional entries for a first trigger entry in the trigger queue, wherein the metadata row includes the first trigger entry in the trigger queue and the one or more additional entries in the recorder array.

[0074] The metadata row may be implemented in many ways in the present technology. However, in this example, the metadata row is formed by an entry in a trigger queue and one or more entries in a recorder array. Providing a trigger queue separate from the recorder array increases the number of different triggers for which a metadata row may be generated and stored, which may simplify prediction.

[0075] In some examples, the training circuitry is responsive to execution of the at least one observed load operation to:

[0076] determining whether there is an available entry in a trigger queue, and in response to determining that there is an available entry in the trigger queue, storing information indicative of the at least one observed load operation in the available entry in the trigger queue; and

[0077] Store the observed load value to an available entry in the recorder array.

[0078] Thus, in this example using a trigger queue and a recorder array, both the trigger queue and the recorder array may be updated in response to observing a single observed load operation. Thus, the observed load operation may provide prediction information for use in multiple predictions—it may act as a trigger for one prediction (e.g., if it is observed in the future, it may be used as an input into the prediction circuitry and used to look up the metadata storage circuitry) and as a prediction for another trigger (e.g., it may form part of a subsequent prediction).

[0079] In some examples, the temporary storage structure is configured to hold a metadata row that includes a trigger entry storing information indicating a trigger load operation and one or more additional entries storing observed load values ​​for each observed load operation. In these examples, the temporary storage structure includes a spin buffer that includes the trigger entry and the one or more additional entries.

[0080] This describes another example of how a row of metadata may be represented in a temporary storage circuit.A rotate buffer may be a relatively space efficient way to store information associated with a sequence of load operations.

[0081] In some examples, the apparatus includes metadata storage circuitry that stores, for a previously executed sequence of load operations, information indicating a corresponding load value for each load operation in the previously executed sequence of load operations, wherein the prediction circuitry is configured to generate the prediction based on the information read from the metadata storage circuitry. In these examples, the apparatus further includes confidence tracking circuitry that, in response to execution of the subsequent load operation, compares a subsequent load value read in response to execution of the subsequent load operation with the predicted load value, and updates a confidence value associated with the given load value based on the comparison.

[0082] This example uses a form of confidence tracking and provides a mechanism for recording the expected accuracy of predictions. Therefore, the confidence tracking circuit of this example can be used to improve the accuracy of predictions output by the prediction circuit. It should be noted that the confidence value can take any of a variety of forms. However, in some examples, the confidence value can be a count value that is incremented for each accurate prediction and decremented for each miss prediction.

[0083] In some examples, the prediction circuitry is configured to refrain from making a prediction until it is determined that a confidence value associated with a given load value satisfies a predetermined condition.

[0084] This is an example of how the above-described confidence tracking circuitry can be used to reduce the chance of a miss prediction occurring. In some specific examples, the predetermined condition can be a threshold confidence value that needs to be met (or exceeded) before the prediction circuitry makes a prediction. Note that once the predetermined condition has been met, the confidence tracking circuitry can continue to update the confidence value (e.g., in response to each prediction made in response to a given load value), or it can stop updating the confidence value once the condition is met unless there is a miss prediction.

[0085] In some examples, the apparatus includes: training circuitry that, in response to execution of at least one observed load operation, stores in temporary storage circuitry an observed load value indicative of a value read in response to execution of the observed load operation; and sampling circuitry that, in response to execution of a sequence of observed load operations, determines whether the observed sequence includes a self-fed sequence of load operations, wherein the training circuitry is configured to refrain from storing the observed load value and an indication of a connection between the observed load operation and the at least one previous value unless the sampling circuitry determines that the at least one observed load operation is part of a self-fed sequence.

[0086] A self-feeding sequence may be a sequence of load operations in which a load address for each load operation is determined based at least in part on the result of a previous load operation in the sequence. For example, a pointer tracking sequence is an example of a self-feeding sequence and involves accessing a memory location to obtain a pointer to a subsequent location, which in turn provides a pointer to another location, and so on. An example of a pointer tracking sequence may be traversing a linked list, because each entry in the linked list holds a pointer to the next entry in the list. A self-feeding sequence of load operations is more likely to be a predictable pointer tracking sequence than a non-self-feeding sequence, and its load values ​​are more likely to form a time series that can be predicted using the prediction circuit of the present technology. Therefore, by limiting training to self-feeding sequences identified by sampling circuits, space in the metadata storage circuit can be saved for storing prediction data that is more likely to be useful for future predictions.

[0087] There are different techniques for detecting self-feeding sequences. In some specific examples, the sampling circuit may use data flow graph analysis (eg, this may be at the rename stage of a processor pipeline) to identify self-feeding loads.

[0088] The concepts described herein may be embodied in computer readable code for manufacturing devices embodying the described concepts. For example, the computer readable code may be used at one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying the concepts. The above computer readable code may additionally or alternatively enable the definition, modeling, simulation, verification and / or testing of devices embodying the concepts described herein.

[0089] For example, computer readable code for making an apparatus embodying the concepts described herein may be embodied in code defining a hardware description language (HDL) representation of the concepts. For example, the code may define a register transfer level (RTL) abstraction for defining one or more logic circuits of an apparatus embodying the concepts. The code may define an HDL representation of one or more logic circuits embodying the apparatus in Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language), as well as intermediate representations such as FIRRTL. The computer readable code may provide definitions embodying concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of concepts that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concepts.

[0090] Additionally or alternatively, the computer readable code may embody a computer readable representation of one or more netlists. The one or more netlists may be generated by applying one or more logic synthesis processes to the RTL representation. Alternatively or additionally, the one or more logic synthesis processes may generate from the computer readable code a bitstream to be loaded into a field programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0091] The computer readable code may include a mixture of code representations for making a device, such as a mixture including one or more of an RTL representation, a netlist representation, or another computer readable definition used in a semiconductor design and manufacturing process to make a device embodying the invention. Alternatively or additionally, concepts may be defined in a combination of a computer readable definition used in a semiconductor design and manufacturing process to make a device and computer readable code defining instructions to be executed by the defined device once manufactured.

[0092] Such computer readable code may be provided in any known transient computer readable medium (such as wired or wireless code transmission over a network) or non-transitory computer readable medium such as a semiconductor, a magnetic disk, or an optical disk. An integrated circuit manufactured using the computer readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concepts alone or collectively.

[0093] Specific examples will now be described with reference to the accompanying drawings.

[0094] Figure 1An example of a data processing device 1 is schematically illustrated. The data processing device has a processing pipeline 17 including a plurality of pipeline stages. In this example, the pipeline stages include a fetch stage 3 for fetching instructions from a memory system (e.g., this may be via an instruction cache); a decode stage 5 for decoding the fetched program instructions to generate micro-operations (decoded instructions) to be processed by the remaining stages of the pipeline; an issue stage 9 for checking whether operands required for a micro-operation are available in a register file 15 (also referred to herein as a general register file GRF), and issuing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 11 (also referred to herein as a processing circuit) for executing a data processing operation corresponding to the micro-operation by processing operands read from the register file 15 to generate a result value; and a writeback stage 13 for writing the result of the processing back to the register file 15. The pipeline 17 also includes a register renaming stage 7 for mapping architectural registers specified by program instructions or micro-operations to physical register descriptors identifying physical registers in the register file 15 - this facilitates out-of-order processing using the data processing apparatus 1. It should be understood that this is only one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, an in-order processor may not include a register renaming stage 7.

[0095] The execute stage is an example of processing circuitry that performs load operations, each load operation being associated with an identifier indicating the position of the load operation in a sequence of load operations. Each load operation may be executed in response to decoding a load instruction in the decode stage 5 .

[0096] It should be understood that Figure 1 This is only a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements that are not illustrated for the sake of brevity, such as branch prediction mechanisms or address translation or memory management mechanisms.

[0097] Figure 2 An example of a sequence 2 of fifteen (15) load operations is shown, where the data obtained from each load operation 4 is used to construct the address of the next load operation. For example, this type of load operation pattern (called a self-feeding or self-generating sequence) can be seen in a pointer tracking sequence, where each load operation obtains a pointer for performing the next load operation. A specific example of a pointer tracking algorithm is traversing a linked list, where each item in the list contains a pointer to the next item in the list. It should be understood that other examples of self-feeding sequences are possible.

[0098] exist Figure 2In the example of , each load operation takes four cycles (labeled as "4C" in the figure; 4C=4 cycles) to complete. Therefore, when the load operations are performed sequentially, a total of sixty cycles (60C) are taken to complete all fifteen load operations.

[0099] Many data processing operations exploit parallelism (executing multiple instructions in parallel) to improve performance by reducing the total number of cycles required to execute a sequence of instructions. Figure 2 It also shows how overlapping execution of load operations (e.g., utilizing parallel execution) can theoretically greatly reduce the number of cycles required to execute a complete sequence. Specifically, Figure 2 A theoretical example is shown in which the execution of each load operation 4 begins one cycle after the execution of the previous load operation, so that up to four load operations can be executed at any given time. As a result of this arrangement, all fifteen operations are executed in eighteen cycles (18C). Based on the steady-state load completion rate and assuming Figure 2 Only a fragment of the time pattern is shown, which gives the average per-load delay to reach the 1 per cycle limit.

[0100] However, Figure 2 The overlap of load operations shown is only possible if the dependencies between the load operations allow it. A dependency exists between two load operations if the result of one operation is needed to execute another load operation—if one load operation depends on another, it cannot generally be executed until the execution of the other operation has completed. Thus, if, for example, any of the second, third, or fourth load operations (each of which overlaps with the first load operation) depends on the first load operation, then Figure 2 Therefore, it should be understood that this arrangement is not suitable for sequences such as pointer tracking sequences, where each load operation depends on the previous load operation.

[0101] Figure 3 and Figure 4 Another way of showing the execution of overlapping load operations is shown; Figure 3 The arrangement in allows all fifteen loads to be completed within eighteen cycles (18C), again averaging 1C per load. Figure 4 The arrangement shown allows all fifteen loads to complete in 21 cycles (note that there is a 3 cycle stall every 8 loads (e.g., before executing the "0x9F" load operation)), which gives an average of 1.375C per load. These examples do allow for some dependencies between adjacent load operations, but still restrict which loads can depend on which other loads. For example, in Figure 3In , the operation on load value 0x0A can depend on the operation on load value 0xFC because the first load completes before the second load begins. However, the operation on load values ​​0x48, 0xD6, and 0x67 cannot depend on load value 0xFC. Similarly, in Figure 4 , operations on load values ​​0x0A, 0x48, and 0x9C may all depend on load value 0xFC, but operations on load value 0xD6 may not depend on it.

[0102] therefore, Figures 2 to 4 shows the performance improvement that can be provided by parallel execution, as long as the dependencies between load operations in the sequence are limited. However, there are load operation patterns—such as pointer-chasing routines, which are seen relatively frequently—that do not allow Figures 2 to 4 Dependency patterns for any of the patterns shown. For example, if sequence 2 represented a linked list traversal, no parallel execution would be possible unless the dependency chain could be broken.

[0103] Examples of the present technology aim to provide a mechanism to reduce the number of cycles required to execute such a sequence of load operations and thus improve performance. Specifically, examples of the present technology aim to use load value prediction to remove some or all dependencies in the sequence.

[0104] Load prediction techniques typically rely on a given load operation being performed multiple times and retrieving the same value each time. Other techniques may rely on a sequence of load operations that use a regular (e.g., linearly varying) pattern of load addresses (e.g., each load value is at an address X bytes after the address of the previous load operation) or a regular pattern of load data values. Such load prediction techniques can be useful in many cases, but they are not particularly useful when the sequence of load operations does not meet any of these requirements. For example, the load values ​​(e.g., the data values ​​read in response to the load operation, or the load addresses from which the data values ​​are read) may follow a time sequence that includes a seemingly arbitrary sequence of values ​​that repeats periodically. This is quite common—for example (as described above), a pointer tracking sequence typically results in a time sequence of load values ​​being observed. Similarly, certain load value prediction techniques may not be particularly useful in cases where the identifiers (such as program counters, loop IDs, or instance counts) associated with two instances of the same load operation vary—which is also quite common, particularly when the sequence of load operations includes fewer operations than the number of available identifiers.

[0105] Examples of the present technique seek to provide an alternative method for load value prediction that can predict load values ​​in time series such as these.

[0106] refer to Figure 5 , each load operation 4 in the sequence 8 is associated with an identification 6 (a loop ID in this example). Figure 5 The sequence 8 shown is an extended version of the sequence shown in the previous figure. As shown, the sequence 8 is a time sequence in which the sequence of 32 load operations (the sequence starts with 0xFC-0x0A-0x48-0x9C-0xD6-etc.) repeats itself.

[0107] However, although the load value repeats itself every 32 operations, each instance of a given load value is associated with a different loop ID. For example, the second instance of the load value 0xFC is associated with loop ID 32, while the first instance is associated with loop ID 0. This is because the periodicity of the time series (e.g., the number of load values ​​in the sequence that are repeated— Figure 5 The periodicity of the sequence in is, for example, 32) is different from the number of available cycle IDs (eg, there are more than 32 available cycle IDs). Thus, the cycle ID of a given load operation does not directly indicate what the load value will be.

[0108] However, the inventors of the present technology have recognized that, although the identification itself may be different between different instances of the same load value, the difference between the identifications of two load values ​​will always be the same. Figure 5 In the sequence 8 shown, three loads of the load value 0xFC (loop IDs 0 and 32) are repeatedly followed by a load value 0x9C (loop IDs 3 and 35)—in other words, the difference between the identifications associated with the load values ​​0xFC and 0x9C (referred to as the "loop ID increment" or ID-increment value) remains constant at 3. This fact is relied upon to implement the prediction circuitry of the examples of the present technique.

[0109] Figure 6 An example of a prediction circuit 10 according to an example of the present technique is shown - note that the prediction circuit is also referred to herein as a "time value predictor" as it is particularly useful for predicting load values ​​in a time series.

[0110] like Figure 6 As shown, the prediction circuit 10 takes as input a load value (e.g., a data value read in response to a load operation, or an address from which a data value is read) and a loop ID associated with the loop value. The prediction circuit then outputs a prediction indicating a subsequent load value and a corresponding identification (or a corresponding ID delta value indicating the difference between the identification of the predicted load value and the identification of the input load value). Figure 6In the particular example shown, a load value of 0xFC and a loop ID of 32 are input. The prediction circuitry then predicts that a subsequent load with an ID increment value of 3 (and therefore a loop ID of 32+3=35) will have a load value of 0x9C. As will be explained in more detail below, this prediction is based on the fact that at least one previous instance of a load value of 0xFC (e.g., a load with loop ID 0) was followed by a load value of 0x9C (e.g., a load with loop ID 3) 3 load operations later. The prediction circuitry 10 is therefore able to predict a subsequent load value in a time series of load values ​​based on the loop ID increment value associated with the input load value.

[0111] The prediction circuit 10 is an example of a prediction circuit that receives a given load value indicating a value read in response to execution of a given load operation, the given load operation being associated with a given identification, wherein the prediction circuit is configured to make at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuit and an ID-increment value indicating a difference between the given identification and the identification of the subsequent load operation. The prediction circuit 10 is also an example of a prediction circuit that is configured to determine the predicted load value based on observing at least one occurrence of each of the given load value and the predicted load value during execution of a previously executed sequence of load operations, wherein the prediction circuit is configured to determine the ID-increment value based on the difference between the identifications associated with at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

[0112] Figure 7 A more detailed view of prediction circuit 10 is shown. Prediction circuit 10 includes a recorder 12 (also referred to as a training circuit) for collecting prediction data used to generate predictions. The prediction data is stored to metadata storage circuit 14 (also referred to as metadata storage). Sequencer 16 (also referred to as a sequencer circuit) is used to generate predictions that are consumed by predictor 18. Each of these elements is described in more detail below.

[0113] Figure 8 The recorder (training circuit) 12 is shown in more detail. Specifically, Figure 8An example is shown of how the prediction circuit 10 can be "trained" based on an observed sequence of load operations to make predictions for subsequent operations in the sequence. As shown, the recorder 12 includes a temporary storage circuit 20 that holds a metadata row. The metadata row includes a tag or trigger value entry 22 that stores a previously observed load value. The tag entry may also store an identifier associated with the trigger load value. The metadata row also includes one of a plurality of entries 24 that stores a subsequent load value observed by the recorder 20. Finally, the metadata row includes one or more entries 26 that store an identifier (or ID-increment value) associated with the subsequent load value. If ID-increment values ​​are stored, these values ​​are calculated relative to the identifier of the trigger load. Note that in some alternative examples, the identifier (or ID-increment value) for the subsequent load value is not necessarily stored - instead, the ID-increment value for a particular load value may be implied from its position in the metadata row.

[0114] In response to a load operation performed by the processing circuitry, the metadata row is filled by the recorder 12. Once certain conditions are met (e.g., once the metadata row is full), the recorder 12 stores the metadata row to the metadata storage 14 and begins recording a new metadata row in the temporary storage circuitry 20.

[0115] Fig. 9 The metadata storage device 14, the sequencer 16 and the predictor 18 are shown in more detail. Specifically, Fig. 9 It is illustrated how the prediction circuit 10 may be used to generate a prediction.

[0116] As described above, the metadata rows 28 populated by the recorder 12 are stored in the metadata storage device 14. For simplicity, Fig. 9 Only one metadata row 28 in the metadata store is shown; however, it should be understood that the metadata store 14 may store data representing multiple metadata rows 28, each metadata row corresponding to a different tag / trigger value.

[0117] The prediction circuitry of the present technique receives a load value 30 and a corresponding cycle ID 38 associated with a given (executed) load operation. The load value 30 is looked up in the metadata storage 14; for example, the load value 30 may be compared to the tag / trigger value 22 in each metadata row 28 until a match is detected. If a match (also referred to as a "hit") is detected (e.g., if it is determined that the metadata storage 14 holds a metadata row with a tag / trigger value 22 that corresponds to the lookup value), one or more subsequent load values ​​24 and associated identification / ID increment values ​​26 are output to the sequencer 16. In this particular example, the metadata row 28 stores the cycle ID increment value.

[0118] In the sequencer 16, a predictor row 32 is created. The predictor row 32 indicates at least one identification (in this example, a loop ID) 34 and at least one corresponding load value 36. In this example, the at least one loop ID 34 is calculated by adding the loop ID increment value 26 read from the metadata row 28 to the loop ID 38 received by the prediction circuit. The predictor row 32 is then provided to the predictor 18, which consumes (uses and / or outputs) the prediction. For example, the prediction may be consumed by loading the predicted load value into a register accessible to the processing circuit.

[0119] Fig.10 An example of a prediction circuit 10 is shown, which demonstrates how the prediction circuit 10 may be trained based on observed load operations.

[0120] Specifically, Fig.10 The results of the load operation (e.g., load values) 40 are shown being received and recorded in the training buffer 42. As indicated by arrows 44, each load value and its associated cycle ID are stored from the training buffer 42 to the next available entry in the recorder array 46 and the next available entry in the trigger queue 48 (if any). The trigger queue 48 and the recorder array 46 together form an example of the temporary storage circuit described above, and a single metadata row comprises the first entry of the trigger queue 48 combined with the recorder array 46. As indicated by arrows 50, 52 and 54, the single metadata row is compressed 56 and stored in an entry of the metadata cache 58. This may occur when the recorder array 46 is full, or may be triggered by satisfying some other condition (e.g., a metadata row may be periodically stored to the metadata cache 58 regardless of whether the recorder array 46 is completely full). The metadata cache 58 is an example of a metadata storage circuit. Thus, when a load operation is observed, the metadata storage circuit is filled with prediction data. Then, in response to an incoming load value that matches one of the stored tag values, data from the metadata cache 58 can be decompressed 66 and stored in a prediction table 62, which can be found in the predictor 18 described above and used to prepare the prediction. In this example, the prediction table 62 stores a valid bit (Vld), a color bit (CB), and a data value (data) in each entry. The data value is the predicted load value, the valid bit indicates whether the entry is valid, and the color bit is the tag value. Using the color bit as a tag instead of a loop ID allows us to have a prediction table with fewer bits than the loop ID. The high bits of the loop ID that do not form an index to the prediction table will instead form a tag or color bit for the entry. However, it should be understood that another form of tag may be used instead (for example, a loop ID may be used).

[0121] In addition to populating the metadata cache 58, the confidence tracker 60 is also updated when a load operation is observed. Specifically, when each load operation is completed, the PC register file or instruction pointer register file (PCRF) in the extraction stage is looked up to obtain the associated program counter (PC) value and loop ID. An entry in the confidence tracker 60 is then created (unless an entry for the load instruction already exists), indicating the program counter (PC) value and the confidence value. The confidence value indicates the confidence for the prediction. Subsequently, whenever a load instruction is executed, the recorder and trigger queues are updated with the observed load value from the operation, and the confidence tracker 60 is also updated. Specifically, the observed load value is compared 64 with the predicted load value stored in the prediction table 62, and the confidence value is updated accordingly. For example, the confidence value may be incremented for a correct prediction and decremented for an incorrect prediction. The confidence value can then be used to determine whether to output the prediction.

[0122] Fig.11 1 shows how prediction circuitry 10 may be used to make predictions after the prediction table has been populated. As shown, the program counter (PC) for the fetched load instruction is used to look up the confidence tracker 60, and if a hit is detected, the confidence value from the identified entry is compared to a threshold 68 to determine whether to output a prediction.

[0123] At the same time, the loop ID for the fetched load instruction is provided to the prediction table 62 so that the loop ID can be determined for each predicted load value by adding the input loop ID to the ID increment value recorded for each predicted load value. The calculated loop ID and the corresponding predicted load value are then stored in the value prediction queue 70. The prediction queue 70 thus holds a sequence of predicted load values ​​and their corresponding loop IDs, which can be output. For example, the predicted load value can be written to a general register file (GRF) for use when the corresponding load operation is subsequently performed.

[0124] The value prediction queue 70 is optional. Because the prediction table 62 is looked up in the fetch stage (where the fetch block is 16 instructions wide), and then realigned or queued in the decode stage, with instructions separated out 10 at a time, the value prediction queue can be useful because it provides a temporary location for data to be stored before the instruction is renamed. Once the instruction is renamed, the data can be written to the associated physical register (e.g., in the GRF). However, other approaches are possible - for example, the loop ID can be tracked to rename, and then the prediction table can be looked up again to obtain the data.

[0125] Fig.12is a flow chart illustrating an example of a method for generating predictions using the prediction circuit 10 of an example of the present technology. The method includes waiting 72 for receiving a loop ID and an associated load value for a completed load operation. When the loop ID and load value are received, the method includes looking up 74 the load value in a metadata storage device. Determining 76 whether the result of the lookup in the metadata storage device hits, and if not, the method returns to waiting 72 for receiving the loop ID and load value without outputting 78 the prediction. On the other hand, if a hit is detected, one or more predicted load values ​​are obtained 80 from the identified one or more entries of the metadata storage device. A difference value (ID increment) for the load operation corresponding to each predicted load value is also obtained 82. The loop ID for each load operation represented by the predicted load value is then calculated 84, and the loop ID is calculated by adding the difference value for the load operation to the input loop ID. Once the prediction has been generated, the prediction is output 86.

[0126] Fig.13 is a flow chart illustrating an example of a method of training a prediction circuit 10. The method includes waiting 88 for receiving a loop ID and a load value from a completed load operation. Once the loop ID and load value are received, the method includes determining 90 whether there is an available entry in the trigger queue, and if there is an available entry, recording 92 the received load value in the next available trigger queue entry. The method also includes recording 94 the received load value in the next available entry in the recorder array regardless of whether there is an available entry in the trigger queue. The method then includes determining 96 whether the recorder array is now full, and if so, popping 98 the top entry of the trigger queue and storing 99 a metadata row including the popped trigger queue entry and the contents of the recorder array to a metadata storage device. The recorder array is then cleared 101.

[0127] Fig.14 1 is a flow chart illustrating an example of a method of updating a confidence tracker when training prediction circuitry 10 of an example of the present technology. The method includes waiting 100 to receive a loop ID and a load value from a completed load operation. Once the loop ID and load value have been received, the method includes the step of looking up the loop ID in the confidence tracker and looking up the load value in the prediction cache (prediction table) 102. It is then determined 104 whether these lookup results both hit, and if they both hit, the received load value is compared 106 with the predicted load value obtained from the prediction cache. It is then determined 108 whether the comparison result matches. If the comparison result matches (e.g., if the predicted load value is the same as the received load value), the confidence value is incremented 112, and if the comparison result does not match, the confidence value is decremented 110.

[0128] The method also includes determining 114 whether a confidence value for a load operation corresponding to the received load value exceeds a predetermined threshold. If it is determined that the threshold is exceeded, the method includes enabling prediction for the load operation.

[0129] The concepts described herein may be embodied in a system including at least one packaged chip. The above-mentioned means are implemented in the at least one packaged chip (implemented in a specific chip of the system, or distributed on more than one packaged chip). The at least one packaged chip is assembled on a board together with at least one system component. A chip-containing product may include a system assembled on another board with at least one other product component. The system or chip-containing product may be assembled into a housing or assembled onto a structural support (such as a frame or blade).

[0130] like Fig.15 As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the above-mentioned device is implemented on one chip or distributed on two or more of these chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer can be provided as a semiconductor package, which includes a protective housing (for example, made of metal, plastic, glass or ceramic) for accommodating a semiconductor device that implements the above-mentioned device and a connector such as a pad, solder ball or pin for connecting the semiconductor device to the external environment. In the case of providing more than one chip 400, these chips can be provided as separate integrated circuits (provided as separate packages), or can be packaged into a multi-chip semiconductor package by a semiconductor provider (for example, using an interposer, or by using three-dimensional integration to provide a multi-layer chip product including two or more vertically stacked integrated circuit layers).

[0131] In some examples, a collection of chiplets (i.e., small modular chips with specific functionality) may themselves be referred to as a chip. A chiplet may be packaged individually in a semiconductor package and / or packaged with other chiplets into a multi-chiplet semiconductor package (e.g., using an interposer, or by using three-dimensional integration to provide a multi-layer chiplet product including two or more vertically stacked integrated circuit layers).

[0132] One or more packaged chips 400 are assembled on board 402 together with at least one system component 404. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, for example, plastic, glass, ceramic, or a flexible substrate material such as paper, plastic, or textile material. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include, for example, any one or more of the following: another packaged chip (e.g., provided by a different manufacturer or produced at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0133] A chip-containing product 416 is manufactured, which includes a system 406 (including board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product component 412 includes one or more additional components that are not part of system 406. As a non-exhaustive list of examples, one or more product components 412 may include user input / output devices such as keyboards, touch screens, microphones, speakers, display screens, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical movement; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 can be assembled onto an additional board 414.

[0134] Plate 402 or additional plates 414 may be disposed on or within a device housing or other structural support (eg, a frame or blade) to provide a product that is manipulable by a user and / or intended for operational use by a person or company.

[0135] System 406 or chip-containing product 416 may be at least one of an end-user product, a machine, a medical device, a computing or telecommunications infrastructure product, or an automated control system. For example, as a non-exhaustive list of examples, the chip-containing product may be any of the following: telecommunications equipment, mobile phones, tablet computers, laptops, computers, servers (e.g., rack servers or blade servers), infrastructure equipment, networking equipment, vehicles or other automotive products, industrial machines, consumer devices, smart cards, credit cards, smart glasses, avionics equipment, robotic equipment, cameras, televisions, smart TVs, DVD players, set-top boxes, wearable devices, home appliances, smart meters, medical devices, heating / lighting control equipment, sensors, and / or control systems for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0136] In this application, the words "configured to..." are used to mean that elements of a device have a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way in order to provide the defined operation.

[0137] Further, the phrase "including at least one of..." in the present application is used to indicate including any one of the following options or any combination of the following options. For example, "at least one of A; B and C" means A or B or C, or any combination of A, B and C (e.g. A and B, or A and C, or B and C).

[0138] Although exemplary embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device, comprising: processing circuitry for executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations; and prediction circuitry for receiving a given load value indicative of a value to be read in response to execution of a given load operation associated with the given identifier, wherein the prediction circuitry is configured to make at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed by the processing circuitry and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation; and wherein the prediction circuitry is configured to determine the predicted load value based on at least one occurrence of each of the given load value and the predicted load value observed during execution of a previously executed sequence of load operations; and Wherein the prediction circuit is configured to determine the ID-increment value based on a difference between an identification associated with the at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

2. The device according to claim 1, wherein: The execution of the subsequent load operation includes reading a data value from a location identified by a load address; and The predicted load value includes at least one of the following: the predicted data value for the subsequent load operation, and A predicted load address for the subsequent load operation.

3. A device according to any preceding claim, comprising metadata storage circuitry for storing, for the previously executed sequence of load operations, information indicating a corresponding load value for each load operation in the previously executed sequence of load operations, Wherein the prediction circuit is configured to generate the prediction based on information read from the metadata storage circuit.

4. The device according to claim 3, wherein For at least one trigger load operation in the previously executed sequence of load operations, the metadata storage circuit includes an entry for storing a corresponding additional load value for at least one additional load operation in the previously executed sequence of load operations, wherein for the at least one additional load operation, the entry indicates a corresponding ID-increment value, and the corresponding ID-increment value indicates a difference between a trigger identifier associated with the trigger load operation and a corresponding identifier associated with the additional load operation.

5. A device according to any preceding claim, wherein The associated flags for each load operation include a loop flag that is incremented for each backward branch taken.

6. A device according to any preceding claim, comprising Training circuitry, responsive to execution of at least one observed load operation, is operable to store in temporary storage circuitry an observed load value indicative of a value read in response to execution of the observed load operation.

7. The device according to claim 6, wherein The training circuitry is responsive to the execution of the at least one observed load operation to store in the temporary storage circuitry an indication of an identification associated with the observed load operation.

8. The device according to claim 6, wherein the training circuitry, responsive to the execution of the at least one observed load operation, for selecting a storage location in the temporary storage circuitry based on an identification associated with the observed load operation, and for storing the observed load value in the selected storage location; and The training circuitry is configured to select the storage location to provide an indication of the identification associated with the observed load operation.

9. The device according to any one of claims 6 to 8, wherein: The temporary storage structure is configured to store a metadata row, the metadata row comprising: a trigger entry for storing information indicating a trigger load operation; and one or more further entries for storing, for each observed load operation, the observed load value; The training circuitry is configured to, in response to determining that a predetermined condition has been satisfied, store the metadata row to the metadata storage circuitry; and The prediction circuit is configured to generate the prediction based on information read from the metadata storage circuit.

10. The device according to any one of claims 6 to 9, wherein The temporary storage structure is configured to store a metadata row, the metadata row comprising: A trigger entry, the trigger entry being used to store information indicating a trigger load operation; and one or more further entries for storing, for each observed load operation, the observed load value; The temporary storage circuit comprises: A trigger queue, wherein the trigger queue is used to store multiple trigger entries; and a recorder array comprising, for a first trigger entry in the trigger queue, the one or more further entries, Wherein the metadata row comprises the first trigger entry in the trigger queue and the one or more further entries in the recorder array.

11. The device according to claim 10, wherein: The training circuitry is responsive to execution of the at least one observed load operation to: determining whether there is an available entry in the trigger queue, and in response to determining that there is an available entry in the trigger queue, storing information indicating the at least one observed load operation in the available entry in the trigger queue; as well as The observed load value is stored in an available entry in the recorder array.

12. The device according to any one of claims 6 to 9, wherein: The temporary storage structure is configured to store a metadata row, the metadata row comprising: a trigger entry for storing information indicating a trigger load operation; and one or more further entries for storing, for each observed load operation, the observed load value; and The temporary storage structure comprises a rotating buffer including the trigger entry and the one or more further entries.

13. An apparatus according to any preceding claim, comprising: metadata storage circuitry to store, for the previously executed sequence of load operations, information indicating a corresponding load value for each load operation in the previously executed sequence of load operations, wherein the prediction circuitry is configured to generate the prediction based on information read from the metadata storage circuitry; and A confidence tracking circuit is provided, responsive to execution of the subsequent load operation, for comparing a subsequent load value read in response to execution of the subsequent load operation with the predicted load value, and for updating a confidence value associated with the given load value based on the comparison.

14. The device according to claim 13, wherein The prediction circuit is configured to refrain from making the prediction until it is determined that the confidence value associated with the given load value satisfies a predetermined condition.

15. An apparatus according to any preceding claim, comprising: training circuitry, the training circuitry responsive to execution of at least one observed load operation, to store in temporary storage circuitry an observed load value indicative of a value read in response to execution of the observed load operation; and a sampling circuit, the sampling circuit being responsive to the execution of an observed sequence of load operations, for determining whether the observed sequence includes a self-fed sequence of load operations, wherein the training circuit is configured to refrain from storing the observed load value and the indication of a relationship between the observed load operation and the at least one previous value unless the sampling circuit determines that the at least one observed load operation is part of the self-feeding sequence.

16. A system, comprising: An apparatus according to any preceding claim implemented in at least one packaged chip; at least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

17. A chip-containing product comprising the system of claim 16 assembled on a further board with at least one other product component.

18. A method comprising: executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations; receiving a given load value indicative of a value read in response to execution of a given load operation, the given load operation being associated with the given identification, performing at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation; determining the predicted load value based on observing at least one occurrence of each of the given load value and the predicted load value during execution of a previously executed sequence of load operations; as well as The ID-increment value is determined based on a difference between identifications associated with the at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

19. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method according to claim 18.

20. A computer program comprising computer readable code for producing an apparatus comprising: processing circuitry for executing load operations, each load operation being associated with an identifier indicating a position of the load operation in a sequence of load operations; and prediction circuitry for receiving a given load value indicative of a value to be read in response to execution of a given load operation associated with the given identifier, wherein the prediction circuitry is configured to make at least one prediction based on the given load value, the at least one prediction indicating a predicted load value for a subsequent load operation to be performed by the processing circuitry and an ID-delta value indicating a difference between the given identification and an identification of the subsequent load operation; and wherein the prediction circuitry is configured to determine the predicted load value based on observing at least one occurrence of each of the given load value and the predicted load value during execution of a previously executed sequence of load operations; and Wherein the prediction circuit is configured to determine the ID-increment value based on a difference between an identification associated with the at least one occurrence of each of the given load value and the predicted load value in the previously executed sequence of load operations.

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