A method for processing large amounts of data based on domestic multi-core DSPs

Abstract

The present invention discloses a method for processing dense signals of large amounts of data based on a domestic multi-core DSP, comprising the following steps: step 1. constructing an external storage space for data processing; step 2. designing a data transmission program; step 3. designing a DSP core data processing program; step 4. designing a data transmission processing state monitoring module; step 5. outputting data processing results by designing an output data processing result module. The purpose of this method is to improve the real-time and universality of dense signal processing of large amounts of data and reduce the difficulty of engineering implementation; this method combines the OpenMP parallel programming program interface to process data in parallel to improve program operation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a method for processing intensive signals with large amounts of data based on a domestically produced multi-core DSP. Background Art

[0002] Digital signal processing plays a vital role in modern communications, audio processing, image processing and other fields. In recent years, with the rapid development of modern communication technology and the increasing application demand, large-scale intensive signal processing systems with DSP (digital signal processor) as the hardware architecture are facing great challenges. How to provide users with convenient and efficient implementation methods for large-scale intensive signal processing under multi-core conditions is gradually becoming a research hotspot in the near future. In order to achieve efficient DSP development, a series of optimization methods and multi-core parallel programming technologies are needed to improve the performance and efficiency of the processing flow. At present, there are two parts that can effectively improve efficiency: data transmission and multi-core parallel processing:

[0003] (1) Data transmission

[0004] In the process of intensive signal processing of large amounts of data, in order to enable different processors to collaborate in executing tasks and improve operating efficiency, data transmission is frequently involved. Although the kernel L1D (first-level data storage controller) and L2 (second-level storage controller) can meet the requirements of efficient access, the capacity is limited, so accessing the external memory is inevitable. In most cases, a large amount of data and temporary variables need to be stored in the external memory. The external memory includes MSMC (Multicore Shared Memory Controller), DDR3 (full name third-generation double-rate synchronous dynamic random access memory) and EMIF (External Memory Interface) peripheral devices. Among them, MSMC has the fastest read and write speed but the smallest storage capacity, and DDR3 has the slowest read and write speed but the largest storage capacity. In the process of intensive signal processing of large amounts of data, storing a large amount of data and temporary variables in the 4MB external memory MSMC obviously cannot meet the needs of large amounts of data, and storing a large amount of data and temporary variables in the external memory DDR3 will lead to a decrease in program running efficiency. At present, it is very expensive to have both the high read and write speed of MSMC and the large storage capacity of DDR3. Therefore, finding an effective data transmission method between MSMC and DDR3 is an effective way to improve the intensive signal processing rate of large data volumes.

[0005] (2) Multi-core parallel processing

[0006] When developing on multi-core DSPs, it is an important issue to give full play to the high performance advantages of multi-core DSPs and perform parallel programming on multi-core platforms. When processing large amounts of dense signals in parallel, there are mainly two traditional multi-core DSP parallel programming methods:

[0007] 1) Multi-core parallel processing method based on master-slave mode

[0008] The multi-core DSP parallel processing method based on the master-slave mode generally artificially divides the 8 DSP cores into master cores and slave cores. Generally, core 0 is configured as the master core, and cores 1 to 7 are configured as slave cores. The master core is responsible for task allocation and process control for the slave cores. In the master-slave mode, the master core has the ability to establish SRIO (Serial RapidIO) communication with external devices. After receiving the data, the master core distributes the data to the master core and 7 slave cores according to the core number. The 8 cores use the same algorithm to process different data, and each core is independent of each other. This method requires that there is no coupling between row data or column data, and the data can be directly processed in blocks, so it is not applicable to all data.

[0009] 2) Multi-core parallel processing method based on data flow mode

[0010] The multi-core DSP parallel processing method based on the data flow mode needs to artificially divide the algorithm into 8 parts according to the algorithm's computational workload and assign them to 8 cores for execution. In this mode, each core executes a part of the algorithm, and the cores are highly dependent on each other and have a strict order relationship. The implementation of the data flow mode requires strict segmentation of the algorithm according to the computational workload. The data flow mode is applicable to the processing of any data, but in the data flow mode, the total algorithm needs to be strictly divided into eight parts according to the computational workload, which greatly increases the workload of engineers and makes engineering implementation more difficult.

[0011] As programs become more complex, it has become increasingly difficult and complex to parallelize the original serial programs through the above two methods. Finding a multi-core parallel data processing method that is convenient, efficient, scalable, and portable under multi-core conditions is an effective way to improve the efficiency of dense signal processing of large amounts of data.

[0012] Current existing technical solutions:

[0013] The Chinese invention patent "A multi-core DSP radar signal processing method" (application number: CN202311062116.3, publication number: CN 117193635 A) is applicable to improving the performance of multi-core DSP radar signal processing. The general process is as follows: First, the 4MB shared storage area MSMC in the multi-core DSP is used as the receiving cache of the SRIO interface and the processing cache of the DSP. The external device continuously sends the radar echo data to the SRIO receiving cache of the DSP through the SRIO interface. Each time a re-frequency data is sent, a doorbell interrupt is sent to the DSP; the DSP core directly takes out the data from the SRIO receiving cache for calculation; in the process of multi-core DSP processing radar signals, each independent processing sub-cache space is only accessed by one core, and according to the cache line alignment, the size of each independent processing sub-cache space in each processing step is consistent. DSP core 0 is used to initialize the DSP core, DDR3, shared storage area, SRIO interface, run the network protocol stack, etc. DSP cores 2 to 7 perform windowing, azimuth FFT and other processing on the data in the array respectively. The processed data are stored in 6 arrays respectively. The address allocation is aligned according to the cache line, and the cache and prefetch are enabled; DSP cores 2 to 7 perform distance CFAR (Constant False Alarm Rate) processing on the data in the array respectively, and store them in the array after processing; DSP cores 2 to 7 perform azimuth CFAR processing on the data in the array respectively; finally, DSP core 0 summarizes the processing results of DSP cores 2 to 7.

[0014] After a series of processing, the method uses the shared memory area MSMC instead of DDR3 as the receiving cache of the SRIO interface and the data processing cache of the DSP. Since the access rate of the shared memory area is 1 / 2 the CPU (Central Processing Unit) clock frequency, its access rate is higher than DDR3, and there will be no problem of reduced access efficiency caused by row switching when the access address is discontinuous, which can improve the program running efficiency; each DSP core allocates independent cache space in the shared memory area, avoiding the problem of multi-core access requiring the closure of the shared memory area due to Cache (cache memory) consistency problems or the problem of the DSP core needing to frequently manually maintain Cache consistency, thereby improving the multi-core parallel computing efficiency.

[0015] Disadvantages of the above solution:

[0016] In the Chinese invention patent "A multi-core DSP radar signal processing method" (application number: CN202311062116.3, publication number: CN 117193635 A), MSMC is used instead of DDR3 as the receiving cache of the SRIO interface and the processing cache of the DSP. The read and write speed of MSMC is higher than that of DDR3. However, the capacity of MSMC is usually only 4MB. Using it as the data processing cache of DSP can only meet the needs of signal processing of small data volumes, such as MTD (moving targets detection) and CFAR processing of radar echo data. For the needs of intensive signal processing of large data volumes, such as SAR (synthetic aperture radar) imaging systems, some data will still need to be placed in DDR3. DDR3 has a small bandwidth, and the non-sequential reading and writing of data is very slow. Frequent access of the kernel to DDR3 will greatly affect the running efficiency of the program, which often cannot meet the real-time requirements of intensive signal processing of large data volumes.

[0017] In the Chinese invention patent "A multi-core DSP radar signal processing method" (application number: CN202311062116.3, publication number: CN 117193635 A), a multi-core parallel processing method based on the master-slave mode is adopted to distribute all data to cores 2 to 7 of the DSP for calculation. This multi-core parallel processing method can directly process the data in blocks, but it cannot handle the situation where there is no coupling between row data or column data. Therefore, this method is not applicable to all data.

[0018] Furthermore, there are many use cases for intensive signal processing of large amounts of data on the imported 6678DSP and its domestic alternative multi-core DSP. In traditional application cases, the data received by the system through SRIO is generally first stored in DDR3, and then the DSP core reads and writes the data from DDR3 and moves the data to the internal cache for data processing. This processing method is less difficult and the program is more intuitive, but there are the following two problems:

[0019] (1) Slow DDR3 read and write speed: The DSP core accesses DDR3 during operation. The DDR3 bandwidth is small, and the non-sequential reading and writing of data is very slow. Frequent access of the core to DDR3 will greatly affect the running efficiency of the program. Reading and writing DDR3 becomes a bottleneck, which often cannot meet the real-time requirements of intensive signal processing of large amounts of data.

[0020] (2) Traditional processing methods are complex and difficult to implement: Currently, there are two main multi-core DSP parallel processing modes: master-slave mode and data flow mode. The multi-core parallel processing method based on the master-slave mode is not applicable to all data. This method requires that there is no coupling between row data or column data, and the data can be directly processed in blocks. The multi-core parallel processing method based on the data flow mode requires strict segmentation of the algorithm, which is difficult and very difficult to implement in engineering.

[0021] The problem to be solved by the present invention is to improve the computational efficiency of intensive signal processing of large amounts of data and reduce the engineering implementation difficulty of multi-core parallel processing. Summary of the invention

[0022] The present invention proposes a method for processing dense signals of large amounts of data based on a domestic multi-core DSP, the purpose of which is to improve the real-time and universality of dense signal processing of large amounts of data and reduce the difficulty of engineering implementation; the method combines the OpenMP (Open Multi-Processing API for parallel programming) parallel programming program interface to perform parallel processing of data to improve the program running efficiency.

[0023] The present invention is a method for processing large amounts of data based on a domestic multi-core DSP. The method comprises the following steps:

[0024] Step 1. Constructing a data processing external storage space, including: Step (1a) constructing a receiving data buffer in DDR3 to receive data from an external device; Step (1b) constructing a ping data processing buffer and a pong data processing buffer in MSMC to store DDR3 data;

[0025] Step 2. Design a data transmission program, including: Step (2a) designing an EDMA data transfer program to transfer data in the DDR3 receiving data buffer to the ping data processing buffer and the pong data processing buffer in the MSMC; Step (2b) designing an EDMA time consumption test program to record the time consumption of a data transfer from DDR3 to MSMC;

[0026] Step 3. Designing a DSP kernel data processing program, including: step (3a) initializing OpenMP parallel processing; step (3b) establishing a program parallel algorithm model; step (3c) designing an OpenMP data parallel processing module; step (3d) designing a data serial processing module; step (3e) designing a data processing time-consuming test program;

[0027] Step 4. Design the data transmission processing status monitoring module:

[0028] Step 5. Output data processing results: Output data processing results by designing an output data processing result module.

[0029] Further, step (1a) specifically includes: calculating the required external storage space size according to the amount of data received, modifying .cmd and opening up a storage block 1 with a storage capacity greater than or equal to the required storage space size, and creating it in DDR3;

[0030] Step (1b) is specifically as follows: allocate storage block 2 and storage block 3 inside MSMC as ping data processing cache and pong data processing cache, and the space sizes of storage block 2 and storage block 3 are equal, both less than or equal to one half of the storage capacity of MSMC.

[0031] Specifically, step (2a) includes: opening the EDMA channel of core 0, configuring the channel controller core transmission channel number; setting the EDMA transfer source data block to storage block 1, the destination data block to storage block 2 and storage block 3, and the transfer length to the storage capacity of storage block 2 or storage block 3; calling the EDMA data transfer function to transfer data, calling the task delay function during the transfer process, giving up the use of the CPU during the transfer process, and actively giving up the CPU to tasks of the same priority to run; and closing the EDMA transmission channel after the transfer is completed;

[0032] Step (2b) is specifically as follows: recording the number of processor clock cycles through the 64-bit counting registers TSCL and TSCH in the DSP core, measuring the time required for EDMA to transfer from storage block 1 to storage block 2 or storage block 3 during a ping operation or pong operation, and storing the result in the global variable cost_edma; creating data transfer flags a0 and a1, and judging according to the value of cost_edma: when an EDMA data transfer from storage block 1 to storage block 2 is completed, a0=1, a1=0; when an EDMA data transfer from storage block 1 to storage block 3 is completed, a0=0, a1=1.

[0033] Specifically, step (3a) is as follows: creating an OpenMP main thread in DSP core 0, configuring thread execution function parameters, and entering the main thread execution function; setting the number of OpenMP startup cores to 8 cores in the main thread execution function;

[0034] Step (3b) specifically includes: performing theoretical algorithm analysis on the original serial program, or using code analysis tools such as the Profiler tool in the CCS suite to analyze the most core and time-consuming part of the program, establishing a parallel algorithm model for the part and formulating a scheduling strategy for it;

[0035] Step (3c) is as follows: DSP core 0 reads and writes data in storage block 2 or storage block 3, starts to execute the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register, and the computing unit in the kernel fetches data from the general register for processing; when the OpenMP main thread created in DSP core 0 encounters the need for parallel computing during the code execution process, it derives another 7 threads to execute tasks in parallel; during parallel execution, the main thread and the derived threads work together, and after the parallel code execution is completed, the thread resources involved in the operation are safely recovered;

[0036] Step (3d) is as follows: when the parallel domain is completed, the 7 child threads derived from core 1 to core 7 will be terminated or suspended, and the main thread created by core 0 will continue to execute the serial part of the program; similarly, DSP core 0 reads and writes the data in storage block 2 or storage block 3, starts to execute the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register, and the computing unit in the core fetches the data from the general register for processing;

[0037] Step (3e) is specifically as follows: the number of processor clock cycles is recorded through the 64-bit counting registers TSCL and TSCH in the DSP core, the time required for the DSP core to process data once is measured, and the result is stored in the global variable cost_culdata; a data transmission flag b is created, and a judgment is made according to the value of cost_culdata: when the DSP starts to process the data in storage block 2 or storage block 3, the flag b=1; when a DSP core data processing is completed, the flag b=0, indicating that the data processing is completed, and EDMA can carry out the next data transfer to storage block 2 or storage block 3.

[0038] Further, step 4 is specifically as follows: the data transmission flag a0, the data transmission flag a1 and the data processing flag b of each cycle are passed to the data transmission processing status monitoring module; the values ​​of a0, a1 and b are stored in the DSP8 core shared storage area, and each machine cycle polls whether the values ​​of a0, a1 and b have changed; when a0=1, a1=0, it means that the data transmission of storage block 2 has been completed and is waiting for the kernel to process, the data selection flag c=1, and the kernel starts to process the data in storage block 2; when a0=0, a1=1, it means that the data transmission of storage block 3 has been completed and is waiting for the kernel to process, the data selection flag c=0, and the kernel starts to process the data in storage block 3.

[0039] Specifically, step 5 is as follows: after the main thread operation of DSP core 0 is completed, DSP core 0 summarizes the operation results of cores 0 to 7; the dynamic resources involved in the operation are destroyed, and the thread resources are safely recycled.

[0040] The present invention has the following beneficial effects:

[0041] The invention proposes a method for processing dense signals with large amounts of data based on a domestic multi-core DSP, the purpose of which is to improve the real-time performance and versatility of dense signal processing with large amounts of data and reduce the difficulty of engineering implementation; the method combines the OpenMP parallel programming interface to process data in parallel to improve program operation efficiency, and the advantages are as follows:

[0042] 1. In the data transmission part (i.e., in the design of the data transmission program in step 2), the off-chip memory DDR3 in the multi-core DSP is used as the receiving data cache of the SRIO interface to realize the storage of large amounts of data; the off-chip memory MSMC in the multi-core DSP is used as the data processing cache to improve the data processing speed. A ping-pong cache space is opened in the MSMC, and one buffer is used as the data processing cache of the DSP core. At the same time, data is transferred from DDR3 to another buffer through EDMA (Enhanced Direct Memory Access), which can save the time overhead of transferring data when the program is executed in a loop. The data transmission and processing status monitoring module is designed to control the switching of the two ping-pong buffers according to the beat and in coordination with each other to ensure that the data transfer and data processing time of each cycle match. This method can greatly improve the data transmission efficiency.

[0043] 2. Parallel processing part (i.e., step (1c) in designing the OpenMP data parallel processing module): analyze the serial program and find out the most core and time-consuming part of the code, build a parallel algorithm model for it, decompose the algorithm into multiple subtasks executed in parallel, and use the OpenMP parallel programming interface to expand the large-scale intensive signal processing algorithm to cores 0 to 7 for parallel computing. The operation is simple and the time consumption is about one-eighth of that of a single core. It fully utilizes the processing performance of multi-core DSP, greatly improves the real-time performance of large-scale intensive signal processing and reduces the difficulty of engineering implementation.

[0044] 3. Create a ping-pong data processing buffer (i.e., ping data processing cache and pong data processing cache) in the external memory MSMC, create a data receiving buffer in the external memory DDR3, store the received data in the large-capacity DDR3, and move the data to the data processing cache of MSMC in a beat through EDMA. Compared with directly using DDR3 as the data processing buffer, MSMC has a larger bandwidth than DDR3 and a faster data reading and writing speed; compared with directly using MSMC as the data processing buffer, DDR3 has a much larger storage capacity than MSMC and can meet the needs of large data processing. This method can not only ensure the storage needs of dense signals with large data volumes, but also have a fast data reading and writing speed.

[0045] 4. Design and implement a data transmission processing status monitoring module to monitor the status of the data transmission flag and data processing flag of each cycle. According to the changes in their values, it is determined whether the kernel data processing is completed and whether the data transfer from DDR3 to MSMC by EDMA is completed. According to the flags in the module, the two ping-pong buffers are controlled to switch in rhythm and in coordination with each other to ensure that the data transfer and data processing time of each cycle match. This method can greatly improve the data transmission efficiency.

[0046] 5. The OpenMP programming model is adopted, which is based on threads and explicitly guides parallelization through compilation guidance instructions. Compared with the traditional master-slave mode parallel processing method and the data flow mode parallel processing method, the OpenMP programming model is simpler to operate; only the code that needs to be parallelized in the algorithm is expanded in parallel, and other codes are kept in serial execution, which is more flexible to use; it supports programming in multiple languages ​​such as C / C++ and can be used across platforms, and the code compatibility is stronger. The OpenMP programming model is used to realize the processing of dense signals with large amounts of data under multi-core DSP, giving full play to the high performance advantages of multi-core DSP. Compared with single-core operation time, the operation time is shortened to about one eighth, which greatly speeds up the operation speed of large amounts of data;

[0047] 6. Through the EDMA module, data transmission between two memory-mapped slave terminals is realized without the participation of the processor, avoiding the occupation of processor resources and improving the transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly and completely describe the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings used in the technical description.

[0049] Figure 1 A flowchart for realizing intensive signal processing of large amounts of data based on a domestic multi-core DSP provided by an embodiment of the present invention;

[0050] Figure 2 The OpenMP algorithm implementation principle diagram of the present invention;

[0051] Figure 3 A system framework diagram for implementing intensive signal processing of large amounts of data based on a domestic multi-core DSP, provided in accordance with an embodiment of the invention. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0053] Embodiment: A method for processing large amounts of data based on a domestic multi-core DSP, referring to Figure 1 , Figure 2 and Figure 3 , the implementation steps of the present invention are as follows:

[0054] Step 1. Build external storage space for data processing;

[0055] Step (1a) constructing a receive data buffer in DDR3 to receive data from an external device;

[0056] Calculate the required external storage space size based on the amount of data received, modify the .cmd (Linker Command Files) and create a storage block 1 with a storage capacity greater than or equal to the required storage space size, and create it in DDR3 (full name: third-generation double-rate synchronous dynamic random access memory). The specific steps are: 1. Create storage block 1 in MEMORY (memory) in the .cmd file, set the starting address of storage block 1 to be in the user-defined area of ​​DDR3, and set the capacity to be less than or equal to the maximum storage space of the user-defined area in DDR3. 2. Complete the segment mapping of storage block 1 in SECTION (segment) of the .cmd file.

[0057] Step (1b) constructing a ping-pong data processing cache and a pong data processing cache (the two are collectively referred to as a ping-pong processing cache) in the MSMC to store DDR3 data;

[0058] In the MSMC (Multicore Shared Memory Controller), storage blocks 2 and 3 are allocated as ping-pong data processing cache and pong data processing cache. The space size of storage blocks 2 and 3 is equal, and both are less than or equal to half of the storage capacity of MSMC. The specific steps are as follows: 1. Create storage blocks 2 and 3 in MEMORY in the .cmd file, set the starting addresses of storage blocks 2 and 3 in the MSMC external memory, and set the capacity to be less than or equal to half of the maximum storage space of MSMC. 2. Complete the segment mapping of storage blocks 2 and 3 in SECTION of the .cmd file.

[0059] Step 2. Design data transmission program;

[0060] Step (2a) Design an EDMA data transfer program to transfer data in the DDR3 receive data buffer to the ping data processing buffer and pong data processing buffer in the MSMC;

[0061] Open the EDMA (Enhanced Direct Memory Access) channel of core 0 and configure the channel number of the channel controller core. Set the EDMA transfer source data block to storage block 1, the destination data block to storage block 2 and storage block 3, and the transfer length to the storage capacity of storage block 2 and storage block 3. Call the EDMA data transfer function to transfer data, call the task delay function during the transfer process, give up the use of the CPU during the transfer process, and actively give the CPU to tasks of the same priority. Close the EDMA transmission channel after the transfer is completed.

[0062] Step (2b) designing an EDMA time-consuming test program to record the time consumed for transferring data from DDR3 to MSMC;

[0063] The number of processor clock cycles is recorded through the 64-bit counting registers TSCL and TSCH in the DSP core, and the time required for EDMA to transfer from storage block 1 to storage block 2 or storage block 3 during a ping or pong operation is measured, and the result is stored in the global variable cost_edma. Create data transmission flags a0 and a1, and judge according to the value of cost_edma: when an EDMA data transfer from storage block 1 to storage block 2 is completed, a0=1, a1=0; when an EDMA data transfer from storage block 1 to storage block 3 is completed, a0=0, a1=1.

[0064] Step 3. Design DSP core data processing program;

[0065] Step (3a) OpenMP parallel processing initialization;

[0066] Create an OpenMP main thread in DSP core 0, configure the thread execution function parameters, and enter the main thread execution function. Set the number of OpenMP startup cores to 8 in the main thread execution function.

[0067] Step (3b) establishing a program parallel algorithm model;

[0068] Conduct theoretical algorithm analysis on the original serial program, or use code analysis tools such as the Profiler tool in the CCS suite to analyze the most core and time-consuming parts of the program, establish a parallel algorithm model for this part, and formulate a scheduling strategy for it.

[0069] Step (3c) designing an OpenMP data parallel processing module;

[0070] DSP core 0 reads and writes data in storage block 2 or storage block 3, starts executing the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register. The computing unit in the kernel then fetches data from the general register for processing. When the OpenMP main thread created in DSP core 0 encounters the need for parallel computing during code execution, it derives another 7 threads to execute tasks in parallel. During parallel execution, the main thread and the derived threads work together. After the parallel code execution is completed, the thread resources involved in the operation are safely recycled.

[0071] Step (3d) designs a data serial processing module;

[0072] When the parallel domain is completed, the 7 child threads derived from core 1 to core 7 will be terminated or suspended, and the main thread created by core 0 will continue to execute the serial part of the program. Similarly, DSP core 0 reads and writes the data in storage block 2 or storage block 3, starts to execute the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register. The computing unit in the core then fetches data from the general register for processing.

[0073] (3e) Design a test procedure for time-consuming data processing;

[0074] The number of processor clock cycles is recorded through the 64-bit counting registers TSCL and TSCH in the DSP core, and the time required for the DSP core to process data is measured, and the result is stored in the global variable cost_culdata. Create a data transmission flag b, and make a judgment based on the value of cost_culdata: when the DSP starts to process the data in storage block 2 or storage block 3, the flag b=1, and when a DSP core data processing is completed, the flag b=0, indicating that the data processing is completed, and EDMA can carry out the next data transfer to storage block 2 or storage block 3.

[0075] Step 4. Design the data transmission processing status monitoring module:

[0076] The data transmission flag a0, data transmission flag a1, and data processing flag b of each cycle are passed to the data transmission processing status monitoring module. The values ​​of a0, a1, and b are stored in the DSP8 core shared storage area, and the values ​​of a0, a1, and b are polled for changes in each machine cycle. When a0=1 and a1=0, it means that the data transmission of storage block 2 has been completed and is waiting for the kernel to process. The data selection flag c=1, and the kernel starts to process the data in storage block 2; when a0=0 and a1=1, it means that the data transmission of storage block 3 has been completed and is waiting for the kernel to process. The data selection flag c=0, and the kernel starts to process the data in storage block 3.

[0077] Step 5. Output data processing results: Output data processing results by designing an output data processing result module.

[0078] After the main thread operation of DSP core 0 is completed, DSP core 0 summarizes the operation results of cores 0 to 7. The dynamic resources involved in the operation are destroyed, and the thread resources are safely recycled.

[0079] To verify the performance of the method for processing dense signals with large amounts of data described in the present invention. Taking dense signal processing with large amounts of data as an example, the following experimental verification is carried out in DSP. When transmitting large amounts of data, the EDMA module is used to move the float type data in DDR3 to the MSMC ping-pong processing cache. As a time-consuming memory copy function memcpy(), the data in DDR3 is moved to the MSMC ping-pong processing cache by direct copying instructions. The comparison is shown in Table 1:

[0080] Table 1 Comparison of data transfer time

[0081] Data volume memcpy() data transfer time / us EDMA data transfer time / us Speedup 32*32 0.0510 0.0030 17.0000 64*64 0.2033 0.0053 38.3585 128*128 0.8127 0.0125 65.0160 128*256 1.6253 0.0233 69.7554 256*256 3.2510 0.0441 73.7188 512*512 13.0055 0.1691 76.9101

[0082] As shown in Table 1, when the amount of data remains unchanged, the time consumed by EDMA for data transfer is much less than the time consumed by the memory copy function memcpy() for data transfer. Therefore, transferring data from DDR3 to MSMC external memory through EDMA can effectively improve the data transfer rate of intensive signal processing with large amounts of data.

[0083] After completing the data transfer, the DSP core will process the data transferred to the ping-pong data processing cache. Taking the matrix multiplication of float (single-precision floating point) type data as an example, OpenMP is used to perform parallel processing on different core numbers. The comparison with serial processing is shown in Table 2, and the comparison with serial processing speedup is shown in Table 3:

[0084] Table 2 Comparison of the time consumption of matrix multiplication parallel and single-core serial processing

[0085] Data volume (time / ms) Number of cores 16*16 32*32 64*64 128*128 128*256 256*256 512*512 Single core serial execution 0.1231 0.9066 7.0430 101.2665 202.1781 808.6884 6463.8324 OpenMP parallel core number 1 0.1323 0.9145 7.0302 101.2371 202.1852 808.7036 6463.7911 OpenMP parallel core number 2 0.7801 0.4680 3.5366 50.6314 101.0870 404.3481 3231.9031 OpenMP parallel core count 3 0.6310 0.3281 2.4315 34.0266 67.9532 271.6963 2158.7958 OpenMP parallel cores 4 0.4952 0.2431 1.7794 25.3332 50.5493 202.1840 1615.9566 OpenMP parallel core count 5 0.4811 0.2167 1.4443 20.6129 41.1070 164.2502 1300.3270 OpenMP parallel cores 6 0.4220 0.1892 1.2257 17.4201 34.7592 135.8545 1085.7103 OpenMP parallel cores 7 0.4273 0.1601 1.1170 15.0744 30.0240 116.9096 934.2435 OpenMP parallel cores 8 0.3440 0.1329 0.9016 12.6896 25.2951 101.1175 807.9784

[0086] Table 3 Comparison of speedup ratios of matrix multiplication parallel and single-core serial execution

[0087] Data volume and number of cores 16*16 32*32 64*64 128*128 128*256 256*256 512*512 OpenMP parallel core number 1 0.9318 0.9912 1.0000 0.9999 0.9999 1.0000 1.0000 OpenMP parallel core number 2 1.5769 1.9359 1.9918 1.9999 1.9999 1.9999 1.9999 OpenMP parallel core count 3 1.9524 2.7622 2.8972 2.9761 2.9752 2.9763 2.9942 OpenMP parallel cores 4 2.5102 3.7284 3.9590 3.9974 3.9996 3.9997 3.9999 OpenMP parallel cores 5 2.5625 4.1944 4.8774 4.9130 4.9183 4.9234 4.9709 OpenMP parallel cores 6 2.9284 4.7937 5.7494 5.8132 5.8166 5.9525 5.9535 OpenMP parallel cores 7 2.9286 5.6625 6.3053 6.7179 6.7338 6.9170 6.9187 OpenMP parallel cores 8 3.6176 6.8636 7.8169 7.9806 7.9928 7.9973 7.9999

[0088] From Tables 2 and 3, it can be seen that when the calculation scale is constant, as the number of cores increases, the time for OpenMP to process data in parallel decreases, and the speedup ratio compared to single-core serial processing increases. As the calculation data scale increases, the speedup ratio of OpenMP parallel processing gradually increases. Therefore, using OpenMP to perform parallel expansion processing on large data volume operations can effectively improve the real-time performance of large data volume intensive signal processing.

[0089] In summary, the present invention provides a method for processing large amounts of data based on a domestic multi-core DSP. The off-chip memory DDR3 in the multi-core DSP is used as a receiving data cache to store large amounts of data; the off-chip memory MSMC is used as a data processing cache to increase the data processing speed. The use of EDMA for data transfer is efficient and does not require CPU intervention. For algorithms that support parallel expansion, the OpenMP parallel programming program interface is used to expand the large amount of data intensive signal processing algorithm to cores 0 to 7 for parallel computing. The operation is simple, and the computing time is shortened to approximately one-eighth of that of a single core, greatly accelerating the data processing speed of large amounts of data.

[0090] Digital signal processing plays a vital role in modern communications, audio processing, image processing and other fields. DSP is usually used as the core device for real-time signal processing and is widely used in industrial control, communications, aerospace and other fields. In terms of the localization of DSP chips, important progress has been made through the unremitting efforts of Chinese scientific and technological workers. The present invention is based on a domestically produced 6678DSP chip, which is an important representative of the current domestically produced DSP. It has 8 cores, is equipped with a rich underlying library, supports fixed-point, floating-point and multi-core parallel computing, and will become an important chip adopted by Chinese radar manufacturers in the future.

[0091] OpenMP is a compilation guidance instruction and application programming interface designed for writing parallel programs on multi-processors, guiding shared memory and multi-threaded parallelism. It can be used in multiple programming languages ​​such as C / C++ and Fortran, and is widely used on multiple operating systems such as Unix, Linux, and Windows. It is highly flexible, can be used across platforms, and has high code compatibility. OpenMP provides programmers with three programming elements: compilation guidance instructions, API function sets, and environment variables to achieve perfect control of parallelization. By using OpenMP, developers can write parallel programs that can run efficiently on multi-core, multi-processor computers. Therefore, using OpenMP to achieve fast parallel optimization of original serial programs or algorithms on multi-core platforms, especially embedded multi-core DSP platforms, is of great significance in the multi-core era.

Claims

1. A method for processing large amounts of data based on a domestic multi-core DSP, characterized in that: The method comprises the following steps: Step 1. Constructing a data processing external storage space, including: Step (1a) constructing a receiving data buffer in DDR3 to receive data from an external device; Step (1b) constructing a ping data processing buffer and a pong data processing buffer in MSMC to store DDR3 data; Step 2. Design a data transmission program, including: Step (2a) designing an EDMA data transfer program to transfer data in the DDR3 receiving data buffer to the ping data processing buffer and the pong data processing buffer in the MSMC; Step (2b) designing an EDMA time consumption test program to record the time consumption of a data transfer from DDR3 to MSMC; Step 3. Designing a DSP kernel data processing program, including: step (3a) initializing OpenMP parallel processing; step (3b) establishing a program parallel algorithm model; step (3c) designing an OpenMP data parallel processing module; step (3d) designing a data serial processing module; step (3e) designing a data processing time-consuming test program; Step 4. Design the data transmission processing status monitoring module: Step 5. Output data processing results: Output data processing results by designing an output data processing result module.

2. The method for processing large amounts of data based on a domestic multi-core DSP according to claim 1, characterized in that: Step (1a) specifically comprises: calculating the required external storage space size according to the amount of data received, modifying .cmd and opening up a storage block 1 with a storage capacity greater than or equal to the required storage space size, and creating it in DDR3; Step (1b) is specifically as follows: allocate storage block 2 and storage block 3 inside MSMC as ping data processing cache and pong data processing cache, and the space sizes of storage block 2 and storage block 3 are equal, both less than or equal to one half of the storage capacity of MSMC.

3. The method for processing large amounts of data based on a domestic multi-core DSP according to claim 2, characterized in that: Step (2a) is specifically as follows: open the EDMA channel of core 0, configure the channel controller core transmission channel number; set the EDMA transfer source data block to storage block 1, the destination data block to storage block 2 and storage block 3, and the transfer length to the storage capacity of storage block 2 or storage block 3; call the EDMA data transfer function to transfer data, call the task delay function during the transfer process, give up the use of the CPU during the transfer process, and actively give the CPU to tasks of equal priority to run; close the EDMA transmission channel after the transfer is completed; Step (2b) is specifically as follows: the number of processor clock cycles is recorded through the 64-bit counting registers TSCL and TSCH in the DSP core, the time required for EDMA to transfer from storage block 1 to storage block 2 or storage block 3 during a ping operation or a pong operation is measured, and the result is stored in the global variable cost_edma; data transfer flags a0 and a1 are created, and judgment is made according to the value of cost_edma: when an EDMA data transfer from storage block 1 to storage block 2 is completed, a0=1, a1=0; when an EDMA data transfer from storage block 1 to storage block 3 is completed, a0=0, a1=1.

4. The method for processing large amounts of data based on a domestic multi-core DSP according to claim 3 is characterized in that: Step (3a) is as follows: create an OpenMP main thread in DSP core 0, configure thread execution function parameters, and enter the main thread execution function; set the number of OpenMP startup cores to 8 cores in the main thread execution function; Step (3b) specifically includes: performing theoretical algorithm analysis on the original serial program, or using code analysis tools such as the Profiler tool in the CCS suite to analyze the most core and time-consuming part of the program, establishing a parallel algorithm model for the part and formulating a scheduling strategy for it; Step (3c) is as follows: DSP core 0 reads and writes data in storage block 2 or storage block 3, starts to execute the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register, and the computing unit in the kernel fetches data from the general register for processing; when the OpenMP main thread created in DSP core 0 encounters the need for parallel computing during the code execution process, it derives another 7 threads to execute tasks in parallel; during parallel execution, the main thread and the derived threads work together, and after the parallel code execution is completed, the thread resources involved in the operation are safely recovered; Step (3d) is as follows: when the parallel domain is completed, the 7 child threads derived from core 1 to core 7 will be terminated or suspended, and the main thread created by core 0 will continue to execute the serial part of the program; similarly, DSP core 0 reads and writes the data in storage block 2 or storage block 3, starts to execute the serial part of the code, moves the data in storage block 2 or storage block 3 to the cache, and then moves it from the cache to the general register, and the computing unit in the core fetches the data from the general register for processing; Step (3e) is specifically as follows: the number of processor clock cycles is recorded through the 64-bit counting registers TSCL and TSCH in the DSP core, the time required for the DSP core to process data once is measured, and the result is stored in the global variable cost_culdata; a data transmission flag b is created, and a judgment is made according to the value of cost_culdata: when the DSP starts to process the data in storage block 2 or storage block 3, the flag b=1; when a DSP core data processing is completed, the flag b=0, indicating that the data processing is completed, and EDMA can carry out the next data transfer to storage block 2 or storage block 3.

5. The method for processing large amounts of data based on a domestic multi-core DSP according to claim 3, characterized in that: Step 4 is specifically as follows: the data transmission flag a0, the data transmission flag a1 and the data processing flag b of each cycle are passed to the data transmission processing status monitoring module; the values ​​of a0, a1 and b are stored in the DSP8 core shared storage area, and each machine cycle polls the values ​​of a0, a1 and b for changes; when a0=1, a1=0, it indicates that the data transmission of storage block 2 has been completed and is waiting for the kernel to process, the data selection flag c=1, and the kernel starts to process the data in storage block 2; when a0=0, a1=1, it indicates that the data transmission of storage block 3 has been completed and is waiting for the kernel to process, the data selection flag c=0, and the kernel starts to process the data in storage block 3.

6. The method for processing large amounts of data based on a domestic multi-core DSP according to claim 5, characterized in that: Step 5 is specifically as follows: after the main thread operation of DSP core 0 is completed, DSP core 0 summarizes the operation results of cores 0 to 7; the dynamic resources involved in the operation are destroyed, and the thread resources are safely recycled.

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