DRAM access control method, DRAM controller, chip and DRAM access control system

Abstract

The present application discloses a DRAM access control method, a DRAM controller, a chip, and a DRAM access control system, and relates to the field of chip memory technology. The method includes: obtaining a request access row address corresponding to a request access array, and generating a current query pointer according to the request access row address; matching in a preset hash table according to the current query pointer to obtain an entry matching result, the preset hash table is generated by a classification result file determined by a pre-test, and the hash entry of the preset hash table includes: a fault row address and corresponding preset operation information; and executing the current request access operation according to the entry matching result. The present application performs entry matching through a preset hash table, and can execute the current request access operation based on the entry matching result, thereby ensuring the normal use of the request access array with a faulty row, thereby improving the memory resource utilization of DRAM.

Description

Technical Field

[0001] The present application relates to the field of chip memory technology, and in particular to a DRAM access control method, a DRAM controller, a chip, and a DRAM access control system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a volatile memory that can be used as external memory of a System on Chip (SOC). DRAM consists of multiple memory arrays (banks). Before using DRAM, a complete pre-test can be performed on each DRAM to identify the faulty bank in each DRAM and mask the address of the faulty bank to ensure that the DRAM to which the faulty bank belongs is still in normal use.

[0003] However, since there are fewer banks in a DRAM (usually around 8 to 16), and each bank consists of rows and columns, only some rows or columns in a faulty bank may be damaged, that is, the damage range is small. In this case, shielding the faulty bank will reduce the available resources of the DRAM to which the faulty bank belongs, thereby affecting DRAM utilization. Summary of the invention

[0004] The main purpose of the present application is to provide a DRAM access control method, a DRAM controller, a chip and a DRAM access control system, aiming to solve the existing technical problem of low resource utilization of the DRAM to which a faulty bank belongs.

[0005] To achieve the above objectives, the present application proposes a DRAM access control method, the DRAM access control method comprising:

[0006] Obtaining a request access row address corresponding to the request access array, and generating a current query pointer according to the request access row address;

[0007] Matching in a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by a classification result file determined by a pre-test, and a hash entry of the preset hash table includes: a fault row address and corresponding preset operation information;

[0008] The currently requested access operation is performed according to the entry matching result.

[0009] In one embodiment, before the step of matching in a preset hash table according to the current query pointer to obtain an entry matching result, the step further includes:

[0010] Obtaining a classification result file corresponding to each repairable faulty DRAM, wherein the classification result file is generated by a pre-test;

[0011] Determine the fault row address in each of the repairable faulty DRAMs according to the classification result file, and determine the preset operation information corresponding to the fault row address;

[0012] A plurality of hash entries and corresponding index pointers are generated according to the fault row address and the preset operation information, and a preset hash table is determined according to each of the hash entries.

[0013] In one embodiment, the step of performing matching in a preset hash table according to the current query pointer to obtain an entry matching result includes:

[0014] Determine the target hash entry corresponding to the current query pointer in the preset hash table;

[0015] The requested access row address is matched with the fault row address corresponding to the target hash entry to obtain an entry matching result, where the entry matching result is a matching success or a matching failure.

[0016] In one embodiment, the step of matching the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result includes:

[0017] Matching the requested access row address with the fault row address corresponding to the target hash entry;

[0018] When the requested access row address does not match the fault row address corresponding to the target hash entry, updating the current query pointer according to the index pointer in the target entry data;

[0019] Return to the step of determining the target hash entry corresponding to the current query pointer in the preset hash table, until the requested access row address matches the fault row address corresponding to the target hash entry, and determine that the entry matching result is a successful match.

[0020] In one embodiment, after returning to the step of determining the target hash entry corresponding to the current query pointer in the preset hash table, the method further includes:

[0021] When the updated current query pointer is a null pointer, it is determined that the entry matching result is a matching failure.

[0022] In one embodiment, the step of performing the currently requested access operation according to the entry matching result includes:

[0023] When the match is successful, obtaining preset operation information corresponding to the target hash entry, determining a replacement access row address according to the preset operation information, and executing the current access request according to the replacement access row address;

[0024] When the match fails, the current requested access operation is performed according to the requested access row address.

[0025] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM controller, wherein the DRAM controller comprises:

[0026] A request receiving module, used for acquiring a request access row address corresponding to the request access array, and generating a current query pointer according to the request access row address;

[0027] An entry matching module, configured to match a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by the faulty row address determined by the pre-test, and a hash entry of the preset hash table includes the faulty row address and corresponding preset operation information;

[0028] The access control module is used to execute the currently requested access operation according to the entry matching result.

[0029] In addition, to achieve the above-mentioned purpose, the present application also proposes a chip, the chip is externally connected to a plurality of DRAMs, the chip is integrated with a read-only memory and the DRAM controller as described above;

[0030] The read-only memory is used to receive and store a classification result file corresponding to each repairable DRAM in each DRAM when the pre-test of each DRAM is completed;

[0031] The read-only memory is also used to transmit the classification result file corresponding to each of the repairable faulty DRAMs to the DRAM controller.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM access control system, the system comprising: a test device and the chip as described above;

[0033] The testing device is used to perform a pre-test on each of the DRAMs, and determine the repairable faulty DRAMs and the corresponding classification result files according to the test results;

[0034] The testing device is also used to generate an identification QR code based on the repairable faulty DRAM, so that the user can store the classification result file corresponding to the repairable faulty DRAM in the read-only memory according to the identification QR code.

[0035] In one embodiment, the test device is further used to traverse the row space and column space in each of the DRAMs, and determine the faulty DRAM according to the traversal result;

[0036] The testing device is further used to obtain a classification result file corresponding to the faulty DRAM, and determine whether the faulty DRAM meets a preset repairable condition based on the classification result file corresponding to the faulty DRAM;

[0037] The testing device is further used to determine that the faulty DRAM is a repairable faulty DRAM when a preset repairable condition is met.

[0038] The present application discloses a DRAM access control method, including: obtaining a request access row address corresponding to a request access array, and generating a current query pointer according to the request access row address; matching in a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by a classification result file determined by a pre-test, and a hash entry of the preset hash table includes: a fault row address and corresponding preset operation information; and executing the current request access operation according to the entry matching result. The present application generates a current query pointer according to the request access row address corresponding to the request access array, and then performs entry matching in a preset hash table including the fault row address and the corresponding preset operation information based on the current query pointer, thereby executing the current request access operation according to the entry matching result, thereby ensuring the normal use of the request access array with a fault row, and thereby improving the memory resource utilization of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 This is a flow chart of the first embodiment of the DRAM access control method of the present application;

[0042] Figure 2 A schematic diagram of querying a preset hash table in the DRAM access control method of this application;

[0043] Figure 3 This is a flow chart of the second embodiment of the DRAM access control method of the present application;

[0044] Figure 4 This is a schematic diagram of the module structure of the DRAM controller of this application;

[0045] Figure 5 This is a schematic diagram of the module structure of the chip of this application;

[0046] Figure 6 This is a schematic diagram of the operation flow of the DRAM access control system of this application.

[0047] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0049] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0050] The present application embodiment provides a DRAM access control method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the DRAM access control method of the present application.

[0051] In this embodiment, the method includes: steps S10 to S30:

[0052] Step S10: obtaining a request access row address corresponding to the request access array, and generating a current query pointer according to the request access row address.

[0053] It should be noted that the method of this embodiment can be applied in the access control scenario of DRAM, especially in the access control scenario of the faulty bank in DRAM. The execution subject of the method of this embodiment can be a DRAM controller (Dram controller) integrated on the SOC chip. The SOC chip can also be connected to several DRAMs, and the DRAM controller can implement access control to these DRAMs.

[0054] It should be understood that, when receiving an access request from a user, the DRAM controller may determine the DRAM requested to be accessed by the access request, and determine the specific requested access bank and requested access row (or requested access column).

[0055] It is understandable that the DRAM controller may use a hash algorithm to process the bank and row address (row address) of the DRAM requested for access, and generate a hash value to be used as a subsequent query pointer in a preset hash table.

[0056] Step S20: performing a match in a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by a classification result file determined by a previous test, and a hash entry of the preset hash table includes a faulty row address and corresponding preset operation information.

[0057] It should be noted that the preset hash table includes a number of hash entries, each of which includes three fields: a comparison address field, an execution operation field, and an index pointer field.

[0058] Among them, the comparison address field includes the fault row address determined according to the classification result file of the previous test, which is used to match the requested access row address corresponding to the current query pointer; the execution operation field is the preset operation information, including the specific operation corresponding to the pre-set fault row address, which is used to execute when the address matches; the index pointer field is used to find the pointer to the next hash entry when the address does not match.

[0059] In order to specifically explain the generation process of the preset hash table, before step S20, the following steps are also included: Steps S01 to S03:

[0060] Step S01: obtaining a classification result file corresponding to each repairable faulty DRAM, wherein the classification result file is generated by a pre-test.

[0061] It should be noted that the pre-test can be a complete test performed on each DRAM before the SOC chip is mounted. In the pre-test: the storage space corresponding to the row / column address of each bank in each DRAM is tested to determine whether each storage space is damaged, and the row / column address with damage is recorded.

[0062] After performing the pre-test on each DRAM, it can be determined whether there is a faulty bank in each DRAM based on the test results; then, it can be determined whether the faulty bank meets the repairable condition based on the type and / or number of the specific faulty row / column addresses in the faulty bank; if not, the faulty bank is directly shielded; if it is, the DRAM to which the faulty bank belongs is regarded as a repairable DRAM, and the classification result file (sorting result file) corresponding to the repairable DRAM is stored. The sorting result file includes the specific faulty row address corresponding to the faulty bank in the repairable DRAM.

[0063] Step S02: determining the faulty row address in each of the repairable faulty DRAMs according to the classification result file, and determining the preset operation information corresponding to the faulty row address.

[0064] It should be noted that when the SOC chip is being packaged, the sorting result file can be stored in the read-only memory (ROM) of the SOC chip or in an external memory through the serial peripheral interface (SPI). The sorting result file can be stored in a special format and is only allowed to be used by users with SOC chip development permissions, thus ensuring security.

[0065] When the SOC chip is operating, the Dram controller can receive the sorting result file transmitted by the ROM or SPI of the SOC chip and store it in the static random access memory (SRAM) inside the Dram controller. This process can be completed in just 100 microseconds.

[0066] It should also be noted that a correspondence table between each comparison address and preset operation information can be pre-built in the SRAM based on the sorting result file and the expected access mode. The preset operation information can be: remapping the comparison address to another row address, or using the SRAM built into the DRAM controller to store the request data.

[0067] Step S03: Generate a plurality of hash entries and corresponding index pointers according to the faulty row address and the preset operation information, and determine a preset hash table according to each of the hash entries.

[0068] It is understandable that the generated preset hash table may also be stored in the SRAM of the Dramcontroller in the form of a table to facilitate subsequent table lookup.

[0069] It should be noted that this can be combined with Figure 2 The present invention describes the process of matching entries in a preset hash table according to a current query pointer when the SOC chip is operating. Figure 2 A schematic diagram of a query of a preset hash table in the DRAM access control method of the present application.

[0070] exist Figure 2In the process, the specific requested access bank and requested access row address corresponding to the received user's access request are first determined; then the hash algorithm is used to calculate and generate the current query pointer (PTR); finally, the PTR is used as a guide to find the corresponding target hash entry in the preset hash table. The preset hash table includes several hash entries, each of which includes: compare address, execution operation (action) and index pointer (Next ptr).

[0071] By adopting the hash algorithm, it is possible to quickly determine in the preset hash table whether the row address to be accessed is a comparison address (faulty row address) that needs to be processed according to the execution operation based on the generated current query pointer, without masking the faulty bank to which the faulty row address belongs in the DRAM, so that DRAM with a small damage range can also be used normally.

[0072] It should also be noted that the specific address requested by the user can be a more specific column address or an address representing the smallest storage unit (cell) in the bank in addition to the row address corresponding to the bank. Therefore, the compare address in the preset hash table can also be set to the fault column address or the address corresponding to the fault cell.

[0073] Since there are a large number of row / column / cell in a bank, this embodiment uses a hash algorithm to generate pointers to obtain entry matching results in a very short time, and can maintain a large number of different compareaddresses and corresponding actions in a preset hash table, thereby further improving the utilization rate of the faulty bank.

[0074] Step S30: Execute the currently requested access operation according to the entry matching result.

[0075] It should be understood that if there is a target hash entry in the preset hash table that matches the current query pointer, the requested access operation can be performed according to the preset operation information in the target hash entry, such as remapping the requested access row address to another row address and then allowing the current requested access operation to be executed; otherwise, the current requested access operation on the requested access row address can be directly allowed to be executed.

[0076] This embodiment generates a current query pointer according to the request access row address corresponding to the request access array, and then matches entries in a preset hash table including the faulty row address and corresponding preset operation information based on the current query pointer, thereby executing the current request access operation according to the entry matching result, thereby ensuring the normal use of the request access array with the faulty row, and thus improving the memory resource utilization of DRAM.

[0077] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 3 , Figure 3 This is a flow chart of the second embodiment of the DRAM access control method of the present application.

[0078] In this embodiment, in order to specifically illustrate the matching process performed in the preset hash table, step S20 specifically includes: steps S201-S202:

[0079] Step S201: Determine a target hash entry corresponding to the current query pointer in the preset hash table.

[0080] In the specific implementation, the current query pointer (PTR) is used as an index to find the corresponding target hash entry in the preset hash table.

[0081] Step S202: Match the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result, where the entry matching result is a matching success or a matching failure.

[0082] It should be noted that the requested access row address can be matched with the fault row address corresponding to the target hash entry; when the requested access row address does not match the fault row address corresponding to the target hash entry, the current query pointer (PTR) is updated according to the index pointer in the target entry data; return to the step of determining the target hash entry corresponding to the current query pointer in the preset hash table until the requested access row address matches the fault row address corresponding to the target hash entry, and the entry matching result is determined to be a successful match, or, until the updated current query pointer (PTR) is a null pointer (Null), and the entry matching result is determined to be a failed match.

[0083] Specifically, if the compare address in the target hash entry pointed to by PTR matches the requested access row address, it represents a hit. In this case, the entry matching result is considered a successful match.

[0084] If the compare address in the target hash entry pointed to by PTR does not match the requested access row address, the index pointer (Next ptr) in the target hash entry is used as the updated current query pointer; and the updated current query pointer indexes the next hash entry to use the next hash entry as the new target hash entry, and repeats the matching of the compare address with the requested access row address.

[0085] Until the compare address in the new target hash entry matches the requested access line address, it represents a hit. In this case, the entry matching result can also be regarded as a successful match.

[0086] In addition, when the updated current query pointer is a null pointer, that is, when all hash entries in the preset hash table are traversed, there is no compare address in the preset hash table that is consistent with the requested access row address, and there is no hit in the preset hash table. In this case, the entry matching result is a matching failure.

[0087] Accordingly, step S30 specifically includes: steps S301-S302:

[0088] Step S301: when the match is successful, obtain preset operation information corresponding to the target hash entry, determine a replacement access row address according to the preset operation information, and execute the current access request according to the replacement access row address.

[0089] Step S302: when the match fails, executing the current requested access operation according to the requested access row address.

[0090] In a specific implementation, when the match is successful, the user's requested access row address is the faulty row address determined in the pre-test, so that the replacement access row address that needs to be remapped can be determined based on the preset operation information in the matched target hash entry, and then the current requested access operation is allowed to be executed based on the replacement access row address; when the match fails, the user's requested access row address is a normal row address, so that the current requested access operation can be allowed to be executed directly based on the requested access row address.

[0091] In this embodiment, by adopting a hash algorithm, each hash entry can be quickly traversed in a preset hash table according to the current query pointer, so that when the requested access row address is a faulty row address, it can be quickly remapped to a replacement access row address in a very short time to perform the current requested access operation. Since the mapping relationship in this embodiment is at the row address level, compared with the traditional method of shielding the faulty array to ensure DRAM utilization, in this embodiment, conventional request access control can be performed on the normal row addresses in the faulty array, and the faulty row addresses in the faulty array are remapped to the replacement access row addresses for request access control, thereby ensuring the availability of the faulty array and further improving the utilization of DRAM.

[0092] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the DRAM access control method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0093] In addition, the present application also provides a DRAM controller, referring to Figure 4 , Figure 4 This is a schematic diagram of the module structure of the DRAM controller of this application.

[0094] like Figure 4 As shown, the DRAM controller includes: a request receiving module 401 , an entry matching module 402 , and an access control module 403 .

[0095] The request receiving module 401 is used to obtain a request access row address corresponding to the request access array, and generate a current query pointer according to the request access row address;

[0096] The entry matching module 402 is used to match the current query pointer in a preset hash table to obtain an entry matching result, wherein the preset hash table is generated by the fault row address determined by the pre-test, and the hash entry of the preset hash table includes the fault row address and the corresponding preset operation information;

[0097] The access control module 403 is used to execute the current requested access operation according to the entry matching result.

[0098] Furthermore, the entry matching module 402 is also used to obtain a classification result file corresponding to each repairable faulty DRAM, the classification result file being generated by a prior test; determining a faulty row address in each repairable faulty DRAM according to the classification result file, and determining preset operation information corresponding to the faulty row address; generating a number of hash entries and corresponding index pointers according to the faulty row address and the preset operation information, and determining a preset hash table according to each hash entry.

[0099] Furthermore, the entry matching module 402 is also used to determine the target hash entry corresponding to the current query pointer in the preset hash table; match the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result, which is a successful match or a failed match.

[0100] Furthermore, the entry matching module 402 is also used to match the requested access row address with the fault row address corresponding to the target hash entry; when the requested access row address does not match the fault row address corresponding to the target hash entry, update the current query pointer according to the index pointer in the target entry data; return to the operation of determining the target hash entry corresponding to the current query pointer in the preset hash table until the requested access row address matches the fault row address corresponding to the target hash entry, and determine that the entry matching result is a successful match.

[0101] Furthermore, the entry matching module 402 is also used to update the current query pointer according to the index pointer in the target entry data when the requested access row address does not match the fault row address corresponding to the target hash entry; return to the operation of determining the target hash entry corresponding to the current query pointer in the preset hash table until the requested access row address matches the fault row address corresponding to the target hash entry, and determine that the entry matching result is a successful match; or, until the updated current query pointer is a null pointer, determine that the entry matching result is a failed match.

[0102] Furthermore, the access control module 403 is also used to obtain preset operation information corresponding to the target hash entry when the match is successful, determine the replacement access row address according to the preset operation information, and execute the current access request according to the replacement access row address; when the match fails, execute the current requested access operation according to the requested access row address.

[0103] This embodiment generates a current query pointer according to the request access row address corresponding to the request access array, and then matches entries in a preset hash table including the faulty row address and corresponding preset operation information based on the current query pointer, thereby executing the current request access operation according to the entry matching result, thereby ensuring the normal use of the request access array with the faulty row, and thus improving the memory resource utilization of DRAM.

[0104] In addition, the present application also provides a chip, referring to Figure 5 , Figure 5 This is a schematic diagram of the module structure of the chip of this application.

[0105] like Figure 5As shown, the chip is a SOC chip, which is externally connected to a plurality of DRAMs 501, and the chip is integrated with a read-only memory 502 and the DRAM controller 503 as described above;

[0106] The read-only memory 502 is used to receive and store the classification result file corresponding to each repairable DRAM in each DRAM 501 when the pre-test of each DRAM 501 is completed.

[0107] The read-only memory 502 is also used to transmit the classification result file corresponding to each of the repairable faulty DRAMs to the DRAM controller 503 .

[0108] In this embodiment, the sorting result file of the repairable faulty DRAM determined by the pre-test is stored in the read-only memory 502, and the sorting result file can be directly sent to the DRAM controller 503 when the SOC chip is powered on (run time), so that the SOC chip does not need additional time to test and repair the DRAM, saving the time for repairing when the SOC chip is running.

[0109] Other embodiments or specific implementations of the chip described in this application can refer to the above-mentioned method embodiments and will not be repeated here.

[0110] In addition, the present application also provides a DRAM access control system, which includes: a test device and the chip as described above.

[0111] The testing device is used to perform a pre-test on each of the DRAMs 501, and determine the repairable faulty DRAMs and the corresponding classification result files according to the test results.

[0112] It should be noted that the test equipment may be a computing electronic device used to perform pre-tests on each DRAM 501, such as a chip tester, a memory chip test equipment, etc. The test equipment may use a complete test mode to test and classify each DRAM to be manufactured before the SOC chip is manufactured, thereby confirming whether the storage space of each row / column address in each DRAM 501 is damaged.

[0113] Specifically, the test device can first traverse the row space and column space in each DRAM 501, and determine the faulty DRAM according to the traversal result; then obtain the classification result file corresponding to the faulty DRAM, and determine whether the faulty DRAM meets the preset repairable condition based on the classification result file corresponding to the faulty DRAM; finally, when the preset repairable condition is met, determine that the faulty DRAM is a repairable faulty DRAM, thereby realizing a complete test classification process for each DRAM 501.

[0114] The preset repairable condition may be a user-defined setting based on the number or type of faulty row / column addresses existing in each DRAM 501 , and this embodiment does not impose any limitation on this.

[0115] The testing device is further used to generate an identification QR code based on the repairable faulty DRAM, so that the user can store the classification result file corresponding to the repairable faulty DRAM in the read-only memory 502 according to the identification QR code.

[0116] It should be noted that, in the repairable faulty DRAM determined by the preliminary test, in order to facilitate the subsequent printing process, an identification QR code can be generated based on the repairable faulty DRAM and printed on the repairable faulty DRAM, so that the user can store the classification result file corresponding to the repairable faulty DRAM in the above-mentioned read-only memory 502 according to the identification QR code.

[0117] In the present embodiment, the testing device tests each DRAM 501 through a complete test mode, identifies the faulty row / column address therein, and determines the faulty DRAM; then classifies them according to the number or type of specific faulty rows / columns, and determines the repairable faulty DRAM; and then stores the classification result files of these faulty DRAMs into the chip's read-only memory 502, so that the classification result files can be quickly called when the chip is powered on and operated subsequently, further improving the access control efficiency of the DRAM controller 503 in the chip, and ensuring that DRAMs with a small number of defects can also be effectively used.

[0118] In addition, you can also refer to Figure 6 The whole operation process of the DRAM access control system of this application is described. Figure 6 This is a schematic diagram of the operation flow of the DRAM access control system of this application.

[0119] exist Figure 6In the test, the test equipment uses a complete test mode to test each DRAM 501. The test process of a certain DRAM is described as follows: the test equipment traverses the row space and column space in the DRAM, and determines whether there is a damaged storage space therein; if there is no damaged storage space in the DRAM, the DRAM is a normal DRAM; if there is a damaged storage space in the DRAM, the DRAM is classified as a faulty DRAM, and the damaged row address and column address (classification result file) are recorded; then it is further determined whether the damaged row address and column address in the faulty DRAM meet the preset repairable conditions, if not, the faulty DRAM is an unrepairable faulty DRAM, and the unrepairable faulty DRAM is discarded; if it meets, the faulty DRAM is determined to be a repairable faulty DRAM, the classification result file is retained, and an identification QR code is generated and printed on the repairable faulty DRAM.

[0120] When the SOC chip is printed, the user can store the classification result file corresponding to each repairable faulty DRAM into the read-only memory 502 of the SOC chip according to the above identification two-dimensional code.

[0121] When the SOC chip is powered on and running, the read-only memory 502 can transmit the classification result files corresponding to each repairable faulty DRAM to the DRAM controller 503, and the DRAM controller 503 generates a preset hash table according to these classification result files and stores it in the internal SRAM.

[0122] When the DRAM controller 503 receives a user request, it can use a hash algorithm to generate a current query pointer based on the requested access array and the corresponding requested access row address, and use the current query pointer to match entries in a preset hash table, that is, to compare the requested access row address with the comparison address.

[0123] If there is a consistent comparison address, the corresponding preset operation is performed: the requested access row address is remapped to the replacement access row address to perform the current requested access operation; if there is no consistent comparison address, it indicates that the requested access row address is a normal row address, and the current requested access operation can be directly executed without remapping.

[0124] Through the DRAM access control system, the damaged array units can be classified and the classification result files can be stored in the read-only memory 502. When the SOC chip is used normally, the classification result files can be loaded into the SRAM table inside the DRAM controller 503 to generate a preset hash table. Therefore, when there is a user's access request, the hash algorithm can be used to quickly confirm whether the row / column / array unit to be accessed needs to be remapped to other rows / columns / array units in a short time, so that the DRAM with a small damage range can be used normally.

[0125] Other embodiments or specific implementations of the DRAM access control system described in this application can refer to the above-mentioned method embodiments, which will not be repeated here.

[0126] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other elements in the process, method, article or system including the element.

[0127] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0129] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A DRAM access control method, characterized in that: The method comprises: Obtaining a request access row address corresponding to the request access array, and generating a current query pointer according to the request access row address; Matching in a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by a classification result file determined by a pre-test, and a hash entry of the preset hash table includes: a fault row address and corresponding preset operation information; Execute the current requested access operation according to the entry matching result; Before the step of matching in a preset hash table according to the current query pointer to obtain an entry matching result, the step further includes: Obtaining a classification result file corresponding to each repairable faulty DRAM, wherein the classification result file is generated by a pre-test; Determine the fault row address in each of the repairable faulty DRAMs according to the classification result file, and determine the preset operation information corresponding to the fault row address; Generate a plurality of hash entries and corresponding index pointers according to the fault row address and the preset operation information, and determine a preset hash table according to each of the hash entries; The step of performing matching in a preset hash table according to the current query pointer to obtain an entry matching result includes: Determine the target hash entry corresponding to the current query pointer in the preset hash table; Matching the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result, wherein the entry matching result is a matching success or a matching failure; The step of matching the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result includes: Matching the requested access row address with the fault row address corresponding to the target hash entry; When the requested access row address does not match the fault row address corresponding to the target hash entry, updating the current query pointer according to the index pointer corresponding to the target hash entry; Return to the step of determining the target hash entry corresponding to the current query pointer in the preset hash table, until the requested access row address matches the fault row address corresponding to the target hash entry, and determine that the entry matching result is a successful match.

2. The method according to claim 1, characterized in that After returning to the step of determining the target hash entry corresponding to the current query pointer in the preset hash table, the method further includes: When the updated current query pointer is a null pointer, it is determined that the entry matching result is a matching failure.

3. The method according to claim 2, characterized in that The step of executing the currently requested access operation according to the entry matching result comprises: When the match is successful, obtaining preset operation information corresponding to the target hash entry, determining a replacement access row address according to the preset operation information, and executing the current access request according to the replacement access row address; When the match fails, the current requested access operation is performed according to the requested access row address.

4. A DRAM controller, characterized in that: The DRAM controller comprises: A request receiving module, used for acquiring a request access row address corresponding to the request access array, and generating a current query pointer according to the request access row address; An entry matching module, configured to match a preset hash table according to the current query pointer to obtain an entry matching result, wherein the preset hash table is generated by the faulty row address determined by the pre-test, and a hash entry of the preset hash table includes the faulty row address and corresponding preset operation information; An access control module, used to execute the currently requested access operation according to the entry matching result; The entry matching module is further used to obtain a classification result file corresponding to each repairable faulty DRAM, wherein the classification result file is generated by a pre-test; determine a faulty row address in each of the repairable faulty DRAMs according to the classification result file, and determine preset operation information corresponding to the faulty row address; generate a plurality of hash entries and corresponding index pointers according to the faulty row address and the preset operation information, and determine a preset hash table according to each of the hash entries; The entry matching module is further used to determine the target hash entry corresponding to the current query pointer in the preset hash table; match the requested access row address with the fault row address corresponding to the target hash entry to obtain an entry matching result, wherein the entry matching result is a match success or a match failure; The entry matching module is also used to match the requested access row address with the fault row address corresponding to the target hash entry; when the requested access row address does not match the fault row address corresponding to the target hash entry, update the current query pointer according to the index pointer corresponding to the target hash entry; return to the operation of determining the target hash entry corresponding to the current query pointer in the preset hash table until the requested access row address matches the fault row address corresponding to the target hash entry, and determine that the entry matching result is a successful match.

5. A chip, characterized in that: The chip is externally connected to a plurality of DRAMs, and the chip is integrated with a read-only memory and a DRAM controller as claimed in claim 4; The read-only memory is used to receive and store a classification result file corresponding to each repairable faulty DRAM in each of the DRAMs when the pre-test of each of the DRAMs is completed; The read-only memory is also used to transmit the classification result file corresponding to each of the repairable faulty DRAMs to the DRAM controller.

6. A DRAM access control system, characterized in that: The system comprises: a test device and the chip as claimed in claim 5; The testing device is used to perform a pre-test on each of the DRAMs, and determine the repairable faulty DRAMs and the corresponding classification result files according to the test results; The testing device is also used to generate an identification QR code based on the repairable faulty DRAM, so that the user can store the classification result file corresponding to the repairable faulty DRAM in the read-only memory according to the identification QR code.

7. The system according to claim 6, characterized in that The testing device is further used to traverse the row space and column space in each of the DRAMs, and determine the faulty DRAM according to the traversal result; The testing device is further used to obtain a classification result file corresponding to the faulty DRAM, and determine whether the faulty DRAM meets a preset repairable condition based on the classification result file corresponding to the faulty DRAM; The testing device is further used to determine that the faulty DRAM is a repairable faulty DRAM when a preset repairable condition is met.

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