Method for training power model for estimating power consumption of chip and computing equipment

Abstract

The invention discloses a method and a computing device for training a power model for estimating power consumption of a chip, wherein the computing device collects a plurality of data samples. Each data sample represents a signal activity of a plurality of signals of the chip. The computing device selects a portion of the plurality of signals as a proxy. The agents are related to the actual power consumption of the chip according to a standard. The computing device trains a power model using signal activity of the plurality of signals as an input and actual power consumption as an output. The computing device fine-tunes the coefficients of the proxy in the power model. The fine tuning adjusts the estimation error between the estimated power consumption output by the power model and the actual power consumption.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 513,902, filed on July 17, 2023. The contents of that application are hereby incorporated by reference. Technical Field

[0003] The present invention relates to power modeling and estimation of an integrated circuit, and in particular to a technology for using machine learning to accelerate data collection and training processes to establish an on-chip or off-chip power model. Background Art

[0004] In chip design, various techniques and technologies have been used for power modeling and estimation. These methods aim to predict the power consumption of a chip based on its design and activities, allowing designers to optimize power efficiency and provide reliable operation within power constraints.

[0005] A common approach to power modeling is to use simulation-based methods. These methods involve simulating the chip design at different levels of abstraction, such as register transfer level (RTL) or gate level, and estimating the power consumption based on the switching activity of circuit elements. However, simulation-based methods are time-consuming and computationally expensive, especially for large and complex chip designs. The process of generating power reports using tools like PrimeTime PX (PTPX) can take hours, even for small time intervals, making it impractical to perform comprehensive power analysis. Summary of the invention

[0006] The following content provides a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all possible aspects, and is intended to neither identify the key or core elements of all aspects nor delimit the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a computing device. The computing device collects a plurality of data samples. Each data sample represents the signal activity of a plurality of signals of a chip. The computing device selects a portion of the signals from the plurality of signals as agents. The agents are related to the actual power consumption of the chip according to a criterion. The computing device uses the signal activity of the plurality of signals as input and the actual power consumption as output to train a power model. The computing device fine-tunes the coefficients of the agents in the power model. This fine-tuning adjusts the estimated error between the estimated power consumption output by the power model and the actual power consumption.

[0008] To accomplish the above and related ends, one or more aspects comprise the features fully described and particularly pointed out in the claims. The following description and drawings set forth in detail certain illustrative features of one or more aspects. However, these features illustrate only a few of the several ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention may be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:

[0010] Figure 1 is a schematic diagram showing the schematic diagram of on-chip or off-chip power model establishment.

[0011] Figure 2 is a schematic diagram showing the framework for generating chip power reports.

[0012] Figure 3 is a schematic diagram showing the proposed power model framework.

[0013] FIG4(A) is a flow chart illustrating the process of creating an orthogonal minimum dataset for training a power model.

[0014] FIG4(B) is a schematic diagram showing an orthogonal minimum data set.

[0015] Figure 5 is a schematic diagram showing the process of creating another orthogonal minimum dataset for training the power model.

[0016] Figure 6 is a flow chart showing the process of implementing similarity filtering to preprocess the power model training data.

[0017] Figure 7(A) shows the power consumption pattern in the dataset before similarity filtering.

[0018] Figure 7(B) shows the power consumption pattern in the dataset after similarity filtering.

[0019] Figure 8 Several agent layouts demonstrating a bottom-up strategy for agent selection are shown.

[0020] Fig. 9 is a schematic diagram showing the process of agent selection using the PICASSO library.

[0021] FIG10(A) is a schematic diagram illustrating the first type of process of agent selection and fine-tuning.

[0022] Figure 10(B) illustrates the second type of process of agent selection and fine-tuning.

[0023] FIG11(A) is a schematic diagram illustrating the first type of process for agent selection and coefficient fine-tuning using the regularized path method.

[0024] Figure 11(B) shows the second type of process for agent selection and coefficient fine-tuning using the regularized path method.

[0025] Fig.12 is a flow chart showing a process (method) of quantizing a power model to reduce the hardware cost of implementing the power model on a chip.

[0026] Fig.13 is a schematic diagram showing an example of a hardware implementation of an apparatus employing a processing system. DETAILED DESCRIPTION

[0027] The following description is intended to illustrate the general principles of the invention and is not to be construed in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

[0028] Several aspects of telecommunication systems will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or a combination of both. Whether these elements are implemented as hardware or software depends on the specific application and design constraints imposed on the overall system.

[0029] For example, an element, any portion of an element, or any combination of elements may be implemented as a "processing system" that includes one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SoC), baseband processors, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this document. One or more processors in a processing system may execute software. Software should be broadly understood to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0030] Thus, in one or more example aspects, the described functionality may be implemented in hardware, software, or a combination of the two. If implemented in software, the function may be stored or encoded as a computer-readable medium on one or more instructions or codes. Computer-readable media include computer storage media. The storage medium may be any available medium that a computer can access. For example, and not limited to, such a computer-readable medium may include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, a combination of the above types of computer-readable media, or any other medium that can be used to store instructions or data structures in the form of computer executable code, which can be accessed by a computer.

[0031] Figure 1 1 is a schematic diagram 100 showing a schematic diagram of on-chip or off-chip power model building. Chip 110 includes multiple internal circuit components that consume power when operating. The power consumption of chip 110 varies with the workload executed by chip 110. The on-chip power of chip 110 is measured to generate signals 120-1, 120-2, ... 120-n, which reflect the power consumption of different components within chip 110. Signals 120-1, 120-2, ... 120-n are input into power model 150 to build the power model.

[0032] Power model 150 may estimate power consumption of chip 110 based on signals 120-1, 120-2, ... 120-n. Signals 120-1, 120-2, ... 120-n may represent activity of a subset of signals within chip 110. Signals 120-1, 120-2, ... 120-n are selected to reduce hardware overhead of power model 150. Signal activity may include T 0 、T 1 and TC signal, where T 0 Represents the duration of the signal at a low voltage level, T 1 represents the duration that a signal is at a high voltage level, while TC stands for the number of switching times of the signal. More specifically, the switching time (TC) refers to the number of times a signal switches between a low voltage level and a high voltage level, or vice versa. In other words, it represents the number of transitions a signal makes between its two states.

[0033] The power model 150 may be implemented in software and executed on a computer, or may be implemented in hardware and integrated into the chip 110. The power model 150 may be used to monitor the power consumption of the chip 110 at runtime, or may be used to estimate the power consumption of the chip 110 at design time.

[0034] The power model 150 may be trained using a machine learning algorithm. A plurality of data samples are collected to train the power model 150. Each data sample includes the value of the signal 120-1, 120-2, ... 120-n, and the corresponding power consumption of the chip 110.

[0035] The training configuration of the power model 150 may include two stages. In the first stage, a portion of the signals are selected as proxies. The proxies are the signals that are most relevant to the power consumption of the chip 110. In the second stage, the coefficients of the proxies are fine-tuned to accurately predict the dynamic power consumption of the chip 110.

[0036] The dynamic power consumption of chip 110 can be expressed as a function of signal activity and the coefficient of the agent, which can be expressed using the following equation:

[0037] Dynamic power=F(Signal_Activity; θ)

[0038] Where θ represents the coefficients of the agent, which are learned by the AI ​​algorithm.

[0039] The power model 150 may be used to accelerate the power estimation process, reduce the hardware cost of on-chip power meters, and enable energy efficiency optimization techniques such as dynamic voltage and frequency scaling (DVFS).

[0040] Figure 2 2 is a schematic diagram 200 showing a framework for generating a chip power report. In the first framework, a register transfer level (RTL) description 210 of a chip design, along with design constraints 212 (such as clock rate), is input into a front-end tool 222, which includes a synthesizer. The front-end tool 222 also takes a cell library 214 as input. The RTL description 210 may be written in a hardware description language such as VHDL.

[0041] The front-end tool 222 performs RTL simulation and synthesis to generate a pre-layout netlist 230. The pre-layout netlist 230 is an idealized representation of the design and does not include a clock tree. The pre-layout netlist 230, along with the design rules 232 and the cell library 234, is then input to the back-end tool 242 for gate-level simulation.

[0042] The back-end tool 242 generates a post-layout netlist 244, which is a more realistic representation of actual chip activity, including clock trees, delays, and glitches. The post-layout netlist 244 is then input to a power analysis tool 260, which performs cycle-by-cycle power tracing to generate a detailed power report 270.

[0043] Power report 270 contains a cycle-by-cycle power consumption breakdown for a given chip design. For example, power report 270 may include a power trace detailing the exact power consumption for each clock cycle during the analysis time range. Power report 270 may include total power consumption. The report aggregates the cycle-by-cycle data to provide the overall power consumed during the analysis period (e.g., for a specific workload or mode). Power report 270 may contain a breakdown by power domain / component. The report shows the power consumption of different functional blocks or power domains within the chip. Power report 270 may include statistical metrics of power data, such as average power, peak power, and power distribution.

[0044] The process of generating a power report 270 using the power analysis tool 260 can be very time consuming. For example, generating a power trace for only a 1 μ second time interval may take 5.5 hours. This becomes a bottleneck in the power estimation process, especially when multiple modes need to be tested.

[0045] To address this issue, in the second framework, an AI-based power model 150 can be used to replace the time-consuming power analysis step. Figure 2 As shown, the power model 150 takes the pre-layout netlist 230 as input, selects a subset of signals that are most relevant to power consumption, and fine-tunes the coefficients of these signals to estimate power consumption. This can significantly reduce the time required to generate power estimates compared to traditional flows using power analysis tools 260.

[0046] The power model 150 can be implemented on-chip to enable real-time power monitoring and optimization techniques such as dynamic voltage frequency scaling (DVFS). By providing runtime power information, the on-chip power model allows the system to dynamically adjust voltage and frequency based on current power consumption, thereby improving energy efficiency.

[0047] Power models are used to estimate the power consumption of a chip. There are two main types of power models: off-chip power models and on-chip power models. Off-chip power models are used to estimate the power consumption of a chip at design time. On-chip power models are used to monitor the power consumption of a chip at runtime. The process of training a power model for chip design faces several challenges that can affect the efficiency and accuracy of the model. Two key challenges are the time-consuming data collection process and the bottleneck of agent selection time.

[0048] Collecting training data for the power model is a time-consuming process. As previously mentioned, generating accurate power reports using the power analysis tool 260 can take considerable time. For example, using the PrimeTime PX (PTPX) tool for RTL signoff can take 5.5 hours to generate a power trace for a time interval of only 1 μs. This becomes a bottleneck in the data collection process, especially when collecting training data covering the full range of power intervals.

[0049] In order to train the power model 150, data samples including signal activities and their corresponding power consumption values ​​need to be collected. The power consumption values ​​are obtained from the power reports 270 generated by the power analysis tool 260. However, the time required to generate these power reports for multiple modes and time intervals may be too long.

[0050] For example, consider a scenario where you are training a power model for a GPU. The GPU may have different power consumption levels, such as low, medium, and high, depending on the workload. Training data covering the full range of power intervals needs to be collected. This requires running various models on the GPU and generating power reports for each model, which can be time consuming.

[0051] Another challenge in training the power model 150 is the bottleneck of agent selection time. As mentioned earlier, the first step in training the configuration is to select a subset of signals that are most relevant to chip power consumption. These selected signals are called agents.

[0052] However, the process of selecting agents becomes a bottleneck in training time, especially for large chip designs. In practice, a mobile chip may have more than 10 million signals. Selecting the most relevant agents from such a large number of signals is computationally expensive and time-consuming.

[0053] Figure 3 is a schematic diagram showing a proposed power model framework 300. The framework 300 includes two main parts: a data-related component and a power model construction component. The framework aims to reduce the time required for data collection and model training.

[0054] The data related components include a data collection component 314 and a data pre-processing component 316. The raw data signal 312 from the hardware design is input to the data collection component 314. The data collection component 314 uses a minimum data set approach to reduce the number of PTPX (PrimeTime PX) power reports that need to be collected, thereby reducing data collection time. The collected data is then passed to the data pre-processing component 316, which applies a similarity filtering approach to remove highly similar data points. This step not only speeds up training time by reducing the amount of training data, but also enhances the model's ability to learn from diverse data points rather than repeated, similar data.

[0055] The power model construction component includes a proxy selection component 332, a coefficient fine-tuning component 334, and a quantization component 336. The preprocessed data is input to the proxy selection component 332, which uses the PICASSO library to select a subset of signals that are most relevant to power consumption from a large number of signals (e.g., 10 million signals) in the hardware design. The PICASSO library is described in Zhao, T., Liu, H., & Zhang, T. (2017); Pathwise coordinate optimization for sparse learning: Algorithm and theory; arXiv: 1412.7477, 9Feb 2017, which is hereby cited in its entirety. The PICASSO library uses various techniques to accelerate the proxy selection process, which will be discussed in detail later. In addition, the proxy selection component 332 applies a maximized thermal initialization method to further optimize the selection process.

[0056] The selected agents are then passed to the coefficient tuning component 334, which tunes the coefficients of each selected signal to accurately predict dynamic power consumption. The coefficient tuning component 334 also employs a regularized path approach to speed up the tuning process.

[0057] The quantization component 336 quantizes the coefficients, signal activity, and power values ​​of the model into fewer bits to reduce the hardware cost of the on-chip power model 350. Quantization is performed not only on the model coefficients, but also on the input signal activity and output power values.

[0058] 4(A) is a flow chart illustrating a process 400 of creating an orthogonal minimum data set 410 for training a power model 150. FIG4(B) is a diagram illustrating an orthogonal minimum data set 410.

[0059] The data collection component 314 obtains the T values ​​of multiple performance monitoring unit (PMU) signals from the design signal 312. 1 Array 402. T of each PMU signal 1 The array represents the duration that the PMU signal is at a high voltage level. The PMU is a hardware unit that integrates performance counters. A performance counter is a register that counts the number of times a specific event occurs. The events counted by the performance counter can vary from chip to chip. For example, some performance counters may count the number of clock cycles, while other performance counters may count the number of instructions executed. Performance counters can be used to measure the activity of the chip. The activity of the chip is related to the power consumption of the chip. Therefore, the PMU signal can be used to estimate the power consumption of the chip.

[0060] The data collection component 314 collects the T of the plurality of PMU signals.1 The array 402 is subjected to a dimensionality reduction method to obtain a plurality of PMU embeddings 404. The data collection component 314 applies a clustering method to the plurality of PMU embeddings 404 to obtain orthogonal clusters 406. The data collection component 314 applies a sampling rule, such as a sampling rule based on group size, to the orthogonal clusters 406 to obtain an orthogonal minimum data set 410.

[0061] Dimensionality reduction and clustering operations use techniques such as UMAP (Uniform Manifold Approximation and Projection) for dimensionality reduction and DBSCAN (Density-Based Spatial Clustering of Applications with Noise) for clustering. These techniques are applied in sequence, first reducing the dimensionality of the high-dimensional PMU signal to T 1 The array is converted to a lower dimensional space (e.g., 2D) and then clustering is performed to group similar data points based on their distribution in the low dimensional space.

[0062] As shown in FIG4(B), the original data set 422 includes orthogonal clusters 406-1, 406-2, 406-3, etc. The data selected from the original data set 422 form an orthogonal minimum data set 410 and a validation data set 426. The orthogonal minimum data set 410 includes clusters 434-1, 434-2, 434-3, etc. The validation data set 426 includes clusters 436-1, 436-2, 436-3, etc.

[0063] The data collection component 314 can determine the group size of the orthogonal minimum data set 410 and the validation data set 426. For example, if cluster 406-1 accounts for 30% of the original data set 422, and cluster 406-1 needs to be reduced by 50% for the orthogonal minimum data set 410, the data collection component 314 can randomly select 30%*50% of the data points in the original data set 422. These selected data points will be displayed as cluster 434-1.

[0064] The orthogonal minimum data set 410 may be used to train the power model 150. The orthogonal minimum data set 410 is smaller than the original data set 422. This may reduce the time required to train the power model 150.

[0065] This process uses the PMU signal T 1 Array 402 clusters the data and then samples according to the group size of each cluster to create an orthogonal minimum data set 410. The orthogonal minimum data set 410 is diverse and covers the entire power range. In some cases, this process can reduce the collection requirements of up to 93% of the data points.

[0066] Figure 55 is a diagram 500 illustrating another process for creating an orthogonal minimum data set 410 for training a power model 150. This process includes performing similarity filtering 508 on the orthogonal clusters 406 to remove highly similar data points within each cluster, further increasing the diversity of the minimum data set.

[0067] The data collection component 314 obtains the T of the PMU signal 1 Array 402. Data collection component 314 performs T 1 The array 402 is subjected to a dimensionality reduction method to obtain a plurality of PMU embeddings 404. Then, the data collection component 314 applies a clustering method to the plurality of PMU embeddings 404 to obtain orthogonal clusters 406. Furthermore, the data collection component 314 applies a sampling rule to the orthogonal clusters 406 to obtain sampled data points.

[0068] The data collection component 314 then performs similarity filtering 508 on the orthogonal clusters 406. The data collection component 314 calculates the similarity between each pair of sampled data points within each cluster 406. For each pair of sampled data points, the data collection component 314 calculates the T of the PMU signal of each sampled data point. 1 The arrays are concatenated into a 1D array. Then, the data collection component 314 calculates the similarity between the two 1D arrays. If the similarity between the two 1D arrays is higher than a threshold, the data collection component 314 removes one of the two sampled data points.

[0069] The combination of the minimum dataset approach and similarity filtering results in a smaller and more diverse dataset for training the power model 150. This reduces training time and improves the generalization ability of the model by preventing it from being biased towards highly similar data points.

[0070] The data within each cluster is more orthogonal, meaning the data points within each cluster are more independent of each other. This can further improve the performance of the model by reducing the correlation between the input features.

[0071] Figure 6 6 is a flow chart 600 illustrating a procedure for implementing similarity filtering to pre-process training data for the power model 150. The procedure is intended to filter out highly similar data points to enhance the generalization ability of the model and speed up the training process.

[0072] In operation 602, the data pre-processing component 316 obtains arrays of all signals from the collected data. Each signal array represents the activity of a signal in the hardware design.

[0073] In operation 604, the data preprocessing component 316 calculates the similarity between each pair of data points. For each pair of data points, the corresponding signal scalars are concatenated into a 1D array. The similarity between the two 1D arrays is then calculated. The similarity measure can be based on various metrics, such as cosine similarity or Euclidean distance.

[0074] In operation 606, the data preprocessing component 316 checks whether the similarity between the two 1D arrays exceeds a predefined threshold. If the similarity is greater than the threshold, one of the two data points is randomly removed. Therefore, highly similar data points are filtered out, reducing redundancy in the training data.

[0075] In operation 608, the data preprocessing component 316 obtains filtered data without highly similar data points. The filtered data is more diverse and contains less redundancy, which can improve the efficiency and effectiveness of the power model 150 training process.

[0076] 7(A) and 7(B) are graphs illustrating the effect of similarity filtering on the training and test datasets, respectively. These graphs show the power consumption patterns before and after applying similarity filtering.

[0077] FIG7(A) shows the power consumption patterns in the dataset before similarity filtering. The horizontal axis represents the data points and the vertical axis represents the power consumption (in Watts). Sections 722-1, 722-2, ..., 722-M represent different patterns in the training dataset. Each pattern corresponds to a specific workload or activity performed by the chip.

[0078] Before similarity filtering, the power consumption pattern contains many flat areas, indicating that the data points are highly similar. These flat areas may bias the learning process of the power model, resulting in overfitting and poor generalization ability.

[0079] FIG7(B) shows the power consumption patterns in the dataset after similarity filtering. Similar to FIG7(A), the horizontal axis represents data points and the vertical axis represents power consumption in watts. Segments 732-1, 732-2, ..., 732-K represent different patterns in the test dataset.

[0080] After applying similarity filtering, the flat areas are reduced, resulting in more diverse and independent data points in the test dataset. This improves the performance of the power model on unseen data, thereby improving accuracy and robustness.

[0081] The following table quantifies the similarity filtering process:

[0082] Table 1 The impact of similarity filtering on training data

[0083]

[0084] Table 1 shows that when the similarity threshold is 0.99, the number of original SAIF (Switching Activity Interchange Format) files is reduced from 4597 to 617, which significantly reduces the size of the training data. The similarity filtering process only takes 4 minutes, demonstrating its efficiency.

[0085] By implementing similarity filtering, the training time of the power model was sped up by 26.3 times in some cases. This significant reduction in training time was possible without compromising the accuracy of the model. In fact, removing highly similar data points enhanced the generalization ability of the power model, resulting in better performance on both the training and test datasets.

[0086] Figure 6 The similarity filtering process described in and illustrated in Figures 7(A) and 7(B) addresses the challenge of redundant and highly similar data points in the training dataset. By filtering out these data points, the power model training process becomes more efficient and effective.

[0087] The filtered data is more diverse and contains less redundancy, which prevents the power model from being biased towards duplicate data points. This enhances the model’s ability to generalize to unseen data, improving its accuracy and robustness.

[0088] The similarity filtering process can be implemented in the data preprocessing component 316 of the proposed power model framework 302. The similarity filtering process works in conjunction with other components (such as the data collection component 314 and the power model construction component) to reduce the time required for data collection and model training.

[0089] Figure 8 A plurality of proxy placements 810, 820, 830, 840 are shown, showing the bottom-up strategy employed by the proxy selection component 332 for proxy selection. The proxy selection algorithm faces challenges in memory usage and speed when selecting agents from large-scale designs for mobile chips, which may contain more than 10 million signals. The bottom-up strategy enables the proxy selection component 332 to process all of these large-scale designs in a single on-chip power model (OPM) while reducing memory usage and execution time.

[0090] The bottom-up approach selects agents sequentially and propagates the selection to the next level until the entire design is processed. Agent layout 810 shows the initial stage of the bottom-up strategy. The design hierarchy is represented by nested rectangles, with the outermost rectangle corresponding to the top-level module. Each level in the hierarchy contains a set of signals, and deeper levels represent smaller modules with fewer signals.

[0091] The agent selection component 332 starts the agent selection process at the deepest level of the hierarchy and works its way up layer by layer. In agent placement 810, the agent selection component 332 first selects agents from Group 1 and Group 2, which are the deepest modules. Each agent group contains a subset of signals that are most relevant to power consumption at its corresponding level of the hierarchy. These selected agents are then combined with all signals in the next layer (Group 3).

[0092] The agent selection component 332 starts the agent selection process at the deepest level of the hierarchy and works upwards layer by layer. In agent placement 810, the agent selection component 332 first selects agents from Group 1 and Group 2, which are the deepest modules. Each agent group contains a subset of signals that are most relevant to power consumption at its corresponding hierarchical level. These selected agents are then combined with all signals at the next level (Group 3) for another round of agent selection, as shown in agent placement 820.

[0093] After this round of selection, the agent selection component 332 obtains selected agents for Group 2, Group 1, and Group 3. These selected agents are then combined with the signals of the surrounding hierarchy to form Group 4, as shown in agent layout 830. This process continues iteratively until the entire design is processed and the final set of agents is selected, as shown in agent layout 840.

[0094] Agent placement 840 represents the final stage of the bottom-up strategy. In this placement, all previously selected agents are combined into a single group, agent group 5. Agent selection component 332 selects the final set of agents from this group. This final set of agents represents the most relevant signals for estimating the power consumption of the entire design.

[0095] Therefore, the agent selection component 332 does not need to process all signals in the design at the same time. Instead, it only needs to consider selected agents from lower level groups and signals from the level currently being processed. This approach significantly reduces memory usage and speeds up the agent selection process because the agent selection component 332 can work with a smaller subset of signals at each iteration.

[0096] Fig. 9 FIG900 is a diagram showing a procedure for agent selection using the PICASSO library. The PICASSO library uses a path coordinate optimization algorithm to reduce agent selection time. The procedure includes an outer loop 950, a middle loop 956, and an inner loop 960.

[0097] In operation 912, the agent selection component 332 initializes a regularization parameter λ. The regularization parameter λ is used to control the sparsity of the solution. A larger value of λ encourages sparser solutions, meaning fewer agents are selected.

[0098] Middle loop 956 includes operations 914, 916, and 918. In operation 914, the proxy selection component 332 applies a strong rule to preselect coordinates. The strong rule includes calculating the gradient of each coordinate and comparing it to a threshold. If the absolute value of the gradient is greater than the threshold, the coordinate is included in the active set; otherwise, it is excluded from the active set. The active set includes the coordinates that are most likely to be related to the predicted power consumption. The inactive set includes the coordinates that are less likely to be related to the predicted power consumption.

[0099] The inner loop 960 includes operation 916. In operation 916, the agent selection component 332 performs active coordinate minimization on the active set. Active coordinate minimization is a technique that iteratively updates the coordinate values ​​in the active set until the objective function is minimized.

[0100] In operation 918, the agent selection component 332 updates the active set. The active set is updated by adding coordinates in the inactive set with large absolute gradient values. Thus, the active set contains the coordinates that are most likely to be related to the predicted power consumption.

[0101] The middle loop 956 (operations 914, 916, and 918) repeats until a convergence criterion is met. The convergence criterion may be based on a change in the value of the objective function or a change in the active set. Once the convergence criterion is met, an output solution 920 is obtained.

[0102] The outer loop 950 includes operations 920 and 922. In operation 920, the agent selection component 332 outputs a solution.

[0103] In operation 922, the agent selection component 332 performs a warm start initialization, where the agent selection component 332 uses the solution of the previous iteration as the starting point for the current iteration. This helps to speed up the convergence of the algorithm because the algorithm does not need to start from scratch at each iteration. The agent selection component 332 initializes a new regularization parameter λ. For example, the agent selection component 332 may decrease the regularization parameter λ to encourage more agents to be selected.

[0104] The outer loop 950 (operations 920 and 922) repeats until all regularization parameters are processed. Once all regularization parameters are processed, the agent selection component 332 selects a set of agents for the power model 150.

[0105] The PICASSO algorithm starts with a large regularization parameter to suppress over-selection of irrelevant coordinates. Gradually, the PICASSO algorithm recovers relevant coordinates to obtain a sparse output solution with optimal statistical properties in parameter estimation and support recovery.

[0106] The PICASSO library includes the following features: active coordinate minimization, strong rules, active set updates, and warm-start initialization.

[0107] Active coordinate minimization involves performing coordinate minimization only on the coordinates in the active set. This eliminates the need to compute the gradient vectors for all coordinates.

[0108] Strong rules are used to preselect coordinates for the active set. This involves calculating the gradient of each coordinate and comparing it to a threshold. If the absolute value of the gradient of a coordinate is greater than the threshold, the coordinate is included in the active set; otherwise, it is included in the inactive set.

[0109] Active set updating involves adding the coordinate with the maximum absolute gradient value to the active set at each iteration.

[0110] Warm start initialization involves using the solution of the previous stage as the initialization for the current stage. This speeds up the convergence of the algorithm.

[0111] Figure 10(A) is a diagram illustrating the process of the first type of agent selection and fine-tuning. The process involves multiple rounds of training, each of which consists of two stages: the first stage (agent selection) and the second stage (fine-tuning).

[0112] In the first round, all signals 1012 are fed into the outer loop 950 (initial one) of the first stage 1021 from the beginning. This outer loop 950 is the bottleneck of the training time because it does not have any previous results to use. After the initial outer loop 950, subsequent outer loops are performed. The selected agents and their coefficients are then passed to the second stage 1031 for fine-tuning operation 1032. The output of the first round is a set of agents and their corresponding coefficients.

[0113] In the second round, the process starts over again using the initial outer loop 950 of the first stage 1023, followed by subsequent outer loops and fine-tuning of the second stage 1033. The output of the second round is another set of surrogates and coefficients.

[0114] Likewise, the third round begins with an initial outer loop 950 of the first stage 1025, followed by subsequent outer loops and fine-tuning of the second stage 1035. The output of the third round is another set of agents and coefficients.

[0115] In this process, each epoch starts with an initial outer loop, which is time-consuming and causes multiple bottlenecks throughout the training process.

[0116] In each round, the first stage 1021, 1023, 1025 selects an agent from the input signal using the PICASSO library. The initial outer loop 950 is the bottleneck of training time when there are no results from the previous round. Subsequent outer loops in the same round are faster because they are based on the results of the previous round. The second stage (1031, 1033, 1035) then fine-tunes the coefficients of the selected agent.

[0117] Figure 10(B) illustrates the second type of agent selection and fine-tuning process. This process utilizes a maximal warm-start initialization approach that aims to reduce the number of bottlenecks by minimizing the number of occurrences of the initial outer loop.

[0118] In the first pass, all signals 1052 are fed into the initial outer loop 950 of the first stage 1061. The results of this initial outer loop are stored in a file 1082. A fine-tuning operation 1072 is applied to the surrogates and coefficients in the second stage 1071, and the output is a set of surrogates and coefficients.

[0119] For the second pass, the initial outer loop 950 of the first stage 1063 is initialized using the stored results of the initial outer loop of the first pass (in file 1082). This reduces the time required for the outer loop because it uses the previous results. The results are stored in file 1084. The fine-tuning operation 1074 is applied to the agents and coefficients in the second stage 1073.

[0120] Likewise, the third pass uses the results of the second pass stored in file 1084 to initialize the outer loop 950 of the first stage 1065. The results are stored in file 1086 and the agents and coefficients are fine-tuned in the second stage 1075.

[0121] By storing and reusing the results of the previous initial outer loop, the second type of process reduces the number of bottlenecks to only one, significantly speeding up the training process. This approach achieves a 5.01x speedup with only a slight drop in accuracy.

[0122] The outer loop 950 in the first stage 1061, 1062, 1063 of the disclosed invention uses a path coordinate optimization algorithm, in particular the PICASSO library, to select agents for power model training.

[0123] More specifically, the initial outer loop 950 in the first stage 1061 is executed only once at the beginning of the training process. It starts with a large regularization parameter λ and an empty active set. In particular, a strong rule is applied to preselect the coordinates of the active set. In operation 916, active coordinate minimization is performed, which is iteratively performed on the coordinates in the active set. In operation 918, an active set update is performed by adding coordinates with large absolute gradient values ​​from the inactive set to the active set. The intermediate loop 956 (strong rule, active coordinate minimization and active set update) iterates until a convergence criterion is met. This criterion can be based on the change in the objective function value or the change in the active set. Once the intermediate loop 956 converges, the output solution of operation 920, containing information used for fine-tuning, such as the selected agents and their coefficients, etc., is stored in file 1082.

[0124] Subsequent outer loops 950 in the first phase 1063 and 1065 use a warm start initialization technique to speed up the agent selection process. Instead of starting from scratch, these outer loops use the output solution of the previous outer loop as initialization. In particular, the output solution from the previous outer loop (stored in files 1082, 1084) is loaded and used as the initial solution for the current outer loop. The regularization parameter λ is also updated, typically reduced, to encourage the selection of more agents. Strong rules are applied again to pre-select coordinates, but this time starting from the pre-filled active set from the previous iteration. Similar to the outer loop in the first phase 1061, the minimization of active coordinates in operation 916 and the updating of the active set in operation 918 are performed. The intermediate loop 956 continues until convergence is reached according to the defined criteria. The updated solution 920, containing the selected agents and their coefficients, is stored in files (1084, 1086).

[0125] 11(A) is a diagram illustrating a first type of process for agent selection and coefficient tuning using the regularized path method. The first type of process involves running multiple rounds to obtain the power model 150. Each round includes a first stage for agent selection and a second stage for coefficient tuning.

[0126] In the first round, all signals 1112 are input to the first stage 1121 for agent selection, using a regularization parameter λ = 1. The selected agents and their coefficients are then passed to the second stage 1131 for fine-tuning. The output of the first round is a set of agents and their corresponding coefficients.

[0127] In the second round, the process starts over, with the first stage 1123 performing agent selection, but this time using a slightly reduced regularization parameter λ = 0.95. The selected agents and coefficients are then passed to the second stage 1133 for fine-tuning. The output of the second round is another set of agents and coefficients.

[0128] Likewise, the third round begins with agent selection in the first stage 1125, using a further reduced regularization parameter λ=0.9025, followed by fine-tuning in the second stage 1135. The output of the third round is another set of agents and coefficients.

[0129] In this process, each round starts with an agent selection phase, which is time-consuming and causes multiple bottlenecks throughout the training process.

[0130] Figure 11(B) shows the second type of process using the regularized path method for agent selection and coefficient fine-tuning. This process aims to minimize the number of agent selection iterations in the first stage by utilizing the regularized path and iteratively fine-tuning the coefficients in the second stage.

[0131] In the first round, all signals 1152 are input to the first stage 1161 for agent selection, using a regularization parameter λ=1. The selected agents and their coefficients are then passed to the second stage 1171 for iterative fine-tuning. In the second stage 1171, the coefficients are fine-tuned in multiple sub-rounds (e.g., round 1-1, round 1-2, ...) using a series of decreasing coefficient scaling parameter α values ​​(e.g., 1, 0.99, ..., 0.001). The output of each sub-round is a set of agents and their corresponding fine-tuning coefficients, for each α value.

[0132] For the second round, the process starts with agent selection from the first stage 1163, but uses a significantly reduced regularization parameter λ = 0.66. This is possible because the coefficients have already been fine-tuned in the second stage 1171 of the first round. The selected agents and coefficients are then passed to the second stage 1173 for another round of iterative fine-tuning, using the same sequence of decreasing α values.

[0133] In some cases, by leveraging regularization paths and iteratively fine-tuning coefficients in the second stage, the second type of process reduces the number of first-stage agent selection iterations, potentially achieving a 2.32x speedup with only a slight drop in accuracy compared to the first type of process.

[0134] The regularized path method solves the bottleneck problem in the agent selection and coefficient fine-tuning process. Compared with the second stage coefficient fine-tuning, the first stage agent selection is more time-consuming. Therefore, reducing the number of first stage iterations can significantly speed up the entire training process.

[0135] The first type of process, as shown in Figure 11(A), performs agent selection in each round and gradually reduces the regularization parameter. However, this method still requires multiple first-stage iterations, resulting in a bottleneck in the entire training process.

[0136] The second type of process, shown in Figure 11(B), uses a regularization path and iterative fine-tuning in the second stage to minimize the number of first-stage iterations. By using a series of decreasing α values ​​for extensive coefficient fine-tuning in the second stage, this process allows for more aggressive reductions in the regularization parameter λ in the first-stage agent selection in subsequent rounds. This approach effectively reduces the number of first-stage iterations, resulting in a significant speedup of the overall training process.

[0137] The regularization parameter λ controls the sparsity of solutions during the agent selection process (first stage). Higher λ enforces sparser solutions, resulting in fewer agents being selected. λ determines the tradeoff between model complexity and accuracy. Larger λ prioritizes a simpler model with fewer agents (less hardware overhead), but may come at the expense of slightly reduced accuracy. Smaller λ allows for a more complex model with more agents, potentially achieving higher accuracy, but with increased hardware overhead.

[0138] α in the second stage (Figure 11(B)) is a scaling factor of a penalty term that limits the number of agents. Higher values ​​of α introduce higher penalties to use more agents. Lower values ​​of α introduce lower penalties to use more agents.

[0139] In Figure 11(B), the second stage uses iterative fine-tuning with decreasing values ​​of α, allowing λ to be reduced more aggressively in subsequent rounds. Extensive fine-tuning thoroughly explores the learning space, allowing the algorithm to confidently use significantly smaller λ in the next round, speeding up the overall training process.

[0140] As shown in Figure 11(A) and Figure 11(B), in Figure 11(A) and Figure 11(B), the regularization parameter λ decreases with each subsequent round of agent selection (first phase). High values ​​of λ strongly penalize the inclusion of many features (signals in this case) in the model. This leads to a very sparse solution, where only a few agents with the strongest correlation with power consumption are selected. Low values ​​of λ relax this penalty, allowing more features into the model, leading to a denser solution.

[0141] The algorithm starts with a large λ to enforce sparsity and avoid overfitting, especially when dealing with millions of signals. As λ is reduced, the algorithm allows more signals (agents) to be included in the model, gradually increasing the model's complexity and potential accuracy. "Warm start" initialization ( Fig. 9 Operation 922 in ) uses the solution of the previous round to make the optimization more efficient.

[0142] The input to each round of the agent selection phase is the signal set 1112 in FIG. 11(A) and the signal set 1152 in FIG. 11(B). As explained in operation 922, the solution of the previous round (the selected agents and their coefficients) is used as the starting point for the current round of optimization. This allows the coordinate optimization to converge faster. In FIG. 11(B), the intensive fine-tuning of the second stage allows a more aggressive reduction of λ in the subsequent first stage. The algorithm benefits from the knowledge gained in previous rounds, allowing it to explore a wider range of agent choices more effectively.

[0143] Fig.12 1200, which describes a process (method) for quantizing the power model 150 to reduce the hardware cost of implementing the power model 150. Quantization is necessary to reduce the hardware cost of the power model 150. Quantizing all coefficients to integers may result in a significant reduction in hardware cost with minimal loss of accuracy. To further save hardware cost, signal activity that is an input to the power model 150 may also be quantized. The dynamic power output of the power model 150 is also quantized. A full search or a sequential search may be used in all cases.

[0144] As mentioned above, the power model can be expressed using the following equation:

[0145] Dynamic power=F(Signal_Activity; θ)

[0146] Dynamic power is the output of the power model and represents the estimated dynamic power consumption of the chip. F is a function that maps the input Signal_Activity and the model coefficient θ to the output Dynamic power. Signal_Activity is the input of the power model and represents the activity of a portion of the signal within the chip. Signal activity can include T 0 、T 1 and TC signals. θ represents the coefficients of the power model, which are learned during the training process using an artificial intelligence algorithm. These coefficients determine the weight or importance of each signal activity in estimating dynamic power consumption.

[0147] More specifically, in operation 1202, the quantization component 336 iteratively quantizes the power model coefficients θ. The coefficients are quantized to a fixed number of bits, such as 8 bits. This reduces the hardware cost of storing and processing the coefficients. This quantization process may find the minimum number of bits to represent the coefficients with minimal loss of precision.

[0148] In operation 1204, the quantization component 336 iteratively quantizes the power model input, Signal_Activity, using the quantization coefficients θ in operation 1202. For example, signal activity may include T 0 、T 1 and TC signals. The signal activity is quantized to a fixed number of bits to reduce the hardware cost of input interfacing and processing. The quantization process of the input may determine the minimum number of bits to represent the signal activity with the minimum loss of accuracy.

[0149] In operation 1206, the quantization component 336 iteratively quantizes the power model output, Dynamic power, using the quantization coefficients θ and the quantized signal activity Signal_Activity in operations 1202 and 1204. The dynamic power output is quantized to a fixed number of bits to reduce the hardware cost of the output interface.

[0150] The quantization order of operations 1202, 1204, and 1206 can be arbitrary. The quantization component 336 can determine a predetermined number of bits (e.g., a minimum number) for each quantization operation to obtain an acceptable decrease in accuracy. Therefore, the quantized power model 150 minimizes hardware cost while maintaining sufficient accuracy.

[0151] The coefficients, input signal activity, and output dynamic power of the quantized power model 150 obtained after the quantization process are represented using fewer bits than the original power model 150. This significantly reduces the hardware cost when implementing the power model 150, making it more suitable for integration into mobile chips and other resource-constrained devices.

[0152] The quantization process can use either a full search or a sequential search to determine the optimal bit width for each component of the power model.

[0153] Fig.13 1300, showing an example of a hardware implementation of an apparatus 1378 using a processing system 1314. The apparatus 1378 can implement a collection component 1342, a training component 1346, and a fine-tuning component 1348. The processing system 1314 can be implemented using a bus architecture, generally represented by a bus 1324. The bus 1324 can include any number of interconnecting buses and bridges, depending on the specific application and overall design constraints of the processing system 1314. The bus 1324 connects various circuits, including one or more processors and / or hardware components, represented by the processor 1304, the network controller 1310, and the computer readable medium / memory 1306. The bus 1324 can also connect various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and are not further described.

[0154] The processing system 1314 may be connected to the network controller 1310. The network controller 1310 provides a means of communicating with various other devices on the network. The network controller 1310 receives signals from the network, extracts information from the received signals, and provides the extracted information to the processing system 1314, particularly the communication component 1320 of the device 1378. In addition, the network controller 1310 receives information from the processing system 1314, particularly the communication component 1320, and generates signals to be sent to the network based on the received information. The processing system 1314 includes a processor 1304 connected to a computer-readable medium / memory 1306. The processor 1304 is responsible for general processing, including executing software stored on the computer-readable medium / memory 1306. When the processor 1304 executes the software, it causes the processing system 1314 to perform various functions of any of the specific devices described above. The computer-readable medium / memory 1306 can also be used to store data that is manipulated by the processor 1304 when executing the software. The processing system also includes a collection component 1342, a training component 1346, and a fine-tuning component 1348. These components may be software components running in the processor 1304 , resident / stored in the computer-readable medium / memory 1306 , one or more hardware components connected to the processor 1304 , or some combination thereof.

[0155] The device 1378 may include executing the above-mentioned reference Figure 10(A) , 10(B) , 11(A), 11(B) and 12. The above-mentioned means may be one or more of the above-mentioned components of the device 1378 and / or the processing system 1314 of the device 1378, configured to perform the functions described by the above-mentioned means.

[0156] It is understood that the specific order or hierarchy of blocks in the disclosed processes / flowcharts is an illustration of example methods. Based on design preferences, the specific order or hierarchy of blocks in the processes / flowcharts may be rearranged. In addition, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in an example order and are not meant to be limited to the specific order or hierarchy presented.

[0157] Although the present invention has been described by way of example and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements (which are obvious to those skilled in the art). Therefore, the scope of the appended claims should be interpreted in the broadest manner so as to cover all such modifications and similar arrangements.

Claims

1. A method for training a power model for estimating chip power consumption, characterized in that: The method includes: Collecting a plurality of data samples, each data sample representing signal activities of a plurality of signals of the chip; According to a criterion, a portion of the signals is selected from the plurality of signals as a proxy related to the actual power consumption of the chip; training the power model using the signal activities of the plurality of signals as input and the actual power consumption as output; and The coefficient of the agent in the power model is fine-tuned to adjust an estimation error between the estimated power consumption output by the power model and the actual power consumption.

2. The method according to claim 1, characterized in that Collecting the multiple data samples includes: Acquire a T1 signal array from the chip, the T1 signal array indicating that one or more signals are at a high voltage level at one or more time points; Applying a dimensionality reduction method to the T1 signal array to obtain multiple embeddings; applying a clustering method to the multiple embeddings to obtain orthogonal clusters; as well as A sampling rule is applied to the orthogonal clusters to obtain an orthogonal minimal data set.

3. The method according to claim 2, characterized in that The T1 signal array is obtained from the chip's performance monitoring unit (PMU).

4. The method according to claim 2, characterized in that The sampling rule is based on a group size.

5. The method according to claim 2, characterized in that Further including: Similarity filtering is performed on the orthogonal clusters to remove highly similar data points within each cluster.

6. The method according to claim 5, characterized in that Performing similarity filtering includes: Calculate the similarity between each pair of data points within each cluster; Concatenate the signal activity of each data point in the pair into a 1D array; Calculate the similarity between the two 1D arrays; as well as If the similarity is above a threshold, one of the two data points is removed.

7. The method according to claim 1, characterized in that The subset of signals chosen as agents includes: A bottom-up strategy is applied, where agents are selected sequentially and the selection is propagated to the next level until the entire design of the chip is processed.

8. The method according to claim 7, characterized in that Applying this bottom-up strategy involves: Select agents starting from the deepest level of the chip design hierarchy; Combine the selected agent at the current level with the signal from the previous level in the design hierarchy; and Another round of agent selection is conducted using the combined signal.

9. The method according to claim 1, characterized in that The subset of signals chosen as agents includes: An optimization algorithm is applied to select the agent, the optimization algorithm comprising: Perform active coordinate minimization on coordinates in an active set; Apply a strong rule to preselect the coordinates of the activity set; Update the active set by adding the coordinates with the largest absolute gradient value from the inactive set; as well as Performs a warm start initialization using the solution from the previous iteration as the starting point for the current iteration.

10. The method according to claim 1, characterized in that Training the power model involves: Execution of the first phase involves selecting this subset of signals as agents using a regularization parameter; as well as Executing the second phase involves iteratively fine-tuning the agent's coefficients using a coefficient scaling parameter, wherein the regularization parameter decreases in one or more iterations of the first stage, and Wherein the coefficient scaling parameter is decreased in a plurality of sub-iterations corresponding to each iteration of the first stage.

11. The method according to claim 1, characterized in that Training the power model involves: Perform multiple rounds of training, each of which consists of a first phase for agent selection and a second phase for coefficient fine-tuning; In this first phase, the results of the initial outer loop of agent selection are stored in a file; as well as In this second stage, the stored results are loaded and coefficient fine-tuning is performed.

12. The method according to claim 1, characterized in that The coefficients for fine-tuning this agent include: Perform multiple rounds of training, each of which consists of a first phase for agent selection and a second phase for coefficient fine-tuning; In this first phase, the regularization parameter is reduced by one in each subsequent round; as well as In this second stage, the coefficients are iteratively fine-tuned using a series of decreasing coefficient scaling parameters.

13. The method according to claim 1, characterized in that Further including: quantizing coefficients of the power model into integers; quantifying signal activity used as input to the power model; as well as The power value output by the power model is quantified.

14. A computing device for training a power model for estimating chip power consumption, characterized in that: include: a memory; and At least one is connected to the memory and is configured as: Collecting a plurality of data samples, each data sample representing signal activities of a plurality of signals of the chip; According to a criterion, a portion of the signals is selected from the plurality of signals as a proxy related to the actual power consumption of the chip; training the power model using the signal activities of the plurality of signals as input and the actual power consumption as output; and The coefficient of the agent in the power model is fine-tuned to adjust an estimation error between the estimated power consumption output by the power model and the actual power consumption.

15. The computing device of claim 14, wherein: To collect the plurality of data samples, the at least one processor is further configured to: Obtain a T1 array of multiple signals from the chip, where the T1 array indicates that one or more signals are at a high voltage level at one or more time points; Apply a dimensionality reduction method to the T1 array to obtain multiple embeddings; Apply clustering methods to multiple embeddings to obtain orthogonal clusters; Apply sampling rules to orthogonal clusters to obtain an orthogonal minimal data set.

16. The computing device of claim 15, wherein: The T1 array is obtained from the chip's performance monitoring unit (PMU).

17. The computing device of claim 15, wherein: The sampling rules are based on the group size.

18. The computing device of claim 15, wherein: The at least one processor is further configured to: Similarity filtering is performed on orthogonal clusters to remove highly similar data points within each cluster.

19. The computing device of claim 18, wherein: To perform similarity filtering, the at least one processor is further configured to: Calculate the similarity between each pair of data points within each cluster; Concatenate the signal activity of each data point into a one-dimensional array; Compute the similarity between two one-dimensional arrays; If the similarity is above a threshold, one of the two data points is removed.

20. A computer readable medium, characterized in that storing computer executable code for computing device operations, including for: Collecting a plurality of data samples, each data sample representing signal activities of a plurality of signals of the chip; Selecting a portion of the signals from the plurality of signals as a proxy related to the actual power consumption of the chip according to a standard; Train a power model using signal activity of multiple signals as input and actual power consumption as output; The coefficients of the agents in the power model are adjusted to adjust the estimation error between the estimated power consumption output by the power model and the actual power consumption.

Images