Data processing system and wavefront correction method for space-based telescope wavefront correction

Abstract

The present invention relates to a wavefront correction system, and in particular to a data processing system and a wavefront correction method for wavefront correction of a space-based telescope, which solves the technical problem that the existing wavefront correction data processing system has a low control bandwidth and is difficult to realize dynamic and high-frequency correction of wave aberrations of a space-based telescope. The present invention utilizes the Shack-Hartmann principle, embeds a wavefront correction algorithm into a heterogeneous model of a combined processing FPGA+data processing FPGA+CPU, adopts a parallel processing structure of a combined processing FPGA, a data processing FPGA and a CPU, improves bandwidth and speed, and matches the optimal hardware resources according to different processing tasks, so that the wavefront correction process reaches the optimal design, thereby achieving the global optimal processing effect, and can be used to process complex optical data. The control unit reaches the thousand-unit level, the data bandwidth reaches 100M, the operation speed is fast, and the dynamic and high-frequency correction of wave aberrations of a space-based telescope can be realized.

Description

Technical Field

[0001] The invention relates to a wavefront correction system, and in particular to a data processing system and a wavefront correction method for space-based telescope wavefront correction. Background Art

[0002] Wavefront correction technology combines electronic technology and optical technology to perform real-time correction of dynamic optical wavefront errors through a closed-loop control of real-time measurement → control → correction, enabling the optical system to automatically adapt to changes in external conditions and maintain the best working state.

[0003] The typical wavefront correction process is as follows: Figure 1 As shown, the wavefront sensor (WFS) uses a high-speed digital computer to perform wavefront restoration (WFC) and control signal calculation (CC) on the measured wavefront distortion signal, and then performs wavefront correction using a deformable mirror / tilt mirror (DM / TM) after digital-to-analog conversion (DAC) and a high-voltage amplifier (HVA).

[0004] Deformable mirrors and tilt mirrors are commonly used wave aberration correctors. The wavefront phase of the light beam can be changed by adjusting the surface shape of the deformable mirror or the position of the tilt mirror. Taking the deformable mirror as an example, the key point of the closed-loop control of wavefront correction is to determine the control voltage value of the deformable mirror according to the wavefront measurement results. The control voltage is applied to each driver of the deformable mirror through the drive circuit, so that the deformable mirror produces the required correction surface shape and performs phase correction on the incident distorted wavefront. The closed-loop operation is repeated in this way, so that the spliced ​​mirror surfaces reach a common phase, and finally the imaging system achieves the best imaging effect.

[0005] Therefore, the real-time and accuracy of wavefront correction are of great significance to the imaging effect of wavefront restoration. The wavefront aberration corrector of space-based telescopes usually uses a deformable mirror with nearly a thousand control units, which requires a large amount of calculation and a higher control bandwidth. The existing wavefront correction system is generally aimed at ground-based telescopes. Since ground-based telescopes have fewer control units, the control bandwidth of the wavefront correction system is low, and the hardware resources and power consumption are also low. It is difficult to meet the control bandwidth requirements of space-based telescope wavefront correction, and it is also difficult to achieve dynamic and high-frequency correction of wavefront aberrations of space-based telescopes. Summary of the invention

[0006] The purpose of the present invention is to solve the technical problem that the existing wavefront correction data processing system has a low control bandwidth and is difficult to achieve dynamic and high-frequency correction of wavefront aberrations of space-based telescopes, and to provide a data processing system and a wavefront correction method for wavefront correction of space-based telescopes.

[0007] To achieve the above object, the technical solution adopted by the present invention is:

[0008] A data processing system for wavefront correction of a space-based telescope, wherein the space-based telescope is provided with a Hartmann sensor and a wavefront aberration corrector, and the system is special in that it comprises a combining processing FPGA, a data processing FPGA and a CPU;

[0009] The input end of the combining processing FPGA is connected to the Hartmann sensor, the data reading and writing end is respectively connected to the first DDR memory and the first NOR FLASH memory, the clock driving end is connected to the clock driving module, and the data transceiver end is connected to the first data transceiver end of the data processing FPGA;

[0010] The combining processing FPGA is used to pre-process the real-time wavefront image collected by the Hartmann sensor to obtain a window split image, store the intermediate image obtained by the data processing FPGA, and store the control voltage of the wave aberration corrector; the first DDR memory is used to store the real-time wavefront image, and the first NOR FLASH memory is used to store the window split image;

[0011] The data read and write ends of the data processing FPGA are respectively connected to the second DDR memory and the second NOR FLASH memory, the clock driving end is connected to the clock driving module, and the control signal output end is connected to the wave aberration corrector;

[0012] The data processing FPGA is embedded with a wavefront correction algorithm, which is used to calculate the wavefront offset according to the window split image, and convert the wavefront offset into a control voltage of a wave aberration corrector, and cooperate with the wave aberration corrector to complete the wavefront correction; the second DDR memory is used to store the wavefront correction algorithm data, and the second NOR FLASH memory is used to store the control parameters and control data of the wave aberration corrector;

[0013] The control instruction output terminal of the CPU is connected to the control terminals of the combiner processing FPGA and the data processing FPGA respectively, and the data transceiver terminal is connected to the second data transceiver terminal of the data processing FPGA;

[0014] The CPU is used to send control instructions, store wavefront correction algorithm initialization parameters, wavefront correction algorithm intermediate parameters and wavefront correction algorithm results, and assist data processing FPGA in calculating wavefront offset; the control instructions include receiving wavefront image instructions, starting wavefront correction instructions and ending wavefront correction instructions.

[0015] Furthermore, the CPU is connected to the combining processing FPGA and the data processing FPGA respectively through the HPI interface;

[0016] The data transceiver end of the combining processing FPGA is the first GTX signal interface and the first GPIO signal interface, and the first data transceiver end of the data processing FPGA is the second GTX signal interface and the second GPIO signal interface; the first GTX signal interface and the second GTX signal interface are connected, and the first GPIO signal interface and the second GPIO signal interface are connected.

[0017] Further, the combined processing FPGA includes a first HPI interface module, a first instruction parsing module and a plurality of combined processing execution modules;

[0018] The input end of the first HPI interface module is connected to the control instruction output end of the CPU as the control end of the combining processing FPGA, and the output end is connected to the input end of the first instruction parsing module. The first HPI interface module is used to complete the transmission of control instructions between the combining processing FPGA and the CPU;

[0019] The output end of the first instruction parsing module is connected to the instruction input ends of the plurality of combined processing execution modules respectively, so as to parse the control instructions sent by the CPU and send them to the corresponding combined processing execution modules;

[0020] The data processing FPGA includes a second HPI interface module, a second instruction parsing module and a plurality of data processing execution modules;

[0021] The input end of the second HPI interface module is connected to the control instruction output end of the CPU as the control end of the data processing FPGA, the data transceiver end is connected to the data transceiver end of the CPU as the second data transceiver end of the data processing FPGA, and the output end is connected to the input end of the second instruction parsing module. The second HPI interface module is used to complete the transmission of data and control instructions between the data processing FPGA and the CPU;

[0022] The output end of the second instruction parsing module is connected to the instruction input ends of multiple data processing execution modules respectively, and is used to parse the control instructions sent by the CPU and send them to the corresponding data processing execution modules.

[0023] Further, the multiple combining processing execution modules include a first NOR FLASH control module, a first instruction parameter selection storage module, a first DDR storage control module, a first GTX control module and a first GTX transceiver module, whose instruction input terminals are respectively connected to the output terminals of the first instruction parsing module;

[0024] The output end of the first NOR FLASH control module is connected to the control end of the first NOR FLASH memory, and is used to implement read and write control of the first NOR FLASH memory;

[0025] The output end of the first instruction parameter selection storage module is connected to the data writing end of the first NOR FLASH memory, and is used to store the control instruction sent by the CPU into the first NOR FLASH memory;

[0026] The output end of the first DDR storage control module is connected to the control end of the first DDR memory, so as to realize the read and write control of the first DDR memory;

[0027] The control end of the first GTX transceiver module is connected to the output end of the first GTX control module, and the transceiver end is connected to the transceiver end of the first GTX signal interface, and is used to send the control voltage of the window split image and the receiving wave aberration corrector.

[0028] Further, the multiple data processing execution modules include a second NOR FLASH control module whose instruction input end is respectively connected to the output end of the second instruction parsing module, a second instruction parameter selection storage module, a second DDR storage control module, a second GTX control module, a second GTX transceiver module, a data parameter reading module, an algorithm parameter storage module, a correction algorithm control module, a correction algorithm module, a wave aberration control module and a tilt control module;

[0029] The output end of the second NOR FLASH control module is connected to the control end of the second NOR FLASH memory, and is used to implement the read and write control of the second NOR FLASH memory;

[0030] The output end of the second instruction parameter selection storage module is connected to the data writing end of the second NOR FLASH memory, and is used to store the control instruction sent by the CPU into the second NOR FLASH memory;

[0031] The output end of the second DDR storage control module is connected to the control end of the second DDR memory, so as to realize the read and write control of the second DDR memory;

[0032] The input end of the algorithm parameter storage module is connected to the data reading and writing end of the second HPI interface module, and the output end is connected to the data writing end of the second NOR FLASH memory, and is used to write the wavefront correction algorithm initialization parameters sent by the CPU into the second NOR FLASH memory;

[0033] The reading end of the data parameter reading module is connected to the data reading end of the second NOR FLASH memory, and the output end is connected to the input end of the correction algorithm module, for reading out the control parameters and control data of the wave aberration corrector;

[0034] The input end of the correction algorithm module is also connected to the output end of the second GTX transceiver module, and the output end is respectively connected to the data writing end of the second DDR memory, the data reading and writing end of the second HPI interface module, the input end of the second GTX transceiver module, the input end of the wave aberration control module, and the input end of the tilt control module, and the control end is connected to the output end of the correction algorithm control module; the correction algorithm module is used to use a wavefront correction algorithm to calculate and send a control voltage of a wavefront aberration corrector according to a window split image, and to send wavefront correction algorithm data, wavefront correction algorithm intermediate parameters, wavefront correction algorithm results and intermediate images; the control voltage of the wavefront aberration corrector includes tilt data and high-order wave data;

[0035] The output ends of the wave aberration control module and the tilt mirror control module are both connected to the control end of the wave aberration corrector, the wave aberration control module is used to transmit high-order wave data, and the tilt control module transmits tilt data;

[0036] The control end of the second GTX transceiver module is connected to the output end of the second GTX control module, and the transceiver end is connected to the transceiver end of the second GTX signal interface, and is used to receive the windowed split image, send the intermediate image and the control voltage of the wave aberration corrector.

[0037] The present invention also provides a wavefront correction method, which uses the above-mentioned data processing system for wavefront correction of a space-based telescope, and the method is characterized in that it includes the following steps:

[0038] Step 1, the data processing FPGA reads the control parameters and control data of the wave aberration corrector from the second NOR FLASH memory. If the reading is successful, step 2 is executed; otherwise, the data processing FPGA enters the standby mode; wherein the control parameters include the control voltage threshold, and the control data include the initial voltage;

[0039] Step 2: Data processing FPGA sends control data to the wave aberration corrector to initialize it;

[0040] Step 3, the CPU sends a wavefront image receiving instruction to the combining processing FPGA, the combining processing FPGA receives the real-time wavefront image collected by the Hartmann sensor, and pre-processes it to obtain a window split image, and then stores the real-time wavefront image in the first DDR memory, and stores the window split image in the first NOR FLASH memory;

[0041] Step 4, the CPU sends a start wavefront correction instruction to the data processing FPGA; after receiving the start wavefront correction instruction, the data processing FPGA sends a wavefront image request signal to the combiner processing FPGA, then reads the wavefront correction algorithm initialization parameters from the CPU, and initializes the wavefront correction algorithm according to the wavefront correction algorithm initialization parameters;

[0042] Step 5: After receiving the wavefront image request signal, the combining processing FPGA reads the window split image from the first NOR FLASH memory and sends it to the data processing FPGA;

[0043] Step 6: After receiving the window split image, the data processing FPGA uses the wavefront correction algorithm to perform parallel calculation on the window split image with the assistance of the CPU to obtain the wavefront offset, and sends the obtained intermediate image to the combining processing FPGA, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU;

[0044] Step 7, data processing FPGA calculates the control voltage of the wave aberration corrector according to the wavefront offset. If the control voltage of the wave aberration corrector is less than or equal to the control voltage threshold, execute step 8; otherwise, assign the initial voltage to the control voltage of the wave aberration corrector and return to step 2;

[0045] Step 8, the data processing FPGA sends the control voltage of the wave aberration corrector to the wave aberration corrector to realize real-time wavefront correction, and sends it to the combined processing FPGA, and then checks whether the end wavefront correction instruction sent by the CPU is received. If not, return to step 3, otherwise, enter the standby mode and complete the wavefront correction.

[0046] Further, in step 4, the start wavefront correction instruction includes a correction mode, and step 6 is specifically:

[0047] Step 6.1, the data processing FPGA parses the instruction to start the wavefront correction. If the correction mode is the synchronous mode, the data processing FPGA receives the window split image and the synchronization signal of the wavefront aberration corrector, and then executes step 6.2;

[0048] Otherwise, after the data processing FPGA receives the window split image, it immediately executes step 6.2;

[0049] Step 6.2, data processing FPGA uses wavefront correction algorithm to perform parallel calculation on the window split image with the assistance of CPU to obtain wavefront offset;

[0050] Step 6.3: The data processing FPGA sends the obtained intermediate image to the combining processing FPGA, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU.

[0051] Furthermore, before step 1, step A is also included: the combining processing FPGA calibrates the Hartmann sensor to determine the wavefront measurement threshold of the Hartmann sensor;

[0052] Then, step 6.2 is specifically as follows: the data processing FPGA uses a wavefront correction algorithm to perform parallel calculations on the windowed split image with the assistance of the CPU to obtain the wavefront offset. If the wavefront offset is within the wavefront measurement threshold of the Hartmann sensor, step 6.3 is executed; otherwise, the data processing FPGA enters standby mode.

[0053] Furthermore, in step 6.2, the CPU assistance specifically refers to the CPU assisting the data processing FPGA to perform square root operation.

[0054] Furthermore, in step 1, the initial voltage is a plurality of groups of initial voltages, and the control parameter further includes an initial voltage group number;

[0055] In step 2, the data processing FPGA sends control data to the wave aberration corrector, specifically: the data processing FPGA sends the initial voltage corresponding to the initial voltage group number to the wave aberration corrector.

[0056] Compared with the prior art, the present invention has the following beneficial technical effects:

[0057] 1. In the data processing system for wavefront correction of space-based telescopes provided by the present invention, the Shack-Hartmann principle is used to embed the wavefront correction algorithm into the heterogeneous model of the combined processing FPGA+data processing FPGA+CPU, and the parallel processing structure of the combined processing FPGA, the data processing FPGA and the CPU is adopted, thereby improving the computing bandwidth and processing speed, and can be used to process complex optical data. The control unit reaches the thousand-unit level, the data bandwidth reaches 100M, the computing speed is fast, and the dynamic and high-frequency correction of the wave aberration of the space-based telescope is realized;

[0058] 2. In the data processing system for wavefront correction of space-based telescopes provided by the present invention, the combining processing FPGA completes the preprocessing of real-time wavefront images, the data processing FPGA completes the real-time calculation and output of wavefront correction, and the CPU completes the control of the entire wavefront correction process and assists the data processing FPGA in calculation. The optimal hardware resources are matched according to different processing tasks, so that the wavefront correction process reaches the optimal design, thereby achieving the global optimal processing effect;

[0059] 3. In the data processing system for wavefront correction of space-based telescopes provided by the present invention, the combiner processing FPGA and the data processing FPGA are connected via a GTX signal interface and a GPIO signal interface. The GTX signal interface has a fast transmission speed, so that the data exchange between the combiner processing FPGA and the data processing FPGA matches the speed of the combiner processing FPGA in processing real-time wavefront images, and the GPIO signal interface can quickly reflect the data transmission status between the combiner processing FPGA and the data processing FPGA, thereby reducing the waiting time;

[0060] 4. In the data processing system for wavefront correction of space-based telescopes provided by the present invention, the CPU is directly connected to the combiner processing FPGA and the data processing FPGA through the HPI interface, and no other circuit devices are required, which can simplify the system structure;

[0061] 5. In the wavefront correction method provided by the present invention, the parallel processing structure of the combined processing FPGA, the data processing FPGA and the CPU is used for collaborative calculation, and the data processing FPGA performs parallel calculation on the window split image, which improves the calculation speed, thereby improving the efficiency of the wavefront correction and realizing real-time correction of the wavefront;

[0062] 6. In the wavefront correction method provided by the present invention, the Hartmann sensor is calibrated to accurately determine the parameters of the Hartmann sensor, reduce the measurement error caused by parameter error in subsequent calculations, and improve the accuracy of wavefront correction;

[0063] 7. In the wavefront correction method provided by the present invention, the CPU assists the data processing FPGA in performing the square root operation, thereby improving the calculation speed of the square root operation and further improving the efficiency of the wavefront correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is a schematic diagram of the existing wavefront correction method;

[0065] Figure 2 is a system architecture diagram of an embodiment of the present invention;

[0066] Figure 3 It is a module structure diagram of the FPGA for combining processing in an embodiment of the present invention;

[0067] Figure 4 It is a module structure diagram of the data processing FPGA in the embodiment of the present invention;

[0068] Figure 5 is a system data flow diagram of an embodiment of the present invention;

[0069] Figure 6 is a flow chart of a method according to an embodiment of the present invention;

[0070] Figure 7 This is a working timing diagram of the CPU, the combining processing FPGA and the data processing FPGA in the embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following is a further detailed description of a data processing system and a wavefront correction method for a space-based telescope wavefront correction proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0072] A data processing system for wavefront correction of space-based telescopes, such as Figure 2 As shown, it includes a combiner processing FPGA, a data processing FPGA and a CPU, wherein a Hartmann sensor and a wave aberration corrector are provided on the space-based telescope. Both the combiner processing FPGA and the data processing FPGA use the JFM7K325T chip, which has rich hardware resources and a large number of logic gates, and can meet various interface requirements. The input end of the combiner processing FPGA is connected to the Hartmann sensor, the data reading and writing ends are respectively connected to the first DDR memory and the first NOR FLASH memory, the clock driving end is connected to the clock driving module, and the data transceiver end is connected to the first data transceiver end of the data processing FPGA. The combiner processing FPGA is used to calibrate the Hartmann sensor, and pre-process the real-time wavefront image collected by it to obtain a windowed split image for wavefront correction, as well as store the intermediate image obtained by the data processing FPGA and store the control voltage of the wave aberration corrector. The first DDR memory is used to store the real-time wavefront image, and the first NORFLASH memory is used to store the windowed split image.

[0073] The data read and write ends of the data processing FPGA are respectively connected to the second DDR memory and the second NOR FLASH memory, the clock drive end is connected to the clock drive module, and the control signal output end is connected to the wave aberration corrector. A wavefront correction algorithm is embedded in the data processing FPGA, which is used to calculate the wavefront offset according to the window split image, and convert the wavefront offset into a control voltage and send it to the wave aberration corrector to complete the wavefront correction; the second DDR memory is used to store the SPGD algorithm data, and the second NORFLASH memory is used to store the control parameters and control data of the wave aberration corrector. In this embodiment, the wavefront correction algorithm adopts the SPGD algorithm.

[0074] The CPU is connected to the combiner processing FPGA and the data processing FPGA respectively through the HPI interface, wherein the control instruction output end of the CPU is connected to the control end of the combiner processing FPGA and the data processing FPGA respectively, and the data transceiver end is connected to the second data transceiver end of the data processing FPGA. The CPU is used to send control instructions, store SPGD algorithm initialization parameters, SPGD algorithm intermediate parameters and SPGD algorithm results, and assist the data processing FPGA in calculating the wavefront offset. Among them, the control instructions include receiving wavefront image instructions, starting wavefront correction instructions and ending wavefront correction instructions. The intermediate parameters of the SPGD algorithm are the feedback of the intermediate state quantity of the wavefront optimization algorithm, including solving, solving completed, and solving times. They are the intermediate parameters fed back to the CPU by the data processing FPGA during the calculation process of the wavefront correction algorithm. The results of the SPGD algorithm include the number of voltage outputs, the value of the evaluation function, etc.

[0075] The data transceiver end of the combined processing FPGA is the first GTX signal interface and the first GPIO signal interface, and the first data transceiver end of the data processing FPGA is the second GTX signal interface and the second GPIO signal interface. The first GTX signal interface and the second GTX signal interface are connected to transmit the window split image obtained by the combined processing FPGA, and the control voltage of the wave aberration corrector obtained by the data processing FPGA. The first GPIO signal interface and the second GPIO signal interface are connected to transmit the wavefront image request signal issued by the data processing FPGA and the wavefront image complete flag issued by the combined processing FPGA. The control voltage of the wave aberration corrector includes tilt data and high-order wave data. After receiving the tilt data and the high-order wave data, the combined processing FPGA stores them as an archive of the display correction process and the correction voltage. Among them, the high-order wave data includes the tilt control voltage and the surface shape control voltage, and the tilt data is the center of mass offset of the Hartmann sub-aperture.

[0076] Specifically, Figure 3 As shown, the combined processing FPGA includes a first HPI interface module, a first instruction parsing module, a first clock and reset module, and multiple combined processing execution modules. Among them, the multiple combined processing execution modules include a first NORFLASH control module, a first instruction parameter selection storage module, a first DDR storage control module, a first GTX control module, and a first GTX transceiver module.

[0077] The input end of the first HPI interface module is connected to the control instruction output end of the CPU as the control end of the combined processing FPGA, and the output end is connected to the input end of the first instruction parsing module. The first HPI interface module is used to complete the transmission of control instructions between the combined processing FPGA and the CPU. The first HPI interface module includes an HPI sending module, an HPI receiving module, an HPI control module and 22 HPI receiving data FIFO IP cores.

[0078] The output end of the first instruction parsing module is respectively connected to the instruction input ends of the first NOR FLASH control module, the first instruction parameter selection storage module, the first DDR storage control module, the first GTX control module and the first GTX transceiver module. The first instruction parsing module is used to parse the received CPU instructions and send them to the corresponding combining processing execution module.

[0079] The output end of the first NOR FLASH control module is connected to the control end of the first NOR FLASH memory, and is used to implement the read and write control of the first NOR FLASH memory. The first NOR FLASH control module includes a NOR FLASH programming module, a NOR FLASH erasing module, a NOR FLASH reading module and a NOR FLASH control module.

[0080] The output end of the first instruction parameter selection storage module is connected to the data writing end of the first NOR FLASH memory, and is used to store the control instruction sent by the CPU in the first NOR FLASH memory. The first DDR storage control module is connected to the control end of the first DDR memory, and is used to realize the read and write control of the first DDR memory. The first DDR storage control module includes a DDR read module, a MIG IP core, a data transmission FIFO and a DDR write module. The control end of the first GTX transceiver module is connected to the output end of the first GTX control module, and the transceiver end is connected to the transceiver end of the first GTX signal interface, and is used to send the control voltage of the window split image and the receiving wave aberration corrector.

[0081] The input end of the first clock and reset module is connected to the output end of the clock driver module, and the output end is respectively connected to the clock driver end of the first HPI interface module, the clock driver end of the first GTX control module, and the clock driver end of the first DDR storage control module. The first clock and reset module provides a 50M clock for the first HPI interface module, a 100M clock for the first GTX control module, and a 200M clock for the first DDR storage control module, which can meet the input requirements of different hardware modules. Specifically, the first clock and reset module includes a first 50M clock module, a first 100M clock module, and a first 200M clock module, whose input ends are respectively connected to the output end of the clock driver module, the output end of the first 50M clock module is connected to the clock driver end of the first HPI interface module, the output end of the first 100M clock module is connected to the clock driver end of the first GTX control module, and the output end of the first 200M clock module is connected to the clock driver end of the first DDR storage control module.

[0082] The modules and their functional descriptions of the FPGA are shown in Table 1.

[0083] Table 1

[0084] Serial number Modules Functional Description 1 First HPI interface module According to the CPU communication protocol, complete the data and instruction transmission between the FPGA and the CPU 2 First instruction parsing module Parse the received CPU control instructions and send them to the corresponding combined processing execution module 3 The first NOR FLASH control module Realize the control of the first NOR FLASH memory, realize the control of reading, writing and erasing 4 The first instruction parameter selects the storage module The control instruction sent by the CPU is stored in the corresponding address in the first NOR FLASH memory 5 First DDR storage control module Implement read and write control of the first DDR memory 6 First GTX control module Implementing GTX communication protocol in FPGA 7 The first GTX transceiver module Combined with the first GTX control module, it can send the window split image and receive the control voltage of the wave aberration corrector. 8 First clock and reset module The input is the 100M clock generated by the clock driver module, and the output is 100M clock, 50M clock and 200M clock.

[0085] like Figure 4 As shown, the data processing FPGA includes a second HPI interface module, a second instruction parsing module, a second clock and reset module, and multiple data processing execution modules. Among them, the multiple data processing execution modules include a second NOR FLASH control module, a second instruction parameter selection storage module, a second DDR storage control module, a second GTX control module, a second GTX transceiver module, a data parameter reading module, an algorithm parameter storage module, a correction algorithm control module, a correction algorithm module, a wave aberration control module, and a tilt control module.

[0086] The input end of the second HPI interface module is connected to the control instruction output end of the CPU as the control end of the data processing FPGA, the data transceiver end is connected to the data transceiver end of the CPU as the second data transceiver end of the data processing FPGA, and the output end is connected to the input end of the second instruction parsing module. The second HPI interface module is used to complete the transmission of data and control instructions between the data processing FPGA and the CPU.

[0087] The output end of the second instruction parsing module is respectively connected to the second NOR FLASH control module, the second instruction parameter selection storage module, the second DDR storage control module, the second GTX control module, the second GTX transceiver module, the data parameter reading module, the algorithm parameter storage module, the correction algorithm control module, the correction algorithm module, the wave aberration control module and the tilt control module. The second instruction parsing module is used to parse the received CPU instructions and send them to the corresponding data processing execution module.

[0088] The output end of the second NOR FLASH control module is connected to the control end of the second NOR FLASH memory, and is used to realize the read and write control of the second NOR FLASH memory. The output end of the second instruction parameter selection storage module is connected to the data writing end of the second NOR FLASH memory, and is used to store the control instruction sent by the CPU into the second NOR FLASH memory.

[0089] The output end of the second DDR storage control module is connected to the control end of the second DDR memory, and is used to implement read and write control of the second DDR memory. The input end of the algorithm parameter storage module is connected to the data read and write end of the second HPI interface module, and the output end is connected to the data write end of the second NOR FLASH memory, and is used to write the wavefront correction algorithm initialization parameters sent by the CPU into the second NOR FLASH memory.

[0090] The reading end of the data parameter reading module is connected to the data reading end of the second NOR FLASH memory, and the output end is connected to the input end of the correction algorithm module, which is used to read out the control parameters and control data of the wave aberration corrector. The input end of the correction algorithm module is also connected to the output end of the second GTX transceiver module, and the output end is respectively connected to the data writing end of the second DDR memory, the data reading and writing end of the second HPI interface module and the input end of the second GTX transceiver module, the wave aberration control module, and the tilt control module, and the control end is connected to the output end of the correction algorithm control module. The correction algorithm module is used to use the wavefront correction algorithm to calculate and send the control voltage of the wave aberration corrector according to the window split image, and to send the wavefront correction algorithm data, the intermediate parameters of the wavefront correction algorithm, the wavefront correction algorithm results and the intermediate image. The control voltage of the wave aberration corrector includes tilt data and high-order wave data. The output ends of the wave aberration control module and the tilt mirror control module are both connected to the control end of the wave aberration corrector, the wave aberration control module is used to transmit the high-order wave data, and the tilt control module is used to transmit the tilt data. The control end of the second GTX transceiver module is connected to the output end of the second GTX control module, and the transceiver end is connected to the transceiver end of the second GTX signal interface, and is used to receive the window split image, send the intermediate image and the control voltage of the wave aberration corrector.

[0091] The input end of the second clock and reset module is connected to the output end of the clock driver module, and the output end is connected to the clock driver end of the second HPI interface module, the clock driver end of the second GTX control module, and the clock driver end of the second DDR storage control module. The second clock and reset module provides a 50M clock for the second HPI interface module, a 100M clock for the second GTX control module, and a 200M clock for the second DDR storage control module, which can meet the input requirements of different hardware modules.

[0092] Among them, the second HPI interface module, the second NOR FLASH control module, the second DDR storage control module, the second clock and reset module have the same structure as the first HPI interface module, the first NOR FLASH control module, the first DDR storage control module, the first clock and reset module respectively.

[0093] The data parameter reading module includes a wave aberration voltage reading module, a power-on initial parameter reading module and an IF parameter reading module, wherein the wave aberration voltage reading module includes a voltage data receiving FIFO IP core, and the IF parameter reading module includes an IF data receiving FIFO IP core. The wave aberration control module includes a wave aberration data packaging module, a wave aberration cache FIFO IP core and a wave aberration data sending module, and the tilt control module includes a fast swing mirror control module, a laser control module and a tilt telemetry acquisition module.

[0094] The various modules of the data processing FPGA and their functional descriptions are shown in Table 2.

[0095] Table 2

[0096] Serial number Modules Functional Description 1 Second HPI interface module According to the CPU communication protocol, complete the data and instruction transmission between the data processing FPGA and the CPU 2 Second instruction parsing module Parse the received CPU control instructions and send them to the corresponding data processing execution module 3 The second NOR FLASH control module Realize the control of the second NOR FLASH memory, realize the control of reading, writing and erasing 4 Data parameter reading module Read the control parameters and control data of the wave aberration corrector stored in the second NOR FLASH memory 5 The second instruction parameter selects the storage module Store the control instructions sent by the CPU into the corresponding address in the second NOR FLASH memory 6 Algorithm parameter storage module The initialization parameters of the wavefront correction algorithm received from the CPU are stored in the corresponding address in the second NOR FLASH memory according to the instruction. 7 Waveform Aberration Control Module Receive high-order wave data specified by the algorithm or instruction, package it, and output it according to the LVDS protocol 8 Second DDR storage control module Implement read and write control of the second DDR memory 9 Second GTX control module Implementing the GTX communication protocol in data processing FPGA 10 Second GTX transceiver module Combined with the second GTX control module receiving the window split image, the control voltage of the wave aberration corrector is sent 11 Correction algorithm control module Implement control over the correction algorithm module 12 Correction algorithm module Realize the mathematical expression of the correction algorithm 13 Second clock and reset module The input is the 100M clock generated by the clock driver module, and the output is 100M clock, 50M clock and 200M clock. 14 Tilt Control Module Through the LVDS protocol, the tilt data can be sent

[0097] The working principle of a data processing system for wavefront correction provided in this embodiment is as follows: the combined processing FPGA receives the real-time wavefront image collected by the Hartmann sensor, and pre-processes it to obtain a window split image. When the combined processing FPGA receives the wavefront image request signal from the data processing FPGA, the window split image is sent to the data processing FPGA. The data processing FPGA calculates the wavefront offset based on the window split image, and then converts it into a control voltage and sends it to the wave aberration corrector. Among them, the CPU internally stores the initialization parameters of the wavefront correction algorithm and sends the instructions required in the correction process.

[0098] HPI interface function and instruction parsing function are the core functions of connecting the combined processing FPGA, data processing FPGA and CPU to form a heterogeneous system. Figure 5 As shown, the data processing FPGA receives the window split image sent by the combined processing FPGA and the SPGD algorithm initialization parameters sent by the CPU. The SPGD initialization parameters include algorithm control instructions, algorithm parameter annotations and algorithm operation data. Then the data processing FPGA performs correction calculations on the wavefront image according to the received algorithm control instructions, algorithm parameter annotations and algorithm operation data. In the wavefront correction calculation, the data processing FPGA transmits the algorithm operation data to the CPU, which assists in the calculation and then transmits it to the data processing FPGA for the next step of calculation. The algorithm telemetry data calculated by the data processing FPGA is transmitted to the CPU, and the control voltage is transmitted to the wave aberration corrector. Among them, the algorithm telemetry data includes the intermediate parameters of the SPGD algorithm and the results of the SPGD algorithm. The combined processing FPGA receives the real-time wavefront image detected by the Hartmann sensor, the tilt data, high-order wave data sent by the data processing FPGA and the control instructions sent by the CPU, and stores the above data in independent FIFOs respectively. There is a chip select signal in the control instruction of the CPU. When the combined processing FPGA or the data processing FPGA detects that the CPU chip select signal triggers a valid value and the CPU read signal is enabled, the corresponding register data is output according to the address given by the CPU. When the combiner processing FPGA or data processing FPGA detects that the CPU chip select signal triggers a valid value and the CPU write signal is enabled, the corresponding register data is written according to the address given by the CPU. The combiner processing FPGA or data processing FPGA uses internal registers to latch the CPU readable register value, thereby ensuring that the data output by the combiner processing FPGA and data processing FPGA is stable during the CPU read operation to avoid metastable problems.

[0099] When processing the windowed split image, the data processing FPGA needs the pixel data of the entire image. Therefore, after the combining processing FPGA pre-processes the real-time wavefront image to obtain the windowed split image, it caches the real-time wavefront image in the first DDR memory, and caches the windowed split image in the first NOR FLASH memory. After the data processing FPGA sends a wavefront image request signal, the combining processing FPGA reads the data from the first NOR FLASH memory, and packages and sends it through the first GTX signal port in accordance with the agreed data format. When the data processing FPGA receives the windowed split image, it calls the internally embedded SPGD algorithm for wavefront correction, and outputs the control voltage of the wave aberration corrector after the calculation is completed. The wavefront correction algorithm data obtained by the data processing FPGA is stored in the second DDR memory, and the intermediate image obtained is stored by the combining processing FPGA.

[0100] This embodiment also provides a wavefront correction method, using the above-mentioned data processing system for wavefront correction of space-based telescopes, such as Figure 6 , Figure 7 As shown, the following steps are included:

[0101] Step A: The FPGA performs calibrating on the Hartmann sensor to determine the wavefront measurement threshold of the Hartmann sensor.

[0102] Step 1: The data processing FPGA reads the control parameters and control data from the second NOR FLASH memory. If the reading is successful, step 2 is executed. Otherwise, the data processing FPGA enters the standby mode. The control parameters include the control voltage threshold, the correction mode, the IF matrix group number M, and the initial voltage group number N. The control data include the initial voltage, the IF matrix, the dark field image, the effective sub-aperture position matrix, and the Gain matrix.

[0103] Step 2: Data processing FPGA sends the Nth group of initial voltages, the Mth group of IF matrices, dark field images, effective sub-aperture position matrices and Gain matrices to the wave aberration corrector to initialize the wave aberration corrector.

[0104] Step 3, the CPU sends a wavefront image receiving instruction to the combining processing FPGA, the combining processing FPGA receives the real-time wavefront image collected by the Hartmann sensor, and pre-processes it to obtain a windowed split image, and then stores the real-time wavefront image in the first DDR memory, and stores the windowed split image in the first NOR FLASH memory.

[0105] The FPGA for combining and processing pre-processes the real-time wavefront image, including segmenting the real-time wavefront image, and then performing morphological operations, expansion and corrosion, opening and closing operations, and dark field optimization in sequence. Pre-processing can improve the imaging quality of the image.

[0106] Step 4, the CPU sends a start wavefront correction instruction to the data processing FPGA; after receiving the start wavefront correction instruction, the data processing FPGA sends a wavefront image request signal to the combiner processing FPGA, then reads the wavefront correction algorithm initialization parameters from the CPU, and initializes the wavefront correction algorithm according to the wavefront correction algorithm initialization parameters.

[0107] Step 5: After receiving the wavefront image request signal, the combining processing FPGA reads the window split image from the first NOR FLASH memory and sends it to the data processing FPGA.

[0108] Step 6: After receiving the window split image, the data processing FPGA uses the wavefront correction algorithm to perform parallel calculations on the window split image with the assistance of the CPU to obtain the wavefront offset, and sends the obtained intermediate image to the combined processing FPGA, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU. Specifically:

[0109] Step 6.1, the data processing FPGA parses the instruction to start the wavefront correction. If the correction mode is the synchronous mode, the data processing FPGA receives the window split image and the synchronization signal of the wavefront aberration corrector, and then executes step 6.2;

[0110] Otherwise, after the data processing FPGA receives the window split image, it immediately executes step 6.2;

[0111] Step 6.2, the data processing FPGA uses the wavefront correction algorithm to perform parallel calculations on the window split image with the assistance of the CPU to obtain the wavefront offset. If the wavefront offset is within the wavefront measurement threshold of the Hartmann sensor, step 6.3 is executed, otherwise, the data processing FPGA enters the standby mode;

[0112] Step 6.3: The data processing FPGA sends the obtained intermediate image to the combining processing FPGA, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU.

[0113] The CPU assistance specifically means that the square root operation in the wavefront offset calculation process is completed by the CPU.

[0114] Step 7, the data processing FPGA calculates the control voltage of the wave aberration corrector according to the wavefront offset. If the control voltage of the wave aberration corrector is less than or equal to the control voltage threshold, execute step 8; otherwise, assign the initial voltage as the control voltage of the wave aberration corrector and return to step 2.

[0115] Step 8, the data processing FPGA sends the control voltage of the wavefront aberration corrector to the wavefront aberration corrector to complete the real-time wavefront correction, and then checks whether the end wavefront correction instruction sent by the CPU is received. If not, return to step 3, otherwise, enter the standby mode to complete the wavefront correction.

[0116] It should be noted that, in the present invention:

[0117] FPGA refers to Field Programmable Gate Array, which is a field programmable logic gate array;

[0118] CPU refers to Central Processing Unit, which is the central processing unit;

[0119] SPGD algorithm refers to Stochastic Parallel Gradient Descent, which is a stochastic parallel gradient descent algorithm;

[0120] DDR memory refers to Double Data Rate SDRAM, which is double data rate synchronous dynamic random access memory;

[0121] NOR FLASH memory is a non-volatile memory with fast read capability, usually used to store firmware and operating systems;

[0122] LVDS protocol refers to a communication protocol that outputs low voltage differential signals;

[0123] HPI refers to Host Port Interface, which is a parallel communication interface used to connect the host processor and peripherals;

[0124] GTX refers to Gigabit Transceiver, which is a high-speed serial communication interface;

[0125] GPIO refers to General Purpose Input / Output, which is a general input and output interface used to connect and exchange data with external devices.

[0126] The IF parameter refers to the coefficient matrix, which is used to obtain the value of the correction voltage based on the offset;

[0127] FIFO stands for First In, First Out, and is a common data buffer structure. In FPGA, the FIFO IP core is a pre-designed, reusable hardware module used to implement first-in, first-out buffering of data.

Claims

1. A data processing system for wavefront correction of a space-based telescope, wherein the space-based telescope is provided with a Hartmann sensor and a wavefront aberration corrector, characterized in that: Including FPGA for combining processing, FPGA for data processing and CPU; The input end of the combining processing FPGA is connected to the Hartmann sensor, the data reading and writing end is respectively connected to the first DDR memory and the first NOR FLASH memory, the clock driving end is connected to the clock driving module, and the data transceiver end is connected to the first data transceiver end of the data processing FPGA; The combining processing FPGA is used to pre-process the real-time wavefront image collected by the Hartmann sensor to obtain a window split image, store the intermediate image obtained by the data processing FPGA, and store the control voltage of the wave aberration corrector; the first DDR memory is used to store the real-time wavefront image, and the first NOR FLASH memory is used to store the window split image; The data read and write ends of the data processing FPGA are respectively connected to the second DDR memory and the second NOR FLASH memory, the clock driving end is connected to the clock driving module, and the control signal output end is connected to the wave aberration corrector; The data processing FPGA is embedded with a wavefront correction algorithm, which is used to calculate the wavefront offset according to the window split image, and convert the wavefront offset into a control voltage of a wave aberration corrector, and cooperate with the wave aberration corrector to complete the wavefront correction; the second DDR memory is used to store the wavefront correction algorithm data, and the second NOR FLASH memory is used to store the control parameters and control data of the wave aberration corrector; The control instruction output terminal of the CPU is connected to the control terminals of the combiner processing FPGA and the data processing FPGA respectively, and the data transceiver terminal is connected to the second data transceiver terminal of the data processing FPGA; The CPU is used to send control instructions, store wavefront correction algorithm initialization parameters, wavefront correction algorithm intermediate parameters and wavefront correction algorithm results, and assist data processing FPGA in calculating wavefront offset; the control instructions include receiving wavefront image instructions, starting wavefront correction instructions and ending wavefront correction instructions.

2. The data processing system for wavefront correction of a space-based telescope according to claim 1, characterized in that: The CPU is connected to the combining processing FPGA and the data processing FPGA respectively through the HPI interface; The data transceiver end of the combining processing FPGA is the first GTX signal interface and the first GPIO signal interface, and the first data transceiver end of the data processing FPGA is the second GTX signal interface and the second GPIO signal interface; the first GTX signal interface and the second GTX signal interface are connected, and the first GPIO signal interface and the second GPIO signal interface are connected.

3. The data processing system for wavefront correction of a space-based telescope according to claim 2, characterized in that: The combined processing FPGA includes a first HPI interface module, a first instruction parsing module and a plurality of combined processing execution modules; The input end of the first HPI interface module is connected to the control instruction output end of the CPU as the control end of the combining processing FPGA, and the output end is connected to the input end of the first instruction parsing module. The first HPI interface module is used to complete the transmission of control instructions between the combining processing FPGA and the CPU; The output end of the first instruction parsing module is connected to the instruction input ends of the plurality of combined processing execution modules respectively, so as to parse the control instructions sent by the CPU and send them to the corresponding combined processing execution modules; The data processing FPGA includes a second HPI interface module, a second instruction parsing module and a plurality of data processing execution modules; The input end of the second HPI interface module is connected to the control instruction output end of the CPU as the control end of the data processing FPGA, the data transceiver end is connected to the data transceiver end of the CPU as the second data transceiver end of the data processing FPGA, and the output end is connected to the input end of the second instruction parsing module. The second HPI interface module is used to complete the transmission of data and control instructions between the data processing FPGA and the CPU; The output end of the second instruction parsing module is connected to the instruction input ends of multiple data processing execution modules respectively, and is used to parse the control instructions sent by the CPU and send them to the corresponding data processing execution modules.

4. The data processing system for wavefront correction of a space-based telescope according to claim 3, characterized in that: The multiple combining processing execution modules include a first NORFLASH control module, a first instruction parameter selection storage module, a first DDR storage control module, a first GTX control module and a first GTX transceiver module, whose instruction input terminals are respectively connected to the output terminals of the first instruction parsing module; The output end of the first NOR FLASH control module is connected to the control end of the first NOR FLASH memory, and is used to implement read and write control of the first NOR FLASH memory; The output end of the first instruction parameter selection storage module is connected to the data writing end of the first NOR FLASH memory, and is used to store the control instruction sent by the CPU into the first NOR FLASH memory; The output end of the first DDR storage control module is connected to the control end of the first DDR memory, so as to realize the read and write control of the first DDR memory; The control end of the first GTX transceiver module is connected to the output end of the first GTX control module, and the transceiver end is connected to the transceiver end of the first GTX signal interface, and is used to send the control voltage of the window split image and the receiving wave aberration corrector.

5. The data processing system for wavefront correction of a space-based telescope according to claim 4, characterized in that: The multiple data processing execution modules include a second NORFLASH control module whose instruction input ends are respectively connected to the output ends of the second instruction parsing module, a second instruction parameter selection storage module, a second DDR storage control module, a second GTX control module, a second GTX transceiver module, a data parameter reading module, an algorithm parameter storage module, a correction algorithm control module, a correction algorithm module, a wave aberration control module and a tilt control module; The output end of the second NOR FLASH control module is connected to the control end of the second NOR FLASH memory, and is used to implement the read and write control of the second NOR FLASH memory; The output end of the second instruction parameter selection storage module is connected to the data writing end of the second NOR FLASH memory, and is used to store the control instruction sent by the CPU into the second NOR FLASH memory; The output end of the second DDR storage control module is connected to the control end of the second DDR memory, so as to realize the read and write control of the second DDR memory; The input end of the algorithm parameter storage module is connected to the data reading and writing end of the second HPI interface module, and the output end is connected to the data writing end of the second NOR FLASH memory, and is used to write the wavefront correction algorithm initialization parameters sent by the CPU into the second NOR FLASH memory; The reading end of the data parameter reading module is connected to the data reading end of the second NOR FLASH memory, and the output end is connected to the input end of the correction algorithm module, for reading out the control parameters and control data of the wave aberration corrector; The input end of the correction algorithm module is also connected to the output end of the second GTX transceiver module, and the output end is respectively connected to the data writing end of the second DDR memory, the data reading and writing end of the second HPI interface module, the input end of the second GTX transceiver module, the input end of the wave aberration control module, and the input end of the tilt control module, and the control end is connected to the output end of the correction algorithm control module; the correction algorithm module is used to use a wavefront correction algorithm to calculate and send a control voltage of a wavefront aberration corrector according to a window split image, and to send wavefront correction algorithm data, wavefront correction algorithm intermediate parameters, wavefront correction algorithm results and intermediate images; the control voltage of the wavefront aberration corrector includes tilt data and high-order wave data; The output ends of the wave aberration control module and the tilt mirror control module are both connected to the control end of the wave aberration corrector, the wave aberration control module is used to transmit high-order wave data, and the tilt control module transmits tilt data; The control end of the second GTX transceiver module is connected to the output end of the second GTX control module, and the transceiver end is connected to the transceiver end of the second GTX signal interface, and is used to receive the windowed split image, send the intermediate image and the control voltage of the wave aberration corrector.

6. A wavefront correction method, using the data processing system for wavefront correction of a space-based telescope according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step 1, the data processing FPGA reads the control parameters and control data of the wave aberration corrector from the second NOR FLASH memory. If the reading is successful, step 2 is executed; otherwise, the data processing FPGA enters the standby mode; wherein the control parameters include the control voltage threshold, and the control data include the initial voltage; Step 2: Data processing FPGA sends control data to the wave aberration corrector to initialize it; Step 3, the CPU sends a wavefront image receiving instruction to the combining processing FPGA, the combining processing FPGA receives the real-time wavefront image collected by the Hartmann sensor, and pre-processes it to obtain a window split image, and then stores the real-time wavefront image in the first DDR memory, and stores the window split image in the first NOR FLASH memory; Step 4, the CPU sends a start wavefront correction instruction to the data processing FPGA; after receiving the start wavefront correction instruction, the data processing FPGA sends a wavefront image request signal to the combiner processing FPGA, then reads the wavefront correction algorithm initialization parameters from the CPU, and initializes the wavefront correction algorithm according to the wavefront correction algorithm initialization parameters; Step 5: After receiving the wavefront image request signal, the combining processing FPGA reads the window split image from the first NOR FLASH memory and sends it to the data processing FPGA; Step 6: After receiving the window split image, the data processing FPGA uses the wavefront correction algorithm to perform parallel calculation on the window split image with the assistance of the CPU to obtain the wavefront offset, and sends the obtained intermediate image to the combining processing FPGA for storage, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU; Step 7, data processing FPGA calculates the control voltage of the wave aberration corrector according to the wavefront offset. If the control voltage of the wave aberration corrector is less than or equal to the control voltage threshold, execute step 8; otherwise, assign the initial voltage to the control voltage of the wave aberration corrector and return to step 2; Step 8, the data processing FPGA sends the control voltage of the wave aberration corrector to the wave aberration corrector to realize real-time wavefront correction, and sends it to the combining processing FPGA for storage, and then checks whether the end wavefront correction instruction sent by the CPU is received. If not, return to step 3, otherwise, enter the standby mode to complete the wavefront correction.

7. A wavefront correction method according to claim 6, characterized in that: In step 4, the start wavefront correction instruction includes a correction mode, and step 6 is specifically as follows: Step 6.1, the data processing FPGA parses the instruction to start the wavefront correction. If the correction mode is the synchronous mode, the data processing FPGA receives the window split image and the synchronization signal of the wavefront aberration corrector, and then executes step 6.2; Otherwise, after the data processing FPGA receives the window split image, it immediately executes step 6.2; Step 6.2, data processing FPGA uses wavefront correction algorithm to perform parallel calculation on the window split image with the assistance of CPU to obtain wavefront offset; Step 6.3: The data processing FPGA sends the obtained intermediate image to the combining processing FPGA, sends the wavefront correction algorithm data to the second DDR memory, and sends the wavefront correction algorithm intermediate parameters and wavefront correction algorithm results to the CPU.

8. A wavefront correction method according to claim 7, characterized in that: Before step 1, step A is also included: the combining processing FPGA calibrates the Hartmann sensor to determine the wavefront measurement threshold of the Hartmann sensor; Then, step 6.2 is specifically as follows: the data processing FPGA uses a wavefront correction algorithm to perform parallel calculations on the windowed split image with the assistance of the CPU to obtain the wavefront offset. If the wavefront offset is within the wavefront measurement threshold of the Hartmann sensor, step 6.3 is executed; otherwise, the data processing FPGA enters standby mode.

9. A wavefront correction method according to claim 7 or 8, characterized in that: In step 6.2, the CPU assistance specifically refers to the CPU assisting the data processing FPGA to perform the square root operation.

10. A wavefront correction method according to claim 9, characterized in that: In step 1, the initial voltage is a plurality of groups of initial voltages, and the control parameter further includes an initial voltage group number; In step 2, the data processing FPGA sends control data to the wave aberration corrector, specifically: the data processing FPGA sends the initial voltage corresponding to the initial voltage group number to the wave aberration corrector.

Images