Liquid crystal screen

Abstract

The present application discloses a liquid crystal screen, comprising: a liquid crystal display; and a driving circuit. The driving circuit includes a medium voltage logic circuit and two voltage level converters, which saves high-voltage transistor area and power consumption compared with traditional driving circuits, and minimizes the number of voltage level converters to control the output signal of the output stage circuit to be in one of four states.

Description

[0001] This application is a divisional application of the invention patent application with the application number 2024108255695, and the filing date of the original application is June 25, 2024. Technical Field

[0002] This application belongs to the field of driving circuits, and relates to a driving circuit that includes fewer voltage level converters and can output a floating state or a high impedance state. Background Art

[0003] When driving a liquid crystal display screen or an electronic paper display, the driving circuit needs to generate scan signals or data signals within a large voltage range to turn on the thin film transistors coupled to the electronic paper display or the liquid crystal display screen and control the color of the pixels.

[0004] Please refer to Figure 1 As shown, it is a block diagram of an existing liquid crystal display screen 100. To control the liquid crystal display 110, the liquid crystal display screen 100 includes a gate control circuit 120 and an output stage circuit 122 of the corresponding gate driving circuit. The liquid crystal display screen 100 also includes a source control circuit 130 and an output stage circuit 132 of the corresponding source driving circuit. To generate the switching control signals corresponding to the liquid crystal display screen, the above output stage circuits 122 and 132 operate between the high positive voltage VPOS and the high negative voltage VNEG. The above output stage circuits 122 and 132 include P-type transistors (hereinafter referred to as PMOS), N-type transistors (hereinafter referred to as NMOS), and / or complementary transistors (hereinafter referred to as CMOS).

[0005] The high-voltage components of the above output stage circuits 122 and 132 will occupy a large chip area and consume a large switching current during operation. Moreover, since it is necessary to convert the medium voltage output by the gate control circuit 120 and the source control circuit 130 or the operating voltage of the logic circuit to a high voltage, a large number of voltage level converters (Level Shifter, hereinafter referred to as LVSH or LS) are required. When multiple LVSHs switch simultaneously, the instantaneous current demand is too large, exceeding the load, and there is a risk of voltage conversion failure.

[0006] Please refer to Figure 2 As shown, it is a timing diagram of various possible states of the output port of the output stage circuit 122 or 132. Figure 2 The upper half of includes the timing 210 of three possible states, Figure 2The lower part of [it] includes a timing sequence 220 of four possible states. Among the timing sequences 210, a short circuit may occur when switching from the voltage VPOS to the ground potential GND or from the ground potential GND to a lower voltage VNEG. To avoid the instantaneous leakage current caused by the short circuit, the potential of its output terminal can be first set to a floating or high impedance (floating or HiZ) state and then switched to avoid short circuit and leakage current. The aforementioned high impedance state is from the perspective of the output port. Those of ordinary skill in the art can understand that the floating or high impedance state is described from different perspectives but is essentially the same meaning.

[0007] In summary, there is an urgent need for a drive circuit that can use fewer high-voltage components. Especially in the case of reducing the use of voltage level converters and high-voltage components and switching to medium-voltage components, it can save chip area and power consumption, and can also be converted to a floating state first when the output high voltage is switched, so as to reduce leakage current and improve the reliability and lifespan of the integrated circuit. Summary of the Invention

[0008] This application proposes a drive circuit to solve the deficiencies in the prior art, aiming to save the area of high-voltage transistors and power compared to traditional circuits. Further, this application can minimize the number of voltage level converters to control the output signal of the output stage circuit.

[0009] To achieve the above object, this application adopts the following technical solutions:

[0010] According to an embodiment of this application, a drive circuit is provided, which is characterized by including: an output port that is in one of the following four states: voltage VPOS, ground voltage GND, voltage VNEG, and floating state, where the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; an output switch circuit that includes a first switch circuit, a second switch circuit, and a third switch circuit, and the outputs of the above-mentioned first switch circuit, the above-mentioned second switch circuit, and the above-mentioned third switch circuit are all coupled to the above-mentioned output port; a first voltage level converter for connecting to the first switch circuit; a second voltage level converter for connecting to the second switch circuit; a medium-voltage logic circuit that receives a first signal from the first voltage level converter, a second signal from the second voltage level converter, and a set of HZ signals for connecting to the third switch circuit; and a control logic circuit that, when receiving a third set of input signals and the set of HZ signals is in a second HZ state, makes the first voltage level converter control the first switch circuit to turn off, makes the second voltage level converter control the second switch circuit to turn off, and the medium-voltage logic circuit makes the third switch circuit turn off, so that the output port is in the floating state.

[0011] Preferably, in order to make the output port output a driving signal with a high voltage, such as the voltage VPOS, when the above control logic circuit receives the first group of input signals and the group of HZ signals is in the first HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to conduct, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are in inverse phase with each other.

[0012] Preferably, in order to make the output port output a driving signal with a ground potential, when the above control logic circuit receives the second group of input signals and the group of HZ signals is in the first HZ state, the first voltage level converter is made to control the first switching circuit to conduct, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are in inverse phase with each other.

[0013] Preferably, in order to make the output port output a driving signal with a high voltage, such as the voltage VNEG, when the above control logic circuit receives the third group of input signals and the group of HZ signals is in the first HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit conduct, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are in inverse phase with each other.

[0014] Preferably, in order to make the output port in a floating state, when the above control logic circuit receives the fourth group of input signals and the group of HZ signals is in the second HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is in the floating state.

[0015] Preferably, in order to make the output port in a floating state, the HZ signal of the above second HZ state is the voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

[0016] Preferably, in order to make the output port not in a floating state, the HZ signal of the above first HZ state is the voltage GND.

[0017] Preferably, in order to make the output port not in a floating state, the above driving circuit further includes a third voltage level converter to provide the HZ signal of the above first HZ state as the voltage VNEG.

[0018] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the first voltage level converter described above includes two medium-voltage transistors for respectively outputting the first signal described above to the medium-voltage logic circuit.

[0019] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the second voltage level converter described above includes two medium-voltage transistors for respectively outputting the second signal described above to the medium-voltage logic circuit.

[0020] Preferably, in order to reduce the chip area and operating power of the medium-voltage logic circuit, the medium-voltage logic circuit described above includes: two medium-voltage transistors for respectively receiving the set of HZ signals described above; two transistors for respectively receiving the first signal and the second signal described above, wherein the voltage of the first signal is the voltage VCC or the voltage VNEG, the voltage of the second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND; and two high-voltage transistors for receiving the voltage VNEG.

[0021] Preferably, in order to be able to control the drive circuit with fewer logic bits and reduce the operating power of the control logic circuit, the third set of input signals described above includes two logic bits, and the maximum operating voltage of the control logic circuit is lower than the voltage VPOS.

[0022] According to an embodiment of the present application, a liquid crystal screen is provided, characterized by comprising: a liquid crystal display; and the drive circuit described above for controlling the display of the pixels of the liquid crystal display through the output port.

[0023] According to an embodiment of the present application, an electronic paper is provided, comprising: an electronic paper display; and the drive circuit described above for controlling the display of the pixels of the electronic paper display through the output port.

[0024] Due to the above solution, the beneficial effects of the present application are as follows: The present application provides a drive circuit that can use fewer high-voltage components. Especially in the case of reducing the use of voltage level converters and high-voltage components and switching to medium-voltage components, it saves chip area and operating power consumption. It can also be switched to a floating state first when the output high voltage is switched, so as to reduce leakage current and improve the reliability and lifespan of the integrated circuit.

[0025] Furthermore, the driving circuit provided by the present application reduces the number of voltage level converters through the use of a medium-voltage logic circuit and can also provide four output states; compared with the logic circuit operating at a high voltage VPOS and the conventional voltage level converter, the medium-voltage logic circuit operating at a lower voltage and the voltage level converter provided by the present application can save more operating power. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 6 is a block diagram of an existing liquid crystal display screen 100.

[0027] Figure 2 FIG. 10 is a timing diagram of various possible states of the output ports of the output stage circuit 122 or 132.

[0028] Figure 3 FIG. 14 is a timing diagram of the operating voltage of the driving circuit according to an embodiment of the present application.

[0029] Figure 4 FIG. 18 is a block diagram of a driving circuit 400 according to an embodiment of the present application.

[0030] Figure 5 FIG. 22 is a block diagram of an output switch circuit 440 according to an embodiment of the present application.

[0031] Figure 6A FIG. 26 is a schematic diagram of a switch circuit 510 according to an embodiment of the present application.

[0032] Figure 6B FIG. 30 is a schematic diagram of a switch circuit 510 according to another embodiment of the present application.

[0033] Figure 6C FIG. 34 is a schematic diagram of a switch circuit 510 according to still another embodiment of the present application.

[0034] Figure 7A FIG. 38 is a block diagram of an output switch circuit 440 according to an embodiment of the present application.

[0035] Figure 7B FIG. 42 is a block diagram of an output switch circuit 440 according to another embodiment of the present application.

[0036] Figure 7C FIG. 46 is a block diagram of an output switch circuit 440 according to another embodiment of the present application.

[0037] Figure 8 FIG. 50 shows a block diagram of a level conversion logic circuit 430 according to an embodiment of the present application.

[0038] Figure 9AA circuit schematic diagram of a voltage level converter 810 according to an embodiment of the present application.

[0039] Figure 9B A circuit schematic diagram of a voltage level converter 810 according to another embodiment of the present application.

[0040] Figure 10A A circuit schematic diagram of a medium - voltage logic circuit 820 according to an embodiment of the present application.

[0041] Figure 10B A circuit schematic diagram of a medium - voltage logic circuit 820 according to another embodiment of the present application.

[0042] Figure 10C A circuit schematic diagram of a medium - voltage logic circuit 820 according to another embodiment of the present application.

[0043] Figure 11 A schematic diagram when the medium - voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application output a positive potential VPOS.

[0044] Figure 12 A schematic diagram when the medium - voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application output a ground potential GND.

[0045] Figure 13 A schematic diagram when the medium - voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application output a negative potential VNEG.

[0046] Figure 14 A schematic diagram when the medium - voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application make the output port 450 at a floating potential. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other implementation manners obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope protected by the present application.

[0048] In the description of this application, the terms "first", "second", "third", etc. (if any) in the specification, claims, and drawings of this application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such described objects can be interchanged under appropriate circumstances. In the description of this application, the meaning of "a plurality of" is two or more, unless otherwise specifically defined. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. Such functional entities can be implemented in software form, or implemented in one or more hardware circuits or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0049] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of this application.

[0050] In the description of this application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the foregoing terms in this application can be understood according to specific circumstances.

[0051] To make the objectives, features, and advantages of this application more obvious and understandable, the following further describes this application in detail with reference to the drawings and specific embodiments.

[0052] Please refer to Figure 3 as shown, which is a timing diagram of the operating voltage of a drive circuit according to an embodiment of this application. In Figure 3Among them, it can be seen that the high voltage VPOS is greater than the voltage VCC, the voltage VCC is greater than the ground potential GND, and the ground potential GND is greater than the high voltage VNEG. Those of ordinary skill in the art can understand that if the components of the driving circuit can operate between the voltage VCC and GND, they are more power-saving and area-saving than the components that operate between VPOS and GND. Similarly, if the components of the driving circuit can operate between the voltage VCC and VNEG, they are more power-saving and area-saving than the components that operate between VPOS and VNEG. And the logic circuit usually operates between the voltage VDD and GND. The voltage VDD is usually lower than the voltage VCC. In some embodiments, the logic circuit can also operate between the voltage VCC and GND. The above-mentioned voltage VCC and voltage VDD can be referred to as medium voltages.

[0053] To adjust the output signal of the control circuit, that is, the output voltage of the logic circuit, from the lower voltage VDD or VCC to the higher voltage VPOS or VNEG, LVSH is usually required. This process can also be referred to as digital-to-analog conversion (DAC).

[0054] Please refer to Figure 4 As shown, it is a block diagram of a driving circuit 400 according to an embodiment of the present application. The driving circuit 400 can be applicable to driving the drain or source of a liquid crystal display or an electronic paper display. The driving circuit 400 can include a control logic circuit 410, a digital-to-analog converter 420, and an output port 450. The control logic circuit 410 is used to output a control signal to the digital-to-analog converter 420. The control logic circuit 410 can operate between the voltage VDD and GND, or can operate between the voltage VCC and GND.

[0055] Those of ordinary skill in the art can understand that the control logic circuit 410 can include any combination of the above-mentioned various types of transistors and logic gates or an equivalent circuit of any combination to achieve the purpose of controlling the digital-to-analog converter 420.

[0056] The digital-to-analog converter 420 includes a level conversion logic circuit 430 and an output switch circuit 440. In other words, the control logic circuit 410 can be used to control the level conversion logic circuit 430 and the output switch circuit 440. In order to raise the voltage of the output port 450 from VDD or VCC to VPOS or VNEG, the level conversion logic circuit 430 can include two LVSH and a logic circuit of medium voltage. In the following Figure 8 Among them, a further explanation of the level conversion logic circuit 430 will be made.

[0057] Please refer to Figure 5As shown, it is a block diagram of an output switch circuit 440 according to an embodiment of the present application. The above-mentioned output switch circuit 440 is also referred to as an output stage circuit. In order to make the output signal of the output port 450 be one of the aforementioned four states, the output switch circuit 440 may include three switch circuits, namely a first switch circuit 510A, a second switch circuit 510B, and a third switch circuit 510C. The designs of these three switch circuits may be the same as or different from each other. The outputs of these three switches are coupled to form the aforementioned output port 450. The input signals of the first switch circuit 510A, the second switch circuit 510B, and the third switch circuit 510C come from the aforementioned level conversion logic circuit 430, and are respectively referred to as interface A, interface B, and interface C.

[0058] According to the design of each switch circuit, interface A, interface B, or interface C may vary. Interface A, interface B, or interface C may include one or more signals. The one or more signals may be Figure 3 one of the voltages VPOS, VNEG, VCC, VDD, or GND shown.

[0059] Please refer to Figure 6A As shown, it is a schematic diagram of a switch circuit 510 according to an embodiment of the present application. The switch circuit 510 includes a P-type transistor and an N-type transistor whose drains are connected to form an output port, and it operates between the voltages VPOS and VNEG and belongs to high-voltage components. The output port of the switch circuit is coupled to the aforementioned output port 450.

[0060] Please refer to Figure 6B As shown, it is a schematic diagram of a switch circuit 510 according to another embodiment of the present application. The switch circuit 510 includes a P-type transistor and belongs to high-voltage components. The drain of the switch circuit 510 is coupled to the aforementioned output port 450, and the source is connected to the voltage VPOS..

[0061] Please refer to Figure 6C As shown, it is a schematic diagram of a switch circuit 510 according to still another embodiment of the present application. The switch circuit 510 includes an N-type transistor and belongs to high-voltage components. The drain of the switch circuit 510 is coupled to the aforementioned output port 450, and the source is connected to the voltage VNEG.

[0062] Those of ordinary skill in the art can understand that Figures 6A to 6C any one of the switch circuits 510 shown can be applicable to Figure 5 one of the first switch circuit 510A, the second switch circuit 510B, and the third switch circuit 510C shown.

[0063] Please refer to Figure 7AAs shown, it is a block diagram of an output switch circuit 440 according to an embodiment of the present application. Incorporating Figures 6A to 6C three embodiments of the switch circuit 510 among Figure 7A The first switch circuit 510A shown uses Figure 6A the switch circuit 510 shown, the second switch circuit 510B uses Figure 6B the switch circuit 510 shown, and the third switch circuit 510C uses Figure 6C the switch circuit 510 shown.

[0064] Please refer to Figure 7B As shown, it is a block diagram of an output switch circuit 440 according to another embodiment of the present application. Incorporating Figure 6A and Figure 6C two embodiments of the switch circuit 510 among Figure 7B The first switch circuit 510A shown uses Figure 6A the switch circuit 510 shown, the second switch circuit 510B uses Figure 6A the switch circuit 510 shown, and the third switch circuit 510C uses Figure 6C the switch circuit 510 shown.

[0065] Please refer to Figure 7C As shown, it is a block diagram of an output switch circuit 440 according to another embodiment of the present application. Incorporating Figure 6A the embodiment of the switch circuit 510 Figure 7C The first switch circuit 510A, the second switch circuit 510B, and the third switch circuit 510C shown all use Figure 6A the switch circuit 510 shown.

[0066] By Figures 7A to 7C the three embodiments, the applicant believes that those of ordinary skill in the art can freely use any combination of various switch circuits 510 to implement the aforementioned output switch circuit 440.

[0067] Please refer to Figure 8As shown, it is a block diagram of a level conversion logic circuit 430 according to an embodiment of the present application. The level conversion logic circuit 430 includes a first voltage level converter 810A, a second voltage level converter 810B, and a mid-voltage logic circuit 820. The level conversion logic circuit 430 receives the control of the control logic circuit 410 for controlling the first signal XXI1_A output by the first voltage level converter 810A. Similarly, the level conversion logic circuit 430 receives the control of the control logic circuit 410 for controlling the second signal XXI1_B output by the second voltage level converter 810B. In one embodiment, the above-mentioned first signal XXI1_A and second signal XXI1_B can each be a logic bit. The first state of the logic bit is voltage VCC, and the second state of the logic bit is voltage VNEG.

[0068] The above-mentioned first voltage level converter 810A is connected to the first switch circuit 510A of the aforementioned output switch circuit 440 through interface A. Similarly, the above-mentioned second voltage level converter 810B is connected to the second switch circuit 510B of the aforementioned output switch circuit 440 through interface B.

[0069] The above-mentioned mid-voltage logic circuit 820 obtains a floating signal HZ or a pair of signals from the control logic circuit 410, that is, the floating signal HZ and its inverted floating signal XHZ signal. It also obtains the first signal XXI1_A from the above-mentioned first voltage level converter 810A and the second signal XXI1_B from the above-mentioned second voltage level converter 810B. The above-mentioned mid-voltage logic circuit 820 is connected to the third switch circuit 510C of the aforementioned output switch circuit 440 through interface C.

[0070] Please refer to Figure 9A As shown, it is a circuit diagram of a voltage level converter 810 according to an embodiment of the present application. The voltage level converter 810 can be divided into left and right sides. The left circuit includes two mid-voltage P-type transistors MVP1 and MVP2. Different from the other transistors of the voltage level converter 810, the drains of these two mid-voltage P-type transistors MVP1 and MVP2 are connected to mid-voltage VCC, and their sources are respectively connected to four high-voltage N-type transistors HVN1 to HVN4. The right circuit includes two high-voltage P-type transistors HVP1 and HVP2 and two high-voltage N-type transistors HVN5 and HVN6. The right circuit operates between high-voltage VPOS and VNEG.

[0071] In Figure 9A the embodiment, the source of the mid-voltage P-type transistor MVP2 is coupled to the drain of the high-voltage N-type transistor HVN2 and the gates of the high-voltage N-type transistors HVN2, HVN3, and HVN6, which is the signal XXI1.

[0072] Please refer to Figure 9B as shown, which is a circuit schematic diagram of a voltage level converter 810 according to another embodiment of the present application. Figure 9B The voltage level converter 810 shown only includes Figure 9A the left - hand circuit of the voltage level converter 810 shown, omitting the four high - voltage transistors HVP1, HVP2, HVN5, and HVN6 in the right - hand circuit.

[0073] Similarly, in Figure 9B the embodiment of, the source of the medium - voltage P - type transistor MVP2 is coupled to the drain of the high - voltage N - type transistor HVN2 and the gates of the high - voltage N - type transistors HVN2 and HVN3, which is the signal XXI1.

[0074] Those of ordinary skill in the art can understand that Figure 9A or Figure 9B the voltage level converter 810 shown can be applicable to Figure 8 the first voltage level converter 810A or the second voltage level converter 810B shown. When it is applicable to the first voltage level converter 810A, the aforementioned signal XXI1 is Figure 8 the first signal XXI1_A shown. When it is applicable to the second voltage level converter 810B, the aforementioned signal XXI1 is Figure 8 the second signal XXI1_B shown.

[0075] Please refer to Figure 10A as shown, which is a circuit schematic diagram of a medium - voltage logic circuit 820 according to an embodiment of the present application. The right - hand side of the medium - voltage logic circuit 820 is interface C. The medium - voltage logic circuit 820 includes two medium - voltage P - type transistors MVP11 and MVP12. The right - hand side of the medium - voltage logic circuit 820 also includes two P - type transistors and two high - voltage N - type transistors. The sources of the two high - voltage N - type transistors are respectively connected to the voltage VNEG. The gates of the medium - voltage P - type transistors MVP11 and MVP12 are respectively connected to the signal XHZ and its inverted signal HZ, which can come from Figure 4 the control logic circuit 410 shown.

[0076] The above-mentioned signal XHZ and its inverted signal HZ are used to control the output switch circuit 440 to be in a floating state. In one embodiment, when the signal XHZ is at the potential GND, the inverted signal HZ is at the potential VCC. Conversely, when the signal XHZ is at the potential VCC, the inverted signal HZ is at the potential GND. In another embodiment, when the signal XHZ is at the potential VNEG, the inverted signal HZ is at the potential VCC. Conversely, when the signal XHZ is at the potential VCC, the inverted signal HZ is at the potential VNEG. In this embodiment, an additional voltage level converter needs to be connected separately to convert the ground potential GND into the high-voltage potential VNEG.

[0077] Please refer to Figure 10B as shown, which is a circuit schematic diagram of the medium-voltage logic circuit 820 according to another embodiment of the present application. On the right side of the medium-voltage logic circuit 820 is interface C. The medium-voltage logic circuit 820 includes two medium-voltage P-type transistors MVP17 and MVP18. On the left side of the medium-voltage logic circuit 820 also includes two P-type transistors and two high-voltage N-type transistors. The gates of the medium-voltage P-type transistors MVP17 and MVP18 are respectively connected to the signal XHZ and its inverted signal HZ, which come from Figure 4 the control logic circuit 410 shown.

[0078] Please refer to Figure 10C as shown, which is a circuit schematic diagram of the medium-voltage logic circuit 820 according to another embodiment of the present application. On the right side of the medium-voltage logic circuit 820 is interface C. The medium-voltage logic circuit 820 includes two medium-voltage P-type transistors MVP21 and MVP22. The medium-voltage logic circuit 820 includes two P-type transistors and two high-voltage N-type transistors. The gates of the medium-voltage P-type transistors MVP21 and MVP22 are respectively connected to the signal XHZ and its inverted signal HZ, which come from Figure 4 the control logic circuit 410 shown.

[0079] The medium-voltage logic circuit 820 is connected to the third switch circuit 510C of the aforementioned output switch circuit through interface C. From Figures 10A to 10C the embodiment, it can be seen that since the medium-voltage logic circuit 820 does not access the high-voltage potential VPOS, the potential output by it can be VCC, GND or VNEG.

[0080] Next, taking the medium-voltage logic circuit 820 shown in Figure 10A and the output switch circuit 440 shown in Figure 7C as embodiments, the working states of the medium-voltage logic circuit 820 and the output switch circuit 440 are explained respectively for the output port 450 being at the voltage VPOS, GND, VNEG and the floating state HiZ.

[0081] Please refer to Figure 11As shown, it is a schematic diagram when the medium-voltage logic circuit 820 and the output switch circuit 440 output the potential VPOS according to an embodiment of the present application. In this embodiment, when the control logic circuit 410 makes the gate of the P-type transistor of the first switch circuit 510A receive the voltage VPOS provided by the interface A, and makes the gate of the N-type transistor of the first switch circuit 510A receive the voltage VNEG provided by the interface A, it will cause the first switch circuit 510A not to conduct.

[0082] When the control logic circuit 410 makes the gate of the P-type transistor of the second switch circuit 510B receive the voltage VNEG provided by the interface B, and makes the gate of the N-type transistor of the second switch circuit 510B receive the voltage VPOS provided by the interface B, it causes the second switch circuit 510B to be conductive.

[0083] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium-voltage P-type transistor MVP11 is turned off and the other medium-voltage P-type transistor MVP12 is conductive. Since the first signal XXI1_A output by the first voltage level converter 810A is at the voltage VNEG and the second signal XXI1_B output by the second voltage level converter 810B is at the voltage VCC, it causes the N-type transistor on the right to conduct, making the output signal of the interface C at the voltage VNEG, resulting in the third switch circuit 510C being cut off.

[0084] Since among the three switch circuits of the output switch circuit 440, the second switch circuit 510B is conductive and the other two switch circuits 510A and 510C are cut off, the output port 450 is at the potential VPOS.

[0085] Please refer to Figure 12 As shown, it is a schematic diagram when the medium-voltage logic circuit 820 and the output switch circuit 440 output the ground potential GND according to an embodiment of the present application. In this embodiment, when the control logic circuit 410 makes the gate of the P-type transistor of the first switch circuit 510A receive the voltage VNEG provided by the interface A, and makes the gate of the N-type transistor of the first switch circuit 510A receive the voltage VPOS provided by the interface A, it causes the first switch circuit 510A to be conductive.

[0086] When the control logic circuit 410 makes the gate of the P-type transistor of the second switch circuit 510B receive the voltage VPOS provided by the interface B, and makes the gate of the N-type transistor of the second switch circuit 510B receive the voltage VNEG provided by the interface B, it will cause the second switch circuit 510B not to conduct.

[0087] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium-voltage P-type transistor MVP11 is turned off and the other medium-voltage P-type transistor MVP12 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VCC and the second signal XXI1_B output by the second voltage level converter 810B is at the voltage VNEG, the N-type transistor on the left side is turned on, making the signal of interface C the voltage VNEG, resulting in the third switch circuit 510C being cut off.

[0088] Among the three switch circuits of the output switch circuit 440, since the first switch circuit 510A is turned on and the other two switch circuits 510B and 510C are cut off, the output port 450 is at the voltage GND.

[0089] Please refer to Figure 13 As shown, it is a schematic diagram when the medium-voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application output the potential VNEG. In this embodiment, when the control logic circuit 410 makes the gate of the P-type transistor of the first switch circuit 510A receive the voltage VPOS and makes the gate of the N-type transistor of the first switch circuit 510A receive the voltage VNEG, the first switch circuit 510A is cut off.

[0090] When the control logic circuit 410 makes the gate of the P-type transistor of the second switch circuit 510B receive the voltage VPOS and makes the gate of the N-type transistor of the second switch circuit 510B receive the voltage VNEG, the second switch circuit 510B will not conduct.

[0091] When the signal HZ is at the potential GND and its inverted signal XHZ is at the potential VCC, the medium-voltage P-type transistor MVP11 is turned off and the other medium-voltage P-type transistor MVP12 is turned on. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VNEG and the second signal XXI1_B output by the second voltage level converter 810B is also at the potential VNEG, the P-type transistors MVP13 and MVP14 are respectively turned on and the N-type transistors on the left and right sides are turned off. Accordingly, the potential of signal C is VCC, further making the third switch circuit 510C conduct.

[0092] Among the three switch circuits of the output switch circuit 440, since the third switch circuit 510C is turned on and the other two switch circuits 510A and 510B are cut off, the output port 450 is at the potential VNEG.

[0093] Please refer to Figure 14As shown, it is a schematic diagram when the medium-voltage logic circuit 820 and the output switch circuit 440 according to an embodiment of the present application make the output port 450 at a floating potential. In this embodiment, when the control logic circuit 410 makes the gate of the P-type transistor of the first switch circuit 510A connected to the voltage VPOS and makes the gate of the N-type transistor of the first switch circuit 510A connected to the voltage VNEG, the first switch circuit 510A is turned off.

[0094] When the control logic circuit 410 makes the gate of the P-type transistor of the second switch circuit 510B connected to the voltage VPOS and makes the gate of the N-type transistor of the second switch circuit 510B connected to the voltage VNEG, the second switch circuit 510B will not conduct.

[0095] To turn off the medium-voltage P-type transistor MVP12, the signal HZ is made at the VCC potential. Its inverted signal XHZ is at the GND potential or the VNEG potential, making the medium-voltage P-type transistor MVP11 conduct. Since the first signal XXI1_A output by the first voltage level converter 810A is at the potential VNEG and the second signal XXI1_B output by the second voltage level converter 810B is also at the potential VNEG, the signal C is at the potential VNEG accordingly, causing the third switch circuit 510C not to conduct either.

[0096] Since the three switch circuits 510A, 510B, and 510C of the output switch circuit 440 are all non-conductive, the potential of the output port 450 is floating.

[0097] Back to Figure 4 , to control the output port 450 of the drive circuit 400 to output one of the aforementioned four voltages, the control logic circuit 410 only needs a set of N-bit input signals and the HZ signal, and N can be 2. In the level conversion logic circuit 430, there are N voltage level converters 810. The number of output voltage types of the output port 450 is 2 to the Nth power, that is, 2 to the 2nd power, 4 voltage outputs. According to the above various embodiments, the following table of the output signals and output signals of the drive circuit 400 can be obtained.

[0098]

[0099]

[0100] As described above, the present application provides a voltage level converter 810 with a medium voltage component, which occupies less chip area and has lower power consumption during operation compared to a conventional voltage level converter without a medium voltage component. The first signal XXI1_A and the second signal XXI1_B respectively output therefrom can be used to assist a medium voltage logic circuit in controlling an output switch circuit 440, so that the latter can output a floating state, reducing the instantaneous current or leakage current during voltage switching.

[0101] If three voltage level converters are used to separately control three switch circuits 510, an additional voltage level converter will occupy a larger chip area. In addition to the transition current, when the three voltage level converters convert voltages together, it will cause instability of the overall current.

[0102] The present application provides a driving circuit that can use fewer high voltage components. In particular, in the case of reducing the use of voltage level converters and high voltage components and switching to medium voltage components, it can save chip area and power consumption during operation, and can also be converted to a floating state first when the output high voltage is switched, so as to reduce leakage current and improve the reliability and lifespan of the integrated circuit.

[0103] According to an embodiment of the present application, there is provided a driving circuit, characterized in that it includes: an output port, which is in one of the following four states: voltage VPOS, ground voltage GND, voltage VNEG, and floating state, wherein the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; an output switch circuit, which includes a first switch circuit, a second switch circuit, and a third switch circuit, and the outputs of the above-mentioned first switch circuit, the above-mentioned second switch circuit, and the above-mentioned third switch circuit are all coupled to the above-mentioned output port; a first voltage level converter, used to connect to the first switch circuit; a second voltage level converter, used to connect to the second switch circuit; a medium voltage logic circuit, receiving a first signal from the first voltage level converter, receiving a second signal from the second voltage level converter, and a set of HZ signals, and used to connect to the third switch circuit; and a control logic circuit, used to, when receiving a third set of input signals and the set of HZ signals are in a second HZ state, make the first voltage level converter control the first switch circuit to turn off, make the second voltage level converter control the second switch circuit to turn off, and the medium voltage logic circuit make the third switch circuit turn off, so that the output port is in the floating state.

[0104] Preferably, in order to make the output port output a driving signal of high voltage, such as voltage VPOS, when the above control logic circuit receives the first group of input signals and the group of HZ signals are in the first HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to conduct, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are in antiphase with each other.

[0105] Preferably, in order to make the output port output a driving signal of ground potential, when the above control logic circuit receives the second group of input signals and the group of HZ signals are in the first HZ state, the first voltage level converter is made to control the first switching circuit to conduct, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are in antiphase with each other.

[0106] Preferably, in order to make the output port output a driving signal of high voltage, such as voltage VNEG, when the above control logic circuit receives the third group of input signals and the group of HZ signals are in the first HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit conduct, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are in antiphase with each other.

[0107] Preferably, in order to make the output port in a floating state, when the above control logic circuit receives the fourth group of input signals and the group of HZ signals are in the second HZ state, the first voltage level converter is made to control the first switching circuit to cut off, the second voltage level converter is made to control the second switching circuit to cut off, and the medium voltage logic circuit makes the third switching circuit cut off, so that the output port is in the floating state.

[0108] Preferably, in order to make the output port in a floating state, the HZ signal of the above second HZ state is voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

[0109] Preferably, in order to make the output port not in a floating state, the HZ signal of the above first HZ state is voltage GND.

[0110] Preferably, in order to make the output port not in a floating state, the above driving circuit further includes a third voltage level converter to provide the HZ signal of the above first HZ state as voltage VNEG.

[0111] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the above-mentioned first voltage level converter includes two medium-voltage transistors for respectively outputting the above-mentioned first signal to the medium-voltage logic circuit.

[0112] Preferably, in order to reduce the chip area and operating power of the voltage level converter, the above-mentioned second voltage level converter includes two medium-voltage transistors for respectively outputting the above-mentioned second signal to the medium-voltage logic circuit.

[0113] Preferably, in order to reduce the chip area and operating power of the medium-voltage logic circuit, the above-mentioned medium-voltage logic circuit includes: two medium-voltage transistors for respectively receiving the above-mentioned set of HZ signals; two transistors for respectively receiving the above-mentioned first signal and the above-mentioned second signal, wherein the voltage of the above-mentioned first signal is voltage VCC or the voltage VNEG, the voltage of the above-mentioned second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, the voltage VCC is greater than the ground voltage GND; and two high-voltage transistors for receiving the voltage VNEG.

[0114] Preferably, in order to only require fewer logic bits to control the drive circuit and reduce the operating power of the control logic circuit, the above-mentioned third set of input signals includes two logic bits, and the maximum operating voltage of the above-mentioned control logic circuit is lower than the voltage VPOS.

[0115] According to an embodiment of the present application, there is provided a liquid crystal screen, characterized in that it includes: a liquid crystal display; and the drive circuit as described above for controlling the display of the pixels of the liquid crystal display through the output port.

[0116] According to an embodiment of the present application, there is provided an electronic paper, including: an electronic paper display; and the drive circuit as described above for controlling the display of the pixels of the electronic paper display through the output port.

[0117] As described above, only the preferred specific embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, according to the technical solution and application concept of the present application, makes equivalent substitutions or changes, and should be covered within the protection scope of the present application.

Claims

1. A liquid crystal screen, characterized in that: Include: Liquid crystal display; and The drive circuit includes: An output port, which is in one of the following four states: a voltage VPOS, a ground voltage GND, a voltage VNEG, and a floating state, wherein the voltage VPOS is greater than the ground voltage GND, and the ground voltage GND is greater than the voltage VNEG; An output switch circuit, comprising a first switch circuit, a second switch circuit and a third switch circuit, wherein outputs of the first switch circuit, the second switch circuit and the third switch circuit are all coupled to the output port to control the display of pixels of the liquid crystal display; A first voltage level converter, used for connecting to the first switch circuit; A second voltage level converter, used for connecting to the second switch circuit; A medium voltage logic circuit receives a first signal from the first voltage level converter, a second signal from the second voltage level converter, and a set of HZ signals for connecting to the third switch circuit; as well as The control logic circuit is used to control the first switch circuit to be cut off by the first voltage level converter, control the second switch circuit to be cut off by the second voltage level converter, and control the third switch circuit to be cut off by the medium voltage logic circuit when a third group of input signals is received and the group of HZ signals is in the second HZ state, so that the output port is in the floating state, and the HZ signal of the second HZ state is a voltage VCC, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND.

2. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives a first set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned off, the second voltage level converter controls the second switch circuit to be turned on, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the voltage VPOS, wherein the first HZ state and the second HZ state are inverse to each other.

3. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the second set of input signals and the set of HZ signals is in the first HZ state, the first voltage level converter controls the first switch circuit to be turned on, the second voltage level converter controls the second switch circuit to be turned off, and the medium voltage logic circuit turns off the third switch circuit, so that the output port is at the ground voltage GND, wherein the first HZ state and the second HZ state are inverse to each other.

4. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the third set of input signals and the set of HZ signals in the first HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit turns on the third switch circuit, so that the output port is at the voltage VNEG, wherein the first HZ state and the second HZ state are inverse to each other.

5. The liquid crystal screen according to claim 1, characterized in that: When the control logic circuit receives the fourth set of input signals and the set of HZ signals is in the second HZ state, the first voltage level converter controls the first switch circuit to be cut off, the second voltage level converter controls the second switch circuit to be cut off, and the medium voltage logic circuit controls the third switch circuit to be cut off, so that the output port is in the floating state.

6. The liquid crystal screen according to any one of claims 2 to 4, characterized in that: The HZ signal in the first HZ state is a voltage of GND.

7. The liquid crystal screen according to any one of claims 2 to 4, characterized in that: The driving circuit further includes a third voltage level converter to provide the HZ signal in the first HZ state as a voltage VNEG.

8. The liquid crystal screen according to claim 1, characterized in that: The first voltage level converter includes two medium voltage transistors for correspondingly outputting the first signal to the medium voltage logic circuit.

9. The liquid crystal screen according to claim 1, characterized in that: The second voltage level converter includes two medium voltage transistors for correspondingly outputting the second signal to the medium voltage logic circuit.

10. The liquid crystal screen according to claim 1, characterized in that: The above-mentioned medium voltage logic circuit comprises: Two medium voltage transistors, used for respectively receiving the above-mentioned group of HZ signals; Two transistors, for respectively receiving the first signal and the second signal, wherein the voltage of the first signal is the voltage VCC or the voltage VNEG, the voltage of the second signal is the voltage VCC or the voltage VNEG, wherein the voltage VPOS is greater than the voltage VCC, and the voltage VCC is greater than the ground voltage GND; and Two high-voltage transistors are used to receive the voltage VNEG.

11. The liquid crystal screen according to claim 1, characterized in that: The third set of input signals includes two logic bits, and the maximum operating voltage of the control logic circuit is lower than the voltage VPOS.

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