Semiconductor frame and semiconductor package including same

Abstract

The invention provides a semiconductor frame and a semiconductor package including the same. The semiconductor frame includes: a lead frame including a mounting portion configured to mount a semiconductor element, a wiring portion spaced apart from the mounting portion, and a lead-out portion extending from the wiring portion; and an insulating layer that overlaps the mounting portion of the lead frame and is provided so as not to overlap the lead-out portion of the lead frame.

Description

Technical Field

[0001] The following description relates to a semiconductor frame and a semiconductor package including the same. Background Art

[0002] As semiconductor devices develop, highly integrated semiconductor packages are being produced.

[0003] If heat is generated internally when a semiconductor element included in a semiconductor package operates, and the internal heat is not dissipated to the outside, the temperature of the semiconductor element may rise and a failure rate of the element may increase.

[0004] In particular, when the semiconductor element included in the semiconductor package is a power semiconductor element, since the power semiconductor element can be driven using a high voltage and a high current, the heat generated when the power semiconductor element is driven increases. The performance of the power semiconductor element may deteriorate and energy loss may occur or an insulating layer inside the semiconductor package may be damaged, thereby reducing the reliability of the semiconductor package due to the heat generated when the power semiconductor element is driven.

[0005] On the other hand, it is beneficial to maintain the heat resistance and physical strength of a support substrate supporting a semiconductor element within a semiconductor package, and at the same time, efforts are required to prevent a complicated manufacturing process or defects such as disconnection of a connection portion.

[0006] The above information is presented as background information only to assist in understanding the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with respect to the present disclosure. Summary of the invention

[0007] This summary is provided to introduce selected concepts in a simplified form that are further described in the detailed description below. This summary is neither intended to identify key features or essential features of the claimed subject matter nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] In general terms, a semiconductor frame comprises: a lead frame including a mounting portion, a wiring portion and a lead-out portion, wherein the mounting portion is configured to mount a semiconductor element, the wiring portion is spaced apart from the mounting portion, and the lead-out portion extends from the wiring portion; and an insulating layer overlapping the mounting portion of the lead frame and arranged in a manner not to overlap the lead-out portion of the lead frame.

[0009] The semiconductor frame may further include a protection layer overlapping the insulating layer, wherein the insulating layer may be disposed between the lead frame and the protection layer.

[0010] The insulating layer may include polyimide, and the protective layer may include a metal material.

[0011] The protective layer may include a metal foil.

[0012] The thickness of the insulating layer may be substantially equal to or greater than the thickness of the protective layer.

[0013] The protective layer may include a copper clad laminate.

[0014] The thickness of the protection layer may be substantially equal to or greater than the thickness of the insulating layer.

[0015] The insulating layer may include a ceramic material.

[0016] In general terms, a semiconductor package includes: a first semiconductor frame, including a first lead frame and a first insulating layer arranged below the first lead frame; a second semiconductor frame, including a second lead frame facing the first lead frame and a second insulating layer arranged above the second lead frame; a semiconductor element arranged between the first semiconductor frame and the second semiconductor frame; and a molding portion surrounding and sealing at least a portion of the first semiconductor frame, at least a portion of the second semiconductor frame, and the semiconductor element.

[0017] The first lead frame may include: a mounting portion configured to mount the semiconductor element; a wiring portion spaced apart from the mounting portion; and a lead portion extending from the wiring portion, and wherein the first insulating layer and the second insulating layer may be arranged to overlap with the mounting portion of the first lead frame and to not overlap with the lead portion of the first lead frame.

[0018] The semiconductor package may further include: a first protection layer disposed under the first insulating layer; and a second protection layer disposed over the second insulating layer.

[0019] Each of the first insulating layer and the second insulating layer may include polyimide, and each of the first protective layer and the second protective layer may include a metal material.

[0020] A surface of the first protective layer may be exposed to an external environment without being surrounded by the molding part.

[0021] Each of the first protective layer and the second protective layer may include a metal foil.

[0022] The thickness of the first insulating layer may be substantially equal to or greater than the thickness of the first protective layer, and the thickness of the second insulating layer may be substantially equal to or greater than the thickness of the second protective layer.

[0023] Each of the first protective layer and the second protective layer may include a copper clad laminate.

[0024] The thickness of the first protective layer may be substantially equal to or greater than the thickness of the first insulating layer, and the thickness of the second protective layer may be substantially equal to or greater than the thickness of the second insulating layer.

[0025] Each of the first insulating layer and the second insulating layer may include a ceramic material.

[0026] A surface of the first insulating layer may be exposed to an external environment without being surrounded by the molding part.

[0027] The lead-out portion may be exposed to an external environment without being surrounded by the molded portion.

[0028] Other features and aspects will be readily apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An exploded perspective view of an example semiconductor frame is shown in accordance with one or more embodiments.

[0030] Figure 2 An exploded perspective view of an example semiconductor frame is shown in accordance with one or more embodiments.

[0031] Figure 3 An exploded perspective view of an example semiconductor frame is shown in accordance with one or more embodiments.

[0032] Figure 4 A perspective view of an example semiconductor package according to one or more embodiments is shown.

[0033] Figure 5 Shown along Figure 4 Cross-sectional view taken along line II'.

[0034] Figure 6 An example semiconductor package according to one or more embodiments is shown. Figure 5 The corresponding cross-sectional view.

[0035] Figure 7 An example semiconductor package according to one or more embodiments is shown. Figure 5 The corresponding cross-sectional view.

[0036] Throughout the drawings and detailed description, unless otherwise described, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and the relative size, proportion, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0037] Hereinafter, although examples of the present disclosure will be described in detail with reference to the accompanying drawings, it is noted that the examples are not limited thereto.

[0038] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, various variations, modifications and equivalents of the methods, devices and / or systems described herein will be readily understood after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but in addition to the operations that must occur in a particular order, changes that will be readily understood may be made after understanding the present disclosure. In addition, for clarity and brevity, descriptions of features known in the art may be omitted.

[0039] The features described herein may be implemented in different forms and will not be interpreted as being limited to the examples described herein. Rather, the examples described herein have been provided only to illustrate some of the many possible ways of implementing the methods, devices and / or systems described herein that will be readily understood after understanding the present disclosure.

[0040] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being "on", "connected to", or "coupled to" another element, the element may be directly "on", "connected to", or "coupled to" another element, or one or more other elements may be present between them. In contrast, when an element is described as being "directly on", "directly connected to", or "directly coupled to" another element, there are no other elements present between them.

[0041] As used herein, the term "and / or" includes any one of the relevant listed items or any combination of any two or more items; similarly, "at least one of..." includes any one of the relevant listed items or any combination of any two or more items.

[0042] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to in the examples may also be referred to as the second member, second component, second region, second layer, or second portion.

[0043] For ease of description, spatially relative terms such as "above", "above", "below", "below", etc. may be used here to describe the relationship of one element to another element as shown in the drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the element described as being "above" or "above" relative to another element will then be "below" or "below" relative to the other element. Therefore, the term "above" includes both above and below orientations depending on the spatial orientation of the device. The device can also be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used here will be interpreted accordingly.

[0044] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" list the presence of the stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0045] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but may include changes in shapes that occur during manufacturing.

[0046] Here, it is noted that the use of the term “may” with respect to an example (eg, with respect to what an example may include or implement) means that there is at least one example that includes or implements such a feature, and is not limited to all examples including or implementing such a feature.

[0047] The features of the examples described herein can be combined in various ways that will be readily understood after understanding the present disclosure. In addition, although the examples described herein have a variety of configurations, other configurations that will be readily understood after understanding the present disclosure are feasible.

[0048] Throughout the specification, patterns, vias, planes, lines, and electrical connection structures may include metal materials (e.g., conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc.), and may be formed according to a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a sputtering method, a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), etc., but this is not restrictive.

[0049] In all one or more examples, the dielectric layer and / or the insulating layer may be implemented with the following materials: a thermosetting resin (such as FR4, liquid crystal polymer (LCP), low temperature co-fired ceramic (LTCC) or epoxy resin), a thermoplastic resin (such as polyimide), a material formed by impregnating a thermosetting resin or a thermoplastic resin with an inorganic filler into a core material (such as glass fiber (for example, glass fabric with glass cloth as an example)) (such as a prepreg, Ajinomoto built-up film (ABF), FR-4, bismaleimide triazine (BT), photosensitive dielectric (PID) resin, copper clad laminate (CCL), glass, ceramic-based insulating material, etc.).

[0050] In all one or more examples, the radio frequency (RF) signal may have a format according to the following protocols, which are merely examples, and any other wireless protocols and wired protocols specified thereafter: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, fifth generation mobile communication technology (5G) protocols, but not limited to these.

[0051] One or more examples may provide a semiconductor frame and a semiconductor package including the same, which may dissipate heat inside the semiconductor package, may not complicate a manufacturing process, and may well support a semiconductor element.

[0052] Reference Figure 1 , an example semiconductor frame according to one or more embodiments will be described. Figure 1 is an exploded perspective view of an example semiconductor frame according to one or more embodiments.

[0053] Reference Figure 1According to one or more embodiments, the semiconductor frame SL1 may include: a base frame LF, a semiconductor element is mounted at or on the base frame LF; an insulating layer AL1 is disposed under the base frame LF and overlaps with at least a portion of the base frame LF; and a protective layer AL2 is disposed under the insulating layer AL1 and overlaps with at least a portion of the insulating layer AL1.

[0054] In an example, the base frame LF may be a lead frame. The base frame LF may include a mounting portion MP on which a semiconductor element is mounted, a wiring portion LP spaced apart from the mounting portion MP, and a lead-out portion OL extending from the wiring portion LP to the outside to receive a signal from the outside.

[0055] In an example, the base frame LF may include a metal material and may be made of a single layer. In a non-limiting example, the base frame LF may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, embodiments are not limited thereto.

[0056] The insulating layer AL1 may overlap the mounting portion MP of the base frame LF, and may not overlap the lead-out portion OL of the base frame LF.

[0057] The insulating layer AL1 may include an insulating material, and the insulating layer AL1 may have a high dielectric constant and high thermal conductivity. In an example, the insulating layer AL1 may include polyimide. However, the embodiment is not limited thereto.

[0058] The insulating layer AL1 may transfer heat generated during operation of the semiconductor element mounted at the base frame LF to the outside.

[0059] In an example, the protection layer AL2 may overlap the insulation layer AL1 .

[0060] The protection layer AL2 may include a metal, and in an example, the metal may be a metal foil including at least one of copper (Cu) and aluminum (Al). However, the embodiment is not limited thereto.

[0061] The protection layer AL2 may protect the insulating layer AL1 , and may increase the transfer of heat from the insulating layer AL1 , and may allow the heat generated or collected in the insulating layer AL1 to be easily transferred to the outside.

[0062] In an example, the thickness of the insulating layer AL1 may be substantially the same as the thickness of the protective layer AL2 , or, in an example, the thickness of the insulating layer AL1 may be greater than the thickness of the protective layer AL2 . However, embodiments are not limited thereto.

[0063] The insulating layer AL1 may support the base frame LF, and may prevent warping of the base frame LF.

[0064] The mounting portion MP and the wiring portion LP of the base frame LF may be supported by being attached to the insulating layer AL1 using an adhesive or a thermal compression method. However, the embodiment is not limited thereto.

[0065] The lead-out portion OL extending from the wiring portion LP may not be separated from the insulating layer AL1 together with the wiring portion LP supported by being attached to the insulating layer AL1 .

[0066] If the semiconductor element mounted on the mounting portion MP of the semiconductor frame SL1 is a power semiconductor element, the power semiconductor element may be heated during the process of outputting power in which the power semiconductor element is repeatedly turned on and off, thereby deteriorating the performance of the power semiconductor element. Typically, a power semiconductor element may be mounted on a mounting substrate in which a metal layer (such as a copper layer) and a circuit layer are stacked on both surfaces of a substrate layer including a ceramic-based alumina material. However, when the capacitance of the power semiconductor element increases, the size of the mounting substrate also increases. Therefore, the manufacturing process of the mounting substrate including multiple layers may be complicated, the manufacturing cost may increase, and defects such as warping may occur in the mounting substrate.

[0067] However, an example semiconductor frame SL1 according to one or more embodiments may include: a base frame LF, a semiconductor element is mounted at the base frame LF and the base frame LF is made of a metal layer; an insulating layer AL1 overlapping at least a portion of the base frame LF; and a protective layer AL2 overlapping at least a portion of the insulating layer AL1, and the base frame LF may be a lead frame. Therefore, the semiconductor element can be mounted on the base frame LF as a lead frame without the need for a complicated process of forming a mounting substrate, so that the manufacturing process can be simple and an increase in manufacturing cost can be prevented. In addition, the heat generated from the semiconductor element can be easily transferred to the outside through the insulating layer AL1 and the protective layer AL2, thereby preventing the performance of the semiconductor element from being deteriorated due to internal heat and warping of the base frame LF.

[0068] Reference Figure 2 , an example semiconductor frame according to one or more embodiments will be described. Figure 2 An exploded perspective view of an example semiconductor frame is shown in accordance with one or more embodiments.

[0069] Reference Figure 2 According to one or more embodiments, the semiconductor frame SL2 may include: a base frame LF, on which a semiconductor element is mounted; an insulating layer AL3, which is disposed under the base frame LF and overlaps with at least a portion of the base frame LF; and a protective layer AL4, which is disposed under the insulating layer AL3 and overlaps with at least a portion of the insulating layer AL3.

[0070] In an example, the base frame LF may be a lead frame. The base frame LF may include a mounting portion MP on which a semiconductor element is mounted, a wiring portion LP spaced apart from the mounting portion MP, and a lead-out portion OL extending from the wiring portion LP to the outside to receive a signal from the outside.

[0071] In an example, the base frame LF may include metal, and may be made of a single layer. In a non-limiting example, the base frame LF may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, embodiments are not limited thereto.

[0072] The insulating layer AL3 may overlap the mounting portion MP of the base frame LF, and may not overlap the lead-out portion OL of the base frame LF.

[0073] The insulating layer AL3 may include an insulating material, and the insulating layer AL3 may have a high dielectric constant and a high thermal conductivity. In an example, the insulating layer AL3 may include polyimide. However, the embodiment is not limited thereto.

[0074] The insulating layer AL3 may transfer heat generated during operation of the semiconductor element mounted at the base frame LF to the outside.

[0075] The insulating layer AL3 may support the base frame LF, and may prevent warping of the base frame LF.

[0076] The mounting portion MP and the wiring portion LP of the base frame LF may be supported by being attached to the insulating layer AL3 using an adhesive or a thermal compression method. However, the embodiment is not limited thereto.

[0077] The lead-out portion OL extending from the wiring portion LP may not be separated from the insulating layer AL3 together with the wiring portion LP supported by being attached to the insulating layer AL3.

[0078] In an example, the protection layer AL4 may overlap the insulating layer AL3.

[0079] In an example, the protection layer AL4 may include a metal material. In a non-limiting example, the protection layer AL4 may be a copper clad laminate (CCL), and may include at least one of copper (Cu) and aluminum (Al). However, embodiments are not limited thereto.

[0080] The protective layer AL4 can protect the insulating layer AL3, and can increase the transfer of heat from the insulating layer AL3, and can easily transfer the heat generated or collected in the insulating layer AL3 to the outside. In addition, the protective layer AL4 can prevent the base frame LF and the insulating layer AL3 from warping.

[0081] In an example, the thickness of the protection layer AL4 may be substantially the same as or greater than the thickness of the insulating layer AL3, and may be about one to about two times the thickness of the insulating layer AL3. However, embodiments are not limited thereto.

[0082] The semiconductor frame SL2 according to the embodiment may include: a base frame LF, a semiconductor element is mounted on the base frame LF and the base frame LF is made of a metal layer; an insulating layer AL3, overlapping the base frame LF; and a protective layer AL4, overlapping the insulating layer AL3, and the base frame LF may be a lead frame. Therefore, the semiconductor element can be mounted on the base frame LF as a lead frame without the need for a complicated process of forming a mounting substrate, so that the manufacturing process can be simple and an increase in manufacturing cost can be prevented. In addition, the heat generated from the semiconductor element can be easily transferred to the outside through the insulating layer AL3 and the protective layer AL4, thereby preventing the performance of the semiconductor element from being deteriorated due to internal heat. In addition, the insulating layer AL3 and the protective layer AL4 can prevent the warping of the base frame LF.

[0083] Reference Figure 3 , a semiconductor frame according to one or more embodiments will be described. Figure 3 An exploded perspective view of an example semiconductor frame is shown in accordance with one or more embodiments.

[0084] Reference Figure 3 , the semiconductor frame SL3 according to one or more embodiments may include: a base frame LF on which a semiconductor element is mounted; and an insulating layer AL5 disposed under the base frame LF and overlapping at least a portion of the base frame LF.

[0085] In an example, the base frame LF may be a lead frame. The base frame LF may include a mounting portion MP on which a semiconductor element is mounted, a wiring portion LP spaced apart from the mounting portion MP, and a lead-out portion OL extending from the wiring portion LP to the outside to receive a signal from the outside.

[0086] In an example, the base frame LF may include a metal material and may be made of a single layer. In a non-limiting example, the base frame LF may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, embodiments are not limited thereto.

[0087] In an example, the insulating layer AL5 may overlap the mounting portion MP of the base frame LF, and may not overlap the lead-out portion OL of the base frame LF.

[0088] In an example, the insulating layer AL5 may include a ceramic material. However, examples are not limited thereto.

[0089] The insulating layer AL5 may transfer heat generated during operation of the semiconductor element mounted on the base frame LF to the outside, may support the base frame LF, and may prevent warping of the base frame LF.

[0090] The mounting portion MP and the wiring portion LP of the base frame LF may be supported by being attached to the insulating layer AL5 using an adhesive or a thermal compression method. However, the embodiment is not limited thereto.

[0091] The lead-out portion OL extending from the wiring portion LP may not be separated from the insulating layer AL5 together with the wiring portion LP supported by being attached to the insulating layer AL5.

[0092] The semiconductor frame SL3 according to the embodiment may include: a base frame LF on which a semiconductor element is mounted and which is made of a metal layer; and an insulating layer AL5 overlapping the base frame LF, and the base frame LF may be a lead frame. Therefore, the semiconductor element may be mounted on the base frame LF as a lead frame without the need for a complicated process of forming a mounting substrate, so that the manufacturing process may be simple and an increase in manufacturing cost may be prevented. In addition, the heat generated from the semiconductor element may be easily transferred to the outside through the insulating layer AL5, thereby preventing the performance of the semiconductor element from being deteriorated due to internal heat.

[0093] Reference Figure 4 and Figure 5 , an example semiconductor package CHPK1 according to one or more embodiments will be described. Figure 4 shows a perspective view of an example semiconductor package according to one or more embodiments, Figure 5 Shown along Figure 4 Cross-sectional view taken along line II'.

[0094] Reference Figure 4 and Figure 5 An example semiconductor package CHPK1 according to one or more embodiments may include: a first semiconductor frame LSL and a second semiconductor frame USL facing each other; a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL; and a molding part ML sealing the plurality of semiconductor elements SCP.

[0095] The first semiconductor frame LSL may include a first base frame LF1 , a first insulating layer AL11 , and a first protective layer AL21 .

[0096] The second semiconductor frame USL may include a second base frame LF2 , a second insulating layer AL12 , and a second protection layer AL22 .

[0097] The first base frame LF1 of the first semiconductor frame LSL may include: a mounting part MP, on which a plurality of semiconductor components SCP are mounted; a wiring part LP, which is spaced apart from the mounting part MP; a lead-out part OL, which extends from the wiring part LP to the outside to receive a signal from the outside; a first connection part CP1, which extends outward from the mounting part MP to be assembled and connected to a semiconductor device; and a first connection hole CPH1, which is formed in the first connection part CP1.

[0098] The first insulating layer AL11 and the first protection layer AL21 of the first semiconductor frame LSL may overlap the mounting portion MP of the first base frame LF1 , and may not overlap the lead-out portion OL and the first connection portion CP1 of the first base frame LF1 .

[0099] The second base frame LF2 of the second semiconductor frame USL may include a mounting portion MP on which a plurality of semiconductor components SCP are mounted, a second connection portion CP2 extending outward from the mounting portion MP to be assembled and connected to a semiconductor device, and a second connection hole CPH2 formed in the second connection portion CP2.

[0100] The second insulating layer AL12 and the second protection layer AL22 of the second semiconductor frame USL may overlap with the mounting portion MP of the second base frame LF2 and may not overlap with the second connection portion CP2 of the second base frame LF2.

[0101] In addition, the first insulating layer AL11 and the second insulating layer AL12 may be disposed to overlap with the mounting portion MP of the first base frame LF1.

[0102] Each of the first base frame LF1 of the first semiconductor frame LSL and the second base frame LF2 of the second semiconductor frame USL may be a lead frame.

[0103] In an example, each of the first base frame LF1 and the second base frame LF2 may include a metal material and may be made of a single layer. In an example, each of the first base frame LF1 and the second base frame LF2 may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, the embodiment is not limited thereto.

[0104] Each of the first insulating layer AL11 of the first semiconductor frame LSL and the second insulating layer AL12 of the second semiconductor frame USL may include an insulating material, and each of the first insulating layer AL11 and the second insulating layer AL12 may have a high dielectric constant and high thermal conductivity. In an example, each of the first insulating layer AL11 and the second insulating layer AL12 may include polyimide. However, the embodiment is not limited thereto.

[0105] The first and second insulating layers AL11 and AL12 may transfer heat generated during operation of the plurality of semiconductor components SCP mounted between the first and second base frames LF1 and LF2 to the outside.

[0106] Each of the first protection layer AL21 of the first semiconductor frame LSL and the second protection layer AL22 of the second semiconductor frame USL may include a metal material, and in an example, each of the first protection layer AL21 of the first semiconductor frame LSL and the second protection layer AL22 of the second semiconductor frame USL may be a metal foil including at least one of copper (Cu) and aluminum (Al). However, the embodiment is not limited thereto.

[0107] The first protective layer AL21 and the second protective layer AL22 can respectively protect the first insulating layer AL11 and the second insulating layer AL12, and can respectively increase the transfer of heat from the first insulating layer AL11 and the second insulating layer AL12, so that the heat generated by the semiconductor device and the heat generated or collected in the first insulating layer AL11 and the second insulating layer AL12 can be easily transferred to the outside.

[0108] In the example, the thickness of the first insulating layer AL11 may be substantially the same as the thickness of the first protective layer AL21, or the thickness of the first insulating layer AL11 may be greater than the thickness of the first protective layer AL21, and the thickness of the second insulating layer AL12 may be substantially the same as the thickness of the second protective layer AL22, or the thickness of the second insulating layer AL12 may be greater than the thickness of the second protective layer AL22, but the embodiment is not limited thereto.

[0109] The first insulating layer AL11 and the second insulating layer AL12 may prevent warping of the first base frame LF1 and the second base frame LF2, respectively.

[0110] The first insulating layer AL11 may support the first base frame LF1. In an example, the mounting portion MP and the wiring portion LP of the first base frame LF1 may be supported by being attached to the first insulating layer AL11 using an adhesive or a heat press method. However, the embodiment is not limited thereto.

[0111] The lead-out portion OL extending from the wiring portion LP may not be separated from the first insulating layer AL11 together with the wiring portion LP supported by being attached to the first insulating layer AL11.

[0112] Similarly, the second insulating layer AL12 may support the second base frame LF2.

[0113] The plurality of semiconductor components SCP may be physically and electrically connected to the first base frame LF1 through the first contact portions SP1 , and may be physically and electrically connected to the second base frame LF2 through the second contact portions SP2 .

[0114] Each of the first contact portion SP1 and the second contact portion SP2 may include solder paste. However, the embodiment is not limited thereto.

[0115] The plurality of semiconductor components SCP may be mounted at the first base frame LF1 through the first contact portions SP1.

[0116] The plurality of semiconductor components SCP may receive electrical signals from the outside through the second contact portion SP2, the first base frame LF1, and the second semiconductor frame USL. The second base frame LF2 may be connected to the wiring portion LP of the first base frame LF1 through the third contact portion SP21, and the plurality of semiconductor components SCP may be connected to the second base frame LF2 connected to the wiring portion LP of the first base frame LF1 through the fourth contact portion SP22. However, the embodiment is not limited thereto.

[0117] In the example, the plurality of semiconductor elements SCP may be power semiconductor elements, the plurality of semiconductor elements SCP may receive a power signal applied to the lead-out portion OL of the first base frame LF1 through the third contact portion SP21, the fourth contact portion SP22, and the second base frame LF2, and the plurality of semiconductor elements SCP may receive a gate signal and a source signal from the second base frame LF2 through the second contact portion SP2. However, the embodiment is not limited thereto.

[0118] The molding part ML may surround and seal the first semiconductor frame LSL, the second semiconductor frame USL, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0119] The molding part ML may protect the first semiconductor frame LSL, the second semiconductor frame USL included therein, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0120] The lead-out portion OL, the first connection portion CP1, and the first connection hole CPH1 of the first base frame LF1 and the second connection portion CP2 and the second connection hole CPH2 of the second base frame LF2 may be exposed to the outside of the molding portion ML.

[0121] In addition, a surface of the first protection layer AL21 of the first semiconductor frame LSL may be exposed to the outside (or external environment) without being surrounded by the molding part ML.

[0122] The molding part ML may include a polymer having excellent insulation and protection characteristics, and in an example, the molding part ML may include an epoxy molding compound (EMC) or a polyimide-based material.

[0123] In the example semiconductor package CHPK1 according to one or more embodiments, a plurality of semiconductor elements SCP may be mounted between a first semiconductor frame LSL and a second semiconductor frame USL facing each other. The first semiconductor frame LSL may include: a first base frame LF1 made of a metal layer or a metal material; a first insulating layer AL11 overlapping the first base frame LF1; and a first protective layer AL21 overlapping the first insulating layer AL11, and the first base frame LF1 may be a lead frame, and the second semiconductor frame USL may include: a second base frame LF2 made of a metal layer or a metal material; a second insulating layer AL12 overlapping the second base frame LF2; and a second protective layer AL22 overlapping the second insulating layer AL12, and the second base frame LF2 may be a lead frame.

[0124] Therefore, a plurality of semiconductor components SCP can be mounted on the first base frame LF1 and the second base frame LF2 as lead frames, respectively, without the need for a complicated process of forming a separate mounting substrate, so that the manufacturing process can be simple and an increase in manufacturing cost can be prevented. In addition, a plurality of semiconductor components SCP can be mounted between the first semiconductor frame LSL and the second semiconductor frame USL facing each other, so that heat generated from the plurality of semiconductor components SCP can be easily transferred to the outside through the first insulating layer AL11, the second insulating layer AL12, the first protective layer AL21, the second protective layer AL22, and the lower and upper parts of the plurality of semiconductor components SCP. Therefore, the performance degradation of the semiconductor components SCP due to internal heat and warping of the first base frame LF1 and the second base frame LF2 can be prevented.

[0125] In addition, a surface of the first protection layer AL21 of the first semiconductor frame LSL may be exposed to the outside (or external environment) without being surrounded by the molding part ML, so that heat generated from the plurality of semiconductor elements SCP may be easily transferred to the outside.

[0126] Reference Figure 6 , an example semiconductor package CHPK2 according to one or more embodiments will be described. Figure 6 An example semiconductor package according to one or more embodiments is shown. Figure 5 The corresponding cross-sectional view.

[0127] Reference Figure 6 , the example semiconductor package CHPK2 according to one or more embodiments is similar to the semiconductor package CHPK2 according to the previous reference Figure 4 and Figure 5 The exemplary semiconductor package CHPK1 of the described embodiment is similar, and detailed description of the same constituent elements is omitted.

[0128] Reference Figure 6An example semiconductor package CHPK2 according to one or more embodiments may include: a first semiconductor frame LSL and a second semiconductor frame USL facing each other; a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL; and a molding part ML sealing the plurality of semiconductor elements SCP.

[0129] The first semiconductor frame LSL may include a first base frame LF1 , a first insulating layer AL31 , and a first protective layer AL41 .

[0130] The second semiconductor frame USL may include a second base frame LF2 , a second insulating layer AL32 , and a second protection layer AL42 .

[0131] Each of the first base frame LF1 of the first semiconductor frame LSL and the second base frame LF2 of the second semiconductor frame USL may be a lead frame.

[0132] In an example, each of the first base frame LF1 and the second base frame LF2 may include a metal material and may be made of a single layer. In an example, each of the first base frame LF1 and the second base frame LF2 may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, the embodiment is not limited thereto.

[0133] Each of the first insulating layer AL31 of the first semiconductor frame LSL and the second insulating layer AL32 of the second semiconductor frame USL may include an insulating material, and each of the first insulating layer AL31 and the second insulating layer AL32 may have a high dielectric constant and high thermal conductivity. In an example, each of the first insulating layer AL31 and the second insulating layer AL32 may include polyimide. However, the embodiment is not limited thereto.

[0134] The first and second insulating layers AL31 and AL32 may transfer heat generated during operation of the plurality of semiconductor components SCP mounted between the first and second base frames LF1 and LF2 to the outside.

[0135] Each of the first protection layer AL41 of the first semiconductor frame LSL and the second protection layer AL42 of the second semiconductor frame USL may include a metal material, and in an example, each of the first protection layer AL41 and the second protection layer AL42 may be a copper clad laminate (CCL) and may include at least one of copper (Cu) and aluminum (Al). However, the embodiment is not limited thereto.

[0136] The first protective layer AL41 and the second protective layer AL42 may respectively protect the first insulating layer AL31 and the second insulating layer AL32, and may respectively increase the transfer of heat from the first insulating layer AL31 and the second insulating layer AL32, and may respectively transfer the heat generated or collected in the first insulating layer AL31 and the second insulating layer AL32 to the outside.

[0137] In an example, the thickness of the first protective layer AL41 may be substantially the same as the thickness of the first insulating layer AL31, or the thickness of the first protective layer AL41 may be greater than the thickness of the first insulating layer AL31, and the thickness of the second protective layer AL42 may be substantially the same as the thickness of the second insulating layer AL32, or the thickness of the second protective layer AL42 may be greater than the thickness of the second insulating layer AL32. In addition, the thickness of the first protective layer AL41 may be about one to about two times the thickness of the first insulating layer AL31, and the thickness of the second protective layer AL42 may be about one to about two times the thickness of the second insulating layer AL32. However, the embodiment is not limited thereto.

[0138] The first protection layer AL41 may prevent warping of the first base frame LF1 together with the first insulating layer AL31, and the second protection layer AL42 may prevent warping of the second base frame LF2 together with the second insulating layer AL32.

[0139] The first insulating layer AL31 may support the first base frame LF1. In an example, the mounting portion MP and the wiring portion LP of the first base frame LF1 may be supported by being attached to the first insulating layer AL31 using an adhesive or a thermal press method. However, the embodiment is not limited thereto.

[0140] The lead-out portion OL extending from the wiring portion LP may not be separated from the first insulating layer AL31 together with the wiring portion LP supported by being attached to the first insulating layer AL31.

[0141] Similarly, the second insulating layer AL32 may support the second base frame LF2.

[0142] The plurality of semiconductor components SCP may be physically and electrically connected to the first base frame LF1 through the first contact portions SP1 , and may be physically and electrically connected to the second base frame LF2 through the second contact portions SP2 .

[0143] Each of the first contact portion SP1 and the second contact portion SP2 may include solder paste. However, the embodiment is not limited thereto.

[0144] The plurality of semiconductor components SCP may receive an electrical signal applied to the first base frame LF1 and the second semiconductor frame USL through the first and second contact portions SP1 and SP2.

[0145] The molding part ML may surround and seal the first semiconductor frame LSL, the second semiconductor frame USL, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0146] The molding part ML may protect the first semiconductor frame LSL, the second semiconductor frame USL included therein, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0147] In an example, a surface of the first protection layer AL41 of the first semiconductor frame LSL may be exposed to the outside (or external environment) without being surrounded by the molding part ML.

[0148] The molding part ML may include a polymer having excellent insulation and protection characteristics, and in an example, the molding part ML may include an epoxy molding compound (EMC) or a polyimide-based material.

[0149] In an example semiconductor package CHPK2 according to one or more embodiments, a plurality of semiconductor elements SCP may be installed between a first semiconductor frame LSL and a second semiconductor frame USL facing each other, the first semiconductor frame LSL may include: a first base frame LF1 made of a metal layer; a first insulating layer AL31 overlapping the first base frame LF1; and a first protective layer AL41 overlapping the first insulating layer AL31, and the first base frame LF1 may be a lead frame, and the second semiconductor frame USL may include: a second base frame LF2 made of a metal layer; a second insulating layer AL32 overlapping the second base frame LF2; and a second protective layer AL42 overlapping the second insulating layer AL32, and the second base frame LF2 may be a lead frame.

[0150] Therefore, a plurality of semiconductor components SCP can be mounted on the first base frame LF1 and the second base frame LF2 as lead frames, respectively, without a complicated process of forming a separate mounting substrate, so that the manufacturing process can be simple and an increase in manufacturing cost can be prevented.

[0151] In addition, the plurality of semiconductor components SCP may be mounted between the first semiconductor frame LSL and the second semiconductor frame USL facing each other, so that heat generated from the plurality of semiconductor components SCP is easily transferred to the outside through the first insulating layer AL31, the second insulating layer AL32, the first protective layer AL41, the second protective layer AL42, and the lower and upper portions of the plurality of semiconductor components SCP. Therefore, the performance degradation of the semiconductor components SCP due to internal heat and warping of the first base frame LF1 and the second base frame LF2 may be prevented.

[0152] In addition, a surface of the first protection layer AL41 of the first semiconductor frame LSL may be exposed to the outside without being surrounded by the molding part ML so that heat generated from the plurality of semiconductor elements SCP is easily transferred to the outside.

[0153] Reference Figure 7 , an example semiconductor package CHPK3 according to one or more embodiments will be described. Figure 7 An example semiconductor package according to one or more embodiments is shown. Figure 5 The corresponding cross-sectional view.

[0154] Reference Figure 7 , an example semiconductor package CHPK3 according to one or more embodiments may include: a first semiconductor frame LSL and a second semiconductor frame USL facing each other; a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL; and a molding part ML sealing the plurality of semiconductor elements SCP.

[0155] The first semiconductor frame LSL may include a first base frame LF1 and a first insulating layer AL51.

[0156] The second semiconductor frame USL may include a second base frame LF2 and a second insulating layer AL52.

[0157] Each of the first base frame LF1 of the first semiconductor frame LSL and the second base frame LF2 of the second semiconductor frame USL may be a lead frame.

[0158] In an example, each of the first base frame LF1 and the second base frame LF2 may include a metal material and may be made of a single layer. In an example, each of the first base frame LF1 and the second base frame LF2 may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, the embodiment is not limited thereto.

[0159] The first insulating layer AL51 of the first semiconductor frame LSL and the second insulating layer AL52 of the second semiconductor frame USL may include a ceramic material. However, the embodiment is not limited thereto.

[0160] The first insulating layer AL51 and the second insulating layer AL52 can transfer heat generated during the operation of the plurality of semiconductor components SCP installed between the first base frame LF1 and the second base frame LF2 to the outside, can respectively support the first base frame LF1 and the second base frame LF2, and can respectively prevent warping of the first base frame LF1 and the second base frame LF2.

[0161] The first insulating layer AL51 may support the first base frame LF1. In an example, the mounting portion MP and the wiring portion LP of the first base frame LF1 may be supported by being attached to the first insulating layer AL51 using an adhesive or a thermal press method. However, the embodiment is not limited thereto.

[0162] The lead-out portion OL extending from the wiring portion LP may not be separated from the first insulating layer AL51 together with the wiring portion LP supported by being attached to the first insulating layer AL51.

[0163] Similarly, the second insulating layer AL52 may support the second base frame LF2.

[0164] The plurality of semiconductor components SCP may be physically and electrically connected to the first base frame LF1 through the first contact portions SP1 , and may be physically and electrically connected to the second base frame LF2 through the second contact portions SP2 .

[0165] Each of the first contact portion SP1 and the second contact portion SP2 may include solder paste. However, the embodiment is not limited thereto.

[0166] The plurality of semiconductor components SCP may receive an electrical signal applied to the first base frame LF1 and the second semiconductor frame USL through the first and second contact portions SP1 and SP2.

[0167] The molding part ML may surround and seal the first semiconductor frame LSL, the second semiconductor frame USL, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0168] The molding part ML may protect the first semiconductor frame LSL, the second semiconductor frame USL included therein, and a plurality of semiconductor elements SCP disposed between the first semiconductor frame LSL and the second semiconductor frame USL.

[0169] A surface of the first insulating layer AL51 of the first semiconductor frame LSL may be exposed to the outside (or external environment) without being surrounded by the molding part ML.

[0170] The molding part ML may include a polymer having excellent insulation characteristics and protection characteristics, and for example, the molding part ML may include epoxy molding compound (EMC) or a polyimide-based material.

[0171] In an example semiconductor package CHPK3 according to one or more embodiments, a plurality of semiconductor elements SCP may be installed between a first semiconductor frame LSL and a second semiconductor frame USL facing each other, the first semiconductor frame LSL may include: a first base frame LF1 made of a metal layer; and a first insulating layer AL51 overlapping the first base frame LF1, and the first base frame LF1 may be a lead frame, and the second semiconductor frame USL may include: a second base frame LF2 made of a metal layer; and a second insulating layer AL52 overlapping the second base frame LF2, and the second base frame LF2 may be a lead frame.

[0172] Therefore, a plurality of semiconductor components SCP can be mounted on the first base frame LF1 and the second base frame LF2 as lead frames, respectively, without a complicated process of forming a separate mounting substrate, so that the manufacturing process can be simple and an increase in manufacturing cost can be prevented.

[0173] In addition, the plurality of semiconductor components SCP may be mounted between the first semiconductor frame LSL and the second semiconductor frame USL facing each other, so that heat generated from the plurality of semiconductor components SCP is easily transferred to the outside through the first insulating layer AL51, the second insulating layer AL52, and the lower and upper portions of the plurality of semiconductor components SCP. Therefore, the performance degradation of the semiconductor components SCP due to internal heat and warping of the first base frame LF1 and the second base frame LF2 may be prevented.

[0174] In addition, a surface of the first insulating layer AL51 of the first semiconductor frame LSL may be exposed to the outside (or external environment) without being surrounded by the molding part ML, so that heat generated from the plurality of semiconductor elements SCP may be easily transferred to the outside.

[0175] Although specific examples have been shown and described above, it will be readily understood after understanding the present disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner, and / or the components in the described system, architecture, device, or circuit are replaced or supplemented by other components or their equivalents, suitable results may be achieved. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be interpreted as included in the present disclosure.

Claims

1. A semiconductor frame, comprising: a lead frame including a mounting portion, a wiring portion, and a lead portion, the mounting portion being configured to mount a semiconductor element, the wiring portion being spaced apart from the mounting portion, and the lead portion extending from the wiring portion; as well as The insulating layer is provided so as to overlap with the mounting portion of the lead frame and not overlap with the lead-out portion of the lead frame.

2. The semiconductor frame according to claim 1, further comprising a protection layer overlapping the insulating layer, in, The insulating layer is disposed between the lead frame and the protection layer.

3. The semiconductor frame according to claim 2, wherein: The insulating layer includes polyimide, and the protective layer includes a metal material.

4. The semiconductor frame according to claim 3, wherein: The protective layer includes a metal foil.

5. The semiconductor frame according to claim 4, wherein: The thickness of the insulating layer is equal to or greater than the thickness of the protective layer.

6. The semiconductor frame according to claim 3, wherein: The protective layer includes a copper clad laminate.

7. The semiconductor frame according to claim 6, wherein: The thickness of the protection layer is equal to or greater than the thickness of the insulation layer.

8. The semiconductor frame according to claim 1, wherein: The insulating layer includes a ceramic material.

9. A semiconductor package, comprising: A first semiconductor frame, comprising a first lead frame and a first insulating layer disposed under the first lead frame; A second semiconductor frame, comprising a second lead frame facing the first lead frame and a second insulating layer disposed above the second lead frame; A semiconductor element is arranged between the first semiconductor frame and the second semiconductor frame; as well as The molding part surrounds and seals at least a portion of the first semiconductor frame, at least a portion of the second semiconductor frame, and the semiconductor element.

10. The semiconductor package according to claim 9, wherein: The first lead frame includes: a mounting portion configured to mount the semiconductor element; a wiring portion spaced apart from the mounting portion; and a lead portion extending from the wiring portion, and The first insulating layer and the second insulating layer are arranged to overlap with the mounting portion of the first lead frame and are arranged not to overlap with the lead-out portion of the first lead frame.

11. The semiconductor package according to claim 9, further comprising: A first protective layer, disposed below the first insulating layer; as well as The second protection layer is arranged on the second insulating layer.

12. The semiconductor package according to claim 11, wherein Each of the first insulating layer and the second insulating layer includes polyimide, and each of the first protective layer and the second protective layer includes a metal material.

13. The semiconductor package according to claim 12, wherein: A surface of the first protection layer is exposed to the external environment without being surrounded by the molding part.

14. The semiconductor package according to claim 13, wherein: Each of the first protective layer and the second protective layer includes a metal foil.

15. The semiconductor package according to claim 14, wherein: The thickness of the first insulating layer is equal to or greater than the thickness of the first protective layer, and the thickness of the second insulating layer is equal to or greater than the thickness of the second protective layer.

16. The semiconductor package according to claim 13, wherein: Each of the first protective layer and the second protective layer includes a copper clad laminate.

17. The semiconductor package according to claim 16, wherein: The thickness of the first protective layer is equal to or greater than the thickness of the first insulating layer, and the thickness of the second protective layer is equal to or greater than the thickness of the second insulating layer.

18. The semiconductor package according to claim 9, wherein: Each of the first insulating layer and the second insulating layer includes a ceramic material.

19. The semiconductor package according to claim 18, wherein: A surface of the first insulating layer is exposed to the external environment without being surrounded by the molding part.

20. The semiconductor package according to claim 10, wherein The lead-out portion is exposed to the external environment without being surrounded by the molded portion.

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