Signal processing device and signal processing method

Abstract

A signal processing apparatus includes a dedicated test mode code generation circuit, a decision error detection circuit, and a debug control circuit. The exclusive test mode code generation circuit generates a plurality of prediction codes according to a plurality of decision codes output by the cutter and a predetermined rule. The decision error detection circuit continuously receives a plurality of decision codes and a plurality of prediction codes in the exclusive test mode, and correspondingly generates a plurality of detection results. The debug control circuit continuously records contents of one or more signals obtained at one or more nodes of the received signal processing circuit in the storage device in the exclusive test mode, and terminates recording the contents of the one or more signals in response to a state of at least one of the plurality of detection results.

Description

Technical Field

[0001] The present invention relates to a signal processing device in a communication system, and more particularly to a signal processing device capable of determining a received symbol decision error in real time during a data exchange phase. Background Art

[0002] A communication system usually includes communication devices such as a transmitter and a receiver. During the modulation process, the transmitter sets the signal to be transmitted to the corresponding voltage level according to the data content it carries, and transmits it after appropriate processing (for example, encoding, amplification and other signal processing). The receiver is responsible for receiving the signal and processing the received signal. The receiver circuit usually includes a decision device, or a slicer, to determine the voltage level corresponding to the received symbol. However, in most communication systems, external or internal interference may cause the transmission signal to have a voltage offset. For example, noise in the transmission channel may cause the voltage level of the transmission signal to offset its ideal voltage level (that is, the voltage level set by the transmitter), thereby causing the decision device to make an incorrect decision.

[0003] Therefore, communication devices are usually equipped with relevant circuits / devices to compensate for the impact of the transmission channel on the signal. The compensation circuit / device can adjust / train the relevant parameters in an adaptive manner to optimize the compensation performance. However, the interference and noise in the real communication environment usually have time-varying characteristics. Therefore, when actually exchanging data, even if the relevant parameters have been adjusted / trained in an adaptive manner to optimize them, the decision-making device may still make wrong decisions due to interference and noise.

[0004] If a decision error occurs during the actual data exchange phase, it is necessary to capture the data and signals inside the communication device for analysis to determine the source of the problem. However, in today's ultra-high-speed data transmission capabilities or high-throughput communication systems, it is difficult to have sufficient storage capacity to fully record all the internal data and signals generated by the communication device during the communication process, so errors cannot be discovered in real time, which greatly increases the difficulty of debugging.

[0005] In view of this, a signal processing device and a corresponding signal processing method are needed that can determine received symbol decision errors in real time. Summary of the invention

[0006] According to an embodiment of the present invention, a signal processing device includes an exclusive test mode symbol generation circuit, a decision error detection circuit, and a debug control circuit. The exclusive test mode symbol generation circuit is coupled to a received signal processing circuit, and is used to generate a plurality of prediction symbols as reference signals according to a plurality of decision symbols output by a clipper of the received signal processing circuit and a predetermined rule. The decision error detection circuit operates in an exclusive test mode, and is used to continuously receive a plurality of decision symbols and a plurality of prediction symbols, and to generate a plurality of detection results accordingly. The debug control circuit is coupled to one or more nodes of the received signal processing circuit, and includes a storage device, and is used to continuously record the contents of one or more signals obtained at one or more nodes in the storage device in the exclusive test mode. The debug control circuit receives a plurality of detection results, and terminates recording the contents of the one or more signals in response to the state of at least one of the plurality of detection results.

[0007] According to an embodiment of the present invention, a signal processing method is provided for processing a signal received by a receiver in a communication system, wherein the receiver includes a receiving signal processing circuit, and the receiving signal processing circuit operates in a data exchange phase after parameter training of a decision feedback equalizer has been completed. The signal processing method includes: entering an exclusive test mode in the data exchange phase in response to a value decision of a buffer; generating a plurality of prediction symbols as reference signals based on a plurality of decision symbols output by a clipper of the receiving signal processing circuit and a predetermined rule; continuously receiving and detecting a plurality of decision symbols and a plurality of prediction symbols, and correspondingly generating a plurality of detection results; continuously recording the contents of one or more signals obtained at one or more nodes of the receiving signal processing circuit; and terminating recording the contents of the one or more signals in response to the status of at least one of the plurality of detection results. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An exemplary block diagram of a signal processing device according to an embodiment of the present invention is shown.

[0009] Figure 2 An exemplary circuit diagram of a linear feedback shift register according to an embodiment of the present invention is shown.

[0010] Figure 3 A schematic diagram showing a decision error occurring at a receiver end according to an embodiment of the present invention is shown.

[0011] Figure 4 An exemplary flow chart of a signal processing method according to an embodiment of the present invention is shown.

[0012] Figure 5A A schematic diagram showing the operation of terminating a recording behavior in a first operation mode according to an embodiment of the present invention.

[0013] Figure 5B A schematic diagram showing the operation of terminating recording in the second operation mode according to an embodiment of the present invention.

[0014] Figure 5C A schematic diagram showing an operation of terminating a recording behavior in a third operation mode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Figure 1 An exemplary block diagram of a signal processing device according to an embodiment of the present invention is shown. The signal processing device 100 may be configured in a communication device in a communication system, for example, may be configured in a receiver or receiving circuit of the communication device to process a received signal. The signal processing device 100 may include a received signal processing circuit 110 and a plurality of circuit devices for assisting the received signal processing circuit 110 to operate in a dedicated test mode (to be described in detail in the following paragraphs).

[0016] The reception signal processing circuit 110 may include a feedforward filter (also called a feedforward equalizer (FFE)) 111 , a feedback filter (also called a feedback equalizer (FBE)) 112 , a slicer (also called a decision device) 113 , and an adder 114 .

[0017] The feedforward filter 111 may perform a filtering operation on the input signal X(n) to generate a filtered input signal X'(n). The feedback filter 112 may perform a filtering operation on the decision signal D(n) to generate a filtered decision signal D'(n). The feedforward filter 111 and the feedback filter 112 may form a decision feedback equalizer (DFE). The adder 114 is coupled to the feedforward filter 111 and the feedback filter 112 to combine the signal X'(n) and the signal D'(n) to generate an equalizer output signal Eq(n). The clipper 113 generates a decision signal D(n) based on the equalizer output signal Eq(n). The decision signal D(n) may be provided to a subsequent circuit (not shown) of the receiver for signal processing required by other communication systems.

[0018] Generally speaking, a decision feedback equalizer includes two functions: (1) filtering the input signal and the decision signal output by the past clipper to reduce the inter-signal interference caused by the channel response, and (2) adapting the filter parameters according to the equalizer error and the default optimization algorithm. The former can improve the signal-to-noise ratio or reduce the bit error rate; the latter allows the filter to adapt to channel variations.

[0019] The normal operation of the decision feedback equalizer depends on the clipper being able to generate a nearly correct decision signal. If the clipper continues to make wrong decisions, the optimization algorithm used to adjust the filter parameters will continue to obtain incorrect equalizer errors, causing the filter parameters to be adjusted in the wrong direction, thereby causing the filter parameters to diverge. In serious cases, the wrong decision will affect the future equalizer output signal through the feedback path of the feedback filter 112 and interfere with the clipper decision. This phenomenon is called error propagation.

[0020] A typical communication system includes a training phase and a data exchange phase when the transmitter and receiver establish a connection. The training phase includes parameter training operations. During the training phase, the transmitter and receiver must exchange the necessary information required to establish a connection and adjust relevant system parameters (such as but not limited to filter parameters) in accordance with the communication system specification to complete parameter training. After the training phase is completed and a stable connection can be established, the data exchange phase is entered to transmit and receive data. For example, the receiver will first complete channel equalization or adjust / train relevant filter parameters during the training phase. Only after the parameter adjustment / training is completed can the clipper make correct decisions, and then officially enter the data exchange phase to receive data normally. During the data exchange phase, the actual application of the communication system officially begins, so the data signal sent by the transmitter includes the data that actually needs to be transmitted to the receiver.

[0021] When the communication device enters the data exchange phase and starts transmitting data, the receiving end cannot detect the error immediately when the decision error occurs because the transmitted data is unknown to the receiving end. In addition, in the application of ultra-high-speed data transmission or long-term data transmission, due to the huge amount of transmitted data, it is difficult for the receiving end to fully record all the relevant information of the operation of each circuit during the transmission process, so it is impossible to use this relevant information for debugging.

[0022] To solve the above problems, in an embodiment of the present invention, a proprietary test mode of a communication system is proposed. Through the operation in the proprietary test mode, when the clipper makes an erroneous decision, the relevant information of the circuit operation can be immediately recorded for subsequent processing and analysis to determine the system problem. In addition, the accurate equalizer error and the actual equalizer error can be obtained in the proprietary test mode, which is also helpful for analyzing the system problem.

[0023] According to an embodiment of the present invention, in the dedicated test mode, both the transmitter and the receiver will generate multiple symbols according to a common default established rule, wherein the symbol generated by the transmitter according to the established rule is a transmission symbol, which is transmitted to the receiver through a transmission channel and received by the receiver as a reception symbol. In addition to the reception symbol, the receiver will also generate a prediction symbol according to the established rule as a reference signal to determine whether a decision error occurs. Therefore, both the transmitter and the receiver must know whether to enter the dedicated test mode during the data exchange phase.

[0024] According to an embodiment of the present invention, the transmitter and the receiver may include a mode control circuit and a buffer, respectively, for example, Figure 1 The mode control circuit 130 and the register 135 are configured in the signal processing device 100 of the receiver. The mode control circuit 130 can determine whether to enter the exclusive test mode in the data exchange phase according to the register value stored in the register 135, and generate a corresponding control signal Ctrl_1 according to the determination result.

[0025] In an embodiment of the present invention, the register values ​​configured at the transmitter and the receiver can be set before establishing a connection. In another embodiment of the present invention, the transmitter and the receiver can also communicate through an information exchange process during the training phase whether to enter the exclusive test mode during the data exchange phase, and the transmitter and the receiver can set their respective registers accordingly according to the communication results.

[0026] For the embodiment in which the register values ​​of the transmitter and the receiver are pre-set before establishing the connection, after the training phase is completed, the transmitter and the receiver can decide whether to enter the exclusive test mode according to the register values ​​before starting the data exchange phase or at a certain time point after the data exchange phase starts. If the judgment result is yes, the transmitter side starts to generate transmission symbols according to the established rules and transmits them to the receiver through the transmission channel. At the receiver side, the synchronization operation of the exclusive test mode is first performed according to the received symbols, so that the symbol time of the receiver side can be aligned with the symbol time of the transmitter side, and the subsequent operations are started after the synchronization is completed.

[0027] On the other hand, if the determination result is negative, the transmitter and the receiver both maintain the data exchange stage and perform normal data exchange. For example, the data signal sent by the transmitter is the data actually to be transmitted to the receiver, and this data signal is usually unknown or unpredictable to the receiver (i.e., the content of the data will be obtained through processing and decision-making by the received signal processing circuit 110).

[0028] In the embodiment of communicating whether to enter the exclusive test mode in the data exchange phase during the training phase, the value of the buffer will be set according to the communication result during the training phase. After the training phase is completed, the transmitter and the receiver can similarly decide whether to enter the exclusive test mode based on the buffer value before starting the data exchange phase or at a certain time point after the data exchange phase starts. If the judgment result is yes, the transmitter side starts to generate transmission symbols according to the established rules and transmits them to the receiver through the transmission channel. The receiver first performs the synchronization operation of the exclusive test mode according to the received symbols so that the symbol time of the receiver can be aligned with the symbol time of the transmitter side, and starts the subsequent operation after the synchronization is completed.

[0029] On the other hand, if the determination result is negative, the transmitter and the receiver maintain the data exchange stage for normal data exchange. For example, the data signal sent by the transmitter is the data actually to be transmitted to the receiver, and this data signal is usually unknown or unpredictable to the receiver (i.e., the content of the data will be obtained through processing and decision-making by the received signal processing circuit 110).

[0030] According to the embodiment of the present invention, as described above, if it is determined that the dedicated test mode needs to be entered, the receiver must first perform a synchronization operation of the dedicated test mode according to the received symbol to align the symbol time.

[0031] In the embodiment of the present invention, the signal processing device 100 may include a dedicated test mode symbol generation circuit 120 and a synchronization module 125. The dedicated test mode symbol generation circuit 120 may be coupled to the reception signal processing circuit 110, and may generate a plurality of prediction symbols as reference signals according to the aforementioned established rules. In the embodiment of the present invention, the dedicated test mode symbol generation circuit 120 may generate a plurality of prediction symbols as reference signals according to a plurality of decision symbols output by the clipper 113 and the established rules. In addition, in the embodiment of the present invention, the dedicated test mode symbol generation circuit 120 may be implemented by a linear feedback shift register (LFSR).

[0032] Figure 2An example circuit diagram of a linear feedback shift register according to an embodiment of the present invention is shown. Assume that the linear feedback shift register 200 includes n-level buffers 211[0] to 211[n-1] and one or more arithmetic logic gates, such as the exclusive or (abbreviated as XOR) logic gates 210 and 220 shown in the figure. The value of each buffer can be set to 0 or 1, and the value in the buffer will shift one level to the right every 1 time unit, that is, the original value in buffer 211[0] will be moved to buffer 211[1], the original value in buffer 211[1] will be moved to buffer 211[2], and so on. The value in buffer 211[n-1] is shifted out to become the output signal of the linear feedback shift register 200. In addition, the value in the input buffer 211[0] can be set to the calculation result of the exclusive or logic gate to Figure 2 For example, the value of the input register 211 [0] is set to the calculation result of the XOR logic gates 210 and 220.

[0033] It should be noted that Figure 2 This is only one of many circuit examples that can be used to implement the dedicated test mode symbol generation circuit, so the present invention is not limited to Figure 2 The content shown.

[0034] In the embodiment of the present invention, the established rules that are mutually agreed upon by the transmitter and the receiver may be (but are not limited to) the XOR logic gate calculation rules in the above-mentioned example. For example, the dedicated test mode symbol generation circuits configured in the transmitter and the receiver may use a linear feedback shift register of the same structure, so that multiple symbols may be generated according to the mutually agreed upon established rules. As described above, the symbols generated by the transmitter according to the established rules are transmission symbols, which are transmitted to the receiver through the transmission channel and received by the receiver as reception symbols. In addition to the reception symbols, the receiver may also generate multiple prediction symbols according to the established rules as reference signals for determining whether a decision error has occurred.

[0035] When starting the dedicated test mode, although the receiver knows the established rule for generating symbols, it is still unable to directly know the symbol time corresponding to the transmitted symbol from the received symbol. Therefore, in order to synchronize the multiple predicted symbols generated by the receiver according to the same rule with the transmitted symbol, the receiver can perform the synchronization operation of the dedicated test mode through the synchronization module 125 to align the symbol time. Once the predicted symbol is synchronized with the transmitted symbol, the decision error detection circuit 140 can accurately determine whether a decision error occurs.

[0036] According to an embodiment of the present invention, in a synchronous operation, the receiving signal processing circuit 110 sequentially receives and processes a plurality of receiving symbols, so that the clipper 113 correspondingly sequentially generates a plurality of decision symbols. The exclusive test mode symbol generation circuit 120 may receive a plurality of decision symbols from the clipper 113 and fill them into a buffer as initial values. Then, the exclusive test mode symbol generation circuit 120 may sequentially generate a plurality of prediction symbols according to the aforementioned established rules. The exclusive test mode symbol generation circuit 120 may continuously generate prediction symbols, while the receiving signal processing circuit 110 also continuously receives and processes the latest receiving symbols. The synchronization module 125 is coupled to the exclusive test mode symbol generation circuit 120 and may include one or more comparison circuits for adjusting the symbol times corresponding to the plurality of prediction symbols in the exclusive test mode so as to align the symbol times corresponding to the plurality of transmission symbols transmitted by the transmitter. Specifically, the synchronization module 125 compares the current prediction symbol generated by the dedicated test mode symbol generation circuit 120 according to the predetermined rule with the current decision symbol output by the clipper 113 to see if they match. If the two do not match, the synchronization module 125 can adjust the symbol time corresponding to the prediction symbol to try to align it with the symbol time corresponding to the plurality of transmission symbols transmitted by the transmitter. For example, the synchronization module 125 can notify the dedicated test mode symbol generation circuit 120 to re-fill the newly obtained decision symbol into the buffer as the initial value, or adjust or update the buffer content in any other way, and re-generate a plurality of prediction symbols in sequence according to the predetermined rule.

[0037] If the current prediction symbol matches the current decision symbol, the synchronization module 125 may continue to compare the subsequent one or more prediction symbols with the subsequent one or more decision symbols. On the other hand, if the prediction symbol does not match the decision symbol, the synchronization module 125 may adjust the symbol time corresponding to the prediction symbol again as described above. If a certain number of prediction symbols and decision symbols are determined to be consistent, the synchronization module 125 may determine that the symbol time corresponding to the prediction symbol is aligned with the symbol time corresponding to the transmission symbol, and the exclusive test mode synchronization has been completed, that is, the prediction symbol is synchronized with the transmission symbol. Once the prediction symbol is synchronized with the transmission symbol, in the exclusive test mode, the prediction symbol generated by the exclusive test mode symbol generation circuit 120 will be consistent with the transmission symbol generated by the transmitter, and the prediction symbol will theoretically be consistent with the decision symbol output by the clipper 113.

[0038] Return to reference Figure 1In addition to the aforementioned receiving signal processing circuit 110, the dedicated test mode symbol generating circuit 120, the synchronization module 125, the mode control circuit 130 and the buffer 135, the signal processing device 100 may also include a coefficient adjustment circuit 115 (which may also be regarded as a part of the receiving signal processing circuit 110), a decision error detection circuit 140 and a debugging control circuit 150.

[0039] In an embodiment of the present invention, the decision error detection circuit 140 may receive the control signal Ctrl_1 and operate in the exclusive test mode in response to the control signal Ctrl_1. For example, the mode control circuit 130 may generate the corresponding control signal Ctrl_1 after determining that the exclusive test mode synchronization is completed, provided that it has been determined that the exclusive test mode needs to be entered. The decision error detection circuit 140 may continuously receive a plurality of decision symbols and a plurality of prediction symbols (in Figure 1 The decision signal D(n) and the reference signal G(n) are respectively represented by the decision signal D(n) and the reference signal G(n), wherein the decision signal D(n) includes a plurality of decision symbols sequentially generated by the clipper 113, and the reference signal G(n) includes a plurality of prediction symbols sequentially generated by the exclusive test mode symbol generation circuit 120), and a plurality of detection results are generated accordingly (in Figure 1 The detection result signal R(n) is represented by the detection result signal R(n), wherein the detection result signal R(n) includes a plurality of detection results sequentially generated by the decision error detection circuit 140). The debugging control circuit 150 receives the plurality of detection results, and terminates recording the contents of one or more signals obtained at one or more nodes of the reception signal processing circuit 110 (for example, an input node or an output node of any component included in the reception signal processing circuit 110) in response to the state of at least one detection result among the plurality of detection results.

[0040] More specifically, in the embodiment of the present invention, since the prediction symbol and the transmission symbol have achieved synchronization in timing and content after the dedicated test mode synchronization is completed, the prediction symbol can be regarded as a golden signal, that is, it includes correct symbol content. Therefore, the decision error detection circuit 140 can compare the decision signal D(n) with the corresponding symbol content in the reference signal G(n) to determine whether a decision error has occurred. If the corresponding symbol content in the decision signal D(n) is different from that in the reference signal G(n), it means that a decision error has occurred. The decision error detection circuit 140 can set the state of the corresponding detection result in the output detection result signal R(n) to indicate that a decision error has occurred, so that the debug control circuit 150 can terminate recording the content of one or more signals accordingly.

[0041] Figure 3A schematic diagram of a decision error occurring at a receiver according to an embodiment of the present invention is shown. As shown in the figure, if the received symbol corresponding to the symbol time RS_7 of the receiver does not match the transmitted symbol content corresponding to the symbol time TS_7 of the receiver, a decision error will occur at the receiver, and the decision error can be detected by comparing the decision signal D(n) with the reference signal G(n).

[0042] Return to reference Figure 1 In the embodiment of the present invention, the debug control circuit 150 may be coupled to one or more nodes of the received signal processing circuit 110, and may include a storage device 151. The debug control circuit 150 continuously records the content of one or more signals obtained at one or more nodes in the storage device 151 in the dedicated test mode. In addition, the debug control circuit 150 may receive a trigger signal Trig, and terminate recording the content of the one or more signals in response to the trigger signal Trig.

[0043] According to an embodiment of the present invention, the content of the one or more signals is stored in the storage device 151 as a plurality of current records. However, due to the limited capacity of the storage device 151, when the storage device 151 is full, the content of the one or more signals obtained most recently will be written to the storage device 151 in a manner of overwriting from the beginning to cover the content stored in the storage device 151 (i.e., the existing current record). In other words, the current record stored in the storage device 151 can be updated through the overwriting operation. When the debug control circuit 150 stops recording the content of the one or more signals in response to the trigger signal Trig, the debug control circuit 150 stops operating and no longer overwrites the content stored in the storage device 151 with the content of the one or more signals obtained most recently, i.e., stops updating the current record, thereby retaining the current record currently stored in the storage device 151.

[0044] According to an embodiment of the present invention, the trigger signal Trig received by the debugging control circuit 150 may be an indication signal of "decision error occurs", for example, the aforementioned detection result signal R(n), or other signals. According to an embodiment of the present invention, the signal recorded in the storage device 151 by the debugging control circuit 150 may be any signal inside the signal processing device 100, including but not limited to the equalizer output signal, the output signal of the feedforward filter 111, the decision signal D(n), etc.

[0045] In addition to detecting decision errors and retaining the records stored in the storage device 151 in real time when decision errors are found, the multiplexer 160 can also be used in the exclusive test mode to selectively provide the accurate equalizer error and the actual equalizer error to the coefficient adjustment circuit 115. More specifically, in the embodiment of the present invention, the mode control circuit 130 can issue another control signal Ctrl_2 to control whether to select the error in the exclusive test mode. The multiplexer 160 selects which signal of the reference signal G(n) and the decision signal D(n) to provide to the adder 116 in response to the setting of the control signal Ctrl_2. If the multiplexer 160 provides the reference signal G(n) to the adder 116, the obtained equalizer error signal Err(n) is the accurate equalizer error, that is, the equalizer error obtained by subtracting the equalizer output signal Eq(n) from the reference signal G(n). If the multiplexer 160 provides the decision signal D(n) to the adder 116, the resulting equalizer error signal Err(n) is the actual equalizer error, ie, the equalizer error obtained by subtracting the equalizer output signal Eq(n) from the decision signal D(n).

[0046] The coefficient adjustment circuit 115 can adaptively adjust one or more coefficients of the decision feedback equalizer according to the received equalizer error signal Err(n). In the dedicated test mode, the equalizer error signal Err(n) is not limited to the actual equalizer error, but can also be the accurate equalizer error generated by the equalizer output signal Eq(n) of the decision feedback equalizer and the reference signal G(n) as described above, which can help analyze system problems.

[0047] Figure 4 An exemplary flow chart of a signal processing method according to an embodiment of the present invention is shown. The signal processing method proposed in the present invention can be used to process a signal received by a receiver in a communication system. The receiver may include a receiving signal processing circuit, and the signal processing method proposed in the present invention can be applied to the data exchange stage after the receiving signal processing circuit operates after the parameter training of the decision feedback equalizer has been completed, so as to solve the problem that the error cannot be found in real time during the data exchange stage in the prior art. The signal processing method proposed in the present invention may include the following steps:

[0048] Step S402: The mode control circuit determines whether to enter the exclusive test mode in the data exchange phase in response to the value (set value) of the register. As described above, the mode control circuit 130 can determine whether to enter the exclusive test mode in the data exchange phase according to the value of the register 135.

[0049] Step S404: The dedicated test mode symbol generation circuit generates a plurality of prediction symbols as reference signals according to a plurality of decision symbols output by the clipper of the receiving signal processing circuit and a predetermined rule. In the embodiment of the present invention, the prediction symbols generated in step S404 can be provided to the synchronization module 125 to perform the synchronization operation of the dedicated test mode.

[0050] Step S406: The decision error detection circuit continues to receive and detect multiple decision symbols and multiple prediction symbols, and generates multiple detection results accordingly. In the embodiment of the present invention, after the synchronization operation is completed, the dedicated test mode symbol generation circuit 120 can continue to generate the latest prediction symbol according to the established rules. Similarly, at the same time, the received signal processing circuit 110 also continues to receive and process the latest received symbol, so the clipper 113 can continue to generate the latest decision symbol. The decision error detection circuit 140 can perform decision error detection according to the latest prediction symbol and the latest decision symbol, and generate the latest detection result accordingly.

[0051] Step S408: The debug control circuit continuously records the content of one or more signals obtained at one or more nodes of the received signal processing circuit. As described above, in the dedicated test mode, the debug control circuit 150 can continuously record the content of one or more signals obtained at one or more nodes in the storage device 151. In the embodiment of the present invention, after the synchronization operation is completed, step S406 and step S408 can be executed in parallel.

[0052] Step S410: The debugging control circuit stops recording the content of one or more signals in response to the state of at least one of the multiple detection results. In the embodiment of the present invention, the debugging control circuit 150 can stop recording the content of the one or more signals in response to the state of the detection result generated by the decision error detection circuit 140 (or other signals that can serve as the source of the trigger signal) (i.e., stop overwriting the content stored in the storage device 151 with the content of the one or more signals obtained most recently), thereby retaining the current record currently stored in the storage device 151. The debugging control circuit 150 can be coupled to one or more external devices through the debugging interface, so that the data and signals recorded in the communication device of the storage device 151 can be provided to the external device for analysis and debugging through the debugging interface.

[0053] According to an embodiment of the present invention, the debugging control circuit 150 may include multiple operation modes. The debugging control circuit 150 may also receive an external control signal through a debugging interface and switch to different operation modes according to the external control signal. The difference between the multiple operation modes may at least include a termination method for terminating the recording behavior in response to a predetermined state or signal level of a trigger signal.

[0054] Figure 5AA schematic diagram showing an operation of terminating a recording behavior in a first operation mode (operation mode A) according to an embodiment of the present invention. Figure 5B The operation diagram of terminating the recording behavior in the second operation mode (operation mode B) according to the embodiment of the present invention is shown. Figure 5C The operation diagram of the termination recording behavior in the third operation mode (operation mode C) according to the embodiment of the present invention is shown. Assume that the storage space of the storage device 151 is designed to record a signal segment with a time window of 1 millisecond, and assume that the debugging control circuit 150 terminates recording the content of the one or more signals in response to the state where the level of the trigger signal is pulled high. In operation mode A, the debugging control circuit 150 will continuously record the content of the one or more signals in the storage space of the storage device 151. If the storage space of the storage device 151 is full, the existing record will be overwritten from the beginning until the recording is terminated when the level of the trigger signal Trig is detected to be pulled high. Therefore, assuming that a signal segment of 1 millisecond is equivalent to L symbol times, and assuming that the debugging control circuit 150 continuously records the signal from time t=0 (the "recorded signal @ t=0" in the figure represents the signal content recorded at time t=0, and so on), until the level of the trigger signal Trig is detected to be pulled high at time t=(n+L-1) and the recording is terminated, then the 1 millisecond long signal segment recorded in the storage space of the storage device 151 will include the signal content recorded from time t=n to time t=(n+L-1).

[0055] Reference to Figure 5B , it is also assumed that a 1 millisecond signal segment is equivalent to L symbol times, and it is assumed that the debugging control circuit 150 starts recording the signal from time t=0 (in the figure, "recorded signal @ t=0" represents the signal content recorded at time t=0, and so on). In operation mode B, the debugging control circuit 150 will continuously record the content of the one or more signals in the storage space of the storage device 151. If the storage space of the storage device 151 is full, the existing record will be overwritten from the beginning until the level of the trigger signal Trig is detected to be pulled up for 0.5 milliseconds (equivalent to half of the storage space being filled), and then the recording will be terminated. Therefore, the 1 millisecond signal segment recorded in the storage space of the storage device 151 will include the signal content recorded from time t=n to time t=(n+L-1).

[0056] Reference to Figure 5C, it is also assumed that a 1 millisecond signal segment is equivalent to L symbol times, and it is assumed that the debugging control circuit 150 starts recording the signal from time t=0 (in the figure, "recorded signal @ t=0" represents the signal content recorded at time t=0, and so on). In operation mode C, the debugging control circuit 150 will continuously transcribe and record the signal after the level of the trigger signal is pulled high until the storage space of the storage device 151 is full. Therefore, assuming that the level of the trigger signal is pulled high at t=n, the 1 millisecond signal segment recorded in the storage space of the storage device 151 will include the signal content recorded from time t=n to time t=(n+L-1).

[0057] It is worth noting that, although the signal contents recorded in the storage device 151 are the same in the three operation modes, the time points at which the level of the trigger signal is raised are different in the three operation modes. Therefore, if the level of the trigger signal is raised at the same time point, the signal contents recorded in the storage device 151 in the three operation modes will not be the same. Therefore, by setting different operation modes, the signal contents can be obtained in different ways, which helps to analyze system problems from different angles.

[0058] In summary, in the embodiment of the present invention, through the operation in the dedicated test mode, the error can be found in real time when the clipper makes an erroneous decision, and the relevant information of the circuit operation can be recorded immediately for subsequent processing and analysis to determine the system problem. In addition, the accurate equalizer error and the actual equalizer error can be obtained in the dedicated test mode, and the signal content can be obtained in different ways by setting different operation modes, which is also helpful for analyzing system problems.

[0059] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0060] Description of reference numerals:

[0061] 100:Signal processing device

[0062] 110: Received signal processing circuit

[0063] 111: Feedforward filter

[0064] 112: Feedback filter

[0065] 113: Clipper

[0066] 114,116: Adder

[0067] 115: Coefficient adjustment circuit

[0068] 120: Exclusive test mode code generation circuit

[0069] 125: Synchronization module

[0070] 130: Mode control circuit

[0071] 135,211[0]~211[n-1]: Buffer

[0072] 140: Decision error detection circuit

[0073] 150: Debug control circuit

[0074] 151: Storage device

[0075] 160:Multiplexer

[0076] 200: Linear Feedback Shift Register

[0077] 210,220: XOR logic gate

[0078] Ctrl_1,Ctrl_2,D(n),D'(n),Eq(n),Err(n),G(n),R(n),Trig,X(n),X'(n): signal

[0079] RS_7,TS_7: symbol time

Claims

1. A signal processing device, comprising: a dedicated test mode symbol generation circuit coupled to the received signal processing circuit for generating a plurality of predicted symbols as reference signals based on a plurality of decision symbols output by a clipper of the received signal processing circuit and a predetermined rule; a decision error detection circuit operating in a dedicated test mode to continuously receive the plurality of decision symbols and the plurality of predicted symbols and to generate a plurality of detection results accordingly; as well as a debug control circuit coupled to one or more nodes of the received signal processing circuit and comprising a storage device for continuously recording the contents of one or more signals obtained at the one or more nodes in the dedicated test mode in the storage device; The debug control circuit receives the plurality of detection results and terminates recording the content of the one or more signals in response to a status of at least one detection result among the plurality of detection results. 2 . The signal processing device of claim 1 , wherein when the status of the at least one detection result among the plurality of detection results indicates that a decision error occurs, the debug control circuit stops recording the content of the one or more signals.

3. The signal processing device according to claim 1 , wherein the received signal processing circuit operates in a data exchange phase after parameter training of a decision feedback equalizer has been completed, and the signal processing device further comprises: The mode control circuit is coupled to the register and is used for determining whether to enter the exclusive test mode during the data exchange phase according to the value of the register.

4. The signal processing apparatus according to claim 1 , further comprising: The coefficient adjustment circuit is used to adaptively adjust one or more coefficients of the decision feedback equalizer according to an equalizer error signal, wherein in the dedicated test mode, the equalizer error signal is generated according to the output signal of the decision feedback equalizer and the reference signal.

5. The signal processing apparatus according to claim 1 , further comprising: The synchronization module is coupled to the exclusive test mode symbol generation circuit and is used for adjusting the symbol times corresponding to the plurality of predicted symbols in the exclusive test mode to align the symbol times corresponding to the plurality of transmitted symbols transmitted by the transmitter.

6. The signal processing device of claim 5 , wherein the synchronization module compares a current predicted symbol generated by the dedicated test mode symbol generation circuit according to the predetermined rule with a current decision symbol output by the sniffer, and when the current predicted symbol matches the current decision symbol, the synchronization module determines that the symbol times corresponding to the plurality of predicted symbols are aligned with the symbol times corresponding to the plurality of transmitted symbols.

7. A signal processing method for processing a signal received by a receiver in a communication system, wherein the receiver includes a received signal processing circuit, the received signal processing circuit operating in a data exchange phase after parameter training of a decision feedback equalizer has been completed, the signal processing method comprising: determining to enter a dedicated test mode during the data exchange phase in response to a value in the register; generating a plurality of predicted symbols as reference signals according to a plurality of decision symbols outputted by a clipper of the received signal processing circuit and a predetermined rule; continuously receiving and detecting the plurality of decision symbols and the plurality of prediction symbols, and correspondingly generating a plurality of detection results; continuously recording the content of one or more signals obtained at one or more nodes of the received signal processing circuit; as well as Recording the content of the one or more signals is terminated in response to a status of at least one of the plurality of detection results.

8. The signal processing method according to claim 7 , wherein the content of the one or more signals is stored in a storage device as a plurality of current records, and the step of continuously obtaining and recording the content of the one or more signals obtained by the one or more nodes of the received signal processing circuit further comprises: When the storage device is full, the content stored in the storage device is overwritten with the content of the one or more signals obtained most recently to update the multiple current records. And wherein the step of terminating recording the content of the one or more signals in response to the status of at least one detection result in the plurality of detection results further comprises: When the status of the at least one detection result among the multiple detection results indicates that a decision error occurs, stop overwriting the stored content in the storage device with the content of the one or more signals obtained most recently to retain the multiple current records.

9. The signal processing method according to claim 7, further comprising: generating an equalizer error signal according to the output signal of the decision feedback equalizer of the receiving signal processing circuit and the reference signal; as well as One or more coefficients of the decision feedback equalizer are adaptively adjusted according to the equalizer error signal.

10. The signal processing method according to claim 7, further comprising: adjusting the symbol times corresponding to the plurality of predicted symbols so as to be aligned with the symbol times corresponding to the plurality of transmitted symbols transmitted by a transmitter in the communication system, When the current predicted symbol generated according to the predetermined rule matches the current decision symbol output by the clipper, it is determined that the symbol times corresponding to the plurality of predicted symbols are aligned with the symbol times corresponding to the plurality of transmitted symbols.

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