Data acquisition method, data processing method and data management system

Abstract

The invention discloses a data acquisition method, a data processing method and a data management system, and relates to the field of electronic testing and measurement. Comprising the steps that a main control module sends a PD packet acquisition instruction to a first data capture module and sends a target data acquisition instruction to a second data capture module; the first data capture module takes the moment when the PD packet acquisition instruction is received as an initial moment, acquires a PD packet from the initial moment, and sends the acquired PD packet with a first timestamp to the main control module; and the second data capture module takes the moment when the target data acquisition instruction is received as the initial moment, starts to acquire the target data from the initial moment, and sends the acquired target data with a second timestamp to the main control module. Therefore, the PD packet and the target data can be efficiently, simply and conveniently acquired, and a data basis is provided for an engineer to analyze problems occurring in a Type-C interface working process.

Description

Technical Field

[0001] The present application relates to the field of electronic testing and measurement, and in particular to a data acquisition method, a data processing method and a data management system. Background Art

[0002] The Type-C analyzer is a device used to analyze, test and verify the USB Type-C interface and its related protocols. The Type-C analyzer can capture, decode and display the communication data on the Type-C interface, such as the USB Power Delivery protocol packet (PD packet), Auxiliary Interface protocol packet (AUX packet), and the voltage and current data of VBus, CC1, CC2, Aux+, and Aux-, to help engineers analyze problems that arise during the operation of the Type-C interface. How to efficiently and easily obtain communication data on the Type-C interface has become one of the technical issues that need to be solved in the field of electronic testing and measurement. Summary of the invention

[0003] Based on the above problems, the present application provides a data acquisition method for efficiently and easily acquiring communication data on the Type-C interface, providing a data basis for engineers to analyze problems that arise during the operation of the Type-C interface.

[0004] The embodiments of the present application disclose the following technical solutions: In a first aspect, the present application provides a data acquisition method, which is applied to a Type-C analyzer, wherein the Type-C analyzer includes a main control module, a first data capture module, and a second data capture module; the method includes: After receiving the data acquisition instruction sent by the host computer, the main control module sends a PD packet acquisition instruction to the first data capture module and sends a target data acquisition instruction to the second data capture module; The first data capture module uses the moment when the PD packet acquisition instruction is received as the initial moment, and starts to acquire PD packets from the initial moment, and sends the acquired PD packets to the main control module; the PD packet carries a first timestamp; the moment corresponding to the first timestamp is the moment when the first data capture module acquires the corresponding PD packet with the initial moment as the starting moment; The second data capture module uses the moment when the target data acquisition instruction is received as the initial moment, and starts to acquire the target data from the initial moment, and sends the acquired target data to the main control module; the target data has a second timestamp; the moment corresponding to the second timestamp is the moment when the second data capture module acquires the corresponding target data with the initial moment as the starting moment; the target data is at least one of the current or voltage generated during the operation of Type-C.

[0005] In an optional implementation, the method further includes: The main control module encapsulates the received multiple PD packets into PD blocks, encapsulates the received multiple target data into data blocks, and sends the PD blocks and the data blocks to the host computer.

[0006] A second aspect of the present application provides a data processing method, which is applied to a host computer; the host computer is communicatively connected to a Type-C analyzer; the Type-C analyzer includes a main control module, a first data capture module and a second data capture module; the method includes: The host computer parses the received PD block into multiple PD packets, and stores each PD packet into a cache in the order of the time of the first timestamp carried by the PD packet to obtain a PD packet cache queue; the moment corresponding to the first timestamp is the moment when the first data capture module obtains the corresponding PD packet with the initial moment as the starting moment; the initial moment is the moment when the first data capture module receives the PD packet acquisition instruction sent by the main control module; after receiving the data acquisition instruction sent by the host computer, the main control module sends the PD packet acquisition instruction to the first data capture module; At the same time, the host computer parses the received data block into multiple target data, and stores each target data into a cache in the time sequence of the second timestamp carried by the target data to obtain a target data cache queue; the moment corresponding to the second timestamp is the moment when the second data capture module obtains the corresponding target data with the initial moment as the starting moment; after receiving the data acquisition instruction sent by the host computer, the main control module sends a target data acquisition instruction to the second data capture module; the target data is at least one of the current or voltage generated during the operation of Type-C.

[0007] In an optional implementation, the method further includes: After determining that the length of the target data cache queue is greater than a first preset value, the host computer determines whether the length of the PD packet cache queue is greater than 0; If the length of the PD packet cache queue is greater than 0, a display image is drawn based on the target data within a first time range; the first time range is a time range determined based on a target timestamp and a second preset value; the target timestamp is the first timestamp of the first PD packet in the PD packet cache queue; If the length of the PD packet cache queue is 0, a portion of the target data is filtered out from the target data cache queue within a preset second time range as data to be processed, and the display image is drawn based on the data to be processed.

[0008] In an optional implementation, after drawing and displaying the image based on the target data within the first time range, the method further includes: Determining a target time based on the target timestamp and a third preset value; the third preset value is greater than the second preset value; A plurality of first timestamps before the target time are determined as timestamps to be processed, and PD packets corresponding to the timestamps to be processed are removed from the PD packet cache queue.

[0009] In an optional implementation, the method further includes: All target data in the target data cache queue within the preset second time range are deleted from the target data cache queue.

[0010] The third aspect of the present application discloses a data management system, the system comprising a Type-C analyzer and a host computer, wherein: The Type-C analyzer is used to receive the data acquisition instruction sent by the host computer, obtain the PD packet with the first timestamp and the target data with the second timestamp; encapsulate the obtained multiple PD packets into PD blocks and send them to the host computer; encapsulate the obtained multiple target data into data blocks and send them to the host computer; the target data is at least one of the current or voltage generated during the operation of Type-C; the moment corresponding to the first timestamp is the moment when the Type-C analyzer obtains the corresponding PD packet with the initial moment as the starting moment; the moment corresponding to the second timestamp is the moment when the Type-C analyzer obtains the corresponding target data with the initial moment as the starting moment; the initial moment is the moment when the first data acquisition module in the Type-C analyzer receives the PD packet acquisition instruction sent by the main control module in the Type-C analyzer; The host computer is used to send a data acquisition instruction to the Type-C analyzer; parse the received PD block into multiple PD packets, and store each of the PD packets into a cache in the order of time of the first timestamp carried by the PD packets to obtain a PD packet cache queue; parse the received data block into multiple target data, and store each of the target data into a cache in the order of time of the second timestamp carried by the target data to obtain a target data cache queue; draw a display image based on the PD packet cache queue and the target data cache queue.

[0011] In an optional implementation, the Type-C analyzer includes a main control module, a first data capture module and a second data capture module; wherein, The main control module is used to receive the data acquisition instruction sent by the host computer; send the PD packet acquisition instruction to the first data capture module; send the target data acquisition instruction to the second data capture module; receive the PD packet sent by the first data capture module; receive the target data sent by the second data capture module; encapsulate the received multiple PD packets into the PD block and send it to the host computer; encapsulate the received multiple target data into the data block and send it to the host computer; The first data capture module is used to receive the PD packet acquisition instruction, take the time when the PD packet acquisition instruction is received as the initial time; take the initial time as the starting time, acquire the PD packet; and send the acquired PD packet to the main control module; The second data capture module is used to receive the target data acquisition instruction, and use the time when the target data acquisition instruction is received as the initial time; use the initial time as the starting time to acquire the target data; and send the acquired target data to the main control module.

[0012] In an optional implementation, the host computer includes a command sending module, a PD packet processing module, a target data processing module and a drawing module; wherein, The instruction sending module is used to send the data collection instruction to the Type-C analyzer; The PD packet processing module is used to receive the PD block sent by the Type-C analyzer, parse the received PD block into multiple PD packets, and store each PD packet into a cache in a time sequence of a first timestamp carried by the PD packet to obtain the PD packet cache queue; The target data processing module is used to receive the data block sent by the Type-C analyzer, parse the received data block into multiple target data, and store each target data into a cache according to the time sequence of the second timestamp carried by the target data to obtain the target data cache queue; The drawing module is used to draw the display image based on the PD packet cache queue and the target data cache queue.

[0013] In an optional implementation, drawing the display image based on the PD packet cache queue and the target data cache queue includes: After determining that the length of the target data cache queue is greater than a first preset value, determining whether the length of the PD packet cache queue is greater than 0; If the length of the PD packet cache queue is greater than 0, a display image is drawn based on the target data within the first time range; and a target moment is determined based on the target timestamp and a third preset value; multiple first timestamps before the target moment are determined as timestamps to be processed, and the PD packets corresponding to the timestamps to be processed are removed from the PD packet cache queue; the first time range is a time range determined based on the target timestamp and the second preset value; the target timestamp is the first timestamp of the first PD packet in the PD packet cache queue; the third preset value is greater than the second preset value; If the length of the PD packet cache queue is 0, part of the target data is filtered out from the target data cache queue within the preset second time range as data to be processed, and the display image is drawn based on the data to be processed; and all target data in the target data cache queue within the preset second time range are deleted from the target data cache queue.

[0014] Compared with the prior art, this application has the following beneficial effects: The present application discloses a data acquisition method, which is applied to a Type-C analyzer including a main control module, a first data capture module and a second data capture module. The method includes: after receiving the data acquisition instruction sent by the host computer, the main control module sends a PD packet acquisition instruction to the first data capture module and sends a target data acquisition instruction to the second data capture module; the first data capture module uses the moment of receiving the PD packet acquisition instruction as the initial moment, and starts to acquire the PD packet from the initial moment, and sends the acquired PD packet with a first timestamp to the main control module; the second data capture module uses the moment of receiving the target data acquisition instruction as the initial moment, and starts to acquire the target data from the initial moment, and sends the acquired target data with a second timestamp to the main control module. In this way, the PD packet and target data can be acquired efficiently and easily, providing a data basis for engineers to analyze problems that occur during the working process of the Type-C interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 A schematic diagram of a distorted display image provided by an embodiment of the present application; Figure 2 A schematic diagram of the structure of a data management system provided in an embodiment of the present application; Figure 3 A schematic diagram of the interaction between various modules during the operation of a Type-C analyzer provided in an embodiment of the present application; Figure 4 A schematic diagram of a host computer workflow provided in an embodiment of the present application; Figure 5 A flowchart of drawing and displaying an image provided by an embodiment of the present application; Fig. 6A A schematic diagram of current and voltage changes provided in an embodiment of the present application; Figure 6B A schematic diagram of another current and voltage change provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] During the plugging and unplugging of Type-C interface devices, short voltage fluctuations lasting 5 to 20 milliseconds will occur on VBus and other lines. In order to accurately capture the complete process of this voltage transient, the Type-C analyzer needs to continuously monitor and record the voltage change data at an extremely high sampling rate and transmit this massive data to the host computer. The host computer cannot efficiently process the massive data received, resulting in interface freezes, flickering or white screens, and taking up a lot of unnecessary storage space.

[0018] If the sampling frequency is reduced to reduce the burden on the host computer, although the data transmission volume and interface refresh frequency can be reduced, the details of the voltage jump will be lost, making the drawn display image (i.e. the image of the current and voltage changing over time) distorted. The distortion of the display image will make it impossible for engineers to accurately locate the problems that occur during the operation of the Type-C interface.

[0019] Figure 1 A schematic diagram of a distorted display image provided in an embodiment of the present application. Figure 1 The horizontal axis is time. Figure 1 It can be seen that the VBus voltage and PD packet (each dot represents a PD packet, and when the time interval is short, it looks like a thick line) change over time during the operation of the Type-C interface. Figure 1 As shown in the figure: When the sampling frequency is low, the Type-C analyzer cannot capture the sudden change of VBus voltage, resulting in a deep V shape in the curve of VBus voltage changing over time, causing the displayed image to be distorted. Therefore, how to ensure data integrity while avoiding the limitation of host computer performance is one of the technical problems that need to be solved in the field of electronic testing and measurement.

[0020] To facilitate understanding of the technical solutions in this application, the technical terms in this application are first explained.

[0021] The PD protocol (USB Power Delivery, USB PD) is a standard protocol developed by the USB-IF (USB Implementers Forum) organization. It is a fast charging technology based on the USB interface, designed to provide higher charging power and charging speed to meet the needs of modern electronic devices for fast charging.

[0022] Type-C is a USB interface designed by the USB-IF organization. It can be inserted from either side, and is approximately 8.3mm×2.5mm in size. Like other interfaces, it supports USB standard functions such as charging, data transmission, and display output.

[0023] VBus (Voltage Bus) is an important component of the USB interface. It mainly provides the required power for the connected devices to ensure that the devices can work normally.

[0024] CC1 and CC2 in the Type-C interface are the abbreviations of Configuration Channel, which are two specific pins in the Type-C interface. They are used to detect the device type, connection direction, and configure data transmission when the device is connected.

[0025] Aux+ and Aux- are the positive and negative poles in the AUX (Auxiliary Interface) interface. The AUX interface is an analog audio signal interface used to connect audio devices such as headphones and speakers.

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] Figure 2 A schematic diagram of the structure of a data management system provided in an embodiment of the present application. Figure 2 As shown, the data management system in the present application includes a Type-C analyzer and a host computer. The Type-C analyzer includes a main control module, a first data capture module and a second data capture module; the host computer includes a command sending module, a PD packet processing module, a target data processing module and a drawing module. Among them, the Type-C analyzer and the host computer are connected through a USB virtual serial port; the first data capture module and the second data capture module in the Type-C analyzer are both connected to the wires of the Type-C power supply end and the Type-C power consumption end.

[0028] The main control module is used to receive the data acquisition instruction sent by the host computer; send the PD packet acquisition instruction to the first data capture module; send the target data acquisition instruction to the second data capture module at the same time; receive the PD packet (also called PD protocol packet) sent by the first data capture module; receive the target data sent by the second data capture module; encapsulate the received multiple PD packets into PD blocks, and send them to the host computer; encapsulate the received multiple target data into data blocks, and send them to the host computer; The first data capture module is used to receive a PD packet acquisition instruction, and take the time when the PD packet acquisition instruction is received as the initial time; take the initial time as the starting time, acquire the PD packet; and send the acquired PD packet to the main control module; The second data capture module is used to receive the target data acquisition instruction, take the time when the target data acquisition instruction is received as the initial time (i.e., complete the time synchronization with the first data capture module); take the initial time as the starting time, acquire the target data; and send the acquired target data to the main control module; A command sending module, used to send data collection commands to the Type-C analyzer; The PD packet processing module is used to receive the PD block sent by the Type-C analyzer, parse the received PD block into multiple PD packets, and store each PD packet in a cache in the order of the time of the first timestamp carried by the PD packet to obtain a PD packet cache queue; wherein the first timestamp is the time when the first data capture module obtains the corresponding PD packet with the initial time as the starting time; The target data processing module is used to receive the data block sent by the Type-C analyzer, parse the received data block into multiple target data, and store each target data into a cache in the time sequence of the second timestamp carried by the target data to obtain a target data cache queue; wherein the time corresponding to the second timestamp is the time when the second data capture module obtains the corresponding target data with the initial time as the starting time; The drawing module is used to draw and display images based on the PD packet buffer queue and the target data buffer queue. The process of "drawing and displaying images based on the PD packet buffer queue and the target data buffer queue" will be described in detail in the subsequent embodiments of this application.

[0029] The target data in this application is at least one of the current or voltage generated during the operation of Type-C, including but not limited to the voltage and current data of VBus, CC1, CC2, Aux+, and Aux-.

[0030] Figure 3 A schematic diagram of the interaction between the modules during the operation of a Type-C analyzer provided in an embodiment of the present application. Figure 3 The process of the coordinated operation of each module in the Type-C analyzer is described in detail.

[0031] After starting the data management system, power on the Type-C analyzer and establish a connection with the host computer. Click the Start Packet Capture button on the display interface of the software installed in the host computer to send the corresponding data acquisition instruction to the main control module.

[0032] After receiving the data acquisition instruction sent by the host computer, the main control module sends a PD packet acquisition instruction to the first data capture module and sends a target data acquisition instruction to the second data capture module.

[0033] The first data capture module takes the moment when the PD packet acquisition instruction is received as the initial moment; and starts to acquire PD packets from the initial moment, and sends the acquired PD packets to the main control module.

[0034] The PD packet carries a first timestamp; the moment corresponding to the first timestamp is the moment when the first data capture module obtains the corresponding PD packet with the initial moment as the starting moment.

[0035] For example, the initial time is set to 0, and the initial time is taken as the starting time. The first PD packet is obtained at 1 ms, and the first timestamp of the first PD packet is 1 ms.

[0036] The second data capture module uses the time when the target data acquisition instruction is received as the initial time, and starts to acquire the target data from the initial time, and sends the acquired target data to the main control module. The target data has a second timestamp.

[0037] The moment corresponding to the second timestamp is the moment when the second data capture module acquires the corresponding target data with the initial moment as the starting moment.

[0038] For example, the initial time is set to 0, and the initial time is taken as the starting time. The first target data is obtained at 2 ms, and the second timestamp of the first target data is 2 ms.

[0039] The main control module encapsulates the received multiple PD packets into PD blocks, encapsulates the received multiple target data into data blocks, and sends the PD blocks and data blocks to the host computer.

[0040] From the above introduction, we can know that the role of Type-C analyzer is to capture PD packets and obtain target data (at least one of the current or voltage generated during the operation of Type-C). The characteristics of PD packets are instantaneous multiple lines, while the characteristics of current and voltage are multi-channel high frequency.

[0041] In this application, the size of the PD packet is 50 bytes, and the size of the PD block is 1-4K bytes. The main control module splices multiple PD packets into PD blocks, splices multiple target data into data blocks, and then sends the PD blocks and data blocks to the host computer. The advantage is that the sending frequency can be reduced and the utilization rate of the serial port between the main control module and the host computer can be improved.

[0042] Figure 4 A schematic diagram of a host computer workflow provided in an embodiment of the present application. Figure 4As shown in the figure, the working process of the host computer in the data management system includes: S401, the Type-C analyzer is powered on and a connection is established with the host computer.

[0043] S402, click the start packet capture button on the display interface of the corresponding software of the host computer, and send the corresponding data acquisition instruction of starting packet capture to the main control module.

[0044] S403, receiving the PD block sent by the Type-C analyzer, parsing the received PD block into multiple PD packets, and storing each PD packet into a cache in the time sequence of the first timestamp carried by the PD packet to obtain a PD packet cache queue.

[0045] S404, receiving a data block sent by the Type-C analyzer, parsing the received data block into multiple target data, and storing each target data into a cache in a time sequence of a second timestamp carried by the target data to obtain a target data cache queue.

[0046] S405 , drawing a display image based on the PD packet cache queue and the target data cache queue.

[0047] For the instantaneous influx of PD packets and high-frequency target data sent by the Type-C analyzer, the host computer uses the highest priority thread to receive the data of the USB virtual serial port into the cache first, and then uses a reasonable filtering strategy to draw a display image based on the PD packet cache queue and the target data cache queue during the system idle time according to the order of the timestamps corresponding to the PD packets and the target data. The display image is a schematic diagram indicating the changes of current, voltage and PD packets over time.

[0048] Figure 5 A flowchart of drawing and displaying an image is provided in an embodiment of the present application. Figure 5 As shown, the process of drawing and displaying an image based on a PD packet cache queue and a target data cache queue disclosed in the present application includes: S501, obtaining a PD packet cache queue and a target data cache queue.

[0049] S502: Determine whether the length of the target data cache queue is greater than a first preset value.

[0050] For example, in the present application, 4000 is used as the first preset value. If the length of the target data cache queue is greater than the first preset value, the process proceeds to S503; otherwise, the process returns to S502.

[0051] S503, determine whether the length of the PD packet buffer queue is greater than 0.

[0052] If the length of the PD packet buffer queue is greater than 0, proceed to S504; if the length of the PD packet buffer queue is 0, proceed to S506.

[0053] S504, determining a first time range based on the target timestamp and the second preset value; and drawing a display image based on the target data within the first time range.

[0054] In this application, the target timestamp is the first timestamp of the first PD packet (the first-order PD packet) in the PD packet cache queue.

[0055] In the present application, the second preset value is 2s, and the time range of 2s before and after the first timestamp can be used as the first time range; the display image is drawn based on the target data (full current and voltage data) within the first time range, thereby ensuring that the drawn display image can truly reflect the changes in current and voltage during the working process of the Type-C device, such as when plugging and unplugging.

[0056] S505, determine the target time based on the target timestamp and the third preset value; determine multiple first timestamps before the target time as timestamps to be processed, and remove the PD packets corresponding to the timestamps to be processed from the PD packet cache queue.

[0057] Exemplarily, the third preset value in the present application is 4s, then the sum of the first timestamp and 4s can be used as the target time; then the multiple first timestamps before the target time are used as timestamps to be processed, and the PD packets corresponding to the timestamps to be processed are removed from the PD packet cache queue to avoid repeated processing and waste of CPU resources.

[0058] S506 , filtering out part of the target data from the target data cache queue within the preset second time range as data to be processed, and drawing a display image based on the data to be processed.

[0059] Exemplarily, the fourth preset value in the present application may be 1s; three target data located at the 1st, 334th and 688th positions may be taken out from the 1000 data packets corresponding to the first 1s in the target data cache queue as data to be processed; the data to be processed are sent to the drawing module in the host computer, and a display image is drawn based on the above data to be processed.

[0060] S507: Delete all target data in the target data cache queue within a preset second time range from the target data cache queue.

[0061] That is, the 1000 data packets corresponding to the first 1s in the target data cache queue are removed from the target data cache queue.

[0062] Assume that in the data management system disclosed in this application, the target data is sampled once every 1ms, and the corresponding threshold, that is, the second preset value is 2s. When the Type-C device is plugged in, there are about 60 PD packets in the 5 seconds before and after, and there are 3-5 PD packets at the 17th second. According to the above algorithm, the full PD packets between -2~7, ..., 15~18 seconds are recorded as 20 seconds × 1000, which are compressed to (9+4) × 1000 + 8 × 3 = 13024. Therefore, the amount of data during plugging and unplugging is reduced by 20000 -13024 = 6976, a reduction of 34.88%. Without plugging and unplugging the device, the amount of data per second is reduced by 997, and the data compression ratio is higher. Therefore, the upper computer disclosed in this application can reduce the storage pressure and the pressure of drawing and displaying images after filtering the target data through a preset strategy.

[0063] Fig. 6A A schematic diagram of current and voltage changes provided in an embodiment of the present application. Figure 6B A schematic diagram of another current and voltage change provided in an embodiment of the present application. Fig. 6A and Figure 6B The horizontal axis in is time. Fig. 6A It can be seen that the CC1 voltage, CC2 voltage, VBus current, VBus voltage and PD packet (each point represents a PD packet, and when the time interval is short, it looks like a thick line) generated during the operation of the Type-C interface change over time. Fig. 6A As shown, by using the Type-C analyzer and host computer in the data management system disclosed in this application, PD packets and target data can be collected at a high frequency, rich curves can be obtained, and the jump of target data (multiple types of current and voltage) within 20 milliseconds can be captured. Figure 6B It can be seen that the CC1 voltage, VBus voltage and PD packet change over time during the working process of the Type-C interface. Figure 6B Figure 2 shows various types of voltage transients with a sampling interval of 5 milliseconds.

[0064] In summary, the present application discloses a data management system, including a Type-C analyzer and a host computer, through which the communication data on the Type-C interface can be monitored at a low cost. In the present application, there is no need for a hardware circuit to judge the plugging and unplugging of a Type-C device, but a threshold (a second preset value) is set according to the arrival time of a PD packet, and the jump situation of the target data (current and voltage) within the threshold range of the PD packet arrival is displayed and stored according to the threshold, so that the Type-C analyzer can perform high-frequency detection on the target data, such as the data of the instantaneous voltage jump during the plugging and unplugging of the Type-C, complete the detection of the details of the entire jump process, and can reasonably transfer it in batches to the host computer. Through the preset filtering strategy, the host computer can filter out some data with no obvious changes before displaying and storing, thereby saving a lot of storage space on the basis of improving display performance.

[0065] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The method embodiment described above is merely schematic, in which the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A data acquisition method, characterized in that: The method is applied to a Type-C analyzer, which includes a main control module, a first data capture module and a second data capture module; the method includes: After receiving the data acquisition instruction sent by the host computer, the main control module sends a PD packet acquisition instruction to the first data capture module and sends a target data acquisition instruction to the second data capture module; The first data capture module uses the moment when the PD packet acquisition instruction is received as the initial moment, and starts to acquire PD packets from the initial moment, and sends the acquired PD packets to the main control module; the PD packet carries a first timestamp; the moment corresponding to the first timestamp is the moment when the first data capture module acquires the corresponding PD packet with the initial moment as the starting moment; The second data capture module uses the moment when the target data acquisition instruction is received as the initial moment, and starts to acquire the target data from the initial moment, and sends the acquired target data to the main control module; the target data has a second timestamp; the moment corresponding to the second timestamp is the moment when the second data capture module acquires the corresponding target data with the initial moment as the starting moment; the target data is at least one of the current or voltage generated during the operation of Type-C.

2. The method according to claim 1, characterized in that: The method further comprises: The main control module encapsulates the received multiple PD packets into PD blocks, encapsulates the received multiple target data into data blocks, and sends the PD blocks and the data blocks to the host computer.

3. A data processing method, characterized in that: The method is applied to a host computer; the host computer is communicatively connected to a Type-C analyzer; the Type-C analyzer includes a main control module, a first data capture module and a second data capture module; the method includes: The host computer parses the received PD block into multiple PD packets, and stores each PD packet into a cache in the order of the time of the first timestamp carried by the PD packet to obtain a PD packet cache queue; the moment corresponding to the first timestamp is the moment when the first data capture module obtains the corresponding PD packet with the initial moment as the starting moment; the initial moment is the moment when the first data capture module receives the PD packet acquisition instruction sent by the main control module; after receiving the data acquisition instruction sent by the host computer, the main control module sends the PD packet acquisition instruction to the first data capture module; At the same time, the host computer parses the received data block into multiple target data, and stores each target data into a cache in the time sequence of the second timestamp carried by the target data to obtain a target data cache queue; the moment corresponding to the second timestamp is the moment when the second data capture module obtains the corresponding target data with the initial moment as the starting moment; after receiving the data acquisition instruction sent by the host computer, the main control module sends a target data acquisition instruction to the second data capture module; the target data is at least one of the current or voltage generated during the operation of Type-C.

4. The method according to claim 3, characterized in that The method further comprises: After determining that the length of the target data cache queue is greater than a first preset value, the host computer determines whether the length of the PD packet cache queue is greater than 0; If the length of the PD packet cache queue is greater than 0, a display image is drawn based on the target data within a first time range; the first time range is a time range determined based on a target timestamp and a second preset value; the target timestamp is the first timestamp of the first PD packet in the PD packet cache queue; If the length of the PD packet cache queue is 0, a portion of the target data is filtered out from the target data cache queue within a preset second time range as data to be processed, and the display image is drawn based on the data to be processed.

5. The method according to claim 4, characterized in that After drawing and displaying the image based on the target data within the first time range, the method further includes: Determining a target time based on the target timestamp and a third preset value; the third preset value is greater than the second preset value; A plurality of first timestamps before the target time are determined as timestamps to be processed, and PD packets corresponding to the timestamps to be processed are removed from the PD packet cache queue.

6. The method according to claim 4, characterized in that Also includes: All target data in the target data cache queue within the preset second time range are deleted from the target data cache queue.

7. A data management system, characterized in that: The system includes a Type-C analyzer and a host computer, wherein: The Type-C analyzer is used to receive the data acquisition instruction sent by the host computer, obtain the PD packet with the first timestamp and the target data with the second timestamp; encapsulate the obtained multiple PD packets into PD blocks and send them to the host computer; encapsulate the obtained multiple target data into data blocks and send them to the host computer; the target data is at least one of the current or voltage generated during the operation of Type-C; the moment corresponding to the first timestamp is the moment when the Type-C analyzer obtains the corresponding PD packet with the initial moment as the starting moment; the moment corresponding to the second timestamp is the moment when the Type-C analyzer obtains the corresponding target data with the initial moment as the starting moment; the initial moment is the moment when the first data acquisition module in the Type-C analyzer receives the PD packet acquisition instruction sent by the main control module in the Type-C analyzer; The host computer is used to send a data acquisition instruction to the Type-C analyzer; parse the received PD block into multiple PD packets, and store each of the PD packets into a cache in the order of time of the first timestamp carried by the PD packets to obtain a PD packet cache queue; parse the received data block into multiple target data, and store each of the target data into a cache in the order of time of the second timestamp carried by the target data to obtain a target data cache queue; draw a display image based on the PD packet cache queue and the target data cache queue.

8. The system according to claim 7, characterized in that The Type-C analyzer includes a main control module, a first data capture module and a second data capture module; wherein, The main control module is used to receive the data acquisition instruction sent by the host computer; send the PD packet acquisition instruction to the first data capture module; send the target data acquisition instruction to the second data capture module; receive the PD packet sent by the first data capture module; receive the target data sent by the second data capture module; encapsulate the received multiple PD packets into the PD block and send it to the host computer; encapsulate the received multiple target data into the data block and send it to the host computer; The first data capture module is used to receive the PD packet acquisition instruction, take the time when the PD packet acquisition instruction is received as the initial time; take the initial time as the starting time, acquire the PD packet; and send the acquired PD packet to the main control module; The second data capture module is used to receive the target data acquisition instruction, and use the time when the target data acquisition instruction is received as the initial time; use the initial time as the starting time to acquire the target data; and send the acquired target data to the main control module.

9. The system according to claim 7, characterized in that The host computer includes a command sending module, a PD packet processing module, a target data processing module and a drawing module; wherein, The instruction sending module is used to send the data collection instruction to the Type-C analyzer; The PD packet processing module is used to receive the PD block sent by the Type-C analyzer, parse the received PD block into multiple PD packets, and store each PD packet into a cache in a time sequence of a first timestamp carried by the PD packet to obtain the PD packet cache queue; The target data processing module is used to receive the data block sent by the Type-C analyzer, parse the received data block into multiple target data, and store each target data into a cache according to the time sequence of the second timestamp carried by the target data to obtain the target data cache queue; The drawing module is used to draw the display image based on the PD packet cache queue and the target data cache queue.

10. The system according to claim 9, characterized in that Drawing the display image based on the PD packet cache queue and the target data cache queue includes: After determining that the length of the target data cache queue is greater than a first preset value, determining whether the length of the PD packet cache queue is greater than 0; If the length of the PD packet cache queue is greater than 0, a display image is drawn based on the target data within the first time range; and a target moment is determined based on the target timestamp and a third preset value; multiple first timestamps before the target moment are determined as timestamps to be processed, and the PD packets corresponding to the timestamps to be processed are removed from the PD packet cache queue; the first time range is a time range determined based on the target timestamp and a second preset value; the target timestamp is the first timestamp of the first PD packet in the PD packet cache queue; the third preset value is greater than the second preset value; If the length of the PD packet cache queue is 0, part of the target data is filtered out from the target data cache queue within the preset second time range as data to be processed, and the display image is drawn based on the data to be processed; and all target data in the target data cache queue within the preset second time range are deleted from the target data cache queue.

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