Method for manufacturing a semiconductor structure, semiconductor structure, memory and electronic device

Abstract

The present disclosure provides a semiconductor structure preparation method, a semiconductor structure, a memory and an electronic device. The semiconductor structure preparation method comprises the following steps: sequentially preparing a first doped layer, a sacrificial layer and a second doped layer on a substrate; etching the second doped layer, the sacrificial layer and the first doped layer along a first direction to form a plurality of first-direction first grooves; etching and removing part of the sacrificial layer exposed in the first-direction first grooves to prepare a first channel sublayer between the first doped layer and the second doped layer; etching the second doped layer, the sacrificial layer and the first doped layer along the first direction to form a plurality of first-direction second grooves, the first-direction second grooves being alternately and spacedly arranged with the first-direction first grooves; etching and removing the sacrificial layer to prepare a second channel sublayer between the first doped layer and the second doped layer, the second channel sublayer being in contact with the first channel sublayer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a preparation method of semiconductor structure, semiconductor structure, memory and electronic device. BACKGROUND

[0002] In the technical field of semiconductor such as memory, reducing the key size of device is an effective way to improve the performance of device, but the short channel effect limits the further miniaturization of device size. Vertical channel transistor (VCT) is a new type of semiconductor device. Compared with the traditional planar transistor, the channel length of vertical channel array transistor can better overcome the problem of short channel effect existing in planar device, so that higher stacking density can be achieved. However, with the continuous reduction of device size, the vertical channel transistor prepared in the traditional technology will have the problem of poor channel quality due to the limitation of actual preparation process. SUMMARY

[0003] Therefore, it is necessary to provide a preparation method of semiconductor structure to improve the channel quality of vertical channel transistor in view of the problems in the background art. Further, a semiconductor structure, a memory and an electronic device are provided.

[0004] According to some embodiments of the present disclosure, the present disclosure provides a preparation method of semiconductor structure, comprising the following steps:

[0005] Prepared in sequence on the substrate are a first doped layer, a sacrificial layer and a second doped layer;

[0006] Etching the second doped layer, the sacrificial layer and the first doped layer along a first direction to form a plurality of first direction first grooves;

[0007] Etching and removing part of the sacrificial layer exposed in the first direction first groove to prepare a first channel sub-layer between the first doped layer and the second doped layer;

[0008] Etching the second doped layer, the sacrificial layer and the first doped layer along the first direction to form a plurality of first direction second grooves, which are alternately and spacedly arranged with the first direction first grooves;

[0009] Etching and removing the sacrificial layer to prepare a second channel sub-layer between the first doped layer and the second doped layer, which contacts the first channel sub-layer.

[0010] In some embodiments of the present disclosure, the step of preparing the second channel sublayer includes: preparing the second channel sublayer by epitaxial growth on the first channel sublayer; and / or,

[0011] The step of preparing the first channel sublayer includes: preparing the first channel sublayer on the sacrificial layer by epitaxial growth.

[0012] In some embodiments of the present disclosure, the thickness of the first channel sublayer in a direction away from the second channel sublayer is 5 nm to 20 nm; and / or,

[0013] The thickness of the second channel sublayer in a direction away from the first channel sublayer is 5 nm to 20 nm.

[0014] In some embodiments of the present disclosure, the thickness of the sacrificial layer in its height direction is 20 nm to 100 nm.

[0015] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following step: preparing a bit line structure in the substrate located below the first doping layer.

[0016] In some embodiments of the present disclosure, the bit line structure extends along a second direction intersecting the first direction;

[0017] Before preparing the bit line structure, the following steps are further included: etching the second doped layer, the sacrificial layer, the first doped layer and the substrate along the second direction to form a plurality of second-direction trenches, wherein the bottoms of the second-direction trenches are located in the substrate, and preparing a second-direction dielectric layer in the second-direction trenches;

[0018] In the step of preparing the bit line structure, the bit line structure is prepared between adjacent second-direction dielectric layers.

[0019] In some embodiments of the present disclosure, the step of forming a plurality of second-direction grooves includes:

[0020] The second doped layer, the sacrificial layer, the first doped layer and the substrate are etched multiple times along the second direction to form a plurality of second-direction trenches spaced apart from each other.

[0021] In some embodiments of the present disclosure, the step of preparing a second-direction dielectric layer in the second-direction trench is performed before the step of forming a plurality of first-direction first trenches;

[0022] The step of preparing the bit line structure is performed after forming a plurality of first trenches in the first direction and forming a plurality of second trenches in the first direction.

[0023] In some embodiments of the present disclosure, the first channel sub-layer and the second channel sub-layer are combined as a channel layer, and the method for manufacturing the semiconductor structure further comprises the following steps: manufacturing a gate dielectric layer surrounding the channel layer, and manufacturing a word line conductive layer on a side of the gate dielectric layer away from the channel layer.

[0024] In some embodiments of the present disclosure, after the first channel sub-layer is manufactured, the method further comprises the following step: manufacturing a first sidewall protection layer on a surface of the first channel sub-layer on a side close to the first direction first groove;

[0025] In some embodiments of the present disclosure, after the second channel sub-layer is manufactured, the method further comprises the following step: manufacturing a second sidewall protection layer on a surface of the second channel sub-layer on a side close to the first direction second groove;

[0026] In some embodiments of the present disclosure, after the gate dielectric layer and the word line conductive layer surrounding the channel layer are manufactured, the method further comprises the following step: removing part of the first sidewall protection layer and part of the second sidewall protection layer to expose the channel layer.

[0027] In some embodiments of the present disclosure, after the second channel sub-layer is manufactured, the method further comprises the following step: manufacturing an isolation layer in the first direction first groove and the first direction second groove;

[0028] The gate dielectric layer and the word line conductive layer are manufactured between the isolation layer and the channel layer.

[0029] In some embodiments of the present disclosure, the material of the sacrificial layer comprises a silicon germanium alloy, and the material of the first channel sub-layer and the material of the second channel sub-layer both comprise silicon.

[0030] Further, the present disclosure also provides a semiconductor structure, which comprises: a substrate and a plurality of active pillars arranged on the substrate, the active pillars comprising a first source-drain layer, a channel layer and a second source-drain layer arranged in sequence on the substrate, the channel layer being arranged between the first source-drain layer and the second source-drain layer;

[0031] The semiconductor structure also has a plurality of first direction first grooves and a plurality of first direction second grooves, the first direction first grooves and the first direction second grooves both extend along the first direction, and the first direction first grooves and the first direction second grooves are alternately and spacedly arranged, and each of the active pillars is located between adjacent first direction first grooves and first direction second grooves;

[0032] The channel layer includes a first channel sublayer and a second channel sublayer in contact with each other. The first channel sublayer is located on a side of the second channel sublayer close to the first trench in the first direction. The second channel sublayer is located on a side of the first channel sublayer close to the second trench in the first direction.

[0033] Furthermore, the present disclosure also provides a memory, which includes a semiconductor structure prepared by the method for preparing a semiconductor structure described in any of the above embodiments, or includes the semiconductor structure described in any of the above embodiments.

[0034] Furthermore, the present disclosure also provides an electronic device, which includes the memory as described in any of the above embodiments.

[0035] In the preparation method of the semiconductor structure disclosed in the present invention, a first channel sublayer is prepared after etching a first groove in a first direction, and a second channel sublayer in contact with the first channel sublayer is prepared after etching a second groove in the first direction. By etching in steps and preparing in batches, it is possible to further prepare a second channel sublayer on the basis of the first channel sublayer. Compared with a single first channel sublayer, further providing a second channel sublayer can significantly increase the overall thickness of the channel layer, which can make it more difficult for the channel layer as a whole to be over-etched. In addition, the first channel sublayer and the second channel sublayer prepared in batches make the channel layer as a whole more symmetrical. Therefore, the preparation method disclosed in the present invention can effectively improve the performance of the channel layer.

[0036] Furthermore, etching the trenches twice in the first direction creates larger gaps between the trenches formed during each etching step, thereby reducing the equipment resolution requirements during the fabrication process. Taking all of these factors into account, the disclosed fabrication method can simultaneously address both pattern layer precision and channel layer quality issues, effectively improving the fabrication yield of high-density, small-size devices.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0039] Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor structure disclosed herein;

[0040] Figure 2A Structure diagram of the substrate and the structure of the first doped layer, the sacrificial layer and the second doped layer arranged on the substrate, Figure 2B Figure 2A Structure diagram of the cross section structure along AA' in the structure shown, Figure 2C Figure 2A Structure diagram of the cross section structure along BB' in the structure shown;

[0041] Figure 3A Structure diagram of forming the first trench in the first direction on the basis of the structure shown, Figure 2A Figure 3B Figure 3A Structure diagram of the cross section structure along AA' in the structure shown, Figure 3C Figure 3A Structure diagram of the cross section structure along BB' in the structure shown;

[0042] Figure 4A Structure diagram of preparing the first dielectric layer on the basis of the structure shown, Figure 3A Figure 4B Figure 4A Structure diagram of the cross section structure along AA' in the structure shown, Figure 4C Figure 4A Structure diagram of the cross section structure along BB' in the structure shown;

[0043] Figure 5A Structure diagram of preparing the second trench in the second direction on the basis of the structure shown, Figure 4A Figure 5B Figure 5A Structure diagram of the cross section structure along AA' in the structure shown, Figure 5C Figure 5A Structure diagram of the cross section structure along BB' in the structure shown;

[0044] Figure 6A Structure diagram of preparing the second dielectric layer on the basis of the structure shown, Figure 5A Figure 6B Figure 6A Structure diagram of the cross section structure along AA' in the structure shown, Figure 6C Figure 6A Structure diagram of the cross section structure along BB' in the structure shown;

[0045] Figure 7A Structure diagram of forming the first trench in the first direction on the basis of the structure shown, Figure 6A Figure 7B Figure 7A Structure diagram of the cross section structure along AA' in the structure shown, Figure 7C Figure 7A ​​​​​​​​​​​​​​​​​A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0046] Figure 8A A structure schematic diagram of the structure shown along the position of AA'; Figure 7A A structure schematic diagram of the structure shown along the position of BB'; Figure 8B A structure schematic diagram of the structure shown along the position of AA'; Figure 8A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 8C A structure schematic diagram of the structure shown along the position of AA'; Figure 8A A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0047] Figure 9A A structure schematic diagram of the structure shown along the position of AA'; Figure 8A A structure schematic diagram of the structure shown along the position of BB'; Figure 9B A structure schematic diagram of the structure shown along the position of AA'; Figure 9A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 9C A structure schematic diagram of the structure shown along the position of AA'; Figure 9A A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0048] Figure 10A A structure schematic diagram of the structure shown along the position of AA'; Figure 9A A structure schematic diagram of the structure shown along the position of BB'; Figure 10B A structure schematic diagram of the structure shown along the position of AA'; Figure 10A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 10C A structure schematic diagram of the structure shown along the position of AA'; Figure 10A A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0049] Figure 11A A structure schematic diagram of the structure shown along the position of AA'; Figure 10A A structure schematic diagram of the structure shown along the position of BB'; Figure 11B A structure schematic diagram of the structure shown along the position of AA'; Figure 11A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 11C A structure schematic diagram of the structure shown along the position of AA'; Figure 11A A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0050] Figure 12A A structure schematic diagram of the structure shown along the position of AA'; Figure 11A A structure schematic diagram of the structure shown along the position of BB'; Figure 12B A structure schematic diagram of the structure shown along the position of AA'; Figure 12A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 12C A structure schematic diagram of the structure shown along the position of AA'; Figure 12A A cross-sectional structure schematic diagram of the structure shown along the position of BB';

[0051] Figure 13A A structure schematic diagram of the structure shown along the position of AA'; Figure 12A A structure schematic diagram of the structure shown along the position of BB'; Figure 13B A structure schematic diagram of the structure shown along the position of AA'; Figure 13A A cross-sectional structure schematic diagram of the structure shown along the position of BB'; Figure 13C for Figure 13A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0052] Figure 14A For Figure 13A A schematic diagram of a bit line structure prepared based on the structure shown in FIG. Figure 14B for Figure 14A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 14C for Figure 14A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0053] Figure 15A For Figure 14A A schematic diagram of a structure in which a portion of the first sidewall protection layer and a portion of the second sidewall protection layer are etched based on the structure shown in FIG. Figure 15B for Figure 15A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 15C for Figure 15A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0054] Figure 16A For Figure 15A A schematic diagram of a word line structure prepared based on the structure shown in FIG. Figure 16B for Figure 16A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 16C for Figure 16A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0055] The reference numerals and their meanings are as follows:

[0056] 10. Substrate; 11. First doped layer; 12. Sacrificial layer; 13. Second doped layer; 14. Hard mask layer; 15. Filling layer; 16. Isolation layer; 17. Top protective layer; 101. First trench in the first direction; 102. Second trench in the first direction; 110. First sidewall protective layer; 120. Second sidewall protective layer; 201. First trench in the second direction; 202. Second trench in the second direction; 210. First dielectric layer; 220. Second dielectric layer; 310. Channel layer; 311. First channel sublayer; 312. Second channel sublayer; 320. First source and drain layer; 330. Second source and drain layer; 410. Bit line structure; 420. Word line structure. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are for the purpose of describing specific embodiments only and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0060] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] The disclosed embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. The same reference numerals in different figures identify the same elements.

[0063] Figure 1 A flow chart of steps of a method for manufacturing a semiconductor structure of the present disclosure. Referring to Figure 1 The method for manufacturing includes steps S1-S6, as follows.

[0064] Step S1, sequentially forming a first doped layer 11, a sacrificial layer 12 and a second doped layer 13 on a substrate 10.

[0065] Figure 2A A schematic diagram of a structure of the substrate 10 and the first doped layer 11, the sacrificial layer 12 and the second doped layer 13 disposed on the substrate 10, Figure 2B A schematic diagram of a cross-sectional structure along AA' of the structure shown, Figure 2A A schematic diagram of a cross-sectional structure along BB' of the structure shown. Figure 2C A schematic diagram of a cross-sectional structure along BB' of the structure shown. Figure 2A A schematic diagram of a cross-sectional structure along BB' of the structure shown.

[0066] The structure shown in Figure 2A has a first direction and a second direction intersecting, the first direction being Figure 2A the x direction labeled in Figure 2A , and the second direction being Figure 2A the y direction labeled in Figure 2A . In this embodiment, the x direction and the y direction are perpendicular to each other. In addition, Figures 2A to 2C the structure shown in Figures 2A to 2C also has a third direction, the third direction being perpendicular to the plane determined by the first direction and the second direction, the third direction being Figures 2A to 2C the z direction labeled in Figures 2A to 2C . Referring toAs shown, the first doped layer 11, the sacrificial layer 12 and the second doped layer 13 are sequentially stacked on the substrate 10 in the third direction. In addition, the stacking direction of the first doped layer 11, the sacrificial layer 12 and the second doped layer 13 is the height direction, and the height direction is the third direction.

[0067] In some examples of the embodiment, the material of the substrate 10 can be a semiconductor material. For example, the material of the substrate 10 can be selected from one or more of silicon, gallium arsenide, silicon carbide and germanium. In the embodiment, the material of the substrate 10 can be silicon, which can be intrinsic silicon material or doped silicon material. Further, the material of the substrate 10 can be single crystal silicon, for example, a single crystal silicon wafer can be used as the substrate 10. The material of the substrate 10 can be used to fabricate the bit line structure 410 in the semiconductor structure. Further, the substrate 10 can also have logic circuits therein, or the material of the substrate 10 can also be used to fabricate logic circuits.

[0068] In some examples of the embodiment, the material of the first doped layer 11 can be a doped semiconductor material, and the first doped layer 11 can have a first doping type. Further, the material of the first doped layer 11 can be selected from one or more of silicon, gallium arsenide, silicon carbide and germanium. In the embodiment, the material of the first doped layer 11 can be silicon.

[0069] In some examples of the embodiment, the first doped layer 11 can be fabricated by epitaxial growth.

[0070] In some examples of the embodiment, the thickness of the first doped layer 11 in the height direction thereof can be 10 nm to 100 nm. For example, the thickness of the first doped layer 11 can be 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, or the thickness of the first doped layer 11 can also be within a range between any two of the above thicknesses.

[0071] In some examples of the embodiment, the sacrificial layer 12 can be fabricated by epitaxial growth.

[0072] In some examples of the embodiment, the thickness of the sacrificial layer 12 in the height direction thereof can be 20 nm to 100 nm. For example, the thickness of the sacrificial layer 12 can be 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, or the thickness of the sacrificial layer 12 can also be within a range between any two of the above thicknesses. In the embodiment, the height direction of the sacrificial layer 12 is the third direction. It can be understood that, in the embodiment, the sacrificial layer 12 is used to preoccupy the position of the channel layer 310. Therefore, the thickness of the sacrificial layer 12 determines the length (height) of the subsequently fabricated channel layer 310. By setting the thickness of the sacrificial layer 12 to be 20 nm to 100 nm, it is convenient to fabricate a channel layer 310 with good performance.

[0073] In some examples of the embodiment, the material of the sacrificial layer 12 is different from the material of the first doped layer 11 and the material of the second doped layer 13, so that the sacrificial layer 12 has a different etching rate from the first doped layer 11 and the second doped layer 13. Further, the sacrificial layer 12 can also be used as a substrate for epitaxial growth of the channel layer 310, and thus the material of the sacrificial layer 12 can be selected according to the material of the channel layer 310 actually grown. In the embodiment, the material of the sacrificial layer 12 can include a silicon germanium alloy. The silicon germanium alloy has a relatively high etching rate and can be used as a substrate for epitaxial growth of silicon material. It can be understood that the material of the sacrificial layer 12 can also be other suitable materials.

[0074] In some examples of the embodiment, the second doped layer 13 can be prepared by epitaxial growth.

[0075] In some examples of the embodiment, the material of the second doped layer 13 can be a doped semiconductor material, and the doping type of the second doped layer 13 can be the same as the doping type of the first doped layer 11. Further, the material of the second doped layer 13 can be selected from one or more of silicon, gallium arsenide, silicon carbide, and germanium. In the embodiment, the material of the second doped layer 13 can be silicon.

[0076] In some examples of the embodiment, the thickness of the second doped layer 13 can be 10 nm to 100 nm. For example, the thickness of the second doped layer 13 can be 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, or the thickness of the second doped layer 13 can also be a range between any two of the above thicknesses. Further, the thickness of the second doped layer 13 can be the same as the thickness of the first doped layer 11.

[0077] In some examples of the embodiment, the method further includes the step of etching the second doped layer 13, the sacrificial layer 12, the first doped layer 11, and the substrate 10 in the second direction to form a plurality of second-direction grooves. Further, the second doped layer 13, the sacrificial layer 12, the first doped layer 11, and the substrate 10 can be etched in the second direction multiple times respectively to form a plurality of second-direction grooves arranged at intervals. The etching performed later can be performed between the second-direction grooves formed by the etching performed earlier.

[0078] In some examples of the embodiment, the method further includes the step of etching the second doped layer 13, the sacrificial layer 12, and the first doped layer 11 in the second direction twice respectively to etch out a plurality of second-direction first grooves 201 and a plurality of second-direction second grooves 202 respectively, and the second-direction first grooves 201 and the second-direction second grooves 202 are arranged alternately at intervals. The first-direction grooves include the second-direction first grooves 201 and the second-direction second grooves 202.

[0079] Figure 3A For Figure 2A A schematic diagram of a structure in which a first groove 201 in the second direction is formed on the basis of the structure shown in FIG. Figure 3B for Figure 3A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 3C for Figure 3A Schematic diagram of the cross-section structure along BB' in the structure shown. Figures 3A to 3C As shown, the second-direction first trench 201 extends along the second direction.

[0080] In some instances of this embodiment, before the first etching, a pattern layer can be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the first groove 201 in the second direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the first groove 201 in the second direction.

[0081] In some examples of this embodiment, the material of the pattern layer may be photoresist.

[0082] In some examples of this embodiment, the first etching method may be dry etching.

[0083] In some examples of this embodiment, the first etching process further includes: etching away a portion of the substrate 10 so that the bottom of the second-direction first trench 201 is located in the substrate 10. It is understood that there may be multiple second-direction first trenches 201, and the multiple second-direction first trenches 201 may be arranged side by side with intervals. Furthermore, the multiple second-direction first trenches 201 may be arranged sequentially with intervals in the first direction.

[0084] In some examples of this embodiment, the step of preparing a first dielectric layer 210 in the first trench 201 in the second direction is further included. Figure 4A For Figure 3A A schematic diagram of the structure of preparing the first dielectric layer 210 based on the structure shown in FIG. Figure 4B for Figure 4A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 4C for Figure 4A Schematic diagram of the cross-section structure along BB' in the structure shown. Figures 4A to 4C As shown, the first dielectric layer 210 is filled in the first trench 201 in the second direction.

[0085] In some examples of this embodiment, the material of the first dielectric layer 210 can be selected from insulating materials. For example, the material of the first dielectric layer 210 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first dielectric layer 210 can be silicon oxide. The first dielectric layer 210 can shield the groove wall of the first trench 201 in the second direction. In addition, the provision of the first dielectric layer 210 can also support the subsequently prepared pattern layer.

[0086] Figure 5A For Figure 4A A schematic diagram of a structure for preparing a second groove 202 in the second direction based on the structure shown in FIG. Figure 5B for Figure 5A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 5C for Figure 5A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0087] In some instances of this embodiment, before performing the second etching, a pattern layer can be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the second groove 202 in the second direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the second groove 202 in the second direction.

[0088] In some examples of this embodiment, the material of the pattern layer may be photoresist.

[0089] In some examples of this embodiment, the second etching method may be dry etching.

[0090] In some examples of this embodiment, the second etching process further includes: etching away a portion of the substrate 10 so that the bottom of the second trench 202 in the second direction is located in the substrate 10. Figures 5A to 5C As shown, there are multiple second-direction second grooves 202, and the multiple second-direction second grooves 202 can be arranged side by side and spaced apart. Further, the multiple second-direction second grooves 202 can be arranged in sequence and spaced apart in the first direction. The second-direction second grooves 202 and the second-direction first grooves 201 are arranged alternately and spaced apart.

[0091] In some examples of this embodiment, the interval between adjacent second-direction first trenches 201 and second-direction second trenches 202 remains constant.

[0092] Compared with the way of etching the grooves along the second direction once, the way of etching twice respectively makes the grooves formed by each etching have a larger interval, so the required pattern size is larger, which can alleviate the problem caused by diffraction effect, is beneficial to reduce the requirement of equipment resolution in the preparation process, and is also helpful to prepare devices with smaller feature size, and further improve the device density.

[0093] In some examples of this embodiment, a step of preparing a second dielectric layer 220 in the second direction second groove 202 is further included. Figure 6A To prepare the structure shown in Figure 5A The structure schematic diagram of preparing the second dielectric layer 220 based on the structure shown in Figure 6B To prepare the structure shown in Figure 6A The cross-sectional structure schematic diagram along AA' in the structure shown in Figure 6C To prepare the structure shown in Figure 6A The cross-sectional structure schematic diagram along BB' in the structure shown in Figures 6A to 6C As shown in the structure shown in the structure shown in

[0094] In some examples of this embodiment, the material of the second dielectric layer 220 can be selected from insulating materials, for example, the material of the second dielectric layer 220 can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the second dielectric layer 220 can be silicon oxide. The second dielectric layer 220 can shield the groove wall of the second direction second groove 202, and in addition, by setting the second dielectric layer 220, the subsequently prepared pattern layer can also be supported.

[0095] Step S2, etching the second doped layer 13, the sacrificial layer 12 and the first doped layer 11 along the first direction to form a plurality of first direction first grooves 101.

[0096] In some examples of this embodiment, before forming the plurality of first direction first grooves 101, a step of preparing a hard mask layer 14 on the second doped layer 13 is further included. Figure 6A To prepare the structure shown in Figure 6A The structure schematic diagram of preparing the hard mask layer 14 based on the structure shown in Figure 6B To prepare the structure shown in Figure 6A The cross-sectional structure schematic diagram along AA' in the structure shown in Figure 6C To prepare the structure shown in Figure 6A The cross-sectional structure schematic diagram along BB' in the structure shown in

[0097] Referring to Figures 6A to 6CAs shown, the hard mask layer 14 is laminated on the second doped layer 13. In some examples of this embodiment, the hard mask layer 14 covers the second doped layer 13. The hard mask layer 14 is used to form a specific pattern and to maintain a stable shape during etching. In addition, the hard mask layer 14 can also protect the second doped layer 13, the sacrificial layer 12 and the first doped layer 11 from unnecessary etching in subsequent etching processes.

[0098] In some examples of this embodiment, the material of the hard mask layer 14 can be an inorganic material, such as silicon nitride or polysilicon. In this embodiment, the material of the hard mask layer 14 is polysilicon.

[0099] Figure 7A To form the first direction first trench 101 based on the structure shown in FIG. 1A, Figure 6A FIG. 1C shows a schematic view of a cross-sectional structure along AA' of the structure shown in FIG. 1A, Figure 7B To form the first direction first trench 101 based on the structure shown in FIG. 1A, Figure 7A FIG. 1C shows a schematic view of a cross-sectional structure along AA' of the structure shown in FIG. 1A, Figure 7C To form the first direction first trench 101 based on the structure shown in FIG. 1A, Figure 7A To form the first direction first trench 101 based on the structure shown in FIG. 1A, Figures 7A to 7C As shown, the first direction first trench 101 extends in the first direction.

[0100] In some examples of this embodiment, before forming the first trench, a pattern layer can be prepared on the second doped layer 13, the opening of the pattern layer defining the position of the first direction first trench 101, and the second doped layer 13, the sacrificial layer 12 and the first doped layer 11 are etched based on the opening of the pattern layer to form the first direction first trench 101. It can be understood that in this step, the step of etching the hard mask layer 14 is also included.

[0101] In some examples of this embodiment, in the step of forming the first direction first trench 101, the etching method can be dry etching.

[0102] In some examples of this embodiment, in the step of forming the first direction first trench 101, the etching is controlled to stop when etching to the substrate 10, so that the bottom of the first direction first trench 101 is flush with the bottom of the first doped layer 11.

[0103] In some examples of this embodiment, the first medium layer 210 and the second medium layer 220 prepared in advance are also etched.

[0104] It can be understood that, Figures 7A to 7COnly a partial region of the semiconductor structure is shown in the figure, and therefore only one first-direction first trench 101 is shown in the figure, but a plurality of first-direction first trenches 101 can be provided in the semiconductor structure as a whole. The plurality of first-direction first trenches 101 can be arranged side by side at intervals. Further, the plurality of first-direction first trenches 101 can be arranged in sequence at intervals in the second direction.

[0105] In step S3, the exposed part of the sacrificial layer 12 in the first trench is etched and removed, and a first-channel sub-layer 311 is prepared between the first doped layer 11 and the second doped layer 13.

[0106] Figure 8A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 7A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 8B In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 8A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 8C In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 8A In order to etch and remove part of the sacrificial layer 12 from the structure shown in

[0107] Referring to FIG. 1, the first-channel sub-layer 311 is prepared between the first doped layer 11 and the second doped layer 13, and the first-channel sub-layer 311 contacts the first doped layer 11 and the second doped layer 13. It can be understood that the first-channel sub-layer 311 can serve as a channel between the first doped layer 11 and the second doped layer 13. Figures 8A to 8C

[0108] In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 9A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 8A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 9B In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 9A In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 9C In order to etch and remove part of the sacrificial layer 12 from the structure shown in Figure 9A In order to etch and remove part of the sacrificial layer 12 from the structure shown in

[0109] Referring to FIG. 1, the first-channel sub-layer 311 is prepared between the first doped layer 11 and the second doped layer 13, and the first-channel sub-layer 311 contacts the first doped layer 11 and the second doped layer 13. It can be understood that the first-channel sub-layer 311 can serve as a channel between the first doped layer 11 and the second doped layer 13. Figures 9A to 9C ​

[0110] In some examples of this embodiment, the step of preparing the first channel sublayer 311 may include: preparing the first channel sublayer 311 by epitaxial growth on the sacrificial layer 12. Furthermore, the first channel sublayer 311 may be prepared by chemical vapor deposition. In this embodiment, the first channel sublayer 311 may be prepared on the sacrificial layer 12 by low-pressure chemical vapor deposition.

[0111] In some examples of this embodiment, the material of the first channel sublayer 311 may include a semiconductor material. In this embodiment, the material of the first channel sublayer 311 includes silicon. The first channel sublayer 311 may have a different doping type from the first doping layer 11 .

[0112] It can be understood that there is a direct relationship between the height of the first channel sublayer 311 (i.e., the channel length) and the thickness of the sacrificial layer 12. Therefore, by setting an appropriate thickness when preparing the sacrificial layer 12, a first channel sublayer 311 of corresponding height can be obtained. The height of the first channel sublayer 311 refers to the distance between the top and bottom of the first channel sublayer 311 in the third direction.

[0113] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 is 5 nm to 20 nm. Figure 1 and Figure 9A As shown, the direction of the first channel sublayer 311 away from the sacrificial layer 12 is along the second direction. It will be understood that the sacrificial layer 12 is removed in the subsequent preparation process, and the second channel sublayer 312 is prepared in the area where the sacrificial layer 12 is located. Therefore, the direction of the first channel sublayer 311 away from the sacrificial layer 12 is also away from the second channel sublayer 312. The thickness of the first channel sublayer 311 refers to the distance between the surface of the first channel sublayer 311 on the side close to the sacrificial layer 12 and the surface on the side away from the sacrificial layer 12.

[0114] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may be 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, or 20 nm. Furthermore, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may also be in a range between any two of the above thicknesses.

[0115] Although the first channel sub-layer 311 can be used as a channel, the first channel sub-layer 311 grown on the sacrificial layer 12 has a limited thickness in the direction away from the sacrificial layer 12, which makes it vulnerable to damage in subsequent processes. In addition, there is a large difference in the topography between the surface of the prepared first channel sub-layer 311 close to the first direction first trench 101 and the surface away from the first direction first trench 101. Both of these factors can lead to a decrease in the performance of the channel layer 310, which in turn affects the yield of the device. The preparation method of the present disclosure improves the above problems by etching the first direction second trench 102 and preparing the second channel sub-layer 312.

[0116] In some examples of this embodiment, after the first channel sub-layer 311 is prepared, a step of preparing a first sidewall protection layer 110 in the first direction first trench 101 can also be included. Figure 10A To prepare the first sidewall protection layer 110 on the basis of the structure shown in Figure 9A The structure diagram of the cross-sectional structure along AA' in the structure shown in Figure 10B To prepare the first sidewall protection layer 110 on the basis of the structure shown in Figure 10A The structure diagram of the cross-sectional structure along AA' in the structure shown in Figure 10C To prepare the first sidewall protection layer 110 on the basis of the structure shown in Figure 10A The structure diagram of the cross-sectional structure along BB' in the structure shown in

[0117] Referring to Figures 10A to 10C As shown, the first sidewall protection layer 110 covers the trench wall of the first direction first trench 101. Further, the first sidewall protection layer 110 also covers the first channel sub-layer 311, which can play a role in protecting the first channel sub-layer 311.

[0118] In some examples of this embodiment, the material of the first sidewall protection layer 110 can be selected from insulating materials, for example, the material of the first sidewall protection layer 110 can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first sidewall protection layer 110 can be silicon oxide.

[0119] In some examples of this embodiment, the first sidewall protection layer 110 can be prepared by atomic layer deposition. In this process, the material of the first sidewall protection layer 110 will also adhere to the bottom of the first direction first trench 101 and above the second doped layer 13, but this can be removed by vertical etching.

[0120] In some examples of this embodiment, after the first sidewall protection layer 110 is prepared, a step of preparing a filling layer 15 in the first direction first trench 101 is also included. The filling layer 15 is used to fill the first direction first trench 101, so as to facilitate the subsequent preparation of a pattern layer on the second doped layer 13.

[0121] In some examples of this embodiment, the material of the filling layer 15 may be selected from insulating materials, for example, the material of the filling layer 15 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the filling layer 15 may be silicon nitride.

[0122] In step S4 , the second doped layer 13 , the sacrificial layer 12 and the first doped layer 11 are etched along the first direction to form a plurality of second trenches 102 in the first direction.

[0123] Figure 11A For Figure 10A A schematic diagram of a structure in which a second groove 102 in the first direction is formed on the basis of the structure shown in FIG. Figure 11B for Figure 11A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 11C for Figure 11A Schematic diagram of the cross-section structure along BB' in the structure shown. Figures 11A to 11C As shown, there may be multiple first-direction second grooves 102. The first-direction second grooves 102 and the first-direction first grooves 101 may be alternately arranged.

[0124] In some examples of this embodiment, the distance between adjacent first-direction first trenches 101 and first-direction second trenches 102 remains constant.

[0125] In some instances of this embodiment, before forming the second groove 102 in the first direction, a pattern layer can be prepared on the second doping layer 13, and the opening of the pattern layer defines the position of the second groove 102 in the first direction. Based on the opening of the pattern layer, the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched to form the second groove 102 in the first direction.

[0126] In some examples of this embodiment, in the step of forming the first-direction second trench 102 , the etching is controlled to stop when the etching reaches the substrate 10 , so that the bottom of the first-direction second trench 102 is flush with the bottom of the first doping layer 11 .

[0127] Reference Figures 11A to 11C As shown, part of the sacrificial layer 12 is still retained in step S3 , and the sacrificial layer 12 is etched through when forming the second trench 102 in the first direction, so the sacrificial layer 12 is also exposed in the second trench 102 in the first direction.

[0128] Step S5 , etching and removing the sacrificial layer 12 , and forming a second channel sublayer 312 between the first doping layer 11 and the second doping layer 13 .

[0129] Figure 12A For Figure 11A A schematic diagram of a structure for preparing a second channel sublayer 312 based on the structure shown in FIG. Figure 12B for Figure 12A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 12C for Figure 12A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0130] Reference Figures 12A to 12C As shown, the sacrificial layer 12 located between the first doped layer 11 and the second doped layer 13 is completely removed. After the sacrificial layer 12 is removed, there is a vacancy between the first doped layer 11 and the second doped layer 13 that was originally occupied by the sacrificial layer 12. At this time, the second channel sublayer 312 can be prepared in this vacancy. The second channel sublayer 312 contacts the first channel sublayer 311. Thus, the second channel sublayer 312 and the first channel sublayer 311 together constitute the channel layer 310 in the semiconductor structure. Unless otherwise specified, the "channel layer 310" in this embodiment includes the first channel sublayer 311 and the second channel sublayer 312.

[0131] In some examples of this embodiment, the step of preparing the second channel sublayer 312 includes: preparing the second channel sublayer 312 by epitaxial growth on the first channel sublayer 311. Furthermore, the second channel sublayer 312 can be prepared by chemical vapor deposition. In this embodiment, the second channel sublayer 312 can be prepared on the first channel sublayer 311 by low-pressure chemical vapor deposition. It can be understood that by epitaxially preparing the second channel sublayer 312 on the first channel sublayer 311, the second channel sublayer 312 has the same height as the first channel sublayer 311, and the second channel sublayer 312 can also directly contact the first doped layer 11 and the second doped layer 13.

[0132] In some examples of this embodiment, the material of the second channel sublayer 312 may include a semiconductor material. In this embodiment, the material of the second channel sublayer 312 includes silicon.

[0133] In some examples of this embodiment, the thickness of the second channel sublayer 312 in the direction away from the first channel sublayer 311 is 5 nm to 20 nm. Figure 1 and Figure 12A As shown, the second channel sublayer 312 is away from the first channel sublayer 311 along the second direction. The thickness of the second channel sublayer 312 refers to the distance between the side surface of the second channel sublayer 312 close to the first channel sublayer 311 and the side surface away from the first channel sublayer 311.

[0134] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may be 5 nm, 7 nm, 10 nm, 12 nm, 15 nm, or 20 nm. Furthermore, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may also be in a range between any two of the above thicknesses.

[0135] It can be understood that, by steps S4-S5, the second channel sub-layer 312 can be further prepared on the basis of the first channel sub-layer 311. Compared with the single first channel sub-layer 311, the further setting of the second channel sub-layer 312 can significantly increase the thickness of the channel layer 310 as a whole, which can make the channel layer 310 as a whole more difficult to have the problem of over-etching. And the first channel sub-layer 311 and the second channel sub-layer 312 prepared in two times make the channel layer 310 as a whole more symmetrical. Therefore, the preparation method of the present disclosure can effectively improve the performance of the channel layer 310.

[0136] In addition, the trench is etched twice in the first direction, which makes the trenches formed by each etching have a larger interval, so it can also reduce the requirement for equipment resolution in the preparation process. In summary of the above factors, the preparation method of the present disclosure can solve the problems of pattern layer precision and channel layer 310 quality at the same time, and therefore can effectively improve the preparation yield of high-density small-size devices.

[0137] In some examples of this embodiment, after the second channel sub-layer 312 is prepared, a step of preparing a second sidewall protection layer 120 in the first direction second trench 102 is further included. Figure 13A For the purpose of Figure 12A a structural schematic diagram of the structure shown in Figure 13B for the purpose of Figure 13A a cross-sectional structural schematic diagram along AA' in the structure shown in Figure 13C for the purpose of Figure 13A a cross-sectional structural schematic diagram along BB' in the structure shown in.

[0138] Referring to Figures 13A to 13C It can be understood that, by steps S4-S5, the second channel sub-layer 312 can be further prepared on the basis of the first channel sub-layer 311. Compared with the single first channel sub-layer 311, the further setting of the second channel sub-layer 312 can significantly increase the thickness of the channel layer 310 as a whole, which can make the channel layer 310 as a whole more difficult to have the problem of over-etching. And the first channel sub-layer 311 and the second channel sub-layer 312 prepared in two times make the channel layer 310 as a whole more symmetrical. Therefore, the preparation method of the present disclosure can effectively improve the performance of the channel layer 310.

[0139] In some examples of this embodiment, the material of the second sidewall protection layer 120 can be selected from insulating materials, for example, the material of the second sidewall protection layer 120 can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the second sidewall protection layer 120 can be silicon oxide.

[0140] In some examples of this embodiment, the second sidewall protection layer 120 can be prepared by atomic layer deposition.

[0141] Referring to Figures 13A to 13CAs shown, after the preparation of the second sidewall protection layer 120, a step of removing the filling layer 15 in the first direction first trench 101 can also be included. It can be understood that when the filling layer 15 is removed, the impact on the first sidewall protection layer 110 and the second sidewall protection layer 120 should be reduced as much as possible, and therefore the material of the filling layer 15 can be different from the material of the first sidewall protection layer 110 and the second sidewall protection layer 120.

[0142] Referring to Figures 13A to 13C As shown, through steps S1-S5, the sacrificial layer 12 between the first doped layer 11 and the second doped layer 13 is removed, and the preparation of the first channel sublayer 311 and the second channel sublayer 312 in the region where the sacrificial layer 12 is located is completed, and the first channel sublayer 311 and the second channel sublayer 312 as a whole serve as the channel layer 310. The plurality of trenches along the first direction and the plurality of trenches along the second direction divide the first doped layer 11 into a plurality of first source-drain layers 320, and divide the second doped layer 13 into a plurality of second source-drain layers 330. The first source-drain layer 320, the second source-drain layer 330 and the channel layer 310 therebetween serve as an active pillar, which can serve as the main functional area of the transistor.

[0143] In some examples of this embodiment, the preparation method of the semiconductor structure can further include the following steps: preparing a word line structure 420 and a bit line structure 410. The extension direction of the bit line structure 410 and the word line structure 420 can be set according to actual needs. In this embodiment, in order to facilitate preparation on the existing structure, the word line structure 420 can extend along the first direction, and the bit line structure 410 can extend along the second direction.

[0144] Figure 14A To prepare the bit line structure 410 based on the structure shown in Figure 13A A structure diagram for preparing the bit line structure 410 based on the structure shown in Figure 14B To prepare the bit line structure 410 based on the structure shown in Figure 14A A cross-sectional structure diagram along AA' in the structure shown in Figure 14C To prepare the bit line structure 410 based on the structure shown in Figure 14A A cross-sectional structure diagram along BB' in the structure shown in

[0145] In some examples of this embodiment, the step of preparing the bit line structure 410 can include: preparing the bit line structure 410 in the substrate 10 under the first doped layer 11.

[0146] In some examples of this embodiment, in the step of preparing the bit line structure 410, the bit line structure 410 is prepared between adjacent second direction dielectric layers.

[0147] Furthermore, the bitline structure 410 can be fabricated based on the material of the substrate 10. For example, a portion of the substrate 10 located between the second-direction dielectric layers can be metallized to convert the substrate 10 material into a conductive metal compound, thereby serving as the bitline structure 410. In this embodiment, the material of the bitline structure 410 can include one or more of cobalt silicide and nickel silicide. It will be appreciated that the substrate 10 material contains silicon, and that metallization of the substrate 10 can form a conductive metal silicide.

[0148] In another embodiment, when etching the first trench 101 in the first direction and etching the second trench 102 in the first direction, part of the substrate 10 can also be etched away, and when preparing the bit line structure 410, a metal conductive material can be prepared between the substrates 10, and the metal conductive material can be diffused into the substrate 10 to form a conductive bit line structure 410.

[0149] Reference Figures 14A to 14C As shown, the bit line structures 410 are separated by the first dielectric layer 210 and the second dielectric layer 220 , so that each bit line structure 410 is independently conductive.

[0150] It is understood that the first channel sublayer 311 and the second channel sublayer 312 are combined to form the channel layer 310. In some examples of this embodiment, preparing the word line structure 420 further includes the following steps: preparing a gate dielectric layer surrounding the channel layer 310, and preparing a word line conductive layer on a side of the gate dielectric layer away from the channel layer 310. It is understood that the word line structure 420 includes the gate dielectric layer and the word line conductive layer.

[0151] Furthermore, before preparing the gate dielectric layer, the following step is further included: removing portions of the first sidewall protection layer 110 and the second sidewall protection layer 120 located on both sides of the first channel sublayer 311 and the second channel sublayer 312 to expose the channel layer 310 . Figure 15A For Figure 14A A schematic diagram of etching a portion of the first sidewall protection layer 110 and a portion of the second sidewall protection layer 120 based on the structure shown in FIG. Figure 15B for Figure 15A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 15C for Figure 15A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0152] Reference Figures 15A to 15CAs shown, the first sidewall protection layer 110 and the second sidewall protection layer 120 located on both sides of the channel layer 310 (including the first channel sub-layer 311 and the second channel sub-layer 312) are removed to expose the first channel sub-layer 311 and the second channel sub-layer 312. In this embodiment, the etching progress can be controlled to reserve part of the first sidewall protection layer 110 and part of the second sidewall protection layer 120 between the first doped layers 11 to avoid the material of the word line conductive layer being deposited between the first doped layers 11.

[0153] Further, in some examples of this embodiment, the first dielectric layer 210 and the second dielectric layer 220 located between adjacent channel layers 310 are also removed. Similarly, the etching progress can be controlled to reserve part of the first dielectric layer 210 and part of the second dielectric layer 220 between the first doped layers 11

[0154] Referring to Figures 15A to 15C As shown, in some examples of this embodiment, before etching the first sidewall protection layer 110 and the second sidewall protection layer 120, a step of preparing an isolation layer 16 in the first direction first trench 101 and the first direction second trench 102 is further included. The isolation layer 16 extends along the second direction to separate the structures on both sides of the first direction trench to avoid crosstalk between the subsequently prepared word line structures 420.

[0155] Figure 16A To prepare the word line structure 420 based on the structure shown in Figure 15A A structural schematic diagram of the structure for preparing the word line structure 420 based on the structure shown in Figure 16B A structural schematic diagram of the structure for preparing the word line structure 420 based on the structure shown in Figure 16A A cross-sectional structural schematic diagram along AA' of the structure shown in Figure 16C A cross-sectional structural schematic diagram along BB' of the structure shown in Figure 16A A cross-sectional structural schematic diagram along BB' of the structure shown in

[0156] Referring to Figures 16A to 16C As shown, the word line structure 420 extends along the first direction.

[0157] In some examples of this embodiment, the material of the word line conductive layer in the word line structure 420 can be selected from a metal material. For example, the material of the word line conductive layer can include one or more of copper, tungsten, silver, and gold.

[0158] In some examples of this embodiment, the way of preparing the word line conductive layer can be an atomic layer deposition method or a chemical vapor deposition method.

[0159] In some examples of this embodiment, before preparing the word line conductive layer, a step of preparing a gate dielectric layer on the sidewall of the channel layer 310 is further included. The gate dielectric layer can be arranged around the channel layer 310, and the gate dielectric layer is used to insulate and separate the word line conductive layer and the channel layer 310.

[0160] In some examples of the embodiment, the material of the gate dielectric layer can be selected from high dielectric constant (high K) materials. For example, the material of the gate dielectric layer can include hafnium oxide.

[0161] In some examples of the embodiment, the gate dielectric layer can be prepared by an atomic layer deposition method or a chemical vapor deposition method.

[0162] In some examples of the embodiment, after the word line structure 420 is prepared, a step of preparing a top protection layer 17 in the first direction first trench 101, the first direction second trench 102, the second direction first trench 201, and the second direction second trench 202 is further included. The top protection layer 17 insulates and separates adjacent second doped layers 13. In addition, the top protection layer 17 can also protect the word line structure 420.

[0163] It can be understood that through the above steps S1-S5 and the specific preparation methods therein, a semiconductor structure can be prepared. The semiconductor structure contains a plurality of vertical channel transistors arranged in an array.

[0164] Referring to Figures 16A to 16C In the embodiment, the semiconductor structure includes a substrate 10 and a plurality of active pillars arranged on the substrate 10. The active pillars include a first source-drain layer 320, a channel layer 310, and a second source-drain layer 330 arranged in sequence on the substrate 10. The channel layer 310 is arranged between the first source-drain layer 320 and the second source-drain layer 330. The semiconductor structure also has a plurality of first direction first trenches 101 and a plurality of first direction second trenches 102. The first direction first trenches 101 and the first direction second trenches 102 both extend along a first direction, and the first direction first trenches 101 and the first direction second trenches 102 are alternately and spacedly arranged. Each active pillar is located between adjacent first direction first trenches 101 and first direction second trenches 102. The channel layer 310 includes a first channel sub-layer 311 and a second channel sub-layer 312 in contact. The first channel sub-layer 311 is closer to the first direction first trench 101, and the second channel sub-layer 312 is closer to the first direction second trench 102.

[0165] It can be understood that the second channel sub-layer 312 and the first channel sub-layer 311 are prepared in sequence. In some examples of the embodiment, the second channel sub-layer 312 is prepared on the first channel sub-layer 311. Further, the second channel sub-layer 312 is epitaxially grown on the first channel sub-layer 311.

[0166] In some examples of the embodiment, the semiconductor structure can further include a gate dielectric layer disposed around the channel layer 310, and a word line structure 420 extending along the first direction, and the word line structure 420 is disposed at a side of the gate dielectric layer away from the channel layer 310. The gate dielectric layer is configured to insulate and separate the word line structure 420 and the channel layer 310.

[0167] In some examples of the embodiment, the semiconductor structure can further include a bit line structure 410. The bit line structure 410 can extend along a second direction intersecting the first direction, and the bit line structure 410 can be disposed under the first source-drain layer 320 and electrically connected to the first source-drain layer 320.

[0168] Further, the present disclosure also provides a memory. The memory can be a dynamic random access memory or a magnetic random access memory. It can be understood that when the memory is a dynamic random access memory, the transistor in the semiconductor structure can be electrically connected to the capacitor.

[0169] Further, the present disclosure also provides an electronic device including the memory described above. The electronic device can be a mobile phone or a computer.

[0170] It should be noted that the above-mentioned embodiments are only for illustrative purposes and do not mean to limit the present disclosure.

[0171] It should be understood that, unless otherwise explicitly stated herein, the execution of the steps described is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, at least a part of the steps described can include multiple sub-steps or multiple stages, which do not necessarily be executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0172] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0173] Each of the technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: sequentially preparing a first doping layer, a sacrificial layer, and a second doping layer on a substrate; Etching the second doped layer, the sacrificial layer and the first doped layer along a first direction to form a plurality of first trenches in a first direction; Etching and removing the portion of the sacrificial layer exposed in the first trench in the first direction, and preparing a first channel sublayer between the first doped layer and the second doped layer; Etching the second doped layer, the sacrificial layer and the first doped layer along the first direction to form a plurality of second trenches in the first direction, wherein the second trenches in the first direction are alternately arranged with the first trenches in the first direction; The sacrificial layer is removed by etching, and a second channel sublayer is formed between the first doping layer and the second doping layer, wherein the second channel sublayer contacts the first channel sublayer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The step of preparing the second channel sublayer includes: preparing the second channel sublayer on the first channel sublayer by epitaxial growth; and / or, The step of preparing the first channel sublayer includes: preparing the first channel sublayer on the sacrificial layer by epitaxial growth.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the first channel sublayer in a direction away from the second channel sublayer is 5 nm to 20 nm; and / or, The second channel sublayer has a thickness of 5 nm to 20 nm in a direction away from the first channel sublayer.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the sacrificial layer in its height direction is 20 nm to 100 nm.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The method for preparing the semiconductor structure further includes the following step: preparing a bit line structure in the substrate below the first doping layer.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The bit line structure extends along a second direction intersecting the first direction; Before preparing the bit line structure, the following steps are further included: etching the second doped layer, the sacrificial layer, the first doped layer and the substrate along the second direction to form a plurality of second-direction trenches, wherein the bottoms of the second-direction trenches are located in the substrate, and preparing a second-direction dielectric layer in the second-direction trenches; In the step of preparing the bit line structure, the bit line structure is prepared between adjacent second-direction dielectric layers.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The steps of forming a plurality of second-direction grooves include: The second doped layer, the sacrificial layer, the first doped layer and the substrate are etched multiple times along the second direction to form a plurality of second-direction trenches spaced apart from each other.

8. The method for preparing a semiconductor structure according to claim 6, wherein: The step of preparing a second-direction dielectric layer in the second-direction trench is performed before the step of forming a plurality of first-direction first trenches; The step of preparing the bit line structure is performed after forming a plurality of first trenches in the first direction and forming a plurality of second trenches in the first direction.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 4 and 6 to 8, wherein: The first channel sublayer and the second channel sublayer are combined as a channel layer, and the method for preparing the semiconductor structure further includes the following steps: preparing a gate dielectric layer surrounding the channel layer, and preparing a word line conductive layer on a side of the gate dielectric layer away from the channel layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein: After preparing the first channel sublayer, the following steps are further included: forming a first sidewall protection layer on a surface of the first channel sublayer close to the first trench in the first direction; After preparing the second channel sublayer, the following steps are further included: forming a second sidewall protection layer on a surface of the second channel sublayer close to the second trench in the first direction; Before preparing the gate dielectric layer and the word line conductive layer surrounding the channel layer, the method further includes the following steps: removing a portion of the first sidewall protection layer and a portion of the second sidewall protection layer to expose the channel layer.

11. The method for preparing a semiconductor structure according to claim 10, wherein: After preparing the second channel sublayer, the following steps are further included: preparing an isolation layer in the first trench in the first direction and the second trench in the first direction; The gate dielectric layer and the word line conductive layer are prepared between the isolation layer and the channel layer.

12. The method for preparing a semiconductor structure according to any one of claims 1 to 4, 6 to 8 and 10 to 11, characterized in that: The material of the sacrificial layer includes a silicon-germanium alloy, and the material of the first channel sublayer and the material of the second channel sublayer both include silicon.

13. A semiconductor structure, characterized in that include: A substrate and a plurality of active pillars disposed on the substrate, the active pillars comprising a first source-drain layer, a channel layer, and a second source-drain layer stacked in sequence on the substrate, the channel layer being disposed between the first source-drain layer and the second source-drain layer; The semiconductor structure further comprises a plurality of first trenches in the first direction and a plurality of second trenches in the first direction, wherein the first trenches in the first direction and the second trenches in the first direction both extend along the first direction, and the first trenches in the first direction and the second trenches in the first direction are alternately arranged, and each of the active pillars is located between adjacent first trenches in the first direction and adjacent second trenches in the first direction; The channel layer includes a first channel sublayer and a second channel sublayer in contact with each other. The first channel sublayer is located on a side of the second channel sublayer close to the first trench in the first direction. The second channel sublayer is located on a side of the first channel sublayer close to the second trench in the first direction.

14. A memory, characterized in that: The semiconductor structure comprises a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 12, or the semiconductor structure according to claim 13.

15. An electronic device, characterized in that: Comprising the memory as claimed in claim 14.

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