Data recovery for partitioned namespace devices

Abstract

A Zone Write Group (ZWG) is used to assist a data storage device and a host device in data recovery. In one embodiment, a data storage device includes a memory that stores a partitioned namespace (ZNS). The ZNS includes a ZWG, the ZWG including a host region and a parity region. An interface connects the data storage device with a host device. The data storage device includes a data storage device controller including an electronic processor and a memory. The data storage device controller populates the ZWG with a buffer received from the host device. The data storage device controller detects corrupted data associated with the ZNS and requests one or more buffers stored in the ZWG. Once the data storage device controller receives the one or more buffers from the ZWG, the data storage device controller performs a recovery event using the one or more buffers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, for all purposes, U.S. non-provisional application Ser. No. 17 / 903,528, filed on Sept. 6, 2022, entitled “Data Recovery for Zoned Namespace Devices.” Technical Field

[0003] The present application generally relates to data storage devices, and more particularly to data storage devices implementing a partitioned namespace architecture and methods of recovering corrupted data using buffered data. Summary of the invention

[0004] To improve performance, the data storage device may implement a zoned namespace (ZNS) architecture, in which if the write input / output (I / O) from the host application is always sequential, then the garbage collection (GC) process will not be performed within the solid-state drive (SSD) of the data storage device. In other words, the ZNS SSD expects the host application to always perform sequential writes, thereby providing stable predictable performance.

[0005] In some implementations, the ZNS zone capacity matches the erase unit size, which makes it problematic to implement a full zone fail-safe feature on the SSD controller. Additionally, this feature may result in significantly less over-provisioned space. Alternatively, the ZNS zone capacity may be increased to match multiple erase unit sizes. However, from a host perspective, larger ZNS zone capacities limit system parallelism and come with their own overhead and limitations.

[0006] To assist in data recovery, embodiments described herein provide zone write groups (ZWGs) that group together host zones of similar data life expectancy ratings (e.g., amount of time to overwrite). Host zones are paired with one or more parity zones to assist with parity accumulation and other storage algorithms. In some cases, ZWGs also assist with GC processes. However, in other cases, a GC process performed by the data storage device is not necessary because the connected host device may instead invalidate the host zone in a timely manner.

[0007] In one embodiment, the present disclosure provides a data storage controller, the data storage controller includes a memory and a data storage device controller. The memory includes multiple regions in a ZNS, the ZNS includes a ZWG, the ZWG includes multiple host regions and multiple parity regions. The data storage device controller includes an electronic processor and a data storage controller memory storing an instruction set, when executed by the electronic processor, the instruction set instructs the controller to detect corrupted data associated with the ZNS and request one or more buffers stored in the ZWG. The controller receives the one or more buffers from the ZWG and performs a recovery process using the one or more buffers.

[0008] The present disclosure also provides a method. The method includes: using a data storage device controller to construct a ZWG including one or more host areas and one or more parity areas. The method includes: using the data storage device controller to write a host data buffer to a host area in the one or more host areas and write a parity buffer to a parity area in the one or more parity areas. The method includes: using the data storage device controller to detect damaged data associated with a ZNS; and using the data storage device controller to request one or more buffers stored in the ZWG. The method includes: using the data storage device controller to receive the one or more buffers from the ZWG; and using the data storage device controller to perform a recovery event using the one or more buffers.

[0009] The present invention also provides a data storage device, which includes: a memory; an interface configured to connect to a host device; and a data storage device controller. The memory includes multiple areas in a ZNS, the ZNS includes a ZWG, and the ZWG includes multiple host areas and multiple parity check areas. The data storage device controller includes an electronic processor and a data storage controller memory storing an instruction set, and when executed by the electronic processor, the instruction set instructs the controller to: receive multiple buffers from the host device; fill a host area in the multiple host areas with a buffer in the multiple buffers; detect damaged data associated with the ZNS; request the buffer stored in the host area; receive the buffer from the host area; and perform a recovery event using the buffer received from the host area.

[0010] Various aspects of the present disclosure provide improvements to data storage devices. The present disclosure may be embodied in various forms, including hardware or circuits controlled by software, firmware, or a combination thereof. The above summary is intended only to give a general idea of ​​various aspects of the present disclosure and is not intended to limit the scope of the present disclosure in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a system including a data storage device and a host device according to some embodiments of the present disclosure.

[0012] Figure 2 is a block diagram of a ZWG according to various aspects of the present disclosure.

[0013] Figure 3 It is an example of the construction according to various aspects of the present disclosure Figure 2 Flowchart of an example method of ZWG.

[0014] Figure 4 is a flow chart illustrating an example method of recovering from a data loss event according to various aspects of the present disclosure.

[0015] Figure 5 is a flow chart illustrating another example method of recovering from a data loss event according to various aspects of the present disclosure.

[0016] Figure 6 is a flow chart illustrating an example method of retrieving a buffer for data recovery according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0017] In the following description, many details are set forth, such as data storage device configuration, controller operation, etc., in order to provide an understanding of one or more aspects of the present disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of the present application. Specifically, the functions associated with the data storage controller may be performed by hardware (e.g., analog or digital circuits), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer-readable medium executed by a processor or control circuit system), or any other suitable component. The following description is intended only to give a general idea of ​​the various aspects of the present disclosure, without limiting the scope of the present disclosure in any way. In addition, it will be apparent to those skilled in the art that, although the present disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid-state memories, such as NOR, PCM ("phase change memory"), ReRAM, MRAM, and the like.

[0018] Figure 1 is a block diagram of a system including a data storage device and a host device according to some embodiments of the present disclosure. Figure 1 In the example of , the system 100 includes a data storage device 102 and a host device 150. The data storage device 102 includes a controller 120 (referred to herein as a “data storage device controller”) and a memory 104 (eg, a non-volatile memory) coupled to the data storage device controller 120.

[0019] An example of structural and functional features provided by the data storage device controller 120 is shown in Figure 1 The data storage device controller 120 may also include Figure 1 Additionally, although the data storage device 102 may include additional modules or components other than those specifically illustrated in Figure 1 102 as including a data storage device controller 120, but in other specific implementations, the data storage device controller 120 is instead located separately from the data storage device 102. Therefore, operations generally performed by the data storage device controller 120 described herein may be performed by another device connected to the data storage device 102.

[0020] The data storage device 102 and the host device 150 may be operatively coupled via a connection (e.g., a communication path 110) such as a bus or a wireless connection. In some examples, the data storage device 102 may be embedded within the host device 150. Alternatively, in other examples, the data storage device 102 may be removable from the host device 150 (i.e., "removably" coupled to the host device 150). For example, the data storage device 102 may be removably coupled to the host device 150 according to a removable universal serial bus (USB) configuration. In some specific implementations, the data storage device 102 may include or correspond to a solid-state drive (SSD), which may be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device or cloud storage drive, or other suitable storage drive.

[0021] The data storage device 102 may be configured to be coupled to a host device 150 via a communication path 110 (such as a wired communication path and / or a wireless communication path). For example, the data storage device 102 may include an interface 108 (e.g., a host interface) that enables communication via the communication path 110 between the data storage device 102 and the host device 150, such as when the interface 108 is communicatively coupled to the host device 150.

[0022] The host device 150 may include an electronic processor and a memory. The memory may be configured to store data and / or instructions that can be executed by the electronic processor. The memory may be a single memory, or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof. The host device 150 may issue one or more commands to the data storage device 102, such as one or more requests to erase data at the memory 104 of the data storage device 102, read data from the memory, or write data to the memory. For example, in order to write data to the memory 104, the host device 150 sends a ZNS host write command to the data storage device 102, which includes both the data written to the ZNS and the buffer in the ZWG stored in the memory 104. Additionally, the host device 150 may issue one or more vendor-specific commands to the data storage device 102 to notify and / or configure the data storage device 102. For example, the host device 150 may be configured to provide data to be stored at the memory 104 (such as user data 132) or request data to be read from the memory 104 through the request 134. Host device 150 may include a mobile smart phone, a music player, a video player, a game console, an e-book reader, a personal digital assistant (PDA), a computer (e.g., a laptop or notebook computer), any combination thereof, or other suitable electronic device.

[0023] The host device 150 communicates via a memory interface that enables reading from and writing to the memory 104. The host device 150 operates in compliance with one or more industrial specifications including the non-volatile memory express (NVMe) host controller specification. Specifically, the host device 150 includes NVMe host software 152, and the electronic processor of the host device 150 executes the NVMe host software to operate in compliance with the NVMe host controller specification. The NVMe host software 152 is part of the software on the host device 150, and the software on the host device 150 includes application software, system software, programming software, driver software, and / or any other suitable software. In some examples, the NVMe host software 152 may be one or more drivers that are part of the driver software on the host device 150. Additionally, in some cases, the host device 150 includes a host ZWG association table 154 that mirrors the ZWG association table 139 stored in the memory 124, as described in more detail below. In some cases, a copy of ZWG association table 139 is stored in memory 104 in addition to ZWG association table 139 stored in memory 124 .

[0024] In other cases, host device 150 may operate in accordance with other specifications, such as the Universal Flash Storage (UFS) host controller interface specification, the Universal Serial Bus specification, or other suitable industry specifications. Host device 150 may also communicate with memory 104 according to any other suitable communication protocol.

[0025] The memory 104 of the data storage device 102 may include a non-volatile memory (e.g., NAND, 3D NAND series memory, or other suitable memory). In some examples, the memory 104 may be any type of flash memory. For example, the memory 104 may be a two-dimensional (2D) memory or a three-dimensional (3D) flash memory. The memory 104 may include one or more memory dies 103. Each memory die in the one or more memory dies 103 may include one or more blocks (e.g., one or more erase blocks). Each block may include one or more groups of storage elements, such as a group of representative storage elements 107A-107N. The group of storage elements 107A-107N may be configured as a word line. The group of storage elements 107 may include a plurality of storage elements, such as representative storage elements 109A and 109N, respectively. The group of storage elements 107A-107N may include a partition namespace for storing data. Representative storage elements 109A and 109N may be SSD ZWGs, as described in more detail below.

[0026] Memory 104 may include support circuitry, such as read / write circuitry 140, to support the operation of one or more memory dies 103. Although depicted as a single component, read / write circuitry 140 may be separated into separate components of memory 104, such as read circuitry and write circuitry. Read / write circuitry 140 may be located external to one or more memory dies 103 of memory 104. Alternatively, one or more separate memory dies may include corresponding read / write circuitry that is operable to read from and / or write to storage elements within the separate memory dies independently of any other read operations and / or write operations at any of the other memory dies.

[0027] The data storage device 102 includes a data storage device controller 120 coupled to a memory 104 (e.g., one or more memory dies 103) via a bus 106, an interface (e.g., an interface circuit system), another structure, or a combination thereof. For example, the bus 106 may include a plurality of different channels to enable the data storage device controller 120 to communicate with each of the one or more memory dies 103 in parallel with and independently of the communication with the other memory dies 103. In some implementations, the memory 104 may be a flash memory.

[0028] The data storage device controller 120 is configured to receive data and instructions from the host device 150 and transmit data to the host device 150. For example, the data storage device controller 120 may transmit data to the host device 150 via the interface 108, and the data storage device controller 120 may receive data from the host device 150 via the interface 108. The data storage device controller 120 is configured to transmit data and commands (e.g., memory operations 136) to the memory 104 and receive data from the memory 104. For example, the data storage device controller 120 is configured to transmit data and write commands so that the memory 104 stores data to a specified address of the memory 104. The write command may specify a physical address of a portion of the memory 104 to be used to store data (e.g., a physical address of a word line of the memory 104).

[0029] The data storage device controller 120 is configured to transmit a read command to the memory 104 to access data from a specified address of the memory 104. The read command may specify a physical address of a region of the memory 104 (e.g., a physical address of a word line of the memory 104). The data storage device controller 120 may also be configured to transmit data and commands to the memory 104 that are associated with background scan operations, garbage collection operations, and / or wear leveling operations or other suitable memory operations.

[0030] The data storage device controller 120 may include a memory 124 (e.g., a random access memory (“RAM”), a read-only memory (“ROM”), a non-transitory computer-readable medium, or a combination thereof), an error correction code (ECC) engine 126, and an electronic processor 128 (e.g., a microprocessor, a microcontroller, a field programmable gate array (“FPGA”) semiconductor, an application-specific integrated circuit (“ASIC”), or another suitable programmable device). The memory 124 stores data and / or instructions that may be executable by the electronic processor 128. For example, the memory 124 stores ZWG build instructions 131, a ZWG association table 139, and an NVMe host memory buffer (HMB) descriptor list 138 that can be executed by the electronic processor 128. In some cases, the ZWG build instructions 131, the ZWG association table 139, and the NVMe HMB descriptor list 138 are permanently stored in the memory 124. In other cases, at least the ZWG build instructions 131 are received from the host device 150.

[0031] The ZWG association table 139 maps the ZWGs (e.g., ZWG IDs) stored in the memory 104 to corresponding host regions and parity regions (e.g., region IDs), as described in more detail below. Therefore, the data storage device controller 120 refers to the ZWG association table 139 to identify the locations of the host regions and parity regions within the ZWGs. In some implementations, the memory 124 stores a forward ZWG association table that maps the ZWGs to corresponding host regions and parity regions, and a reverse ZWG association table that maps the host regions and parity regions to their corresponding ZWGs.

[0032] Additionally, although the data storage device controller 120 Figure 1 102, but in other specific implementations, some or all of the memory 124 is instead located at a location separate from the data storage device controller 120 and can be executed by the electronic processor 128 or a different electronic processor located outside the data storage device controller 120 and / or the data storage device 102. For example, the memory 124 can be a dynamic random access memory (DRAM) that is separate and different from the data storage device controller 120 and includes some or all of the NVMe HMB descriptors in the NVMe HMB descriptor list 138. Therefore, operations that would normally be performed only by the data storage device controller 120 described herein can be performed by the following items: 1) the electronic processor 128 and a different memory located inside the data storage device 102; 2) the electronic processor 128 and a different memory located outside the data storage device 102; 3) a different electronic processor located outside the data storage device controller 120 and communicating with the memory of the data storage device 102; and 4) a different electronic processor located outside the data storage device controller 120 and communicating with the memory located outside the data storage device 102.

[0033] The NVMe HMB descriptor list 138 is a list of HMB address ranges dedicated for the data storage device controller 120. The NVMe HMB descriptor list 138 is initially created during the aforementioned NVMe mode of the data storage device controller 120.

[0034] The data storage device controller 120 may transmit a memory operation 136 (e.g., a read command) to the memory 104 to enable the read / write circuit system 140 to sense data stored in the storage element. For example, the data storage device controller 120 may transmit a read command to the memory 104 in response to receiving a request for read access from the host device 150.

[0035] As described above, the set of storage elements 107A-107N may include a partitioned namespace for storing data. In some cases, the partitioned namespace includes a ZWG that includes a host region for storing host data and a parity region for storing parity data. Figure 2 An example ZWG 200 stored in a partitioned namespace is illustrated. The ZWG 200 includes a plurality of host regions 205 and a plurality of parity regions 210. Each host region 205 stores a buffer received from a host device 150 using a ZNS host write command. Each parity region 210 stores a parity buffer for data stored in the plurality of host regions 205. The plurality of parity regions 210 are allocated from a free region pool during construction of the ZWG 200, as described in more detail below.

[0036] Although Figure 2 A single ZWG 200 is provided, but in some cases, the partitioned namespace includes multiple ZWGs 200 having a specific number of host regions 205 and parity regions 210. Each ZWG in the ZWG 200 may include a varying number of host regions 205, a varying number of parity regions 210, or a combination thereof. For example, a first ZWG may include five host regions 205 and one parity region 210, while a second ZWG may include ten host regions 205 and two parity regions 210.

[0037] Additionally, the host region 205 and the parity region 210 forming the ZWG 200 may be spread over multiple memory dies. Therefore, in some specific implementations, the host region 205 and the parity region 210 include indicators (e.g., ZWG indicators, metadata, or other suitable indicators) indicating the ZWG 200 to which they belong or are associated. Additionally, in some cases, the indicator indicates the type of the region. For example, the indicator indicates whether the region is the host region 205 or whether the region is the parity region 210. For example, the indicator may be a header included in a data frame stored in the host region 205 and a header included in a data frame stored in the parity region 210. In some embodiments, the indicator also indicates the type of the region (e.g., whether the region is the host region 205 or the parity region 210). By using the indicator to identify the region and spreading the ZWG 200 over multiple memory dies, the data storage device controller 120 can recover from the failure of a single die and recreate the lost data.

[0038] Figure 3 is a flow chart illustrating an example process 300 for constructing a ZWG 200 according to various aspects of the present disclosure. The process 300 is relative to Figure 1 The data storage device controller 120 is described below. Figure 3 A specific order of steps is illustrated, but in some embodiments, the steps may be performed in a different order. Additionally, in some embodiments, process 300 includes additional steps or fewer steps.

[0039] like Figure 3 As illustrated, the process 300 includes the data storage device controller 120 receiving a host write command (at block 302). The host write command (e.g., a ZNS host write command) may include data to be written and region construction information, such as an indicator (e.g., a ZWG indicator, indicator metadata, or other suitable indicator), a host region count indicating the number of hosts to be included in the ZWG, a parity region count indicating the number of parity regions to be included in the ZWG, a parity buffer accumulation instruction, a host buffer accumulation instruction, or a combination thereof.

[0040] The process 300 includes the data storage device controller 120 building the ZWG 200 (at block 304 ). For example, the data storage device controller 120 applies the ZWG building instructions 131 stored in the memory 124 to the region building information to build the ZWG 200 .

[0041] The process 300 includes the data storage device controller 120 dividing the segments of the partition namespace into ZWGs 200 (at block 306). For example, the data storage device controller 120 designates a subset of the regions within the ZWG 200 as host regions 205 and a subset of the regions within the ZWG 200 as parity regions 210. The number of host regions 205 and the number of parity regions 210 are based on a host region count and a parity region count provided by a host write command.

[0042] The process 300 includes the data storage device controller 120 associating the host region 205 with the parity region 210 (at block 308). For example, the memory 124 includes a ZWG association table 139 that stores information indicating which host regions 205 and which parity regions 210 form the ZWG 200. Additionally, the ZWG association table 139 stores information indicating which parity region 210 stores parity data for which host region 205. By associating the host region 205 with the parity region 210, the data storage device controller 120 identifies which parity region 210 corresponds to which host region 205 during a recovery process, even if the regions are spread across different memory dies. Once the ZWG 200 is constructed and the host region 205 is associated with the parity region 210, the ZWG 200 is enabled for write operations and parity buffer accumulation.

[0043] In some implementations, when constructing the ZWG 200, the data storage device controller 120 selects regions for the plurality of host regions 205 based on their expected lifespans (e.g., expected lifespan persistence). For example, the data storage device controller 120 identifies regions with similar expected lifespans and selects those regions as the plurality of host regions 205. As previously described, in a ZNS SSD, data is written sequentially. By grouping the host regions 205 together based on expected lifespans (e.g., age of the data), older data that may be overwritten is grouped together, thereby providing easy access and identification by the data storage device controller 120. In some implementations, the host regions 205 are grouped together during a data garbage collection or relocation process.

[0044] In some cases, the host device 150 invalidates regions of the ZWG 200 in a timely manner to achieve close lifespans between host regions 205 and avoid the need for garbage collection by the data storage device controller 120. Therefore, in some implementations, the host device 150 assists in the construction of the ZWG 200 by accumulating and providing buffers (such as parity buffers), providing construction instructions, assisting or reducing garbage collection operations, other assisting operations, or various combinations thereof.

[0045] Once the ZWG 200 is constructed, the data storage device controller 120 stores the various buffers in the ZWG 200. In one example, the composition of the ZWG 200 includes data provided by the host device 150. For example, to write data to the memory 104, the host device 150 sends a ZNS host write command to the data storage device controller 120. The ZNS host write command includes memory buffers used by the data storage device controller 120 to construct the ZWG 200. In one case, the data storage device controller 120 writes to both the plurality of host regions 205 and the plurality of parity regions 210 using the memory buffers provided by the host device 150. In another case, the data storage device controller 120 writes only to the plurality of host regions 205 using the memory buffers provided by the host device 150, while the data storage device controller 120 writes to the plurality of parity regions 210 using the buffers that the data storage device controller 120 accumulates from those written to the plurality of host regions 205.

[0046] However, in other cases, the host device 150 is unaware of the ZWG 200 stored in the memory 104, and the data composition within the ZWG 200 is completely defined by the data storage device controller 120. For example, both the plurality of host regions 205 and the plurality of parity regions 210 are written using a buffer accumulated by the data storage device controller 120. In some cases where the host device 150 includes a host ZWG association table 154, the host device 150 populates the host ZWG association table 139 by requesting information stored in the ZWG association table 154 from the data storage device controller 120. In other specific implementations, the host device 150 is completely unaware of the ZWG 200 and does not store any information related to the ZWG 200.

[0047] If some aspect of the memory 104 experiences an error, such as a memory die failure, the data storage device controller 120 uses the ZWG 200 (or the ZWG 200 with the region stored at the failed die and an additional ZWG) to reconstruct the data. Figure 4 is a flow chart illustrating an example process 400 for recovering from a data loss event according to various aspects of the present disclosure. The process 400 is relative to Figure 1 During process 400, parity accumulation occurs on host device 150. Figure 4 A specific order of steps is illustrated, but in some embodiments, the steps may be performed in a different order. Additionally, in some embodiments, process 400 includes additional steps or fewer steps.

[0048] The process 400 includes the data storage device controller 120 writing a buffer from the host device 150 to the host area 205 and writing a parity buffer to the parity area 210 forming the ZWG 200 stored in the memory 104 (at block 402). As an example, the data storage device controller 120 receives a host write command from the host device 150. The host write command includes the parity buffer stored in the host area 205 and the parity area 210. In some cases, the parity buffer provided by the host device 150 is stored only in the parity area 205.

[0049] Process 400 includes the data storage device controller 120 detecting corrupted data (at block 404). For example, the data storage device controller 120 detects that the memory die 103 has become corrupted or receives an indication (from, for example, the memory 104) that the memory die 103 has become corrupted. When the data storage device controller 120 detects a memory failure, the data storage device controller 120 initiates a recovery event (at block 406).

[0050] The process 400 includes the data storage device controller 120 recreating non-corrupted data using buffers from non-corrupted areas (at block 408). For example, when a memory die 103 storing host data fails, the data storage device controller 120 uses the accumulated host buffers written to the host area 205 and / or the parity buffers written to the parity area 210 to recreate the data before the data becomes corrupted (e.g., lost or destroyed), thereby performing a recovery process. In some implementations, the buffers used to recreate the non-corrupted data are buffers from the same ZWG 200 of the corrupted data. Thus, the data storage device controller 120 recovers the data before the data becomes corrupted by using the data stored in the ZWG 200.

[0051] Figure 5 is a flow chart illustrating another example process 500 for recovering from a data loss event in accordance with various aspects of the present disclosure. During process 500, parity accumulation occurs on data storage device 102 and ZWG 200 is stored on memory 104. Figure 5 A specific order of steps is illustrated, but in some embodiments, the steps may be performed in a different order. Additionally, in some embodiments, process 500 includes additional steps or fewer steps.

[0052] Process 500 includes data storage device controller 120 writing accumulated buffers to host area 205 and parity area 210 forming ZWG 200 stored in memory 104 (at block 502). For example, data storage device controller 120 accumulates buffers while writing host data to host area 205.

[0053] Process 500 includes: the data storage device controller 120 detects corrupted data (at block 504). For example, the data storage device controller 120 detects that the memory die 103 has become corrupted, or receives an indication that the memory die 103 has become corrupted. When the data storage device controller 120 detects a memory failure, the data storage device controller 120 initiates a recovery event (at block 506).

[0054] The process 500 includes the data storage device controller 120 recreating non-corrupted data using the buffer from the non-corrupted area (at block 508). For example, when a memory die 103 storing host data fails, the data storage device controller 120 uses the accumulated parity buffer written to the host area 205 and the parity area 210 to recreate the data before the data becomes corrupted (e.g., lost or destroyed), thereby performing a recovery process. Thus, the data storage device controller 120 replaces the corrupted data with an earlier, non-corrupted version of the corrupted data by using the data stored in the ZWG 200 and thus by using the buffer provided by the data storage device controller 120 itself.

[0055] Figure 6 is a flow chart illustrating an example process 600 for retrieving a buffer for data recovery according to various aspects of the present disclosure. The process 600 is relative to Figure 1 The data storage device controller 120 is described below. Figure 6 A specific order of steps is illustrated, but in some embodiments, the steps may be performed in a different order. Additionally, in some embodiments, process 600 includes additional steps or fewer steps.

[0056] The process 600 includes the data storage device controller 120 identifying a first parity region included in the ZWG 200 (at block 602). For example, the data storage device controller 120 identifies the parity region 210 included in the ZWG 200 stored in the memory 104 by referring to the ZWG association table 139. The process 600 includes the data storage device controller 120 retrieving an indicator of the first parity region (at block 604). The indicator indicates a location of the parity region 210 within the ZWG 200.

[0057] Process 600 includes the data storage device controller 120 requesting a parity buffer stored in the first parity region based on the indicator at block 606. Process 600 includes the data storage device controller 120 recreating a non-damaged region using the parity buffer at block 608.

[0058] Although process 600 is described with respect to data storage device controller 120 identifying a parity region and receiving a parity buffer, in some cases, data storage device controller 120 instead identifies a host region (at block 602) and retrieves an indicator of the host region (at block 604). Data storage device controller 120 requests a host buffer stored in the host region included in ZWG 200 (at block 606), receives the host buffer (at block 608), and recovers the damaged region using the host buffer (at block 610). Additionally, although process 600 is described with respect to data storage device controller 120, in some cases, host device 150 performs process 600.

[0059] Additionally, in some cases, process 600 includes data storage device controller 120 (at block 602) requesting only a single parity buffer when a single parity buffer is needed to recreate a non-damaged region. In other cases, process 600 includes data storage device controller 120 requesting two or more parity buffers.

[0060] It should be understood that the above description is intended to be exemplary and not restrictive. Upon reading the above description, many embodiments and applications other than the examples provided will be apparent. The scope should not be determined with reference to the above description, but rather with reference to the appended claims together with the full range of equivalents to which such claims are entitled to be used. It is anticipated and intended that the technology discussed herein will undergo future development, and the disclosed systems and methods will be incorporated into such future implementations. In short, it should be understood that the present application is capable of modification and variation.

[0061] All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those familiar with the technology described herein, unless expressly indicated to the contrary herein. In particular, use of singular articles such as "a," "an," "the," and the like should be understood to recite one or more of the indicated elements, unless a claim recites an express limitation to the contrary.

[0062] An abstract of the specification is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that the content submitted is not used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying the present disclosure. This method of disclosure should not be interpreted as reflecting such an intention: the claimed embodiment requires more features than those explicitly stated in each claim. On the contrary, as reflected in the following claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

Claims

1. A data storage device, comprising: a memory comprising a plurality of zones in a zoned name space (ZNS), the ZNS comprising a zone write group (ZWG), the zone write group (ZWG) comprising a plurality of host zones and a plurality of parity zones; and A data storage device controller comprising an electronic processor and a data storage controller memory storing a set of instructions, which, when executed by the electronic processor, instructs the controller to: detecting corrupted data associated with said ZNS, Requests one or more buffers to be stored in the ZWG, receiving the one or more buffers from the ZWG, and A recovery process is performed using the one or more buffers.

2. The data storage device of claim 1, wherein the data storage device comprises an interface configured to connect to a host device, wherein the data storage controller memory comprises a set of construction instructions, and wherein the data storage device controller is further configured to: receiving a host write command from the host device, the host write command including build information, and The ZWG is constructed based on the construction information using the construction instruction set. 3 . The data storage device of claim 2 , wherein the construction information includes a ZWG indicator, a host region count indicating the number of the plurality of host regions, and a parity region count indicating the number of the plurality of parity regions.

4. The data storage device according to claim 2, wherein in order to construct the ZWG based on the construction information, the data storage device controller is further configured to: Each host region included in the plurality of host regions is associated with one or more parity regions included in the plurality of parity regions.

5. The data storage device of claim 2, wherein the data storage device controller is further configured to: receiving a host data buffer associated with the host write command, and The plurality of host regions are populated with the host data buffer.

6. The data storage device of claim 1, wherein the data storage device controller is configured to perform the recovery process by recreating non-corrupted data associated with the ZNS using the one or more buffers received from the ZWG.

7. The data storage device of claim 1 , wherein the data storage device controller is further configured to: identifying a first parity region included in the ZWG, retrieving an indicator of said first parity region, requesting a parity buffer stored in the first parity area based on the indicator, and The parity buffer is received.

8. A method comprising: A zone write group (ZWG) is constructed using a data storage device controller, wherein the zone write group (ZWG) includes one or more host zones and one or more parity zones, writing, with the data storage device controller, a host data buffer to a host area of ​​the one or more host areas and a parity buffer to a parity area of ​​the one or more parity areas, detecting, with the data storage device controller, corrupted data associated with a zone name space (ZNS), requesting, using the data storage device controller, one or more buffers stored in the ZWG, receiving, with the data storage device controller, the one or more buffers from the ZWG, and A recovery process is performed using the data storage device controller using the one or more buffers.

9. The method according to claim 8, further comprising: receiving, with the data storage device controller, a write command from a host device, the write command including build information, and Wherein constructing the ZWG using the data storage device controller includes constructing the ZWG using the construction information. 10 . The method of claim 8 , wherein the construction information includes a ZWG indicator, a host region count indicating the number of host regions, and a parity region count indicating the number of parity regions.

11. The method according to claim 8, further comprising: Associating, with the data storage device controller, a first indicator with the host region and a second indicator with the parity region, identifying, with the data storage device controller, the host region based on the first indicator, and The parity region is identified, with the data storage device controller, based on the second indicator.

12. The method of claim 8, wherein performing the recovery process comprises recreating non-corrupted data associated with the ZNS using the one or more buffers received from the ZWG.

13. The method according to claim 8, further comprising: The plurality of host regions are selected, utilizing the data storage device controller and during a garbage collection event, based on the host regions having similar ages.

14. A data storage device, comprising: a memory comprising a plurality of zones in a zoned name space (ZNS), the ZNS comprising a zone write group (ZWG), the zone write group (ZWG) comprising a plurality of host zones and a plurality of parity zones; an interface configured to connect to a host device; and A data storage device controller comprising an electronic processor and a data storage controller memory storing a set of instructions, which, when executed by the electronic processor, instructs the controller to: receiving a plurality of buffers from the host device, filling a host region of the plurality of host regions with a buffer of the plurality of buffers, detecting corrupted data associated with said ZNS, requesting said buffer to be stored in the host area, receiving the buffer from the host region, and A recovery event is performed using the buffer received from the host region.

15. The data storage device of claim 14, wherein the data storage controller memory includes a set of build instructions, and wherein the data storage device controller is further configured to: receiving a host write command from the host device, the host write command including build information, and The ZWG is constructed based on the construction information using the construction instruction set. 16 . The data storage device of claim 15 , wherein the construction information comprises a ZWG indicator, a host region count indicating the number of the plurality of host regions, and a parity region count indicating the number of the plurality of parity regions.

17. The data storage device of claim 15, wherein the host write command includes the plurality of buffers.

18. The data storage device of claim 14, wherein the data storage device controller is further configured to: Each host region included in the plurality of host regions is associated with one or more parity regions included in the plurality of parity regions.

19. The data storage device of claim 14, wherein the data storage device controller is further configured to: identifying the host region included in the ZWG, retrieving an indicator of said host region, requesting the buffer stored in the host region based on the indicator, and The buffer is received.

20. The data storage device of claim 14, wherein the data storage device controller is further configured to: filling a parity check area among the plurality of parity check areas with a second buffer among the plurality of buffers, requesting the second buffer to be stored in the parity area, receiving the second buffer from the parity region, and The recovery process is performed using the second buffer received from the parity area.

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