Optical calculation method and system, controller and storage medium

Abstract

The invention relates to an optical calculation method and system, a controller and a storage medium. The optical computing system includes: an analog-to-digital converter array configured to convert a current generated in the case of translocation of a polymer relative to a nanopore into a digital signal; and the optical computing chip is configured to identify the arrangement of the polymer units in the polymer according to the digital signal. The optical computing chip with the computing power superior to that of a GPU is applied to polymer sequencing based on nanopores, and the computing speed of'identifying polymer units in effective signals' of the optical computing chip under the condition that multiple nanopores generate data in parallel 'is optimized.

Description

Optical computing method and system, controller and storage medium Technical Field

[0001] The present disclosure relates to the field of polymer unit sequencing analysis in polymers, and in particular to an optical computing method and system, a controller, and a storage medium. Background Art

[0002] Related technologies use nanopores to estimate a type of measurement system for the target sequence of polymer units in a polymer. This type of system causes the polymer to translocate relative to the nanopore, and determines the arrangement of polymer units in the polymer through changes in physical properties such as the current generated by each polymer unit when the polymer monomer passes through the nanopore, using methods such as artificial neural networks.

[0003] Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided an optical computing system, comprising:

[0005] an analog-to-digital converter array configured to convert a current generated when the polymer is translocated relative to the nanopore into a digital signal;

[0006] An optical computing chip is configured to recognize the arrangement of polymer units in a polymer based on a digital signal.

[0007] In some embodiments of the present disclosure, the optical computing chip is configured to determine whether the digital signal is a valid signal, and identify the arrangement of polymer units in the polymer by identifying the valid signal.

[0008] In some embodiments of the present disclosure, the optical computing system further includes:

[0009] a controller configured to split a digital signal output by each analog-to-digital converter in the analog-to-digital converter array into a plurality of sub-signals, and add a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier;

[0010] The first cache includes multiple sub-caches, is arranged between the analog-to-digital converter array and the optical computing chip, and is configured to store sub-signals with corresponding identifiers added; when a sub-cach in the first cache stores a sub-signal, the sub-cach is switched and the sub-signal in the sub-cach is output to the optical computing chip.

[0011] In some embodiments of the present disclosure, the optical computing system further includes:

[0012] a second cache, disposed between the first cache and the optical computing chip, configured to cache the sub-signal output by the first cache and then output it to the optical computing chip;

[0013] The controller is further configured to set the bandwidth of each sub-signal of the second cache output to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

[0014] In some embodiments of the present disclosure, the optical computing chip includes:

[0015] A first computing chip is configured to determine whether the digital signal is a valid signal;

[0016] The second computing chip is configured to identify the arrangement of polymer units in the polymer by identifying the effective signal.

[0017] In some embodiments of the present disclosure, the optical computing system further includes:

[0018] The third cache is provided between the first computing chip and the second computing chip, and is configured to store the valid signal calculated by the first computing chip.

[0019] In some embodiments of the present disclosure, the third buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array.

[0020] In some embodiments of the present disclosure, the controller is further configured to place sub-signals with multiple consecutive timestamps from the same nanopore in the third cache into the same segment in a time series; or to sequentially enter the sub-signals from the same nanopore in the third cache into the optical computing chip through a reference pointer.

[0021] In some embodiments of the present disclosure, the second buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array.

[0022] In some embodiments of the present disclosure, the controller is further configured to place the sub-signals of multiple consecutive timestamps from the same nanopore in the second cache in the same segment in a time series; or to sequentially enter the sub-signals from the same nanopore in the second cache into the optical computing chip through a reference pointer.

[0023] In some embodiments of the present disclosure, the analog-to-digital converter array is an analog-to-digital converter array including a plurality of analog-to-digital converters.

[0024] In some embodiments of the present disclosure, the length of the sub-signals in the first buffer is less than or equal to the length of the sequence that the optical computing chip is configured to process.

[0025] In some embodiments of the present disclosure, a transmission bandwidth from the first cache to the optical computing chip is equal to a computing speed of the optical computing chip.

[0026] In some embodiments of the present disclosure, the controller is further configured to, when the length of the current sub-signal in the first cache is less than the sequence length configured to be processed by the optical computing chip, use at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal to complete the current sub-signal, so that the length of the current sub-signal in the first cache is equal to the sequence length configured to be processed by the optical computing chip.

[0027] In some embodiments of the present disclosure, the optical computing chip includes:

[0028] a light source configured to output unmodulated light for computing;

[0029] A first digital-to-analog conversion array is configured to receive external input data and convert the external input data into a first analog signal;

[0030] a modulator array configured to form tensor data according to the light output by the light source and the first analog signal;

[0031] a weight data cache configured to store weight data of the multiplication matrix;

[0032] a second digital-to-analog conversion array, configured to convert the weight data into a second analog signal;

[0033] The optoelectronic matrix multiplication module is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to realize optical path calculation.

[0034] According to another aspect of the present disclosure, there is provided an optical computing method, comprising:

[0035] The current generated when the polymer is translocated relative to the nanopore is converted into a digital signal by an analog-to-digital converter array;

[0036] The control optical computing chip recognizes the arrangement of polymer units in the polymer based on digital signals.

[0037] In some embodiments of the present disclosure, controlling the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal includes: controlling the optical computing chip to determine whether the digital signal is a valid signal, and identifying the arrangement of polymer units in the polymer by identifying the valid signal.

[0038] In some embodiments of the present disclosure, the optical computing method further includes:

[0039] Splitting a digital signal output by each analog-to-digital converter in the analog-to-digital converter array into a plurality of sub-signals, and adding a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier;

[0040] The first cache is controlled to store the sub-signal with the corresponding identifier added thereto. When a sub-cach in the first cache stores the sub-signal, the sub-cach is switched and the sub-signal in the sub-cach is output to the optical computing chip, wherein the first cache includes multiple sub-caches.

[0041] In some embodiments of the present disclosure, the optical computing method further includes:

[0042] After caching the sub-signal output by the first cache through the second cache, the sub-signal is output to the optical computing chip;

[0043] The bandwidth of each sub-signal of the second buffer output to the optical computing chip is set to be higher than the computing operating frequency of the optical computing chip.

[0044] In some embodiments of the present disclosure, the controlling the optical computing chip to determine whether the digital signal is a valid signal, and identifying the arrangement of polymer units in the polymer by identifying the valid signal includes:

[0045] Controlling the first computing chip to determine whether the digital signal is a valid signal;

[0046] Storing the valid signal calculated by the first computing chip through the third cache;

[0047] The second computing chip is controlled to identify the arrangement of polymer units in the polymer by identifying the effective signal.

[0048] In some embodiments of the present disclosure, the optical computing method further includes:

[0049] The sub-signals with multiple consecutive time stamps from the same nanopore in the third buffer are placed in the same segment in time series.

[0050] In some embodiments of the present disclosure, the optical computing method further includes:

[0051] By referencing the pointer, the sub-signals from the same nanopore in the third cache are sequentially entered into the optical computing chip.

[0052] In some embodiments of the present disclosure, the optical computing method further includes:

[0053] placing the sub-signals of a plurality of consecutive time stamps from the same nanopore in the second buffer into the same segment in time series;

[0054] In some embodiments of the present disclosure, the optical computing method further includes: sequentially entering the sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

[0055] In some embodiments of the present disclosure, the optical computing method further includes:

[0056] Setting the length of the sub-signals in the first buffer to be less than or equal to the length of the sequence that the optical computing chip is configured to process;

[0057] The transmission bandwidth from the first cache to the optical computing chip is set to be equal to the computing speed of the optical computing chip.

[0058] In some embodiments of the present disclosure, the optical computing method further includes:

[0059] When the length of the current sub-signal in the first cache is less than the sequence length configured for processing by the optical computing chip, at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal is used to padded the current sub-signal, so that the length of the current sub-signal in the first cache is equal to the sequence length configured for processing by the optical computing chip.

[0060] According to another aspect of the present disclosure, there is provided a controller, comprising:

[0061] a first control module, configured to convert a current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array;

[0062] The second control module is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

[0063] According to another aspect of the present disclosure, there is provided a controller, comprising:

[0064] a memory for storing instructions;

[0065] The processor is configured to execute the instructions so that the controller performs operations to implement the optical computing method as described in any one of the above embodiments.

[0066] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the optical computing method as described in any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0068] FIG1 is a schematic diagram of some embodiments of the optical computing system disclosed herein.

[0069] FIG2 is a schematic diagram of some other embodiments of the optical computing system disclosed herein.

[0070] FIG3 is a schematic diagram of some further embodiments of the optical computing system disclosed herein.

[0071] FIG4 is a schematic diagram of some other embodiments of the optical computing system disclosed herein.

[0072] FIG5 is a schematic diagram of some further embodiments of the optical computing system disclosed herein.

[0073] FIG. 6 is a schematic diagram of cache segmentation setup and sorting in some embodiments of the present disclosure.

[0074] FIG7 a , FIG7 b , FIG7 c and FIG7 d are schematic diagrams of sub-signals in some embodiments of the present disclosure.

[0075] FIG8 is a schematic diagram of some further embodiments of the optical computing system disclosed herein.

[0076] FIG9 is a schematic diagram of some embodiments of the optical computing method disclosed herein.

[0077] FIG. 10 is a schematic diagram of some embodiments of the controller disclosed herein.

[0078] FIG11 is a schematic structural diagram of other embodiments of the controller disclosed herein. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0080] Unless specifically stated otherwise, the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0081] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0082] Technologies, methods and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods and equipment should be considered part of the authorization specification.

[0083] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0084] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0085] The inventors have discovered through research that the present invention relates to analyzing measurements taken from polymer units in a polymer (such as, but not limited to, a polynucleotide) during translocation of the polymer relative to a nanopore.

[0086] Related Art: A type of measurement system that uses nanopores to estimate the target sequence of polymer units in a polymer. This system translocates a polymer relative to the nanopore and, based on changes in physical properties such as the current generated by each polymer unit as the polymer monomer passes through the nanopore, determines the arrangement of the polymer units in the polymer using methods such as artificial neural networks. This type of measurement system using nanopores holds considerable promise, particularly in the field of sequencing polynucleotides such as DNA or RNA, and has been the subject of recent developments.

[0087] Protein peptide chains can also be sequenced using nanopores. Related technologies have disclosed a single-molecule peptide sequencing method based on nanopore technology. Under the action of Hel308 DNA helicase, a DNA-peptide conjugate is pulled through the MspA nanopore, generating a unique step-like current signal in the ion flow. Using accompanying recognition software, the current signal can be accurately identified and the median current analyzed to retrospectively confirm sequence information.

[0088] Related art can identify polymer sequencing signals using neural networks. The related art discloses using recurrent neural networks (RNNs) machine learning techniques to analyze polymer signals passing through a nanopore and derive a posterior probability matrix. Each posterior probability matrix represents, for different corresponding historical sequences of polymer units corresponding to measurement results prior to the corresponding measurement, the posterior probability of multiple different variations of the corresponding historical sequences of polymer units resulting in a new sequence of polymer units. The analysis can include performing convolution on a set of consecutive measurement results using a trained feature detector, such as a convolutional neural network, to derive a series of feature vectors that serve as the RNN's operational targets.

[0089] The current signal emitted by a nanopore is not always a valid signal from polymer units passing through the nanopore, but the comparative document does not provide the process and structure for identifying valid signals. Taking DNA as an example, both identifying valid signals and identifying the base sequence within the signal require a significant amount of computing power. DNA moves through a nanopore at a speed of 420 nt / s, and arrays typically contain over 1,000 nanopores. Artificial neural networks, such as CNN, RNN, LSTM, and Transformer, are used, requiring a large number of matrix operations and operators.

[0090] Through research, the inventors found that the GPU computing power of related technologies is insufficient. The computing power of a single GPU core is at the level of 10-100G Flops. The GPU computing power of related technologies is insufficient to support the real-time analysis of data generated by tens of thousands of nanopores and realize effective signal recognition and base recognition in effective signals.

[0091] In view of at least one of the above technical problems, the present disclosure provides an optical computing method and system, a controller, and a storage medium. The present disclosure is described below through specific embodiments.

[0092] FIG1 is a schematic diagram of some embodiments of the optical computing system disclosed herein. As shown in FIG1 , the optical computing system disclosed herein includes an analog-to-digital converter array 100, a nanohole array 300, and an optical computing chip 200, wherein:

[0093] The analog-to-digital converter (ADC) array 100 is configured to convert the current generated when the polymer is translocated relative to the nanopore into a digital signal.

[0094] The optical computing chip 200 is configured to identify the arrangement of polymer units in the polymer according to the digital signal.

[0095] In some embodiments of the present disclosure, the optical computing chip 200 may be configured to determine whether the digital signal is a valid signal, and identify the arrangement of polymer units in the polymer by identifying the valid signal.

[0096] The above-mentioned embodiments of the present disclosure process the signals generated by the nanohole array and the ADC array through an optical computing chip, determine whether the signal is a valid signal through the optical computing chip capable of accelerating matrix multiplication, and identify the arrangement of polymer units in the polymer.

[0097] The reasons for the invalid signal are: 1) no nucleic acid sequence passes through the nanopore, 2) the nucleic acid sequence passes through the nanopore, but does not move continuously under the action of the electric field, resulting in a stable potential difference between the two sides of the membrane and unstable signals generated by electromagnetic interference and impurities in the pore.

[0098] In some embodiments of the present disclosure, the optical computing chip 200 can be configured to remove the invalid signal according to the potential difference after filtering out the unstable signal through low-pass filtering. The method of the above embodiment of the present disclosure has a small amount of calculation, but low accuracy.

[0099] In other embodiments of the present disclosure, the optical computing chip 200 may also be configured to perform inference on the signal after training the model through a classifier or a neural network to achieve effective signal recognition.

[0100] In some embodiments of the present disclosure, the optical computing chip 200 is configured to identify bases in effective signals through electrical signals obtained by nanopore collection. The algorithm used is generally obtained by neural network training. The neural network model can be in the form of a recurrent neural network (RNN), a convolutional neural network (CNN), a long short-term memory (LSTM), and a Transformer, etc., and is obtained by training by collecting multiple measurement results of a polymer unit sequence containing a determined target sequence or its complementary sequence. Using the obtained model reasoning, the target sequence of the newly measured polymer unit can be estimated by inferring the effective signal obtained by the electrical signal collected by the nanopore. In the inference and estimation process, each model measurement relies on the k-mer (k polymer units) model to process the input signal sequence into an observation value of the k-mer state. Through the model, the k-mer type and input sequence of each model are processed into a multidimensional k-mer state and an estimate of the polymer unit sequence is generated.

[0101] In some embodiments of the present disclosure, the optical computing chip 200 may include a photonic matrix-vector multiplier based on wavelength routing.

[0102] In some embodiments of the present disclosure, the optical computing chip 200 may include an all-optical diffraction neural network implemented on an optical waveguide and / or an optical chip.

[0103] In some embodiments of the present disclosure, in the optical computing chip 200, an optoelectronic processing device having a segmented optical modulator is provided, including an optical waveguide device having three or more segments, which can improve the analog-to-digital conversion accuracy of the Mach-Zehnder interferometer, the data to be processed includes vector element values ​​of an input vector and matrix element values ​​of a model matrix associated with a neural network model, and processing the data includes calculating multiple intermediate vectors based on element-by-element vector multiplication between different subsets of the vector element values ​​and different corresponding preprocessing vectors.

[0104] The above-mentioned embodiments of the present disclosure apply an optical computing chip with computing power superior to that of a GPU to nanopore-based polymer sequencing, thereby optimizing the computing speed of the optical computing chip in "identifying valid signals" and "identifying polymer units in valid signals" when multiple nanopores generate data in parallel.

[0105] The above-mentioned embodiments of the present disclosure use a type of measurement system for estimating the target sequence of polymer units in a polymer using nanopores. This type of system has multiple nanopores and multiple ADC units. When the polymer is translocated relative to the nanopore, the current generated is converted into a digital signal through the ADC unit array.

[0106] The above-mentioned embodiments of the present disclosure process the signals generated by the nanohole array and the ADC array through an optical computing chip, determine whether the signal is a valid signal through the optical computing chip capable of accelerating matrix multiplication, and identify the arrangement of polymer units in the polymer.

[0107] FIG2 is a schematic diagram of other embodiments of the optical computing system disclosed herein. As shown in FIG2 , the optical computing system disclosed herein includes an analog-to-digital converter array 100, a nanohole array 300, an optical computing chip 200, a first cache 400, a controller, and an output sequence signal cache 500, wherein:

[0108] In some embodiments of the present disclosure, the controller may include a system controller 610 and an ADC array controller 620, wherein:

[0109] The ADC array controller 620 is used to control the analog-to-digital converter array 100 , the nanopore array 300 and the first buffer 400 .

[0110] The system controller 610 is used to control each component module of the system.

[0111] In some embodiments of the present disclosure, the controller (system controller 610 and ADC array controller 620) is configured to divide the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and add a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier.

[0112] The purpose of adding time and ADC identification in the above embodiment of the present disclosure is to allow the segmented sub-signals to be spliced ​​together according to the timestamp and ADC identification to form a complete signal after the optical computing chip recognizes the base.

[0113] In some embodiments of the present disclosure, the first cache 400 includes multiple sub-caches, which are arranged between the analog-to-digital converter array and the optical computing chip, and are configured to store sub-signals with corresponding identifiers added; when a sub-cache in the first cache stores a sub-signal, the sub-cache is switched and the sub-signal in the sub-cache is output to the optical computing chip.

[0114] In some embodiments of the present disclosure, the first cache 400 can be configured to switch the sub-cache and output the sub-signal in the sub-cache to the optical computing chip when the storage ratio of a sub-cache in the first cache is greater than a predetermined value, the remaining storage space is less than a preset value, or data of a preset size is written. That is, when a sub-cache is close to overflowing, the sub-cache is switched and the sub-signal in the sub-cache that is close to being full is output to the optical computing chip.

[0115] In some embodiments of the present disclosure, the analog-to-digital converter array 110 may be an analog-to-digital converter array including a plurality of analog-to-digital converters.

[0116] In some embodiments of the present disclosure, the length of the sub-signals in the first buffer 400 is less than or equal to the length of the sequence that the optical computing chip is configured to process.

[0117] In some embodiments of the present disclosure, the transmission bandwidth from the first cache 400 to the optical computing chip is equal to the computing speed of the optical computing chip.

[0118] In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache.

[0119] In some embodiments of the present disclosure, the controller can also be configured to use at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal to complete the current sub-signal when the length of the current sub-signal in the first cache is less than the sequence length configured to be processed by the optical computing chip, so that the length of the current sub-signal in the first cache is equal to the sequence length configured to be processed by the optical computing chip.

[0120] In the above-described embodiments of the present disclosure, the output signal of the signal output unit of each ADC unit enters a ping-pong buffer and, after preliminary segmentation, is divided into multiple sub-signals. Each sub-signal is assigned a corresponding identifier, which can be a timestamp plus an ADC identifier. When the length of a sub-signal is less than the sequence length N that the optical computing chip is configured to process, the signal at the end of the previous sub-signal and the beginning of the next sub-signal are used to pad the length to N.

[0121] FIG3 is a schematic diagram of further embodiments of the optical computing system disclosed herein. As shown in FIG3 , the optical computing system disclosed herein includes an analog-to-digital converter array 100, a nanohole array 300, an optical computing chip 200, a first cache 400, a controller, and an output sequence signal cache 500. In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache.

[0122] In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache.

[0123] In some embodiments of the present disclosure, sub-matrix-vector multiplication (MVM) mainly includes three categories, namely, matrix calculation based on (single / multi) plane light conversion (PLC), matrix calculation based on Mach Zehnder interferometer (MZI) network, and matrix calculation based on wavelength division multiplexing (WDM).

[0124] This disclosure takes the MZI and WDM methods as an example. The output vector length of MZI and WDM is generally less than 100, and they are mainly used for integrated photon matrix computing chips.

[0125] In some embodiments of the present disclosure, the optical computing chip may have a built-in cache, so that the sequence length N processed by the optical computing chip includes multiple vectors of length L.

[0126] Compared with the embodiment of FIG. 2 , the embodiment of FIG. 3 further provides a specific structure of an optical computing chip 200. As shown in FIG. 3 , the optical computing chip 200 includes an optical computing chip controller 201, a weight data cache 202, a light source 203, a first digital-to-analog conversion array 204, a modulator array 205, multiple second digital-to-analog conversion arrays 206, multiple optoelectronic matrix multiplication modules 207, and an analog-to-digital conversion array 208, wherein:

[0127] The light source 203 is configured to output unmodulated light for calculation.

[0128] The first digital-to-analog conversion array (first DAC array) 204 is configured to receive external input data and convert the external input data into a first analog signal.

[0129] The modulator array 205 is configured to form tensor data to be subjected to matrix multiplication operation according to the light output by the light source and the first analog signal.

[0130] The weight data buffer 202 is configured to store weight data of the multiplication matrix.

[0131] In some embodiments of the present disclosure, the weight data cache 202 is configured to store weights so that when the model used for inference is switched according to the sample type, the weights of the artificial neural network in the corresponding optical computing chip 200 can also be changed accordingly.

[0132] The second digital-to-analog conversion array (second DAC array) 206 is configured to convert the weight data into a second analog signal.

[0133] The optoelectronic matrix multiplication module 207 is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to realize optical path calculation.

[0134] As shown in FIG3 , the optical computing chip controller 201 of the optical computing chip 200 is configured through the system control 610 so that the chip performs matrix calculations at a certain speed.

[0135] The optoelectronic matrix multiplication module 207 is configured to perform optical calculations of the matrix and waveguide vectors, and judge the conditions of DNA single-strand binding, membrane penetration, pore passage, and pore separation corresponding to the digital signal through the changes in the digital signal, identify the valid signal, and identify the base sequence in the valid signal.

[0136] In some embodiments of the present disclosure, the optoelectronic matrix multiplication module 207 can be configured to perform matrix calculations based on a Mach-Zehnder interferometer (MZI) network and matrix calculations based on wavelength division multiplexing (WDM). The tensor propagates through multiple optoelectronic matrix multiplication modules via an optical path to perform multiple matrix multiplication operations, where the coefficients of the matrix multiplication are derived from a machine learning model. Since optical path calculation is used, this step can save computing power and computation time. The calculation results are output to the system controller 610 via the ADC array 208.

[0137] In some embodiments of the present disclosure, due to the high speed of the optical computing process, it is necessary to coordinate the first DAC array 204, the second DAC array 206, and the ADC array 208 to work together. The optical paths, circuit switches, and data transfer involved are performed by the optical computing chip controller 201.

[0138] In some embodiments of the present disclosure, the system controller 610 is configured to process the result data output by the ADC array and output the result data to the output sequence signal buffer 500 based on the library settings and information about the nanopore 300 and the analog-to-digital converter array 100.

[0139] In some embodiments of the present disclosure, the cache of the output sequence signal cache 500 does not have to be a high-speed cache, but its data writing speed must be able to match the speed at which the optical computing chip outputs results.

[0140] In some embodiments of the present disclosure, a nanopore array 300 composed of 256×256 nanopores is used to read single-stranded DNA fragments. An array 100, comprised of multiple ADC units, reads the current signals obtained from the multiple nanopores in the nanopore array 100 under the control of an ADC array controller 620 and converts them into digital signals. Under the control of a system controller 610 or an ADC array controller 620, the digital signals obtained by the ADC array are tagged with sampling times and corresponding ADC identifiers, resulting in multiple sub-signals that are stored in a ping-pong buffer 400.

[0141] In some embodiments of the present disclosure, the ping-pong buffer 400 may have more than one sub-buffer, and the ADCs in the ADC array may have a one-to-one or one-to-many relationship.

[0142] In some embodiments of the present disclosure, when multiple nanopores correspond to one ADC (for example, 256×256 nanopores correspond to 128×128 ADC units), the generated subsequence includes both an ADC identifier and a system time identifier.

[0143] In some embodiments of the present disclosure, four nanopores correspond to one ADC. During the sequencing process, it is determined whether DNA has passed through the pores, and the ADC detects the nanopores with passing signals, which can improve the utilization rate of the ADC.

[0144] In some embodiments of the present disclosure, since the correspondence between the nanopore and the ADC is dynamically determined during the sequencing process based on the sequence passing through the pore, the system controller 610 or the ADC array controller 620 records the time when switching the correspondence, thereby corresponding the signal of a specific time period to the nanopore signal.

[0145] In some embodiments of the present disclosure, as shown in FIG6 , for ADC1, the sub-signal in a specific time period t0-t3 corresponds to nanopore A, while for ADC1, the sub-signal in a specific time period t4-t7 corresponds to nanopore B. Therefore, ADC1+timestamp (t0-t1), ADC1+timestamp (t1-t2), and ADC1+timestamp (t2-t3) are three consecutive sub-signals from nanopore A. ADC1+timestamp (t4-t5), ADC1+timestamp (t5-t6), and ADC1+timestamp (t6-t7) are three consecutive sub-signals from nanopore B.

[0146] In some embodiments of the present disclosure, the length of the signal acquired by the ADC is typically longer than the length of the sequence processed by the optical computing chip. When the signal acquired by the ADC is transferred to the ping-pong buffer, the signal can be segmented so that the length of the sub-signals in the ping-pong buffer is consistent with the length of the sequence processed by the optical computing chip. When one of the ping-pong buffers is close to overflowing, the buffer is switched, and the sub-signals in the full buffer are output to the optical computing chip. The transmission bandwidth is consistent with the computing speed of the optical computing chip, thereby maximizing the computing power of the optical computing chip.

[0147] The above-mentioned embodiments of the present disclosure fully utilize the computing power of the optical computing chip by adding a ping-pong cache and a high-speed cache between the ADC array and the optical chip that can accelerate multiplication matrix operations, making the generation and calculation of digital signals more efficient and rapid.

[0148] FIG4 is a schematic diagram of other embodiments of the optical computing system disclosed herein. FIG5 is a schematic diagram of still other embodiments of the optical computing system disclosed herein. Compared to the embodiments of FIG2 and FIG3 , in the embodiments of FIG4 and FIG5 , the optical computing system includes, in addition to the analog-to-digital converter array 100, the nanohole array 300, the optical computing chip 200, the first cache 400, the controller and output sequence signal cache 500, the system controller 610, and the ADC array controller 620, a second cache 700, wherein:

[0149] The second cache 700 is provided between the first cache 400 and the optical computing chip 200 and is configured to cache the sub-signal output by the first cache and then output it to the optical computing chip.

[0150] The controller (system controller 610 and ADC array controller 620) may also be configured to set the bandwidth of each sub-signal output from the second cache to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

[0151] In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache; the second cache 700 may be a high-speed cache.

[0152] The above embodiment of the present disclosure adds a high-speed cache (103) between the ping-pong cache and the optical computing chip, thereby ensuring that the switching of the ping-pong cache does not affect the computing speed of the optical computing chip. First, the present disclosure sets the output bandwidth of the high-speed cache to be consistent with the read speed of the optical computing chip; second, the present disclosure sets the high-speed write bandwidth to be higher than the output bandwidth of the sub-storage of the ping-pong storage. As a result, the optical computing chip of the present disclosure can continuously read the high-speed cache without being affected by the switching of the ping-pong storage cache.

[0153] In some embodiments of the present disclosure, the second cache 700 is a plurality of parallel cache arrays corresponding to the analog-to-digital converter array 100 .

[0154] In some embodiments of the present disclosure, the controller may further be configured to place the sub-signals of multiple consecutive timestamps from the same nanopore in the second cache in the same segment in a time series; or to sequentially enter the sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

[0155] In some embodiments of the present disclosure, each sub-signal carries the identifier of the nanopore ADC. Therefore, an algorithm can alternatively be used to store signals from the same nanopore ADC in a cache in adjacent order, or a reference pointer can be used to ensure that the sub-signals from the same ADC enter the optical computing chip in sequence.

[0156] In some embodiments of the present disclosure, it can be determined that the signals in the cache are from the same nanopore ADC by using the ADC identifier and the system time identifier.

[0157] In some embodiments of the present disclosure, the cache may also be an array controlled by a controller to ensure correspondence between adjacent nanopores.

[0158] In some embodiments of the present disclosure, a sub-signal with a signal identification identifier is directly written into a cache of a specific, matching optical computing element. The cache can be implemented as an on-chip or off-chip linear storage device such as SRAM, GDDR, HBM, or a storage device with a special structure customized through FPGA or ASIC.

[0159] In some embodiments of the present disclosure, the frequency at which each cached sub-signal is output to the DAC array on the optical computing chip is consistent with the computing operating frequency of the optical computing element (i.e., the minimum value of the maximum operating frequency of the DAC array, modulator array, optoelectronic matrix multiplication unit, and ADC array on the optical computing chip).

[0160] In some embodiments of the present disclosure, the output bandwidth (output frequency) of cached data is higher than the operating frequency of the optical computing chip to maximize the computing power of the optical computing chip. The frequency at which each cached sub-signal is output to the DAC array on the optical computing chip refers to the output bandwidth from the last cache.

[0161] In some embodiments of the present disclosure, due to the varying implementation principles of optical computing components across manufacturers, the computing frequency can be either variable in real time or fixed. When this frequency changes in real time, the speed at which the optical computing component reads the cache memory also changes in real time. Therefore, it is necessary to ensure that the output bandwidth (output frequency) of the cache data is higher than the computing frequency of the optical computing chip.

[0162] In some embodiments of the present disclosure, the cache may be a FIFO cache capable of storing multiple sub-signals simultaneously.

[0163] In the above embodiments of the present disclosure, cache segments can be set and sorted so that sub-signals with multiple consecutive timestamps from the same nanopore are placed in the same segment in a time series, or register linked list pointers can be used to ensure that the sub-signals can be output continuously.

[0164] The above embodiments of the present disclosure set up a ping-pong cache and a high-speed cache that matches the speed of the optical computing chip. The above embodiments of the present disclosure greatly improve the accuracy of the "identifying valid signals" and "identifying polymer units in valid signals" operations through the optimized cache structure.

[0165] Figure 6 is a schematic diagram of cache segmentation and sorting in some embodiments of the present disclosure. As shown in Figure 6, for ADC1, the sub-signal in the specific time period t0-t3 corresponds to nanopore A, while for ADC1, the sub-signal in the specific time period t4-t7 corresponds to nanopore B. Therefore, ADC1 + timestamp (t0-t1), ADC1 + timestamp (t1-t2), and ADC1 + timestamp (t2-t3) are three consecutive sub-signals from nanopore A. ADC1 + timestamp (t4-t5), ADC1 + timestamp (t5-t6), and ADC1 + timestamp (t6-t7) are three consecutive sub-signals from nanopore B. ADC3 + timestamp (t0-t1), ADC3 + timestamp (t1-t2), and ADC3 + timestamp (t2-t3) are three consecutive sub-signals from nanopore C. ADC2+timestamp (t0-t1), ADC2+timestamp (t1-t2), and ADC2+timestamp (t2-t3) are three continuous sub-signals from nanopore D.

[0166] In the above embodiments of the present disclosure, since the correspondence between the nanopore and the ADC is dynamically determined during the sequencing process based on the sequence passing through the pore, the system records the time when the correspondence switches, thereby enabling the signal in a specific time period to be associated with the nanopore signal.

[0167] In some embodiments of the present disclosure, the ADC identifier + timestamp is equivalent to the nanopore identifier.

[0168] In some embodiments of the present disclosure, for the case where "multiple nanopores correspond to one ADC", whether only the nanopore identifier (nanopore A or nanopore B) is added, and the ADC identifier does not need to be added, it can also ensure that the sub-signals of multiple consecutive timestamps of the same nanopore are placed in the same segment in a time series.

[0169] Figures 7a, 7b, 7c and 7d are schematic diagrams of sub-signals in some embodiments of the present disclosure. As shown in Figure 7a, the sub-signal may include a nanopore identifier, an ADC identifier, a timestamp and a sub-signal of length N.

[0170] In some other embodiments of the present disclosure, as shown in FIG7 b , the ADC identifier + timestamp may be equivalent to the nanopore identifier. Thus, the sub-signal may include the ADC identifier, the timestamp, and the sub-signal of length N.

[0171] As shown in Figures 7c and 7d, in addition to the timestamp and ADC identifier, the sub-signal entering the cache may also include the end data of the previous sub-signal of the same ADC (the sub-signal with the previous timestamp) or the beginning data of the next sub-signal, which is then sent to the linear cache. In the embodiment of Figure 7c, the sub-signal entering the cache includes the timestamp, ADC identifier, the end data (Nn) of the previous sub-signal of the same ADC, and the sub-signal with the current timestamp length n.

[0172] In the embodiment of FIG7d , the sub-signal entering the cache includes a timestamp, an ADC identifier, a sub-signal with a timestamp length of n, and data of the beginning (Nn) of the next sub-signal.

[0173] Therefore, there is a repeated signal between the sub-signals disclosed in the present invention, which can reduce signal validity segment errors and base recognition errors caused by sub-signal truncation.

[0174] FIG8 is a schematic diagram of further embodiments of the optical computing system disclosed herein. Compared to the embodiments of FIG4 and FIG5 , the optical computing system in the embodiment of FIG8 , in addition to including the analog-to-digital converter array 100, the nanopore array 300, the first buffer 400, the controller and output sequence signal buffer 500, the system controller 610, and the ADC array controller 620, may also include a first computing chip 210 and a second computing chip 220, wherein:

[0175] In some embodiments of the present disclosure, as shown in FIG8 , the optical computing chip 200 shown in any one of the embodiments of FIG1 to FIG5 may include a first computing chip 210 and a second computing chip 220 , wherein:

[0176] The first computing chip 210 is configured to determine whether the digital signal is a valid signal.

[0177] The second computing chip 220 is configured to identify the arrangement of polymer units in the polymer by identifying the effective signal.

[0178] In some embodiments of the present disclosure, the first computing chip 210 and the second computing chip 220 may be implemented as the specific structure of the optical computing chip 200 in the embodiment of FIG. 3 or FIG. 5 .

[0179] In some embodiments of the present disclosure, one of the first computing chip 210 and the second computing chip 220 (usually the first computing chip 210 ) can be replaced with a GPU chip.

[0180] The above-mentioned embodiment of the present disclosure can solve the problems of "identifying valid signals" and "identifying bases in valid signals" respectively by connecting the first computing chip 210 and the second computing chip 220 in series, thereby improving signal processing efficiency.

[0181] In some embodiments of the present disclosure, as shown in FIG8 , the optical computing system may further include a third cache 800 , wherein:

[0182] The third cache 800 is provided between the first computing chip and the second computing chip, and is configured to store the valid signal calculated by the first computing chip.

[0183] In some embodiments of the present disclosure, the first cache 400 may be a ping-pong cache; the second cache 700 and the third cache 800 may be high-speed caches.

[0184] In some embodiments of the present disclosure, the third buffer is a plurality of parallel buffer arrays corresponding to the analog-to-digital converter array.

[0185] In some embodiments of the present disclosure, the segmented cache can be changed to multiple parallel cache arrays corresponding to the ADC or nanopore.

[0186] In some embodiments of the present disclosure, the cache array may be arranged one-to-one, many-to-one, or one-to-many with the analog-to-digital converters in the ADC array 100 .

[0187] In some embodiments of the present disclosure, the controller is further configured to place sub-signals with multiple consecutive timestamps from the same nanopore in the third cache into the same segment in a time series; or to sequentially enter the sub-signals from the same nanopore in the third cache into the optical computing chip through a reference pointer.

[0188] In some embodiments of the present disclosure, sub-signals entering cache 800 include, in addition to a timestamp and ADC identifier, the end data of the previous sub-signal or the beginning data of the next sub-signal of the same ADC, and are then sent to the linear cache. This allows for a repeating signal between sub-signals, thereby reducing signal validity segment errors and base call errors caused by sub-signal truncation.

[0189] Based on the above-mentioned embodiments of the present disclosure (e.g., the embodiments of Figures 1-8 ), the nanopore used for DNA sequencing is replaced with a nanopore for detecting protein peptides, and corresponding adaptation is performed on the ADC so that it can generate a step-like current signal when the "DNA-peptide" conjugate passes through the nanopore. By loading the corresponding artificial neural network model and corresponding weight data on the optical computing chip, the current signal can be identified and the median current can be analyzed to retroactively confirm the information of the "DNA-peptide" segment sequence. The role of DNA is to achieve binding with the nanopore structure, thereby allowing single-stranded DNA to pass through the nanopore and guide the coupled peptide segment followed by the DNA through the nanopore.

[0190] In the above embodiments of the present disclosure, multiple optical computing chips are used in combination to detect effective signals and identify polymer units in effective signals, respectively.

[0191] The above-mentioned embodiment of the present disclosure separates the operations of “identifying a valid signal” and “identifying a polymer unit in a valid signal”, thereby greatly improving the efficiency of signal processing.

[0192] The above-mentioned embodiments of the present disclosure utilize cascaded optical computing chips to address both the "valid signal identification" and "base identification within valid signals," significantly improving signal processing efficiency. The algorithm used for "valid signal identification" is simple but requires a high degree of parallelism; the algorithm used for "base identification within valid signals" is typically more complex. The valid signal identification step in nanopore sequencing generally requires the simultaneous processing of digital signals generated by multiple nanopores and ADC units. Based on development trends, the number of nanopores in a single device could exceed 10,000.

[0193] The above-described embodiments of the present disclosure enrich valid signals through the "valid signal identification" step, enabling "base identification within valid signals" to operate more efficiently and improving overall system efficiency. This disclosure can increase the proportion of valid signals in the buffer, thereby freeing up computing resources, such as the optical computing coprocessor, to be used more for base identification within valid signals.

[0194] FIG9 is a schematic diagram of some embodiments of the optical computing method disclosed herein. Preferably, this embodiment can be performed by the optical computing system disclosed herein or the controller disclosed herein. The method may include at least one of steps 91 and 92, wherein:

[0195] In step 91 , the current generated when the polymer is translocated relative to the nanopore is converted into a digital signal by an analog-to-digital converter array.

[0196] Step 92: Control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

[0197] In some embodiments of the present disclosure, step 92 may include: controlling the optical computing chip to determine whether the digital signal is a valid signal, and identifying the arrangement of polymer units in the polymer by identifying the valid signal.

[0198] In some embodiments of the present disclosure, the optical computing method may further include: dividing the digital signal output by each analog-to-digital converter in the analog-to-digital converter array into multiple sub-signals, and adding a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier; controlling the first cache to store the sub-signal with the corresponding identifier added, and when a sub-cache in the first cache stores the sub-signal, switching the sub-cache and outputting the sub-signal in the sub-cache to the optical computing chip, wherein the first cache includes multiple sub-caches.

[0199] In some embodiments of the present disclosure, the optical computing method may further include: when the storage ratio of a sub-cache in the first cache is greater than a predetermined value, the remaining storage space is less than a preset value, or data of a preset size is written, switching the sub-cache and outputting the sub-signal in the sub-cache to the optical computing chip, that is, when a sub-cache is close to overflowing, switching the sub-cache and outputting the sub-signal in the sub-cache that is close to being full to the optical computing chip.

[0200] In some embodiments of the present disclosure, the optical computing method may further include: caching the sub-signals output by the first cache through a second cache and outputting them to the optical computing chip; and setting the bandwidth of each sub-signal output from the second cache to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

[0201] In some embodiments of the present disclosure, step 92 of the embodiment of Figure 9 may include: controlling the first computing chip to determine whether the digital signal is a valid signal; storing the valid signal calculated by the first computing chip through the third cache; and controlling the second computing chip to identify the arrangement of polymer units in the polymer by identifying the valid signal.

[0202] In some embodiments of the present disclosure, the optical computing method may further include: placing sub-signals with multiple consecutive timestamps from the same nanopore in the third buffer in the same segment in time series.

[0203] In some embodiments of the present disclosure, the optical computing method may further include: sequentially entering sub-signals from the same nanopore in the third cache into the optical computing chip by referencing a pointer.

[0204] In some embodiments of the present disclosure, the optical computing method may further include: placing sub-signals with multiple consecutive timestamps from the same nanopore in the second buffer in the same segment in time series.

[0205] In some embodiments of the present disclosure, the optical computing method may further include: sequentially entering sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

[0206] In some embodiments of the present disclosure, the optical computing method may further include: setting the sub-signal length in the first cache to be less than or equal to the sequence length configured to be processed by the optical computing chip; and setting the transmission bandwidth from the first cache to the optical computing chip to be equal to the computing speed of the optical computing chip.

[0207] In some embodiments of the present disclosure, the optical computing method may further include: when the length of the current sub-signal in the first cache is less than the sequence length configured and processed by the optical computing chip, using at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal to complete the current sub-signal, so that the length of the current sub-signal in the first cache is equal to the sequence length configured and processed by the optical computing chip.

[0208] FIG10 is a schematic diagram of some embodiments of the controller of the present disclosure. As shown in FIG10 , the controller of the present disclosure may include a first control module 101 and a second control module 102, wherein:

[0209] The first control module 101 is configured to convert the current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array.

[0210] In some embodiments of the present disclosure, the first control module 101 may be implemented as the ADC array controller 620 in the embodiments of FIG. 2 to FIG. 5 and FIG. 8 .

[0211] The second control module 102 is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

[0212] In some embodiments of the present disclosure, the second control module 102 is configured to control the optical computing chip to determine whether the digital signal is a valid signal, and identify the arrangement of polymer units in the polymer by identifying the valid signal.

[0213] In some embodiments of the present disclosure, the second control module 102 may be implemented as the system controller 610 and the optical computing chip controller 201 in the embodiments of FIG. 2 to FIG. 5 and FIG. 8 .

[0214] In some embodiments of the present disclosure, the controller may be configured to execute operations implementing the optical computing method described in any of the above embodiments (eg, the embodiment of FIG. 9 ).

[0215] FIG11 is a schematic diagram of the structure of another embodiment of the controller of the present disclosure. As shown in FIG11 , the controller includes a memory 111 and a processor 112 .

[0216] The memory 111 is used to store instructions. The processor 112 is coupled to the memory 111 . The processor 112 is configured to execute the optical computing method described in the above embodiment (eg, the embodiment of FIG. 9 ) based on the instructions stored in the memory.

[0217] As shown in Figure 11, the controller also includes a communication interface 113 for exchanging information with other devices. At the same time, the controller also includes a bus 114 through which the processor 112, the communication interface 113, and the memory 111 communicate with each other.

[0218] Memory 111 may include high-speed RAM memory or non-volatile memory, such as at least one disk storage device. Memory 111 may also be a memory array. Memory 111 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

[0219] Furthermore, the processor 112 may be a central processing unit (CPU), or may be an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present disclosure.

[0220] The controller described in FIG. 10 or FIG. 11 of the present disclosure may be implemented as the system controller 610 , the ADC array controller 620 , and the optical computing chip controller 201 of the embodiments of FIG. 2 to FIG. 5 and FIG. 8 .

[0221] The above-mentioned embodiments of the present disclosure apply an optical computing chip with computing power superior to that of a GPU to nanopore-based polymer sequencing, thereby optimizing the computing speed of the optical computing chip in "identifying valid signals" and "identifying polymer units in valid signals" when multiple nanopores generate data in parallel.

[0222] The above-mentioned embodiments of the present disclosure use a type of measurement system for estimating the target sequence of polymer units in a polymer using nanopores. This type of system has multiple nanopores and multiple ADC units. When the polymer is translocated relative to the nanopore, the current generated is converted into a digital signal through the ADC unit array.

[0223] The above-mentioned embodiments of the present disclosure process the signals generated by the nanohole array and the ADC array through an optical computing chip, determine whether the signal is a valid signal through the optical computing chip capable of accelerating matrix multiplication, and identify the arrangement of polymer units in the polymer.

[0224] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the optical computing method as described in any of the above embodiments (such as the embodiment of FIG. 9 ) is implemented.

[0225] In some embodiments of the present disclosure, the computer-readable storage medium may be a non-transitory computer-readable storage medium.

[0226] The above-mentioned embodiments of the present disclosure fully utilize the computing power of the optical computing chip by adding a ping-pong cache and a high-speed cache between the ADC array and the optical chip that can accelerate multiplication matrix operations, making the generation and calculation of digital signals more efficient and rapid.

[0227] In the above embodiments of the present disclosure, multiple optical computing chips are used in combination to detect effective signals and identify polymer units in effective signals, respectively.

[0228] The above-mentioned embodiment of the present disclosure separates the operations of “identifying a valid signal” and “identifying a polymer unit in a valid signal”, thereby greatly improving the efficiency of signal processing.

[0229] The above-mentioned embodiments of the present disclosure utilize cascaded optical computing chips to address the problems of "identifying valid signals" and "identifying bases within valid signals," respectively, significantly improving signal processing efficiency. The algorithm used for "identifying valid signals" is simple but requires a high degree of parallelism; the algorithm used for "identifying bases within valid signals" is typically more complex. The step of identifying valid signals in nanopore sequencing generally requires the simultaneous processing of digital signals generated by multiple nanopores and ADC units. Based on development trends, the number of nanopores in a single device could exceed 10,000.

[0230] The above-described embodiments of the present disclosure enrich valid signals through the "valid signal identification" step, enabling "base identification within valid signals" to operate more efficiently and improving overall system efficiency. This disclosure can increase the proportion of valid signals in the buffer, thereby freeing up computing resources, such as the optical computing coprocessor, to be used more for base identification within valid signals.

[0231] Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, apparatus, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable non-transient storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0232] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram and the combination of the processes and / or boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0233] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0234] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0235] The controller described above can be implemented as a general-purpose processor, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic devices, discrete hardware components or any appropriate combination thereof for performing the functions described in this application.

[0236] The present disclosure has been described in detail so far. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0237] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by instructing the relevant hardware through a program, and the program may be stored in a non-transitory computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0238] The description of the present disclosure is provided for purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the disclosed form. Many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present disclosure and to enable those skilled in the art to understand the present disclosure and design various embodiments with various modifications suitable for specific applications.

Claims

1. An optical computing system, comprising: an analog-to-digital converter array configured to convert a current generated when the polymer is translocated relative to the nanopore into a digital signal; An optical computing chip is configured to recognize the arrangement of polymer units in a polymer based on a digital signal.

2. The optical computing system of claim 1 , wherein: The optical computing chip is configured to determine whether the digital signal is a valid signal, and identify the arrangement of polymer units in the polymer by identifying the valid signal.

3. The optical computing system of claim 2 , further comprising: a controller configured to split a digital signal output by each analog-to-digital converter in the analog-to-digital converter array into a plurality of sub-signals, and add a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier; The first cache includes multiple sub-caches, is arranged between the analog-to-digital converter array and the optical computing chip, and is configured to store sub-signals with corresponding identifiers added; when a sub-cach in the first cache stores a sub-signal, the sub-cach is switched and the sub-signal in the sub-cach is output to the optical computing chip.

4. The optical computing system according to claim 3, further comprising: a second cache, disposed between the first cache and the optical computing chip, configured to cache the sub-signal output by the first cache and then output it to the optical computing chip; The controller is further configured to set the bandwidth of each sub-signal of the second cache output to the optical computing chip to be higher than the computing operating frequency of the optical computing chip.

5. The optical computing system according to claim 4, wherein: The optical computing chip includes: A first computing chip is configured to determine whether the digital signal is a valid signal; The second computing chip is configured to identify the arrangement of polymer units in the polymer by identifying the effective signal.

6. The optical computing system of claim 5 , further comprising: The third cache is provided between the first computing chip and the second computing chip, and is configured to store the valid signal calculated by the first computing chip.

7. The optical computing system of claim 6, wherein: The third cache is a plurality of parallel cache arrays corresponding to the analog-to-digital converter array; and / or, The controller is further configured to place the sub-signals of multiple consecutive timestamps from the same nanopore in the third buffer into the same segment in time series; or to sequentially enter the sub-signals from the same nanopore in the third buffer into the optical computing chip by referencing a pointer.

8. The optical computing system according to any one of claims 4 to 7, wherein: The second cache is a plurality of parallel cache arrays corresponding to the analog-to-digital converter array; and / or, The controller is further configured to place the sub-signals of multiple consecutive timestamps from the same nanopore in the second cache into the same segment in time series; or to sequentially enter the sub-signals from the same nanopore in the second cache into the optical computing chip by referencing a pointer.

9. The optical computing system according to any one of claims 3 to 7, wherein: The analog-to-digital converter array is an analog-to-digital converter array comprising a plurality of analog-to-digital converters; and / or, The length of the sub-signal in the first buffer is less than or equal to the length of the sequence that the optical computing chip is configured to process; and / or, The transmission bandwidth from the first cache to the optical computing chip is equal to the computing speed of the optical computing chip.

10. The optical computing system according to any one of claims 3 to 7, wherein: The controller is further configured to, when the length of the current sub-signal in the first cache is less than the sequence length configured to be processed by the optical computing chip, use at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal to complete the current sub-signal, so that the length of the current sub-signal in the first cache is equal to the sequence length configured to be processed by the optical computing chip.

11. The optical computing system according to any one of claims 1 to 7, wherein: The optical computing chip includes: a light source configured to output unmodulated light for computing; A first digital-to-analog conversion array is configured to receive external input data and convert the external input data into a first analog signal; a modulator array configured to form tensor data according to the light output by the light source and the first analog signal; a weight data cache configured to store weight data of the multiplication matrix; a second digital-to-analog conversion array, configured to convert the weight data into a second analog signal; The optoelectronic matrix multiplication module is configured to perform a matrix multiplication operation according to the tensor data and the second analog signal to realize optical path calculation.

12. A light computing method, comprising: The current generated when the polymer is translocated relative to the nanopore is converted into a digital signal by an analog-to-digital converter array; The control optical computing chip recognizes the arrangement of polymer units in the polymer based on digital signals.

13. The optical computing method according to claim 12, wherein: The controlling the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal comprises: The optical computing chip is controlled to determine whether the digital signal is a valid signal, and the arrangement of the polymer units in the polymer is identified by identifying the valid signal.

14. The optical computing method according to claim 13, further comprising: Splitting a digital signal output by each analog-to-digital converter in the analog-to-digital converter array into a plurality of sub-signals, and adding a corresponding identifier to each sub-signal, wherein the identifier includes a timestamp and an analog-to-digital converter identifier; The first cache is controlled to store the sub-signal with the corresponding identifier added thereto. When the storage ratio of a sub-cache in the first cache is greater than a predetermined value, the sub-cache is switched and the sub-signal in the sub-cache is output to the optical computing chip, wherein the first cache includes multiple sub-caches.

15. The optical computing system of claim 14, further comprising: After caching the sub-signal output by the first cache through the second cache, the sub-signal is output to the optical computing chip; The bandwidth of each sub-signal of the second buffer output to the optical computing chip is set to be higher than the computing operating frequency of the optical computing chip.

16. The optical computing method according to claim 15, wherein: The controlling optical computing chip determines whether the digital signal is a valid signal, and identifies the arrangement of polymer units in the polymer by identifying the valid signal, including: Controlling the first computing chip to determine whether the digital signal is a valid signal; Storing the valid signal calculated by the first computing chip through the third cache; The second computing chip is controlled to identify the arrangement of polymer units in the polymer by identifying the effective signal.

17. The optical computing method according to claim 16, further comprising: placing the sub-signals of a plurality of consecutive time stamps from the same nanopore in the third buffer into the same segment in time series; or, By referencing the pointer, the sub-signals from the same nanopore in the third cache are sequentially entered into the optical computing chip.

18. The optical computing method according to any one of claims 15 to 17, further comprising: placing the sub-signals of a plurality of consecutive time stamps from the same nanopore in the second buffer into the same segment in time series; or, By referencing the pointer, the sub-signals from the same nanopore in the second cache are sequentially entered into the optical computing chip.

19. The optical computing method according to any one of claims 14 to 17, further comprising: Setting the length of the sub-signals in the first buffer to be less than or equal to the length of the sequence that the optical computing chip is configured to process; The transmission bandwidth from the first cache to the optical computing chip is set to be equal to the computing speed of the optical computing chip.

20. The optical computing method according to any one of claims 14 to 17, further comprising: When the length of the current sub-signal in the first cache is less than the sequence length configured for processing by the optical computing chip, at least one of the end data of the previous sub-signal and the beginning data of the next sub-signal is used to padded the current sub-signal, so that the length of the current sub-signal in the first cache is equal to the sequence length configured for processing by the optical computing chip.

21. A controller comprising: a first control module, configured to convert a current generated when the polymer is translocated relative to the nanopore into a digital signal through an analog-to-digital converter array; The second control module is used to control the optical computing chip to identify the arrangement of polymer units in the polymer according to the digital signal.

22. A controller comprising: a memory for storing instructions; The processor is configured to execute the instructions so that the controller performs operations to implement the optical computing method according to any one of claims 12 to 20.

23. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the optical computing method according to any one of claims 12 to 20 is implemented.

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