Display device

Abstract

A display device is provided. According to one embodiment, a display device includes at least: a bank layer defining a light emitting area in which a light emitting device is disposed; a first electrode and a second electrode disposed in the light emitting region to be spaced apart from each other with a light emitting device therebetween; and an electrode pattern layer disposed on the bank layer, the light emitting device, the first electrode, and the second electrode. The electrode pattern layer may include: a mesh pattern portion that does not overlap the light emitting region and surrounds an edge of the light emitting region; and a slit pattern portion overlapping the light emitting region.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of multimedia technology, display devices have become increasingly important. Therefore, various types of display devices are currently used, such as organic light-emitting display (OLED) devices and liquid crystal display (LCD) devices.

[0003] The display device includes a display panel for displaying an image, such as an organic light-emitting display panel and a liquid crystal display panel. Among them, the light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) may include an organic light-emitting diode (OLED) using an organic material as a fluorescent material and an inorganic light-emitting diode using an inorganic material as a fluorescent material.

[0004] An inorganic light emitting diode using an inorganic semiconductor as a fluorescent material has advantages in that it has durability under a high temperature environment and it has higher blue light efficiency than an organic light emitting diode. Summary of the invention

[0005] Technical issues

[0006] The disclosed aspects provide a display device having improved light emitting efficiency of pixels.

[0007] The disclosed aspects also provide a display device that can prevent damage to elements due to static electricity.

[0008] It should be noted that the objects of the disclosure are not limited to the above objects; and other objects of the disclosure will be clear to those skilled in the art from the following description.

[0009] Technical Solution

[0010] According to a disclosed embodiment, a display device includes: a dam layer, which defines an emission area, and a light-emitting element is arranged in the emission area; a first electrode and a second electrode, which are spaced apart from each other in the emission area, and the light-emitting element is placed between the first electrode and the second electrode; and an electrode pattern layer, which is arranged above the dam layer, the light-emitting element, the first electrode and the second electrode, wherein the electrode pattern layer includes: a grid pattern, which does not overlap with the emission area and surrounds the edge of the emission area; and a slit pattern, which overlaps with the emission area.

[0011] According to a disclosed embodiment, a display device includes: a substrate; a first electrode, arranged on the substrate to receive a first power supply voltage; a second electrode, spaced apart from the first electrode on the substrate to receive a second power supply voltage, the second power supply voltage having a level lower than the first power supply voltage; a light-emitting element arranged in a space between the first electrode and the second electrode; a covering layer, arranged above the first electrode, the second electrode and the light-emitting element; and a ground electrode, arranged on the covering layer, wherein the ground electrode is electrically connected to the second electrode.

[0012] According to an embodiment, a display device includes: a substrate; a dam layer, which is arranged on the substrate to define an emission area, and a light-emitting element is arranged in the emission area; a first electrode and a second electrode, which are arranged on the substrate and are spaced apart from each other in the emission area, and the light-emitting element is placed between the first electrode and the second electrode; a covering layer, which is arranged above the dam layer, the first electrode, the second electrode and the light-emitting element; and a plurality of scattering members, which are arranged on the covering layer so that the plurality of scattering members are spaced apart from each other, wherein at least one of the plurality of scattering members overlaps with the light-emitting element.

[0013] Beneficial Effects

[0014] According to the disclosed embodiments, the light emitting efficiency of pixels in a display device may be improved.

[0015] According to the disclosed embodiments, elements in a display device can be prevented from being damaged due to static electricity.

[0016] The effects according to the embodiments are not limited to the contents exemplified above, and more various effects are included in this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a plan view showing a display device according to a disclosed embodiment.

[0018] Figure 2 is a plan view schematically illustrating a film member, a display panel, and a chassis member included in a display device according to an embodiment.

[0019] Figure 3 is schematically shown along Figure 2 A cross-sectional view of a section taken along line X1-X1'.

[0020] Figure 4 is a circuit diagram of a pixel of a display device according to a disclosed embodiment.

[0021] Figure 5 is a plan view schematically showing a light emitting element, an alignment electrode, and a connection electrode of a display device according to a disclosed embodiment.

[0022] Figure 6is a view showing a structure of a light emitting element of a display device according to a disclosed embodiment.

[0023] Figure 7 is a plan view showing an electrode pattern layer of a display device according to a disclosed embodiment.

[0024] Figure 8 is a plan view schematically showing a wavelength control region of a display device according to a disclosed embodiment.

[0025] Fig. 9 is schematically shown along Figure 5 , Figure 6 and Figure 8 A cross-sectional view of a section taken along line X2-X2'.

[0026] Fig.10 is schematically shown along Figure 5 and Figure 8 A cross-sectional view of a section taken along line X3-X3'.

[0027] Fig.11 is schematically shown along Figure 5 and Figure 8 A cross-sectional view of the section taken along line X4-X4'.

[0028] Fig.12 and Fig.13 is a view for illustrating a path through which static electricity is released through an electrode pattern layer of a display device according to an embodiment.

[0029] Fig.14 is a plan view showing an electrode pattern layer of a display device according to another disclosed embodiment.

[0030] Fig.15 is a plan view showing an electrode pattern layer of a display device according to yet another disclosed embodiment.

[0031] Fig.16 is a plan view schematically showing a light emitting element, an alignment electrode, and a connection electrode of a display device according to still another disclosed embodiment.

[0032] Fig.17 It shows that according to Fig.16 A plan view of an electrode pattern layer of a display device of an embodiment. DETAILED DESCRIPTION

[0033] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0034] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0035] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0036] Each of the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and various interlocks and drives are technically feasible. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0037] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0038] Figure 1 is a plan view showing a display device according to a disclosed embodiment.

[0039] exist Figure 1 In the figure, a first direction DR1, a second direction DR2, and a third direction DR3 are defined. The first direction DR1 and the second direction DR2 are perpendicular to each other, the first direction DR1 and the third direction DR3 are perpendicular to each other, and the second direction DR2 and the third direction DR3 may be perpendicular to each other. The first direction DR1 may refer to the horizontal direction in the drawings, the second direction DR2 may refer to the vertical direction in the drawings, and the third direction DR3 may refer to the up and down direction (i.e., the thickness direction in the drawings). As used herein, unless otherwise specifically stated, a direction may refer to a direction indicated by an arrow as well as an opposite direction. If it is necessary to distinguish the two opposite directions, one of the two directions may be referred to as "one side in the direction" and the other direction may be referred to as "the opposite side in the direction". In the figure, Figure 1 , a side indicated by an arrow in one direction is referred to as a side in the one direction, and an opposite side is referred to as an opposite side in the one direction.

[0040] In the following description of the surface of the display device 1 or an element of the display device 1, for ease of explanation, the surface facing the side of the display image (i.e., the third direction DR3) will be referred to as the upper surface, and the opposite surface will be referred to as the lower surface. However, it should be understood that the disclosure is not limited to this. The surface and the opposite surface of the element may be referred to as the front surface and the rear surface, respectively, or may be referred to as the first surface and the second surface, respectively. In addition, in the description of the relative position of the elements of the display device 1, the side on the second direction DR2 may be referred to as the upper side, and the opposite side on the second direction DR2 may be referred to as the lower side.

[0041] Reference Figure 1 , the display device 1 displays a moving image or a still image. The display device 1 may refer to any electronic device that provides a display screen. For example, the display device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a portable video camera, etc.

[0042] The display device 1 includes a display panel 300 (see Figure 2 ). Examples of the display panel 300 may include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. In the following description, an inorganic light emitting diode display panel is used as an example of the display panel 300, but the disclosure is not limited thereto. Any other display panel may be used as long as the disclosed technical concept can be equally applied.

[0043] The shape of the display device 1 may be modified in various ways. For example, the display device 1 may have a shape such as a rectangle with longer lateral sides, a rectangle with longer vertical sides, a square, a quadrilateral with rounded corners (vertices), other polygons, a circle, etc. The shape of the display area DA of the display device 1 may also be similar to the overall shape of the display device 1. Figure 1 In the example shown in , the display device 1 has a rectangular shape having longer sides in the first direction DR1 .

[0044] The display device 1 may include a display area DA and a non-display area NDA. In the display area DA, an image may be displayed. In the non-display area NDA, no image is displayed. The display area DA may be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the display device 1. However, it should be understood that the disclosure is not limited thereto.

[0045] The non-display area NDA may be disposed around the display area DA. In other words, the non-display area NDA may surround the edge of the display area DA. In some embodiments, the display area DA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DA. However, it should be understood that the disclosure is not limited thereto. The non-display area NDA may form a frame of the display device 1. A line or circuit driver included in the display device 1 may be disposed in each of the non-display areas NDA, or an external device may be installed in each of the non-display areas NDA.

[0046] The display area DA and the non-display area NDA of the display device 1 may also be applied to elements included in the display device 1. Hereinafter, the elements included in the display device 1 will be described.

[0047] Figure 2 is a plan view schematically illustrating a film member, a display panel, and a chassis member included in a display device according to an embodiment. Figure 3 is schematically shown along Figure 2 A cross-sectional view of a section taken along line X1-X1'.

[0048] Reference Figure 2 and Figure 3 , the display device 1 may include a film member 100, a display panel 300, and a chassis member 500. The display device 1 may be constructed by stacking the chassis member 500, the display panel 300, and the film member 100 in this order in the third direction DR3. For ease of explanation, the film member 100, the display panel 300, and the chassis member 500 will be described in this order.

[0049] The film member 100 may protect the display device 1 from the outside. The film member 100 may be disposed at the top of the display device 1 to protect the display panel 300 disposed under the film member 100. In other words, the film member 100 may be attached to the upper surface of the display panel 300 by the sealing member 700 disposed between the film member 100 and the display panel 300.

[0050] The area of ​​the film member 100 may be greater than that of the display panel 300, and may be greater than that of the chassis member 500. In other words, the film member 100 may completely cover the display panel 300 and the chassis member 500, and may extend beyond the display panel 300 and the chassis member 500. The structure of the film member 100 will be described later.

[0051] The display panel 300 may display an image thereon. The display panel 300 may define a display area DA of the display device 1. The display area DA of the display panel 300 may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form. When viewed from the top, the shape of each of the pixels PX may be a rectangle or a square, but is not limited thereto. For example, the shape of each of the pixels PX may have a rhombus shape having sides inclined relative to one direction.

[0052] Each of the pixels PX may include a plurality of emission regions, each of which emits light of a specific wavelength band. For example, the pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Figure 2 In the example shown in FIG. 1 , a single pixel PX includes three sub-pixels SPXn, but the disclosure is not limited thereto. The pixel PX may include more than three sub-pixels SPXn.

[0053] The first subpixel SPX1 may emit light of a first color, the second subpixel SPX2 may emit light of a second color, and the third subpixel SPX3 may emit light of a third color. For example, the light of the first color may be red light having a peak wavelength in the range of 610nm to 650nm, the light of the second color may be green light having a peak wavelength in the range of 510nm to 550nm, and the light of the third color may be blue light having a peak wavelength in the range of 440nm to 480nm. However, it should be understood that the disclosure is not limited thereto.

[0054] The display panel 300 may include a substrate SUB and a circuit element layer CCL disposed on the substrate SUB. The structure of the display panel 300 will be described in detail later.

[0055] The chassis member 500 may support the bottom of the display panel 300 to improve mechanical strength. The chassis member 500 may be disposed on the bottom of the display panel 300. The chassis member 500 may include a material having rigidity to ensure mechanical strength, for example, a metal such as SUS304 and aluminum.

[0056] A flexible printed circuit board COF may be provided at one side of the display panel 300 to supply a driving signal to the pixel PX of the display panel 300. More than one flexible printed circuit board COF may be provided so that they are spaced apart from each other. The flexible printed circuit board COF may be electrically connected to the pixel PX through the circuit element layer CCL of the display panel 300.

[0057] As used herein, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In addition, such an element may be understood as a single integral element with one portion connected to another portion. In addition, when an element is referred to as being "connected" to another element, it may be in direct contact with the other element and also electrically connected to the other element.

[0058] The flexible printed circuit board COF may extend from one side of the display panel 300 to the chassis member 500, and may be attached to the bottom of the chassis member 500. Figure 3 As shown in FIG. 1 , a flexible printed circuit board COF may be disposed at an end of a substrate SUB of a display panel 300 and bent toward a chassis member 500 to be attached to a bottom of the chassis member.

[0059] The driving chip DC generating the driving signal may be mounted on the flexible printed circuit board COF. For example, the driving chip DC may be electrically connected to the first voltage line VL1 (see Fig.10 ) and the second voltage line VL2 (see Fig.10 ). In some embodiments, the driving chip DC may be disposed on one surface of the flexible printed circuit board COF to face the outside of the display device 1, but the disclosure is not limited thereto.

[0060] The resin RF may be interposed between the flexible printed circuit board COF and the side surface of the substrate SUB of the display panel 300. The resin RF may compensate for the level difference between the display panel 300 and the chassis member 500 in the second direction DR2, so that it may relieve stress that may be applied to the flexible printed circuit board COF due to bending of the flexible printed circuit board COF.

[0061] Hereinafter, a pixel driving circuit of a pixel PX of a display device according to an embodiment will be described.

[0062] Figure 4 is a circuit diagram of a pixel of a display device according to a disclosed embodiment.

[0063] Reference Figure 4, each of the pixels PX or sub-pixels SPXn of the display device 1 includes a pixel driving circuit, where n is an integer from 1 to 3. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors of each pixel driving circuit may be changed in various ways. According to the disclosed embodiment, each of the sub-pixels SPXn of the display device 1 may have a 3T1C structure (i.e., the pixel driving circuit includes three transistors and one capacitor). In the following description, a pixel driving circuit with a 3T1C structure will be described as an example. However, it should be understood that the disclosure is not limited thereto. Various modified structures may be adopted, such as a 2T1C structure, a 7T1C structure, and a 6T1C structure.

[0064] Each of the sub-pixels SPXn of the display device 1 according to the embodiment includes three transistors T1 , T2 , and T3 and one storage capacitor Cst in addition to the light emitting diode EL.

[0065] The light emitting diode EL emits light proportional to the current supplied by the first transistor T1. The light emitting diode EL includes a first electrode, a second electrode, and at least one light emitting element disposed between the first electrode and the second electrode. The light emitting element can emit light in a specific wavelength range by an electrical signal transmitted from the first electrode and the second electrode.

[0066] A first end of the light emitting diode EL can be connected to the source electrode of the first transistor T1, and a second end of the light emitting diode EL can be connected to a second voltage line VL2, from which a low-level voltage (hereinafter referred to as a second power supply voltage) lower than a high-level voltage of the first voltage line VL1 (hereinafter referred to as a first power supply voltage) is applied.

[0067] The first transistor T1 adjusts the current flowing from the first voltage line VL1 to the light emitting diode EL according to the voltage difference between the gate electrode and the source electrode, and the first power supply voltage is supplied from the first voltage line VL1. For example, the first transistor T1 can be a driving transistor for driving the light emitting diode EL. The gate electrode of the first transistor T1 can be connected to the source electrode of the second transistor T2, the source electrode of the first transistor T1 can be connected to the first electrode of the light emitting diode EL, and the drain electrode of the first transistor T1 can be connected to the first voltage line VL1 to which the first power supply voltage is applied.

[0068] The second transistor T2 is turned on by the scan signal of the scan line SL to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the scan line SL, the source electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1, and the drain electrode of the second transistor T2 can be connected to the data line DTL.

[0069] The third transistor T3 can be turned on by the scan signal of the scan line SL to connect the initialization voltage line VIL to one end of the light emitting diode EL. The gate electrode of the third transistor T3 can be connected to the scan line SL, the drain electrode of the third transistor T3 can be connected to the initialization voltage line VIL, and the source electrode of the third transistor T3 can be connected to one end of the light emitting diode EL or the source electrode of the first transistor T1.

[0070] The source electrode and the drain electrode of each of the transistors T1, T2 and T3 are not limited to those described above. They may be connected in the opposite manner. Each of the transistors T1, T2 and T3 may be formed as a thin film transistor. Figure 3 In the example shown in , although each of the transistors T1, T2 and T3 is implemented as an n-type MOSFET (metal oxide semiconductor field effect transistor), the disclosure is not limited thereto. That is, each of the transistors T1, T2 and T3 may be implemented as a p-type MOSFET, or some of the transistors T1, T2 and T3 may be implemented as n-type MOSFETs, while the other transistors may be implemented as p-type MOSFETs.

[0071] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst stores a voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0072] According to the disclosed embodiment, the gate electrode of the second transistor T2 may be connected to the scan line SL, and the gate electrode of the third transistor T3 may be connected to the scan line SL. In other words, the second transistor T2 and the third transistor T3 may be turned on by a scan signal applied from the same scan line. However, it should be understood that the disclosure is not limited thereto. The second transistor T2 and the third transistor T3 may be connected to different scan lines and may be turned on in response to scan signals applied from different scan lines.

[0073] Hereinafter, the structure of the pixel PX of the display device 1 according to the disclosed embodiment will be described.

[0074] Figure 5 is a plan view schematically showing a light emitting element, an alignment electrode, and a connection electrode of a display device according to a disclosed embodiment. Figure 6 is a view showing a structure of a light emitting element of a display device according to a disclosed embodiment. Figure 7 is a plan view showing an electrode pattern layer of a display device according to a disclosed embodiment. Figure 8 is a plan view schematically showing a wavelength control region of a display device according to a disclosed embodiment.

[0075] exist Figures 5 to 8Although the emission area EMA or the wavelength control areas LA1, LA2, and LA3 of each sub-pixel SPXn have the same area, the disclosure is not limited thereto. In some embodiments, the emission area EMA or the wavelength control areas LA1, LA2, and LA3 of each sub-pixel SPXn may have different areas.

[0076] Reference Figures 5 to 7 , each sub-pixel SPXn of the pixel PX of the display device 1 according to the embodiment may include an emission area EMA and a non-emission area. In the emission area EMA, a light-emitting element ED is provided to emit light of a specific wavelength band. In the non-emission area, no light-emitting element ED is provided, and light emitted from the light-emitting element ED does not reach the non-emission area, so no light is emitted from the non-emission area.

[0077] The emission area EMA of the sub-pixel SPXn may include an area in which the light emitting element ED is disposed, and may include an area adjacent to the light emitting element ED where light emitted from the light emitting element ED exits. For example, the emission area EMA may also include an area in which the light emitted from the light emitting element ED is reflected or refracted by other elements to exit. A plurality of light emitting elements ED may be respectively disposed in the pixel PX, and the emission area EMA may include an area in which the light emitting element is disposed and an adjacent area.

[0078] Each of the sub-pixels SPXn may further include a sub-region SA disposed in a non-emission region. The sub-region SA of each sub-pixel SPXn may be disposed on both sides of the emission region EMA in the second direction DR2. The emission region EMA and the sub-region SA may be alternately arranged in the second direction DR2, and each sub-region SA may be disposed between emission regions EMA of different pixels PX spaced apart from each other in the second direction DR2. For example, the emission region EMA and the sub-region SA may be alternately arranged in the second direction DR2, and the emission region EMA may be repeatedly arranged in the first direction DR1, and the sub-region SA may also be so. However, it should be understood that the disclosure is not limited thereto.

[0079] No light emitting element ED is provided in the sub-region SA, so no light is emitted from the sub-region SA. The alignment electrode RME provided in the sub-pixel SPXn may be partially provided in the sub-region SA. The alignment electrodes RME provided in different sub-pixels SPXn may be provided separately from each other at the separation region ROP of the sub-region SA.

[0080] The display device 1 may include a plurality of alignment electrodes RME ( RME1 and RME2 ), bank patterns BP1 and BP2 , a bank layer BNL, a light emitting element ED, and connection electrodes CNE ( CNE1 and CNE2 ).

[0081] When viewed from the top, the bank layer BNL may be disposed on the entire surface of the display area DA in a grid pattern (the grid pattern includes portions extending in the first direction DR1 and the second direction DR2). For example, the bank layer BNL may surround each of the sub-pixels SPXn. The bank layer BNL may surround each of the plurality of sub-pixels SPXn and may define an emission area EMA and a sub-region SA. The distances between the sub-pixels SPXn, the emission area EMA, and the sub-region SA may vary according to the width of the bank layer BNL.

[0082] The bank patterns BP1 and BP2 may be disposed in the emission area EMA of each sub-pixel SPXn. Each of the bank patterns may have a shape having a constant width in the first direction DR1 and extending in the second direction DR2.

[0083] For example, the dam pattern may include a first dam pattern BP1 and a second dam pattern BP2 spaced apart from each other in the first direction DR1 in the emission area EMA of each of the sub-pixels SPXn. The first dam pattern BP1 may be disposed at opposite sides of the center of the emission area EMA in the first direction DR1, and the second dam pattern BP2 may be disposed at one side of the center of the emission area EMA in the first direction DR1. The first dam pattern BP1 and the second dam pattern BP2 may be alternately arranged along the first direction DR1, and may be disposed in the display area DA in an island pattern. A plurality of light emitting elements ED may be disposed between the first dam pattern BP1 and the second dam pattern BP2 spaced apart from each other.

[0084] The width of the first embankment pattern BP1 in the first direction DR1 may be equal to the width of the second embankment pattern BP2 in the first direction DR1. However, it should be understood that the disclosure is not limited thereto. The width of the first embankment pattern BP1 in the second direction DR2 and the width of the second embankment pattern BP2 in the second direction DR2 are equal to each other and may be smaller than the width of the emission area EMA surrounded by the embankment layer BNL in the second direction DR2. In some embodiments, the first embankment pattern BP1 and the second embankment pattern BP2 may be spaced apart from a portion of the embankment layer BNL extending in the first direction DR1. However, it should be understood that the disclosure is not limited thereto.

[0085] The alignment electrodes RME (RME1 and RME2) have a shape extending in one direction and are disposed in each of the subpixels SPXn. A plurality of alignment electrodes RME may extend in the second direction DR2 to be disposed in the emission area EMA and the subarea SA of the subpixel SPXn, and they may be spaced apart from each other in the first direction DR1.

[0086] The alignment electrode RME may include a first alignment electrode RME1 and a second alignment electrode RME2. The first alignment electrode RME1 may be disposed at opposite sides of the center of the emission area EMA in the first direction DR1, and the second alignment electrode RME2 may be disposed at one side of the center of the emission area EMA in the first direction DR1. The first alignment electrode RME1 may be disposed on the first embankment pattern BP1, and the second alignment electrode RME2 may be disposed on the second embankment pattern BP2. The first alignment electrode RME1 and the second alignment electrode RME2 may extend beyond the embankment layer BNL and may be partially disposed in the emission area EMA and the sub-area SA of the sub-pixel SPXn. The first alignment electrode RME1 and the second alignment electrode RME2 of the sub-pixel SPXn may be spaced apart from the first alignment electrode RME1 and the second alignment electrode RME2 of the other sub-pixel SPXn at a separation area ROP positioned in the sub-area SA of one of the sub-pixels SPXn.

[0087] The first alignment electrode RME1 may be electrically connected to the circuit element layer CCL through the first electrode contact hole CTD (see Fig.10 ), the second alignment electrode RME2 can be electrically connected to the circuit element layer CCL through the second electrode contact hole CTS (see Fig.10 ).

[0088] exist Figure 5 In the embodiment, although two alignment electrodes RME are provided in each of the sub-pixels SPXn and have a shape extending in the second direction DR2, the disclosure is not limited thereto. For example, more than two alignment electrodes RME may be provided in a single sub-pixel SPXn of the display device 1, or the alignment electrode RME may be partially bent and may have a width that varies depending on a position.

[0089] A plurality of light emitting elements ED may be disposed in the emission area EMA. In other words, a plurality of light emitting elements ED may be disposed in a space between a first embankment pattern BP1 and a second embankment pattern BP2 disposed in the emission area EMA of one sub-pixel SPXn, and may be arranged so that they are spaced apart from each other in the second direction DR2. According to the disclosed embodiment, a plurality of light emitting elements ED may have a shape extending in one direction, and both ends of the light emitting elements ED may be respectively disposed on different alignment electrodes RME. The width of the light emitting element ED in the first direction DR1 may be greater than the width of the space between the first alignment electrode RME1 and the second alignment electrode RME2 in the first direction DR1. The light emitting elements ED may be arranged so that the direction in which they extend is substantially perpendicular to the second direction DR2 along which the alignment electrode RME extends. However, it should be understood that the disclosure is not limited thereto. For example, the light emitting element ED may extend in the first direction DR1 or in a direction inclined relative to the first direction DR1.

[0090] The light emitting element ED may be a light emitting diode. Specifically, the light emitting element ED may have a size from nanometers to micrometers, and may be an inorganic light emitting diode composed of an inorganic material. Since polarity is generated by forming an electric field in a specific direction between two electrodes, the light emitting element ED may be aligned between two electrodes facing each other.

[0091] The light emitting element ED according to the embodiment may have a shape extending in one direction. In some embodiments, the light emitting element ED may have a shape of a cylinder, a rod, a wire, a tube, etc., but is not limited thereto.

[0092] The light emitting element ED may include a semiconductor layer doped with a dopant of a conductive type (eg, p-type or n-type), and may emit light of a specific wavelength band by transmitting an electrical signal applied from an external power source.

[0093] like Figure 6 As shown in , the light emitting element ED may include a first semiconductor layer 31 , a second semiconductor layer 32 , an emission layer 36 , an electrode layer 37 , and an insulating film 38 .

[0094] The first semiconductor layer 31 of the light emitting element ED may be an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor material having the following chemical formula: Al x Ga y In 1-x-y N(0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer 31 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped into the first semiconductor layer 31 may be Si, Ge, Sn, or the like.

[0095] The second semiconductor layer 32 of the light emitting element ED is disposed above the first semiconductor layer 31, and the emission layer 36 is between the second semiconductor layer 32 and the first semiconductor layer 31. The second semiconductor layer 32 may be a p-type semiconductor and may include a semiconductor material having the following chemical formula: Al x Ga y In 1-x-y N(0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 32 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped into the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, or the like.

[0096] In the drawings, although each of the first semiconductor layer 31 and the second semiconductor layer 32 is implemented as a signal layer, the disclosure is not limited thereto. Depending on the material of the emission layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include a greater number of layers, for example, a cap layer or a tensile strain barrier lowering (TSBR) layer.

[0097] The emission layer 36 of the light emitting element ED is disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The emission layer 36 may include a material having a single quantum well structure or a multiple quantum well structure. When the emission layer 36 includes a material having a multiple quantum well structure, the structure may include quantum layers and well layers stacked alternately with each other. The emission layer 36 may emit light when electron-hole pairs are combined therein in response to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. The emission layer 36 may include materials such as AlGaN, AlGaInN, and InGaN. In particular, when the emission layer 36 has a multiple quantum well structure in which quantum layers and well layers are stacked alternately with each other, the quantum layers may include AlGaN or AlGaInN, and the well layers may include materials such as GaN and AlGaN.

[0098] The emission layer 36 may have a structure in which semiconductor materials having large band gap energy and semiconductor materials having small band gap energy are alternately stacked with each other, and may include other group III to group V semiconductor materials according to the wavelength range of the emitted light. The light emitted by the emission layer 36 may be blue light having a peak wavelength in the blue band (i.e., in the range of 440nm to 480nm).

[0099] The electrode layer 37 of the light emitting element ED may be an ohmic connection electrode. However, it should be understood that the disclosure is not limited thereto. The electrode layer 37 may be a Schottky connection electrode. The light emitting element ED may include at least one electrode layer 37. The light emitting element ED may include one or more electrode layers 37. However, it should be understood that the disclosure is not limited thereto. The electrode layer 37 may be removed.

[0100] The electrode layer 37 can reduce the resistance between the light emitting element ED and the electrode or the connecting electrode when the light emitting element ED is electrically connected to the electrode or the connecting electrode in the display device 1. The electrode layer 37 may include a metal or a metal oxide having conductivity. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0101] The insulating film 38 of the light emitting element ED can protect the semiconductor layer and the electrode layer of the light emitting element ED. If the insulating film 38 is in direct contact with the electrode through which the electrical signal is transmitted to the light emitting element ED, an electrical short circuit that may occur in the emission layer 36 can be prevented. In addition, the insulating film 38 can prevent a decrease in light emitting efficiency.

[0102] The insulating film 38 is provided to surround the outer surfaces of the above-mentioned plurality of semiconductor layers and electrode layers. For example, the insulating film 38 may be provided to surround at least the outer surface of the emission layer 36, and both ends of the light emitting element ED in the longitudinal direction are exposed. In addition, a portion of the upper surface of the insulating film 38 may be rounded in cross section, and the portion is adjacent to at least one of the ends of the light emitting element ED.

[0103] The insulating film 38 may include a material having insulating properties, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ). In the drawings, although the insulating film 38 is formed as a single layer, the disclosure is not limited thereto. In some embodiments, the insulating film 38 may be composed of a multilayer structure in which a plurality of layers are stacked on each other.

[0104] Return to reference Figure 5 , a plurality of connection electrodes CNE may be disposed on the plurality of alignment electrodes RME and the bank pattern. The plurality of connection electrodes CNE may each have a shape extending in one direction and may be spaced apart from each other. Each of the connection electrodes CNE may contact the light emitting element ED and may be electrically connected to the alignment electrode RME or the circuit element layer CCL thereunder (see Fig.10 ).

[0105] The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed in each sub-pixel SPXn.

[0106] The first connection electrode CNE1 may have a shape extending in the second direction DR2 and may be disposed on the first alignment electrode RME1 or the first bank pattern BP1. The first connection electrode CNE1 may partially overlap the first alignment electrode RME1 and may be disposed from the emission area EMA to the sub area SA beyond the bank layer BNL.

[0107] The second connection electrode CNE2 may have a shape extending in the second direction DR2 and may be disposed on the second alignment electrode RME2 or the second bank pattern BP2. The second connection electrode CNE2 may partially overlap the second alignment electrode RME2 and may be disposed from the emission area EMA to the sub area SA beyond the bank layer BNL.

[0108] The first link electrode CNE1 may be electrically connected to the first alignment electrode RME1 through the first contact CT1 , and the second link electrode CNE2 may be electrically connected to the second alignment electrode RME2 through the second contact CT2 .

[0109] Reference Figure 7 The electrode pattern layer 200 may be disposed on the bank layer BNL. The electrode pattern layer 200 may include a mesh pattern 210 surrounding an edge of the emission area EMA and / or the sub-area SA of each sub-pixel SPXn, a slit pattern 230 forming a slit SL in the emission area EMA, and a ground contact 250 overlapping the second electrode contact hole CTS.

[0110] The mesh pattern 210 of the electrode pattern layer 200 may provide a path for discharging static electricity that may be generated in the display panel 300. The mesh pattern 210 may not overlap the emission area EMA of each subpixel SPXn in the third direction DR3, and may overlap the bank layer BNL in the third direction DR3.

[0111] The mesh pattern 210 may include a first ground portion 210a extending in a first direction DR1 and a second ground portion 210b extending in a second direction DR2. The first ground portion 210a and the second ground portion 210b may be parts of the mesh pattern 210. The first ground portion 210a may refer to a portion of the mesh pattern 210 extending in the first direction DR1, and the second ground portion 210b may refer to a portion of the mesh pattern 210 extending in the second direction DR2. The first ground portion 210a and the second ground portion 210b may be integrally formed at their intersection. In other words, the first ground portion 210a and the second ground portion 210b may share an intersection as part of the mesh pattern 210.

[0112] The first ground portion 210a may extend in the second direction DR to cross two edges of each sub-pixel SPXn in the first direction DR1. The first ground portion 210a may cross two edges of a plurality of sub-pixels SPXn arranged in the second direction DR2 in the first direction DR1 (see FIG. Fig.12 ).

[0113] The second ground portion 210b may extend in the first direction DR1 to cross opposite edges of the emission area EMA of each sub-pixel SPXn in the second direction DR2 and one edge of the sub-area SA in the second direction DR2. The second ground portion 210b may cross opposite edges of the emission area EMA of the sub-pixels SPXn repeatedly arranged in the first direction DR1 and one edge of the sub-area SA in the second direction DR2 (see FIG. Fig.12 ).

[0114] The slit pattern 230 and the ground contact 250 may be disposed in each of regions defined by the first and second ground portions 210a and 210b of the mesh pattern 210 (ie, in each of regions surrounding edges of the emission area EMA and / or the sub-areas SA adjacent thereto).

[0115] The slit pattern 230 of the electrode pattern layer 200 may be disposed to overlap the emission area EMA of each sub-pixel SPXn in the third direction DR3 to scatter light output from the light emitting element ED. The slit pattern 230 may include a first scattering member 230a extending in the first direction DR1 and a second scattering member 230b extending in the second direction DR2.

[0116] The first scattering members 230a of the slit pattern 230 may be disposed adjacent to both ends of the emission area EMA in the second direction DR2. For example, two first scattering members 230a may be disposed at one end and an opposite end of the emission area EMA in the second direction DR2 of each sub-pixel SPXn. However, it should be understood that the disclosure is not limited thereto. For ease of explanation, the first scattering member 230a disposed at one side of the emission area EMA in the second direction DR2 will be referred to as an upper first scattering member, and the first scattering member 230a disposed at the opposite side of the emission area EMA in the second direction DR2 will be referred to as a lower first scattering member.

[0117] The plurality of second scattering members 230b of the slit pattern 230 may be arranged along the first direction DR1 between the upper first scattering member and the lower first scattering member. In other words, the plurality of second scattering members 230b may overlap the emission area EMA in the third direction DR3, and may be spaced apart from each other in the first direction DR1. The opposite side of each of the plurality of second scattering members 230b in the second direction DR2 may contact the upper first scattering member, and one side of each of the plurality of second scattering members 230b in the second direction DR2 may contact the lower first scattering member.

[0118] The spaces between the plurality of second scattering members 230b may be defined as slits SL. Therefore, the slits SL may extend in the second direction DR2 by following the shape of the second scattering members 230b. In other words, the extending direction of the slits SL may intersect with the extending direction of the light emitting elements ED (ie, the first direction DR1).

[0119] The plurality of second scattering members 230b arranged on the emission area EMA in which the light emitting element ED is disposed may scatter the light output from the light emitting element ED. In some embodiments, the length of each of the plurality of second scattering members 230b in the second direction DR2 may be at least greater than the length of the space in which the light emitting element ED is disposed in the second direction DR2. In some embodiments, at least one of the plurality of second scattering members 230b may overlap with the light emitting element ED in the third direction DR3 to effectively scatter the light output from the light emitting element ED. However, it should be understood that the disclosure is not limited thereto.

[0120] The ground contact 250 of the electrode pattern layer 200 can be electrically connected to the driving chip DC so that the static electricity flowing through the mesh pattern 210 can be discharged. The ground contact 250 is a portion of the mesh pattern 210 protruding from the mesh pattern 210 and electrically connected to the mesh pattern 210. The ground contact 250 can overlap with the second electrode contact hole CTS in the third direction DR3. For example, the ground contact 250 can protrude from the opposite side of the second ground portion 210b in the first direction DR1 to extend in the first direction DR1, so that the ground contact 250 crosses between the side of the emission area EMA in the second direction DR2 and the opposite side of the sub-area SA on the side of the emission area in the second direction DR2, and may not extend to the adjacent second ground portion 210b. However, it should be understood that the disclosure is not limited thereto. It should be noted that the first ground portion 210a, the second ground portion 210b and the ground contact 250 of the mesh pattern 210 can be described as a ground electrode in the claims.

[0121] The ground contact 250 may be electrically connected to the second alignment electrode RME2 through the second electrode contact hole CTS. The second alignment electrode RME2 may be electrically connected to the second alignment electrode RME2 through the second electrode contact hole CTS. Fig.10 The second voltage line VL2 of the circuit element layer CCL shown in FIG. 1 may be electrically connected to the driving chip DC mounted on the flexible printed circuit board COF as described above, and thus the ground contact 250 may be electrically connected to the driving chip DC.

[0122] The mesh pattern 210, the slit pattern 230 and the ground contact 250 may be integrally formed via a single process. Therefore, the mesh pattern 210, the slit pattern 230 and the ground contact 250 may include the same material. In some embodiments, the mesh pattern 210, the slit pattern 230 and the ground contact 250 may include a transparent conductive oxide (TCO) such as ITO, IZO and ITZO. Therefore, the electrode pattern layer 200 may be prevented from being degraded due to subsequent processes performed after the electrode pattern layer 200 has been formed during the process of manufacturing the display device 1 according to the embodiment, and the light output from the light emitting element ED may be scattered by the slit pattern 230, and the light output from the light emitting element ED may be prevented from being absorbed or reflected. In this way, the luminous efficiency of the pixel PX may be improved.

[0123] Reference Figure 8 , the wavelength control regions LA1 , LA2 , and LA3 and the light blocking regions BA surrounding the wavelength control regions LA1 , LA2 , and LA3 may be disposed on the electrode pattern layer 200 .

[0124] The wavelength control region may include a first wavelength control region LA1, a second wavelength control region LA2, and a third wavelength control region LA3. The first wavelength control region LA1 may convert the wavelength of light output from the light emitting element ED into red light having a peak wavelength in the range of 610nm to 650nm, the second wavelength control region LA2 may convert the wavelength of light output from the light emitting element ED into green light having a peak wavelength in the range of 510nm to 550nm, and the third wavelength control region LA3 may transmit the wavelength of light output from the light emitting element ED as is.

[0125] Each of the wavelength control areas LA1, LA2, and LA3 may overlap with the emission area EMA of each sub-pixel SPXn. For example, the first wavelength control area LA1 may overlap with the emission area EMA of the first sub-pixel SPX1 in the third direction DR3, the second wavelength control area LA2 may overlap with the emission area EMA of the second sub-pixel SPX2 in the third direction DR3, and the third wavelength control area LA3 may overlap with the emission area EMA of the third sub-pixel SPX3 in the third direction DR3.

[0126] The light blocking region BA may overlap the bank layer BNL and may block light output from the light emitting element ED from being recognized from the outside.

[0127] Hereinafter, a stack structure of the display device 1 according to the embodiment will be described.

[0128] Fig. 9 is schematically shown along Figure 5 , Figure 6 and Figure 8A cross-sectional view of a section taken along line X2-X2'. Fig.10 is schematically shown along Figure 5 and Figure 8 A cross-sectional view of a section taken along line X3-X3'. Fig.11 is schematically shown along Figure 5 and Figure 8 A cross-sectional view of the section taken along line X4-X4'. Fig.12 and Fig.13 is a view for illustrating a path through which static electricity is discharged through the electrode pattern layer of the display device according to the embodiment.

[0129] Reference Figures 9 to 13 The display panel 300 may include a substrate SUB, a circuit element layer CCL, a via insulating layer VIA, embankment patterns BP1 and BP2, a first passivation layer PAS1, a plurality of alignment electrodes RME, a embankment layer BNL, a second passivation layer PAS2, a light emitting element ED, a plurality of connection electrodes CNE, a third passivation layer PAS3, a fourth passivation layer PAS4, a first cover layer CPL1, an electrode pattern layer 200, an upper embankment layer UBN, color control structures WCL1, WCL2 and TPL, a second cover layer CPL2, a low refractive layer LRL, a second cover layer CPL2, a first overcoat layer OC1, a color filter layer CFL and a second overcoat layer OC2.

[0130] The substrate SUB may be used as a base of the display panel 300. The substrate SUB may be made of an insulating material such as glass, quartz, and polymer resin. In addition, the substrate SUB may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. The bottom of the substrate SUB may be the bottom of the display panel 300.

[0131] The circuit element layer CCL may be disposed on the substrate SUB. In the circuit element layer CCL, various lines for transmitting electrical signals to the light emitting elements disposed on the substrate SUB may be disposed. Fig.10 and Fig.11 As shown in , the circuit element layer CCL includes a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, etc. as a plurality of conductive layers, and may include a buffer layer BL, a first gate insulating layer GI, a first interlayer dielectric layer IL1 and a first passivation layer PV1 as a plurality of insulating layers.

[0132] The first conductive layer may be disposed on the substrate SUB. The first conductive layer includes a bottom metal layer BML. The bottom metal layer BML is disposed with the first active layer ACT1 of the first transistor T1. The bottom metal layer BML may prevent light from being incident on the first active layer ACT1 of the first transistor, or may be electrically connected to the first active layer ACT1 to stabilize the electrical characteristics of the first transistor T1. However, it should be noted that the bottom metal layer BML may be removed.

[0133] The buffer layer BL may be disposed on the bottom metal layer BML and the substrate SUB. The buffer layer BL may be formed on the substrate SUB to protect the transistor of the pixel PX from moisture permeating through the substrate SUB susceptible to moisture permeation and may also provide a flat surface.

[0134] The semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include a first active layer ACT1 of the first transistor T1 and a second active layer ACT2 of the second transistor T2. The first active layer ACT1 and the second active layer ACT2 may be disposed to partially overlap first and second gate electrodes G1 and G2 of a second conductive layer to be described later, respectively.

[0135] The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, an oxide semiconductor, etc. In other embodiments, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be one or more oxide semiconductors selected from GIZO, zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), or a combination thereof. For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), etc.

[0136] exist Fig.11 In the embodiment, although the first transistor T1 and the second transistor T2 are provided in the sub-pixel SPXn of the display device 1 , the disclosure is not limited thereto. A greater number of transistors may be included in the display device 1 .

[0137] The first gate insulating layer GI is disposed on the semiconductor layer in the display area DA. The first gate insulating layer GI can be used as a gate insulating film of the transistors T1 and T2. In the example shown in the accompanying drawings, the first gate insulating layer GI is patterned together with the gate electrodes G1 and G2 of the second conductive layer to be described later, and is partially disposed between the second conductive layer and the active layers ACT1 and ACT2 of the semiconductor layer. However, it should be understood that the disclosure is not limited thereto. In some embodiments, the first gate insulating layer GI can be completely disposed on the buffer layer BL.

[0138] The second conductive layer is disposed on the first gate insulating layer GI. The second conductive layer may include a first gate electrode G1 of the first transistor T1 and a second gate electrode G2 of the second transistor T2. The first gate electrode G1 may overlap with the channel region of the first active layer ACT1 in the third direction DR3 as the thickness direction. The second gate electrode G2 may overlap with the channel region of the second active layer ACT2 in the third direction DR3 as the thickness direction.

[0139] The first interlayer dielectric layer IL1 is disposed on the second conductive layer. The first interlayer dielectric layer IL1 may serve as an insulating film between the second conductive layer and other layers disposed on the second conductive layer, and may protect the second conductive layer.

[0140] The third conductive layer is disposed on the first interlayer dielectric layer IL1. The third conductive layer may include first and second voltage lines VL1 and VL2, a first conductive pattern CDP1, and source and drain electrodes S1 and S2 and D1 and D2 of transistors T1 and T2 disposed in the display area DA.

[0141] A high level voltage (or a first power supply voltage) may be applied to the first voltage line VL1 to be transmitted to the first alignment electrode RME1, and a low level voltage (or a second power supply voltage) may be applied to the second voltage line VL2 to be transmitted to the second alignment electrode RME2. A portion of the first voltage line VL1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer dielectric layer IL1. The first voltage line VL1 may serve as a first drain electrode D1 of the first transistor T1. The second voltage line VL2 may be directly connected to a second alignment electrode RME2 to be described later.

[0142] The first conductive pattern CDP1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer dielectric layer IL1. The first conductive pattern CDP1 may contact the bottom metal layer BML through another contact hole penetrating the first interlayer dielectric layer IL1 and the buffer layer BL. The first conductive pattern CDP1 may serve as a first source electrode S1 of the first transistor T1. In addition, the first conductive pattern CDP1 may be connected to a first alignment electrode RME1 or a first connection electrode CNE1 to be described later. The first transistor T1 may transmit a first power supply voltage applied from a first voltage line VL1 to the first alignment electrode RME1 or the first connection electrode CNE1.

[0143] Each of the second source electrode S2 and the second drain electrode D2 may make contact with the second active layer ACT2 of the second transistor T2 through a contact hole penetrating the first interlayer dielectric layer IL1 .

[0144] The first passivation layer PV1 is disposed on the third conductive layer. The first passivation layer PV1 may serve as an insulating film between the third conductive layer and other layers, and may protect the third conductive layer.

[0145] The buffer layer BL, the first gate insulating layer GI, the first interlayer dielectric layer IL1, and the first passivation layer PV1 may be composed of a plurality of inorganic layers alternately stacked on each other. For example, the buffer layer BL, the first gate insulating layer GI, the first interlayer dielectric layer IL1, and the first passivation layer PV1 may be composed of a plurality of inorganic layers alternately stacked on each other. x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) are stacked on each other or a multilayer in which they are alternately stacked on each other.

[0146] The via insulating layer VIA may be disposed on the circuit element layer CCL. Specifically, the via insulating layer VIA may be disposed on the first passivation layer PV1 of the circuit element layer CCL. The via insulating layer VIA may include an organic insulating material (e.g., an organic insulating material such as polyimide (PI)) to provide a flat surface over various lines having different heights in the circuit element layer CCL. It should be noted that in some embodiments, the via insulating layer VIA may be removed.

[0147] A plurality of dam patterns BP1 and BP2 may be disposed on the via insulating layer VIA. For example, the dam patterns BP1 and BP2 may be directly disposed on the via insulating layer VIA, and may have a structure protruding at least partially from the upper surface of the via insulating layer VIA. The protruding portions of the dam patterns BP1 and BP2 may have an inclined side surface or a curved side surface having a predetermined curvature. Light emitted from the light emitting element ED may be reflected by the alignment electrode RME disposed on the dam patterns BP1 and BP2, so that the light may be emitted toward the upper side of the via insulating layer VIA. The dam patterns BP1 and BP2 may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0148] A plurality of alignment electrodes RME (RME1 and RME2) may be disposed on the embankment patterns BP1 and BP2 and the via insulating layer VIA. For example, the first alignment electrode RME1 and the second alignment electrode RME2 may be disposed at least on the inclined side surfaces of the embankment patterns BP1 and BP2. The width of the plurality of alignment electrodes RME measured in the second direction DR2 may be smaller than the width of the embankment patterns BP1 and BP2 measured in the second direction DR2. The distance between the first alignment electrode RME1 and the second alignment electrode RME2 spaced apart from each other in the second direction DR2 may be smaller than the distance between the embankment patterns BP1 and BP2. At least a portion of the first alignment electrode RME1 and the second alignment electrode RME2 may be disposed directly on the via insulating layer VIA so that they may be disposed on the same plane.

[0149] The light emitting element ED disposed between the bank patterns BP1 and BP2 may emit light through both ends. The emitted light may be guided to the alignment electrode RME disposed on the bank patterns BP1 and BP2.

[0150] A portion of each of the alignment electrodes RME disposed on the bank patterns BP1 and BP2 may reflect light emitted from the light emitting element ED. The first and second alignment electrodes RME1 and RME2 may be disposed to cover side surfaces of the bank patterns BP1 and BP2 at least on one side to reflect light emitted from the light emitting element ED.

[0151] Each of the alignment electrodes RME may be in direct contact with the third conductive layer through electrode contact holes CTD and CTS at a position where it overlaps the bank layer BNL. The first electrode contact hole CTD may be formed at a position where the bank layer BNL and the first alignment electrode RME1 overlap each other. The second electrode contact hole CTS may be formed at a position where the bank layer BNL and the second alignment electrode RME2 overlap each other. The first alignment electrode RME1 may be in contact with the first conductive pattern CDP1 through the first electrode contact hole CTD penetrating the via insulating layer VIA and the first passivation layer PV1. The second alignment electrode RME2 may be in contact with the second voltage line VL2 through the second electrode contact hole CTS penetrating the via insulating layer VIA and the first passivation layer PV1. The first alignment electrode RME1 may be electrically connected to the first transistor T1 through the first conductive pattern CDP1 to receive the first power supply voltage. The second alignment electrode RME2 may be electrically connected to the second voltage line VL2 to receive the second power supply voltage. However, it should be understood that the disclosure is not limited thereto. According to another embodiment, each of the alignment electrodes RME1 and RME2 may not be electrically connected to the voltage lines VL1 and VL2 of the third conductive layer, and a connection electrode CNE to be described later may be directly connected to the third conductive layer.

[0152] Each of the alignment electrodes RME may include a conductive material having a high reflectivity. For example, the alignment electrode RME may include a metal such as silver (Ag), copper (Cu) and aluminum (Al), or may include an alloy containing aluminum (Al), nickel (Ni) or lanthanum (La), etc., or a stack of a metal layer such as titanium (Ti), molybdenum (Mo) and niobium (Nb) and the alloy. In some embodiments, the alignment electrode RME may be composed of a double layer or multiple layers in which an alloy containing aluminum (Al) and at least one metal layer composed of titanium (Ti), molybdenum (Mo) and niobium (Nb) are stacked on each other.

[0153] However, it should be understood that the disclosure is not limited thereto. The alignment electrode RME may also include a transparent conductive material. For example, each of the alignment electrodes RME may include materials such as ITO, IZO, and ITZO. In some embodiments, each of the alignment electrodes RME1 and RME2 may have a structure in which one or more layers of a transparent conductive material and one or more metal layers having a high reflectivity are stacked on each other, or may be composed of a single layer including them. For example, each of the alignment electrodes RME may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The alignment electrode RME may be electrically connected to the light emitting element ED, and may reflect some of the light emitted from the light emitting element ED toward the upper side of the substrate SUB.

[0154] The first passivation layer PAS1 may be disposed on the front surface of the display area DA, and may be disposed on the via insulating layer VIA and the plurality of alignment electrodes RME. The first passivation layer PAS1 may include an insulating material, and may protect the plurality of alignment electrodes RME, and may insulate different alignment electrodes RME from each other. Since the first passivation layer PAS1 is disposed to cover the alignment electrodes RME before forming the embankment layer BNL, the alignment electrodes RME may be prevented from being damaged during the process of forming the embankment layer BNL. In addition, the first passivation layer PAS1 may also prevent the light emitting element ED disposed thereon from contacting other elements and being damaged.

[0155] In an embodiment, the first passivation layer PAS1 may have a step such that a portion of the upper surface is recessed between the alignment electrodes RME spaced apart from each other in the second direction DR2. The light emitting element ED may be disposed at the step of the upper surface of the first passivation layer PAS1, and a space may be formed between the light emitting element ED and the first passivation layer PAS1.

[0156] like Fig.10 As shown in , the first passivation layer PAS1 may include contacts CT1 and CT2. The contacts may be positioned so that they overlap with different alignment electrodes RME, respectively. For example, the contacts may include a first contact CT1 overlapping with the first alignment electrode RME1 and a second contact CT2 overlapping with the second alignment electrode RME2. The first contact CT1 and the second contact CT2 may penetrate the first passivation layer PAS1 to expose a portion of the upper surface of the first alignment electrode RME1 or the second alignment electrode RME2 disposed thereunder. Each of the first contact CT1 and the second contact CT2 may also penetrate some of the other insulating layers disposed on the first passivation layer PAS1. The alignment electrode RME exposed by the contacts may contact the connection electrode CNE.

[0157] The bank layer BNL may be disposed on the first passivation layer PAS1. In some embodiments, the bank layer BNL may overlap with the first electrode contact hole CTD or the second electrode contact hole CTS in the third direction DR3, but the disclosure is not limited thereto. For example, the bank layer BNL may not overlap with the first electrode contact hole CTD or the second electrode contact hole CTS in the third direction DR3.

[0158] The light emitting element ED may be electrically connected to the alignment electrode RME and the conductive layer under the via insulating layer VIA by contacting the connection electrodes CNE ( CNE1 and CNE2 ), and an electrical signal may be applied to the light emitting element ED so that light of a specific wavelength range may be emitted.

[0159] The bank layer BNL may have a predetermined height similar to the bank patterns BP1 and BP2. In some embodiments, the top surface of the bank layer BNL may have a height higher than that of the top surfaces of the bank patterns BP1 and BP2, and the thickness of the bank layer BNL may be equal to or greater than the thickness of the bank patterns BP1 and BP2. The bank layer BNL may prevent ink from overflowing into adjacent sub-pixels SPXn during an inkjet printing process of a process for manufacturing the display device 1. Similar to the bank patterns BP1 and BP2, the bank layer BNL may include an organic insulating material such as polyimide.

[0160] The second passivation layer PAS2 may be disposed on the light emitting element ED, the first passivation layer PAS1, and the embankment layer BNL. The second passivation layer PAS2 may extend along the first direction DR1 between the embankment patterns BP1 and BP2, and may include a pattern portion disposed on a plurality of light emitting elements ED. The pattern portion may be disposed to partially surround the outer surface of the light emitting element ED, and may not cover both sides or both ends of the light emitting element ED. When viewed from the top, the pattern portion may form a linear pattern or an island pattern in each sub-pixel SPXn. The pattern portion of the second passivation layer PAS2 may protect the light emitting element ED, and may fix the light emitting element ED during the process of manufacturing the display device 1. In addition, the second passivation layer PAS2 may be disposed to fill the space between the light emitting element ED and the first passivation layer PAS1 thereunder. In addition, a portion of the second passivation layer PAS2 may be disposed on the embankment layer BNL.

[0161] The second passivation layer PAS2 may include contacts CT1 and CT2. For example, the second passivation layer PAS2 may include a first contact CT1 overlapping the first alignment electrode RME1 and a second contact CT2 overlapping the second alignment electrode RME2. In addition to the first passivation layer PAS1, the contact may penetrate the second passivation layer PAS2. Each of the first contact CT1 and the second contact CT2 may expose a portion of the upper surface of the first alignment electrode RME1 or the second alignment electrode RME2 thereunder.

[0162] The third passivation layer PAS3 is disposed on the second passivation layer PAS2. The third passivation layer PAS3 may be completely disposed on the second passivation layer PAS2 to cover the second connection electrode CNE2, and one of the two ends of the light emitting element ED may be exposed. As will be described later, the second connection electrode CNE2 of the connection electrodes CNE may contact one first end of the light emitting element ED that is not exposed by the third passivation layer PAS3, and the first connection electrode CNE1 may contact the other end of the light emitting element ED that is exposed by the third passivation layer PAS3. The third passivation layer PAS3 may insulate the first connection electrode CNE1 and the second connection electrode CNE2 from each other so that they do not directly contact each other.

[0163] The third passivation layer PAS3 may include first contacts CT1. The first contacts CT1 may penetrate the third passivation layer PAS3 in addition to the first passivation layer PAS1 and the second passivation layer PAS2. The plurality of first contacts CT1 may expose a portion of the upper surface of the first alignment electrode RME1 thereunder.

[0164] A plurality of connection electrodes CNE (CNE1 and CNE2) may be disposed so that they at least partially overlap with a plurality of alignment electrodes RME and the bank patterns BP1 and BP2 in the third direction DR3. The first connection electrode CNE1 may be disposed so as to overlap with the first alignment electrode RME1 and the first bank pattern BP1 in the third direction DR3. The first connection electrode CNE1 may at least partially overlap with the first alignment electrode RME1 and may extend from the emission area EMA beyond the bank layer BNL. The second connection electrode CNE2 may be disposed so as to overlap with the second alignment electrode RME2 and the second bank pattern BP2 in the third direction DR3. The second connection electrode CNE2 may at least partially overlap with the second alignment electrode RME2 and may extend from the emission area EMA beyond the bank layer BNL.

[0165] The first connection electrode CNE1 may be disposed on the third passivation layer PAS3, and the second connection electrode CNE2 may be disposed on the second passivation layer PAS2 to contact the light emitting element ED. For example, the first connection electrode CNE1 may partially overlap the first alignment electrode RME1 and may contact one end (hereinafter, referred to as the "first end") of the light emitting element ED, and the second connection electrode CNE2 may partially overlap the second alignment electrode RME2 and may contact the other end (hereinafter, referred to as the "second end") of the light emitting element ED.

[0166] The connection electrode CNE may be in contact with the light emitting element ED and may be electrically connected to the third conductive layer. For example, in the display device 1, the connection electrode CNE may be in contact with the alignment electrode RME through the contacts CT1 and CT2. The first connection electrode CNE1 may be in contact with the first alignment electrode RME1 through the first contact CT1 penetrating the first passivation layer PAS1, the second passivation layer PAS2, and the third passivation layer PAS3. The second connection electrode CNE2 may be in contact with the second alignment electrode RME2 through the second contact CT2 penetrating the first passivation layer PAS1 and the second passivation layer PAS2. The connection electrode CNE may be electrically connected to the third conductive layer through the corresponding alignment electrode RME. The first connection electrode CNE1 may be electrically connected to the first transistor T1 to be applied with a first power supply voltage, and the second connection electrode CNE2 may be electrically connected to the second voltage line VL2 to be applied with a second power supply voltage. Therefore, the first connection electrode CNE1 may be in contact with the first end of the light emitting element ED to apply the first power supply voltage to the first end of the light emitting element ED, and the second connection electrode CNE2 may be in contact with the second end of the light emitting element ED to apply the second power supply voltage to the second end of the light emitting element ED.

[0167] The connection electrode CNE may include a conductive material. For example, the connection electrode CNE may include ITO, IZO, ITZO, aluminum (Al), etc. For example, the connection electrode CNE may include a transparent conductive material, and light emitted from the light emitting element ED may be transmitted through the connection electrode CNE to be emitted.

[0168] The fourth passivation layer PAS4 may be disposed on the third passivation layer PAS3, the connection electrodes CNE1 and CNE2, and the bank layer BNL. The fourth passivation layer PAS4 may protect layers disposed on the substrate SUB. It should be noted that the fourth passivation layer PAS4 may be removed.

[0169] Each of the first passivation layer PAS1, the second passivation layer PAS2, the third passivation layer PAS3, and the fourth passivation layer PAS4 may include an inorganic insulating material or an organic insulating material. According to the disclosed embodiment, each of the first passivation layer PAS1, the second passivation layer PAS2, the third passivation layer PAS3, and the fourth passivation layer PAS4 may be made of silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiO x N y ). The first passivation layer PAS1, the second passivation layer PAS2, the third passivation layer PAS3 and the fourth passivation layer PAS4 may be made of the same material. Alternatively, some of them may be made of the same material, while others may be made of different materials, or they may be made of materials different from each other.

[0170] The first cover layer CPL1 may be disposed on the fourth passivation layer PAS4. The first cover layer CPL1 may prevent the light output from the light emitting element ED from degrading the color control structures TPL, WCL1, and WCL2 to be described later. Generally, the intensity of the light output from the light emitting element ED is greater the closer to the light emitting element ED. Therefore, by increasing the distance between the light emitting element ED and the color control structures TPL, WCL1, and WCL2, the light output from the light emitting element ED may be prevented from degrading the color control structures TPL, WCL1, and WCL2 to be described later.

[0171] In other words, if the color control structures TPL, WCL1, and WCL2 are directly disposed on the light emitting element ED, the intensity of light output from the light emitting element ED is relatively strong, and thus the color control structures TPL, WCL1, and WCL2 may be degraded. In view of the above, the first cover layer CPL1 is disposed between the light emitting element ED and the color control structures TPL, WCL1, and WCL2, so that the intensity of light reaching the color control structures TPL, WCL1, and WCL2 can be reduced.

[0172] The first cover layer CPL1 may include an inorganic insulating material or an organic insulating material. In addition, the first cover layer CPL1 may provide a flat surface over the light emitting element ED, the bank patterns BP1 and BP2, and the bank layer BNL having different heights.

[0173] The electrode pattern layer 200 may be disposed on the first cover layer CPL1 and may include a mesh pattern 210 forming a discharge path of static electricity, a slit pattern 230 for scattering light output from the light emitting element ED, and a ground contact 250 connected to the second voltage line VL2 through a second electrode contact hole CTS.

[0174] As described above, the mesh pattern 210 may overlap the bank layer BNL in the third direction DR3 and may not overlap the emission area EMA in the third direction DR3. In addition, the slit pattern 230 may overlap the emission area EMA in the third direction DR3.

[0175] Since at least a portion of the slit pattern 230 overlaps the light emitting element ED in the third direction DR3, light output from the light emitting element ED is scattered by the slit pattern 230 and can reach the color control structures TPL, WCL1, and WCL2 disposed on the electrode pattern layer 200. Therefore, light output from the light emitting element ED can be prevented from damaging the color control structures TPL, WCL1, and WCL2, and the light emitting efficiency of the pixel PX can be improved.

[0176] The ground contact 250 may protrude from a portion of the mesh pattern 210. The ground contact 250 may contact and be electrically connected to a portion of the second alignment electrode RME2 exposed through the second electrode contact hole CTS that penetrates the first cover layer CPL1, the fourth passivation layer PAS4, the third passivation layer PAS3, the second passivation layer PAS2, the bank layer BNL, and the first passivation layer PAS1. Therefore, since the mesh pattern 210 is electrically connected to the ground contact 250 and the ground contact 250 is electrically connected to the second voltage line VL2, static electricity that may be generated in the display area DA may be discharged to the second voltage line VL2 through the mesh pattern 210 and the ground contact 250.

[0177] Specifically, Fig.12 and Fig.13 As shown in , static electricity generated near one subpixel SPXn may pass through the second voltage line VL2 via the contact 250 along the mesh pattern 210 surrounding the edge of one subpixel SPXn, and may be released to the driving chip DC through the flexible printed circuit board COF via the second voltage line VL2.

[0178] With the above configuration, the electrode pattern layer 200 may scatter light output from the light emitting element ED to prevent degradation of the color control structures TPL, WCL1, and WCL2, and may discharge static electricity that may be generated in the display panel 300 to the outside.

[0179] Incidentally, the wavelength control areas LA1, LA2, and LA3 may be disposed on the first cover layer CPL1 and the electrode pattern layer 200. For example, an upper bank layer UBN, color control structures TPL, WCL1, and WCL2, color patterns CP1, CP2, and CP3, and color filter layers CFL1, CFL2, and CFL3 may be disposed on the first cover layer CPL1 and the electrode pattern layer 200. A plurality of cover layers CPL2 and CPL3, a low refractive layer LRL, and a first outer coating layer OC1 may be disposed between the color control structures TPL, WCL1, and WCL2 and the color filter layers CFL1, CFL2, and CFL3, and a second outer coating layer OC2 may be disposed on the color filter layers CFL1, CFL2, and CFL3.

[0180] The upper bank layer UBN may be disposed on the fourth passivation layer PAS4 to overlap with the bank layer BNL. When viewed from the top, the upper bank layer UBN may be disposed in a grid pattern including portions extending in the first direction DR1 and the second direction DR2. The upper bank layer UBN may surround the emission region or a portion where the light emitting element ED is disposed. The upper bank layer UBN may define a space in which the color control structures TPL, WCL1, and WCL2 are disposed.

[0181] The color control structures TPL, WCL1 and WCL2 may be disposed on the fourth passivation layer PAS4 so that they are surrounded by the upper bank layer UBN. The color control structures TPL, WCL1 and WCL2 may be disposed in the wavelength control areas LA1, LA2 and LA3 surrounded by the upper bank layer UBN to form an island pattern in the display area DA. However, it should be understood that the disclosure is not limited thereto. The color control structures TPL, WCL1 and WCL2 may extend in one direction and be disposed across a plurality of sub-pixels SPXn to form a linear pattern.

[0182] In an embodiment in which the light emitting element ED of each of the sub-pixels PXn emits blue light of a third color, the color control structures TPL, WCL1 and WCL2 may include a first wavelength conversion layer WCL1 arranged in the first sub-pixel SPX1 in accordance with the first wavelength control area LA1, a second wavelength conversion layer WCL2 arranged in the second sub-pixel SPX2 in accordance with the second wavelength control area LA2, and a transparent layer TPL arranged in the third sub-pixel SPX3 in accordance with the third wavelength control area LA3.

[0183] The first wavelength conversion layer WCL1 may include a first matrix resin BRS1 and first wavelength conversion particles WCP1 dispersed in the first matrix resin BRS1. The second wavelength conversion layer WCL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2 dispersed in the second matrix resin BRS2. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 convert and transmit the wavelength of the blue light of the third color incident from the light emitting element ED. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 may also include scattering particles SCP included in their respective matrix resins, and the scattering particles SCP may increase the wavelength conversion efficiency.

[0184] The transparent layer TPL may include a third matrix resin BRS3 and scattering particles SCP dispersed in the third matrix resin BSR3. The transparent layer TPL transmits the wavelength of the blue light of the third color incident from the light emitting element ED as it is. The scattering particles SCP of the transparent layer TPL may adjust the emission path of the outgoing light passing through the transparent layer TPL. The transparent layer TPL may not include a wavelength conversion material.

[0185] The scattering particles SCP may be metal oxide particles or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2) etc. Examples of the material of the organic particles may include acrylic resin, urethane resin, etc.

[0186] The first to third base resins BRS1, BRS2, ​​and BRS3 may include a transparent organic material. For example, the first to third base resins BRS1, BRS2, ​​and BRS3 may include epoxy resin, acrylic resin, cardo resin, or imide resin, etc. The first to third base resins BRS1, BRS2, ​​and BRS3 may be made of the same material, but are not limited thereto.

[0187] The first wavelength conversion particle WCP1 can convert the blue light of the third color into the red light of the first color, and the second wavelength conversion particle WCP2 can convert the blue light of the third color into the green light of the second color. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 can be quantum dots, quantum rods, phosphors, etc. The quantum dots can include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or a combination thereof.

[0188] In some embodiments, the color control structures TPL, WCL1 and WCL2 may be formed via an inkjet printing process or a photoresist process. After the material forming the color control structures TPL, WCL1 and WCL2 is sprayed or applied in the space surrounded by the upper bank layer UBN, the color control structures TPL, WCL1 and WCL2 may be formed via a drying or exposure and development process. For example, in an embodiment in which the color control structures TPL, WCL1 and WCL2 are formed via an inkjet printing process, the upper surface of each layer of the color control structures TPL, WCL1 and WCL2 is formed to be curved so that its edge adjacent to the upper bank layer UBN in the drawings may be higher than its center. However, it should be understood that the disclosure is not limited thereto. In an embodiment in which the color control structures TPL, WCL1 and WCL2 are formed via a photoresist process, unlike the examples shown in the accompanying drawings, the upper surface of each layer of the color control structures TPL, WCL1 and WCL2 is formed to be flat, so that the edge adjacent to the upper bank layer UBN can be parallel to the upper surface of the upper bank layer UBN, or the center of the color control structures TPL, WCL1 and WCL2 can be higher than it.

[0189] Although the light emitting elements ED of different sub-pixels SPXn may emit light of the same color (i.e., blue light of the third color), light of different colors may be emitted from different sub-pixels SPXn. For example, light emitted from the light emitting element ED disposed in the first sub-pixel SPX1 is incident on the first wavelength conversion layer WCL1, light emitted from the light emitting element ED disposed in the second sub-pixel SPX2 is incident on the second wavelength conversion layer WCL2, and light emitted from the light emitting element ED disposed in the third sub-pixel SPX3 is incident on the transparent layer TPL. Light incident on the first wavelength conversion layer WCL1 may be converted into red light, light incident on the second wavelength conversion layer WCL2 may be converted into green light, and light incident on the transparent layer TPL may be transmitted as the same blue light without wavelength conversion. Although the sub-pixels SPXn include light emitting elements ED that emit light of the same color, light of different colors may be output by disposing color control structures TPL, WCL1, and WCL2 above them.

[0190] The second cover layer CPL2 may be disposed on the color control structures TPL, WCL1 and WCL2 and the upper bank layer UBN. The second cover layer CPL2 may prevent impurities such as moisture and air introduced from the outside from damaging or contaminating the color control structures TPL, WCL1 and WCL2. The second cover layer CPL2 may include an inorganic insulating material.

[0191] The low refractive layer LRL may be disposed on the second cover layer CPL2. The low refractive layer LRL may be an optical layer that recycles light that has passed through the color control structures TPL, WCL1, and WCL2, and may improve the emission efficiency and color purity of the display device 1. The low refractive layer LRL may be made of an organic material having a low refractive index, and may provide a flat surface over the color control structures TPL, WCL1, and WCL2 having different heights and the upper bank layer UBN.

[0192] The third cover layer CPL3 may be disposed on the low refractive layer LRL and may prevent impurities such as moisture and air from penetrating from the outside to damage or contaminate the low refractive layer LRL. The third cover layer CPL3 may include an inorganic insulating material similar to the second cover layer CPL2.

[0193] The first overcoat layer OC1 may be disposed on the third cover layer CPL3 across the entire display area DA and the entire non-display area NDA. The first overcoat layer OC1 may overlap the color control structures TPL, WCL1, and WCL2 in the display area DA.

[0194] In addition to the multiple cover layers CPL1 and CPL2 and the low refractive layer LRL, the first overcoat layer OC1 can also protect the elements disposed on the substrate SUB and can partially provide a flat surface over these elements having different heights. In particular, the first overcoat layer OC1 can provide a flat surface over the color control structures TPL, WCL1 and WCL2 having different heights, the upper bank layer UBN and the bank layer BNL thereunder in the display area DA, so that the color filter layers CFL1, CFL2 and CFL3 can be formed on the flat surface.

[0195] A plurality of color filter layers CFL1, CFL2, and CFL3 may be disposed on the first overcoat layer OC1. The color filter layers CFL1, CFL2, and CFL3 may be disposed in wavelength control areas LA1, LA2, and LA3, respectively, and may be partially disposed in the light blocking area BA. The color filter layers CFL1, CFL2, and CFL3 may overlap with other color filter layers CFL1, CFL2, and CFL3 or color patterns CP1, CP2, and CP3 in the light blocking area BA. The wavelength control areas LA1, LA2, and LA3 from which light is output may be positions of the color filter layers CFL1, CFL2, and CFL3 that are not overlapped with other color filter layers CFL1, CFL2, and CFL3. The light blocking area BA in which light is blocked may be a position where different color filter layers CFL1, CFL2, and CFL3 overlap with each other or where the color patterns CP1, CP2, and CP3 are disposed.

[0196] The color filter layers CFL1, CFL2, and CFL3 may include a first color filter layer CFL1 disposed in a first sub-pixel SPX1, a second color filter layer CFL2 disposed in a second sub-pixel SPX2, and a third color filter layer CFL3 disposed in a third sub-pixel SPX3. The color filter layers CFL1, CFL2, and CFL3 may be formed as linear patterns disposed in a plurality of wavelength control areas LA1, LA2, and LA3. However, it should be understood that the disclosure is not limited thereto. The color filter layers CFL1, CFL2, and CFL3 may be disposed in the wavelength control areas LA1, LA2, and LA3, respectively, and may form an island pattern.

[0197] The color filter layers CFL1, CFL2, and CFL3 may include colorants (such as dyes and pigments) that absorb light in other wavelength ranges except for a specific wavelength range. The color filter layers CFL1, CFL2, and CFL3 may be respectively disposed in the sub-pixel SPXn to transmit only some of the light incident on the color filter layers CFL1, CFL2, and CFL3 in the corresponding sub-pixel SPXn. The sub-pixel SPXn of the display device 1 may selectively display only the light transmitted through the color filter layers CFL1, CFL2, and CFL3. According to the disclosed embodiment, the first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. The light emitted from the light emitting element ED may pass through the color control structures TPL, WCL1, and WCL2 to be emitted through the color filter layers CFL1, CFL2, and CFL3.

[0198] The color patterns CP1, CP2, and CP3 may be disposed on the first overcoat layer OC1 or the color filter layers CFL1, CFL2, and CFL3. The color patterns CP1, CP2, and CP3 may include the same material as the color filter layers CFL1, CFL2, and CFL3, and may be disposed in the light blocking area BA. In the light blocking area BA, the color patterns CP1, CP2, and CP3 and the different color filter layers CFL1, CFL2, and CFL3 are disposed so that they are stacked on each other, and the transmission of light may be blocked in the area where they are stacked on each other.

[0199] The first color pattern CP1 may include the same material as that of the first color filter layer CFL1, and may be disposed in the light blocking area BA. The first color pattern CP1 may be disposed directly on the first overcoat layer OC1 in the light blocking area BA, but may not be disposed in the light blocking area BA adjacent to the first wavelength control area LA1 of the first subpixel SPX1. The first color pattern CP1 may be disposed in the light blocking area BA between the second subpixel SPX2 and the third subpixel SPX3. The first color filter layer CFL1 may be disposed in the light blocking area BA around the first subpixel SPX1.

[0200] The second color pattern CP2 may include the same material as that of the second color filter layer CFL2, and may be disposed in the light blocking area BA. The second color pattern CP2 may be disposed directly on the first overcoat layer OC1 in the light blocking area BA, but may not be disposed in the light blocking area BA adjacent to the second wavelength control area LA2 of the second sub-pixel SPX2. The second color pattern CP2 may be disposed in the light blocking area BA between the first sub-pixel SPX1 and the third sub-pixel SPX3, or at a boundary between the outermost sub-pixel SPXn of the display area DA and the non-display area NDA. The second color filter layer CFL2 may be disposed in the light blocking area BA around the second sub-pixel SPX2.

[0201] Similarly, the third color pattern CP3 may include the same material as that of the third color filter layer CFL3, and may be disposed in the light blocking area BA. The third color pattern CP3 may be disposed directly on the first overcoat layer OC1 in the light blocking area BA, but may not be disposed in the light blocking area BA adjacent to the third wavelength control area LA3 of the third sub-pixel SPX3. The third color pattern CP3 may be disposed in the light blocking area BA between the first sub-pixel SPX1 and the second sub-pixel SPX2. The third color filter CFL3 may be disposed in the light blocking area BA around the third sub-pixel SPX3.

[0202] In the display device 1, the area where the bank layer BNL and the upper bank layer UBN overlap each other may be a light blocking area BA. In the light blocking area BA, each of the first color pattern CP1, the second color pattern CP2, and the third color pattern CP3 may be disposed to overlap at least one of the color filter layers CFL1, CFL2, and CFL3 including different color materials. For example, the first color pattern CP1 may be disposed to overlap the second color filter layer CFL2 and the third color filter layer CFL3, the second color pattern CP2 may be disposed to overlap the first color filter layer CFL1 and the third color filter layer CFL3, and the third color pattern CP3 may be disposed to overlap the first color filter layer CFL1 and the second color filter layer CFL2. In each of the light blocking areas BA, the color patterns CP1, CP2, and CP3 having different colorants and the different color filter layers CFL1, CFL2, and CFL3 overlap each other, so that the transmission of light can be blocked.

[0203] The color patterns CP1 , CP2 , and CP3 may be stacked on the color filter layers CFL1 , CFL2 , and CFL3 , and may prevent color mixing between adjacent regions by including materials of different colorants.

[0204] The second overcoat layer OC2 may be disposed on the color filter layers CFL1, CFL2, and CFL3 and the color patterns CP1, CP2, and CP3. The second overcoat layer OC2 may be disposed in the entire display area DA and may be partially disposed in the non-display area NDA. The second overcoat layer OC2 may include an organic insulating material to protect elements disposed in the display area DA from an external environment. An upper surface of the second overcoat layer OC2 may be an upper surface of the display panel 300.

[0205] The film member 100 may be disposed on the second outer coating layer OC2. Specifically, an adhesive layer ADH may be interposed between the film member 100 and the second outer coating layer OC2 so that the second outer coating layer OC2 and the film member 100 may be adhered to each other.

[0206] The film member 100 may protect the upper surface of the display device 1 as described above. The film member 100 may include an anti-fingerprint film 110 and a base film 130 disposed at the top.

[0207] The anti-fingerprint film 110 of the film member 100 may prevent a user's fingerprint from being left on the display device 1. The structure of the anti-fingerprint film 110 is well known in the art; therefore, it will not be described here.

[0208] The base film 130 of the film member 100 may be used as a base of the film member 100. The base film 130 may include a material having a certain degree of rigidity. In some embodiments, the base film 130 may include triacetyl cellulose (TAC), but is not limited thereto. As described above, the base film 130 has a certain degree of rigidity so that it can protect the exterior of the display device 1.

[0209] As described above, the chassis member 500 may support the bottom of the display panel 300 to increase mechanical strength. The chassis member 500 may be disposed on the bottom of the display panel 300 (ie, the bottom of the substrate SUB of the display panel 300).

[0210] The heat dissipation layer GP may be disposed between the chassis member 500 and the display panel 300. The heat dissipation layer GP may block electromagnetic waves output from the display panel 300. In some embodiments, the heat dissipation layer GP may include graphite, but is not limited thereto. Hereinafter, display devices according to other disclosed embodiments will be described.

[0211] In the following description, the same or similar elements will be denoted by the same or similar reference numerals, and a redundant description will be omitted or briefly described.

[0212] Fig.14 is a plan view showing an electrode pattern layer of a display device according to another disclosed embodiment.

[0213] In accordance with Fig.14 In the display device 1_1 of the embodiment, the slits SL_1 formed by the slit pattern 230_1 of the electrode pattern layer 200_1 may extend in the first direction DR1. In other words, the extending direction of the slit pattern 230_1 may be substantially the same as the extending direction of the light emitting element ED.

[0214] According to this embodiment, a plurality of slit patterns 230_1 may be extendedly disposed so that they may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. Therefore, when the emission area EMA has a rectangular shape including a longer side in the second direction DR2 and a shorter side in the first direction DR1, the number of slits SL_1 may increase so that light output from the light emitting element ED may be more easily scattered.

[0215] Fig.15 is a plan view showing an electrode pattern layer of a display device according to yet another disclosed embodiment.

[0216] In accordance with Fig.15 In the display device 1_2 of the embodiment, the slit SL_2 formed by the slit pattern 230_2 of the electrode pattern layer 200_2 may extend in an oblique direction relative to the emission area EMA. For example, the extending direction of the slit SL_2 may be a direction between the first direction DR1 and a direction opposite to the second direction DR2.

[0217] According to this embodiment, the ground contact 250_2 may extend in the first direction DR1 so that it crosses between one side of the emission area EMA in the second direction DR2 and the opposite side of the sub-area SA disposed on one side of the emission area in the second direction DR2 in the second direction DR2, may be connected between two adjacent second ground portions 210b, and may be integrally formed with the end of the slit pattern 230_2 extending to one side of the emission area EMA in the second direction DR2 among the slit patterns 230_2. Therefore, both ends of the slit pattern 230_2 extending from one side of the emission area EMA in the first direction DR1 to one side in the second direction DR2 may be stably fixed. As a result, the mechanical stability of the slit pattern 230_2 may be improved.

[0218] According to this embodiment, since the extension direction of the slits SL_2 obliquely crosses the extension direction of the light emitting element ED, the number of slits SL_2 can be increased, and light output from the light emitting element ED can be scattered more effectively.

[0219] Fig.16 is a plan view schematically showing a light emitting element, an alignment electrode, and a connection electrode of a display device according to still another disclosed embodiment. Fig.17 It shows that according to Fig.16A plan view of an electrode pattern layer of a display device of an embodiment.

[0220] Reference Fig.16 and Fig.17 In the display device 1_3 according to this embodiment, the light emitting elements ED are arranged in a plurality of columns, and the light emitting elements ED may be connected in series in each column. In some embodiments, the light emitting elements ED may be arranged in two columns, but are not limited thereto. For example, the light emitting elements ED may be arranged in three or more columns, and the light emitting elements ED may be connected in series in each column. Fig.16 and Fig.17 In the example shown in , the light emitting elements ED are arranged in two columns. In the following description, for convenience of explanation, it is assumed that the light emitting elements ED are arranged in two columns. The display device 1_3 according to this embodiment may further include a third alignment electrode RME3_3, a third connection electrode CNE3_3 and a third bank pattern BP3.

[0221] The third bank pattern BP3 may be disposed at one side of the second bank pattern BP2 in the first direction DR1. The third alignment electrode RME3_3 may be disposed on the third bank pattern BP3.

[0222] The first alignment electrode RME1_3 according to this embodiment is consistent with the first alignment electrode RME1_3 according to Figure 5 The first alignment electrode RME1 of the display device 1 according to the embodiment is substantially the same, and the second alignment electrode RME2_3 according to this embodiment is substantially the same as that according to the embodiment. Figure 5 The second alignment electrodes RME2 of the display device 1 of the embodiments of FIG. 1 are substantially the same; therefore, a redundant description will be omitted.

[0223] The third alignment electrode RME3_3 may be disposed at one side of the second alignment electrode RME2_3 in the first direction DR1 and may extend beyond the emission area EMA to the sub-area SA in the second direction DR2. The third alignment electrode RME3_3 of one sub-pixel SPXn may be separated from the third alignment electrode RME3_3 of an adjacent sub-pixel SPXn at the separation area ROP.

[0224] A plurality of first light emitting elements ED1_3 may be arranged along the second direction DR2 between the first alignment electrode RME1_3 and the second alignment electrode RME2_3 , and a plurality of second light emitting elements ED2_3 may be arranged along the second direction DR2 between the second alignment electrode RME2_3 and the third alignment electrode RME3_3 .

[0225] The orientation of the first light emitting element ED1_3 and the orientation of the second light emitting element ED2_3 may be opposite. For ease of explanation, one end of each of the first light emitting element ED1_3 and the second light emitting element ED2_3 adjacent to the second semiconductor layer 32 is referred to as the first end, and the end adjacent to the first semiconductor layer 31 (see Figure 6 ) is referred to as the second end. The first end of each of the first light emitting elements ED1_3 may be disposed on the first alignment electrode RME1_3, the second end may be disposed on the second alignment electrode RME2_3, the second end of each of the second light emitting elements ED2_3 may be disposed on the second alignment electrode RME2_3, and the first end may be disposed on the third alignment electrode RME3_3.

[0226] In the display device 1_3 according to the embodiment, the first connection electrode CNE1_3 may be disposed on the first alignment electrode RME1_3 to contact the first end of each of the first light emitting elements ED1_3 and may be electrically connected to the first alignment electrode RME1_3 via the first contact CT1.

[0227] The second connection electrode CNE2_3 may be disposed on the second alignment electrode RME2_3 and the third alignment electrode RME3_3. A portion of the second connection electrode CNE2_3 may contact the second end of each of the first light emitting elements ED1_3, and another portion may contact the first end of each of the second light emitting elements ED2_3. The second connection electrode CNE2_3 may have a shape that is bent at least once.

[0228] The third connection electrode CNE3_3 may be disposed on the second alignment electrode RME2_3 to contact the second end of each of the second light emitting elements ED2_3. The third connection electrode CNE3_3 may be electrically connected to the second alignment electrode RME2_3 through a second contact CT2.

[0229] Due to the connection relationship between the light emitting elements ED1_3 and ED2_3 as described above, even if one light emitting element is electrically connected to other electrodes instead of the connection electrodes CNE1_3, CNE2_3, and CNE3_3 and does not emit light, other light emitting elements may emit light. For example, if one of the first light emitting elements ED1_3 is electrically connected to other electrodes instead of the connection electrodes CNE1_3, CNE2_3, and CNE3_3, poor connection occurs. As a result, all of the plurality of first light emitting elements ED1_3 arranged in the second direction DR2 may not be able to emit light. In this case, regardless of the poor connection of the first light emitting element ED1_3, the second light emitting element ED2_3 is able to emit light. Therefore, it is necessary to scatter the light output from the second light emitting element ED2_3 to compensate for the reduction in light efficiency caused by the first light emitting element ED1_3 not emitting light.

[0230] For this reason, Fig.17 As shown in FIG. 2 , by providing the electrode pattern layer 200 , light output from the light emitting elements ED1_3 and ED2_3 can be scattered. Fig.17 Shows the settings according to Figure 7 The electrode pattern layer 200 of the embodiment of the present invention is disclosed, but the disclosure is not limited thereto. For example, the electrode pattern layer 200 according to the embodiment of the present invention may also be applied. Fig.14 The electrode pattern layer 200_1 of the embodiment or according to Fig.15 The electrode pattern layer 200_2 of the embodiment.

[0231] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing from the principles of the present invention. Therefore, the preferred embodiments of the disclosed invention are intended for general and descriptive purposes only and not for limiting purposes.

Claims

1. A display device, comprising: a bank layer defining an emission region, wherein the light emitting element is disposed in the emission region; A first electrode and a second electrode are spaced apart from each other in the emission region, and the light emitting element is disposed between the first electrode and the second electrode; as well as an electrode pattern layer, disposed above the bank layer, the light emitting element, the first electrode and the second electrode, Wherein, the electrode pattern layer includes: a grid pattern, which does not overlap with the emission area and surrounds the edge of the emission area; and a slit pattern, which overlaps with the emission area.

2. The display device according to claim 1, wherein: The mesh pattern overlaps the bank layer, and wherein the slit pattern does not overlap the bank layer.

3. The display device according to claim 2, wherein: A first power supply voltage is applied to the first electrode, wherein a second power supply voltage is applied to the second electrode, the second power supply voltage having a level lower than the first power supply voltage, and Wherein, the electrode pattern layer further includes a contact element electrically connected to the second electrode.

4. The display device according to claim 3, wherein: The second electrode is in direct contact with the contact member.

5. The display device according to claim 1, wherein: The slit pattern includes a plurality of scattering members spaced apart from each other, with slits extending across the emission area between the plurality of scattering members, and At least one of the plurality of scattering members overlaps with the light emitting element.

6. The display device according to claim 5, further comprising: a covering layer disposed between the light emitting element and the plurality of scattering members; as well as A wavelength conversion material is provided on the upper surfaces of the plurality of scattering members to convert the wavelength of light output from the light emitting element.

7. The display device according to claim 6, wherein: The plurality of scattering members and the mesh pattern include a same material.

8. The display device according to claim 7, wherein: The plurality of scattering members include a transparent conductive oxide.

9. The display device according to claim 6, wherein: The slit extends in a direction parallel to an extending direction of the light emitting element.

10. The display device according to claim 6, wherein: The slit extends in a direction intersecting with an extending direction of the light emitting element.

11. A display device, comprising: substrate; A first electrode, disposed on the substrate to receive a first power supply voltage; a second electrode spaced apart from the first electrode on the substrate to receive a second power supply voltage having a lower level than the first power supply voltage; a light emitting element, disposed in a space between the first electrode and the second electrode; A covering layer, disposed above the first electrode, the second electrode and the light emitting element; as well as A ground electrode is disposed on the cover layer, Wherein, the ground electrode is electrically connected to the second electrode.

12. The display device according to claim 11, further comprising: a second power supply voltage line disposed between the substrate and the second electrode and applying the second power supply voltage to the second electrode; as well as a driver, disposed on the substrate to apply a driving signal to the light emitting element, Wherein, the second power supply voltage line and the driver are electrically connected to each other.

13. The display device according to claim 12, further comprising: a via insulating layer, disposed between the second power supply voltage line and the second electrode, The second electrode contacts the second power supply voltage line through an electrode contact hole penetrating the via insulating layer.

14. The display device according to claim 13, wherein: The electrode contact hole passes through the cover layer, and Wherein, the ground electrode is in direct contact with the second electrode through the electrode contact hole.

15. The display device according to claim 14, wherein: The ground electrode does not overlap the light emitting element.

16. The display device according to claim 12, further comprising: a plurality of scattering members spaced apart from each other, at least one of the plurality of scattering members overlapping the light emitting element, Wherein, the ground electrode and the plurality of scattering members include the same material.

17. The display device according to claim 16, wherein: The ground electrode includes a transparent conductive oxide.

18. A display device, comprising: substrate; A bank layer is disposed on the substrate to define an emission region, and a light emitting element is disposed in the emission region; a first electrode and a second electrode, disposed on the substrate and spaced apart from each other in the emission region, and the light emitting element is disposed between the first electrode and the second electrode; a capping layer disposed above the bank layer, the first electrode, the second electrode and the light emitting element; as well as a plurality of scattering members disposed on the cover layer such that the plurality of scattering members are spaced apart from each other, At least one of the plurality of scattering members overlaps with the light emitting element.

19. The display device according to claim 18, wherein: The plurality of scattering members do not overlap the bank layer.

20. The display device according to claim 19, wherein: The plurality of scattering members include a transparent conductive oxide.

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