Low dropout voltage regulator circuit

Abstract

The invention relates to a low dropout voltage regulator circuit. The LDO regulator has a pass device disposed between an input node and an output node. The pass device is controlled at the control node by the error amplifier. A first current generator provides a compensation current to the control node, a cascode device is disposed between the control node and the compensation node, and a second current generator draws the compensation current from the compensation node. A compensation capacitor is disposed between the output and the compensation node. A load current through the pass device is sensed to generate a feedback current at the first feedback node. An input branch of the current mirror receives a feedback current. A filter circuit is coupled between the control terminal of the input branch and the second feedback node. An output branch of the current mirror receives an additional compensation current from the compensation node and the control node, respectively, the additional compensation current being proportional to the feedback current.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000015027 filed on July 18, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present invention relates to a low dropout (LDO) voltage regulator circuit, or LDO regulator for short. Such LDO regulators can be used, for example, to supply digital circuits, such as the digital section of a sensor device (eg, ultra-wideband MEMS accelerometer, smart sensor, etc.).

[0004] In particular, the present description relates to low power and high bandwidth LDO regulators. Background Art

[0005] Digital systems (e.g., memory, microcontrollers, etc.) are typically powered by a digital supply voltage that must be compatible with the thin gate oxide of (CMOS) transistors. Such a digital supply voltage is typically generated by an LDO regulator. In particular, a large bandwidth LDO regulator is used to stabilize the output regulation voltage for possible variations in capacitive and current loads. In this regard, an LDO regulator that implements Miller cascode compensation (MCC) is particularly advantageous.

[0006] Figure 1 is a circuit diagram of an exemplary MCC LDO regulator 10. The LDO regulator 10 has a circuit configured to receive a system power supply voltage V DD The input node 102 is configured to generate a regulated output voltage V reg A transfer device P2 having tunable conductivity is arranged between the input node 102 and the output node 104 to provide current to the load and adjust the output voltage V reg In the figure, the load of the LDO regulator is composed of a load capacitor C arranged between node 104 and ground. L and a load current source G arranged between node 104 and ground L To illustrate (eg, for modeling purposes), the load current source G L The load current I is drawn from the node 104 LThe transfer device P2 may be a MOS transistor having a conductive channel disposed between nodes 102 and 104, such as a p-channel MOS transistor having a source terminal coupled to node 102 and a drain terminal coupled to node 104. Additionally, the LDO regulator 10 includes an error amplifier 12 that generates a control signal V for the gate of the transfer device P2. c , the control signal V c is the regulated voltage V reg and reference voltage V ref or, more specifically, the regulation voltage V reg Proportional signal V' reg and reference voltage V ref For example, the signal V' reg The regulating voltage V may be obtained by, for example, dividing the regulating voltage V via a resistive voltage divider (not visible in the figure for ease of illustration). reg Specifically, the error amplifier 12 may include a transistor input differential pair M1a, M1b biased by a tail current generator G1, and the transistor input differential pair M1a, M1b is generated by drawing a tail current I T The tail current generator G1 is biased by the tail current generator G1 and is loaded by the current mirrors M2a, M2b arranged between the input pair M1a, M1b and the input node 102. Specifically, the first n-channel MOS transistor M1a has a source terminal coupled to the tail node 106, a drain terminal coupled to the bias node 108, and is configured to receive the voltage V' reg (or voltage V reg ) has a gate terminal. The second n-channel MOS transistor M1b has a source terminal coupled to the tail node 106, coupled to the control signal V generated therein. c The drain terminal of the control node 110 and is configured to receive a reference voltage V ref A current generator G1 (which may be implemented as a current mirror that mirrors a reference current) is coupled between the tail node 106 and ground to draw a tail current I from the node 106. T The first p-channel diode-connected MOS transistor M2a has a source terminal coupled to the node 102, a drain terminal coupled to the node 108, and a gate terminal connected to its drain terminal. The second p-channel MOS transistor M2b has a source terminal coupled to the node 102, a drain terminal coupled to the node 110, and a gate terminal coupled to the gate terminal of transistor M2a.

[0007] The output branch of the LDO regulator 10 (ie, the current branch including the pass element P2) is biased by a bias current I B Bias. Bias current IB For example, it is drawn from the node 104 to ground through a current generator G4 such as a current mirror or through a resistive path.

[0008] In a Miller compensated (MC) LDO regulator, a compensation capacitor is placed between the output node 104 and the control node 110 to improve stability. Figure 1 In the Miller cascode compensation (MCC) LDO regulator 10 shown, a cascode stage is additionally provided between the output of the error amplifier 12 and the pass device P2. Specifically, the cascode stage may include: a current generator G2, which is arranged between the input node 102 and the control node 110 and is configured to provide a compensation current I to the node 110. C ; a common-source common-gate amplifier device M3 having a conductive channel arranged between the control node 110 and the compensation node 112; and a current generator G3 arranged between the compensation node 112 and ground and configured to draw a compensation current I from the node 112 C Specifically, the cascode device M3 may be an n-channel MOS transistor having a drain terminal coupled to the node 110, a source terminal coupled to the node 112, and a gate terminal configured to receive a fixed voltage. This fixed voltage provides proper biasing and ensures that the MOS transistors in the compensation path (e.g., M3 and the current mirror G3) operate in a saturated state. The compensation capacitor C C It is provided between the output node 104 and the compensation node 112 to improve stability.

[0009] Compared with the MC LDO regulator, the MCC LDO regulator has a higher capacitance even when the load capacitance C L When the input voltage is high, it also provides improved power supply rejection ratio (PSRR) and wider bandwidth. Figure 1 The transfer function of the MCC LDO regulator shown has the following parameters:

[0010] A 0 =-g m1 r out1 g m2 r out2

[0011]

[0012]

[0013]

[0014]

[0015] Among them A 0is the open-loop gain at DC, g mC is the transconductance of the cascode device M3, and p 1 、p 2 、p 3 and z 1 are the frequencies of the poles and zeros of the transfer function, respectively. Here, if p 3 >>p 2 , then the pole frequency p 2 and p 3 The further output pole separation of the MCC LDO regulator compared to the MC LDO regulator helps achieve high load capacitance values ​​C L Large bandwidth.

[0016] However, the MCC architecture has a large bias current due to the cascode bias branch (i.e., the current I C ) introduces additional offset, and for certain load conditions, the two poles p 2 and p 3 into a complex conjugate pole pair, which may result in a regulated voltage V during transient response reg To this end, we can refer to Figure 2 and Figure 3 , Figure 2 and Figure 3 It shows that when the condition p is satisfied 3 >>p 2 ( Figure 2 ) and does not satisfy the condition p 3 >>p 2 ( Figure 3 ) is a Bode magnitude plot of the magnitude of the frequency response of the MCC LDO regulator. Figure 2 and Figure 3 The horizontal axis in represents the 0dB level. Figure 2 As shown in the example, if we assume that p 3 >>p 2 is valid and C L >>C C (e.g. nF compared to pF), then p 3 ≈z 1 , which leads to the fact that p 2 With GBWP = gm 1 / C C In contrast, if we assume that p 3 >>p 2 is not valid, such as Figure 3 As shown in the example, the frequency z 1 is fixed, the pole p 2 Pushed to the extreme point p 3 , and the two extreme points p 2 and p3 At frequency p CC The points become complex conjugate pole pairs:

[0017]

[0018] leads to oscillations during transients, more noticeably at frequency p CC The smaller the margin G between the amplitude at and the 0dB level. Note that assuming p 3 >>p 2 may be invalid for one or more of the following reasons: m2 is load-dependent (so the current I flowing through the pass device P2 P2 From I B Change to I L +I B );C L Can change; g mC is fixed and depends on I C Therefore, the worst case is when the current I P2 At maximum value (I P2 MAX ) and the capacitor C L At the minimum value (C L MIN ), this is because p 2 Move to high frequencies.

[0019] Therefore, there is a need in the art to provide a regulated voltage V having improved stability and / or which can reduce (eg, suppress) the regulated voltage V during transient response. reg oscillation of the MCC LDO regulator.

[0020] There is also a need in the art to provide a method for providing a system having improved stability and / or transient response (e.g., at a load current I L Such an MCC LDO regulator has fewer and / or lower voltage oscillations after the change. Summary of the invention

[0021] Embodiments herein relate to low dropout voltage regulator circuits.

[0022] According to one aspect of the present specification, a low dropout voltage regulator circuit includes an input node configured to receive an input voltage and an output node configured to generate a regulated output voltage. The LDO regulator includes a transfer device arranged between the input node and the output node and configured to receive a control signal from a control node. The conductivity of the transfer device is controlled by the control signal. The LDO regulator includes an error amplifier, which is configured to generate the control signal at the control node according to the difference between the regulated output voltage and a reference voltage. The LDO regulator includes a cascode stage, which includes a first current generator configured to provide a compensation current to the control node, a cascode device having a conductive channel arranged between the control node and the compensation node, and a second current generator configured to draw a compensation current from the compensation node. The LDO regulator includes a compensation capacitor arranged between the output node and the compensation node.

[0023] The LDO regulator further includes a current sensing circuit configured to sense a load current flowing through the transfer device and provide a feedback current to a first feedback node, the feedback current being proportional to the load current. The LDO regulator includes an input branch of a current mirror circuit having a conductive path arranged between the first feedback node and ground and configured to receive the feedback current. The LDO regulator includes a low pass filter coupled between a control terminal of the input branch and a second feedback node. The LDO regulator includes a first output branch of the current mirror circuit coupled to the second feedback node, the first output branch being configured to draw a first additional compensation current from the compensation node, the first additional compensation current being a function of the feedback current. The LDO regulator includes a second output branch of the current mirror circuit coupled to the second feedback node, the second output branch being configured to supply a second additional compensation current to the control node, the second additional compensation current being equal to the first additional compensation current. The LDO regulator includes a third output branch of the current mirror circuit coupled to the second feedback node, the third output branch being configured to draw an additional bias current from the error amplifier, the additional bias current being a function of the feedback current.

[0024] Thus, one or more embodiments may provide a MCC LDO regulator with improved stability.

[0025] According to another aspect of the present specification, a low dropout voltage regulator circuit includes an input node configured to receive an input voltage and an output node configured to generate a regulated output voltage. The LDO regulator includes a transfer device arranged between the input node and the output node and configured to receive a control signal from a control node. The conductivity of the transfer device is controlled by the control signal. The LDO regulator includes an error amplifier configured to generate the control signal at the control node as a function of the difference between the regulated output voltage and a reference voltage. The LDO regulator includes a cascode stage, which includes a first current generator configured to provide a compensation current to the control node, a cascode device having a conductive channel arranged between the control node and the compensation node, and a second current generator configured to draw a compensation current from the compensation node. The LDO regulator includes a compensation capacitor arranged between the output node and the compensation node.

[0026] The LDO regulator further includes a current sensing circuit configured to sense a load current flowing through the transfer device and provide a feedback current to a first feedback node, the feedback current being proportional to the load current. The LDO regulator includes an input branch of a current mirror circuit having a conductive path arranged between the first feedback node and ground and configured to receive the feedback current. The LDO regulator includes a high pass filter connected between a control terminal of the input branch of the current mirror circuit and a second feedback node. The LDO regulator includes a first output branch of the current mirror circuit coupled to the second feedback node, the first output branch being configured to draw a first additional compensation current from the compensation node, the first additional compensation current being a function of the feedback current. The LDO regulator includes a second output branch of the current mirror circuit coupled to the second feedback node, the second output branch being configured to provide a second additional compensation current to a control node, the second additional compensation current being equal to the first additional compensation current.

[0027] Thus, one or more embodiments may provide a MCC LDO regulator with improved transient response. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0029] Figure 1 is an exemplary circuit diagram of a conventional MCC LDO regulator presented previously;

[0030] Figure 2 is a Bode magnitude plot showing the magnitude of the transfer function (frequency response) of a conventional MCC LDO regulator when the frequency of the third pole is much higher than the frequency of the second pole;

[0031] Figure 3 is a Bode magnitude plot showing the magnitude of the transfer function (frequency response) of a conventional MCC LDO regulator when the frequency of the third pole is not much higher than the frequency of the second pole;

[0032] Figure 4 is an example of a Bode magnitude plot of the magnitude of a transfer function (frequency response) of an MCC LDO regulator according to one or more embodiments of the present specification;

[0033] Figure 5 is an exemplary circuit diagram of implementation details of a DC coupling loop in an MCC LDO regulator according to one or more embodiments of the present specification;

[0034] Figure 6 is an exemplary circuit diagram of implementation details of an AC coupling loop in an MCC LDO regulator according to one or more embodiments of the present specification;

[0035] Figure 7 is an exemplary circuit diagram of implementation details of a current sensing circuit for an AC-coupled loop and a DC-coupled loop in an MCC LDO regulator according to one or more embodiments of the present specification;

[0036] Figure 8 is an example Bode plot of magnitude and phase of a transfer function (frequency response) of an MCC LDO regulator according to one or more embodiments; and

[0037] Fig. 9 is a graph including exemplary signal waveforms of transient responses of an MCC LDO regulator according to one or more embodiments. DETAILED DESCRIPTION

[0038] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0039] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0040] The headings / reference signs used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0041] In the drawings attached hereto, unless the context otherwise indicates, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for the sake of brevity.

[0042] One or more embodiments are directed to an improved MCC LDO regulator with improved stability and / or transient response. In particular, an LDO regulator according to the present disclosure has a configuration designed to avoid two extremes. 2 and p 3 Considering the point p 2 The frequency depends on the load current I L The proposed architecture helps to separate the extreme points p 2 and p 3 frequency so that the condition p is also met in the MCC LDO regulator 3 >>p 2 The structure relies on at least one additional loop (e.g., a DC coupling loop and / or an AC coupling loop) that allows current to be injected in the compensation path, thereby increasing the transconductance g of the cascode device M3. mC The magnitude of the injected current is the load current I L function (for example, its relationship with the load current I L By doing so, the third pole p 3 is pushed to higher frequencies, such as Figure 4 As shown, Figure 4 is a Bode magnitude plot showing the magnitude of the transfer function (frequency response) of an MCC LDO regulator according to one or more embodiments, which satisfies the condition p 3 >>p 2 Here, the damping factor (δ) of the complex pole pair increases, which results in a frequency p 3 The margin G' between the amplitude at and the 0dB level is greater than the margin G of a conventional MCC LDO regulator (see again Figure 3 ).

[0043] Therefore, on the one hand, the architecture proposed here can improve the stability of the LDO regulator and increase its bandwidth, and on the other hand, it can improve and speed up the transient response (from the AC behavior point of view).

[0044] Figure 5 1 is an exemplary circuit diagram of implementation details of a DC coupling loop in an MCC LDO regulator 10′ according to one or more embodiments of the present specification. In essence, the LDO regulator 10′ includes: Figure 1All circuit components of a conventional MCC LDO regulator 10 are shown, plus the load current sensing circuit 50 and the DC coupling loop.

[0045] like Figure 5 As shown, the current sensing circuit 50 is configured to sense the current I flowing through the pass device P2. P2 , and generates a current I P2 The function of the feedback current I 50 , especially with current I P2 Proportional feedback current I 50 In one or more exemplary embodiments, the circuit 50 includes a replica transistor P2′ configured to replicate the behavior of the transistor P2 (e.g., a scaled one), i.e., the transistor P2′ may be a MOS transistor whose conductive channel is arranged between the node 102 and the replica output node 504 and is configured to receive the same control signal V as the transistor P2. c , for example a p-channel MOS transistor, whose source terminal is coupled to node 102, whose drain terminal is coupled to node 504, and whose gate terminal is coupled to node 110. In addition, circuit 50 may include a circuit configured to set the voltage of node 504 to be equal to the voltage V of node 104. reg The circuit arrangement is such that the drain-source voltage of transistor P2' is equal to the drain-source voltage of transistor P2. To this end, the circuit 50 may include a transconductance amplifier (OTA) 506 having a first input terminal coupled to the node 104 and a second input terminal coupled to the node 504, and an output terminal coupled to the gate terminal of transistor P3, the conductive channel of transistor P3 being serially coupled to the conductive channel of transistor P2'. For example, transistor P3 may be a p-channel MOS transistor having a source terminal coupled to the node 504, a drain terminal coupled to the feedback node 508, and a gate terminal coupled to the output of the amplifier 506. Basically, the amplifier 506 with the transistor P3 and the corresponding feedback connection provides a buffer circuit. Therefore, the circuit 50 converts the feedback current I 50 Provided to node 508, the feedback current I 50 is the current I P2 function (for example, with the current I P2 proportional).

[0046] like Figure 5 As shown, diode-connected transistor N1 is disposed between feedback node 508 and ground. Specifically, transistor N1 may be an n-channel MOS transistor having a drain terminal coupled to node 508, a source terminal coupled to ground, and a gate terminal coupled to its drain terminal. As will be discussed further below, transistor N1 operates as an input branch of a plurality of current mirrors configured to convert current I 50Mirrored into or from nodes 106, 110 and 112 (and possibly rescaled) is the current I 50 .

[0047] like Figure 5 As shown, the DC coupling loop includes a low pass filter inserted between the input branch N1 and the output branch of the current mirror. The low pass filter may include, for example, an RC filter including a resistor R1 coupled between the gate terminal of the transistor N1 and a node 510, and a capacitor C1 coupled between the node 510 and ground.

[0048] like Figure 5 As shown, the DC coupling loop includes an output branch of a first current mirror, which is configured to draw a current I from the compensation node 112. C EX (e.g., with the current I drawn by generator G3 C For example, the output branch of such a first current mirror may include an n-channel MOS transistor N2 having a drain terminal coupled to node 112, a source terminal coupled to ground, and a gate terminal coupled to node 510, such that transistor N2 draws a current I from node 112. 50 A (e.g., scaled, proportional) copy of a .

[0049] like Figure 5 As shown, the DC coupling loop includes an output branch of a second current mirror, which is configured to convert the current I C EX Provided to the control node 110 (eg, with the current I provided by the generator G2) C 510). For example, the output branch of this second current mirror may include an n-channel MOS transistor N3 having a drain terminal coupled to the input of another p-channel current mirror at node 512, a source terminal coupled to ground, and a gate terminal coupled to node 510. The other p-channel current mirror is configured to mirror (and possibly rescale) the current drawn by transistor N3 such that current I C EX is injected into node 110. Specifically, another p-channel current mirror may include an input p-channel diode-connected MOS transistor P4 having a drain terminal coupled to node 512, a source terminal coupled to node 102, and a gate terminal coupled to its drain terminal, and an output p-channel MOS transistor P5 having a drain terminal coupled to node 110, a source terminal coupled to node 102, and a gate terminal coupled to the gate terminal of transistor P4. In summary, transistors N3, P4, and P5 are sized such that transistor P5 provides a current I to node 110 that is equal to the current I drawn by transistor N2 from node 112.C EX The same current I C EX For example, transistor N3 may have the same size (W / L) as transistor N2, and the mirror factor of current mirror P4-P5 may be equal to 1.

[0050] like Figure 5 As shown, the DC coupling loop includes an output branch of a third current mirror, which is configured to draw a current I from the tail node 106. T EX (For example, with the current I drawn by generator G1 T ). For example, the output branch of this third current mirror may include an n-channel MOS transistor N4 having a drain terminal coupled to node 106, a source terminal coupled to ground, and a gate terminal coupled to node 510, such that transistor N4 draws (e.g., scales) current I from node 106. 50 Additional tail current I T EX The transistors M1a and M1b of the input differential pair are equally divided.

[0051] Discussed below Figure 5 The DC behavior of the DC coupled loop illustrated in FIG. The current drawn from node 112 by transistor N2 and the current provided to node 110 by transistor P5 are equal (both are I C EX ), and the currents flowing through transistors M2b and M1b are equal (both are I T EX / 2). Therefore, the net current at node 110 is zero (null), which causes the DC gain of the loop to also be zero (null), which is useful in a DC-coupled loop designed to (only) regulate bias (DC) to avoid AC peaking (i.e., as Figure 3 and Figure 4 As shown in the example, the third pole p 3 The frequency relative to the load current moves away from the pole p 2 frequency, thereby improving frequency response and system stability) is expected.

[0052] Discussed below Figure 5 Due to the additional pull-up current at node 110 and the fact that the current through transistors M2b and P5 passes through an additional current mirror, as the frequency increases, the current provided to node 110 by transistor M2b is less than the current drawn from node 110 by transistor M1b (e.g., it is less than I T EX / 2), and the current provided by transistor P5 to node 110 is less than the current drawn from node 112 by transistor N2 (e.g., it is less than I C EX ). Therefore, overall, current is drawn from node 110, which causes the AC gain of the loop to be positive. The positive AC gain of the loop will accelerate the load transient response, but this boost action is limited by the low-pass filter (R1, C1), which ensures that the loop AC gain remains at 0dB level; otherwise, the transient response may show undesirable oscillations during the transient.

[0053] Therefore, if Figure 5 The DC coupled loop shown (R1, C1, N2, N3, P4, P5, N4) has two effects. P2 function (for example, with the load current I P2 proportional to the bias current of the common source and common gate branch (i.e., the current I C EX Provides current I to node 110 and draws current I from node 112 C EX )(For example, tracking I P2 The transconductance g of the cascode device M3 mC Increase, and extremely 3 The frequency of the load current I L The function shifts (i.e., increases or decreases accordingly, so as to maintain the pole p 2 and p 3 As a second effect, by dividing the bias current of the input differential pair (i.e., the current drawn from node 106, I T EX) changes to load current I P2 function (for example, with the load current I P2 proportional to) (e.g., tracking I P2 The ratio of the transconductance of the cascode device M3 to the transconductance of the input differential pair is g. mC / gm IN This results in an increase in the gain bandwidth product (GBWP) of the loop and a fixed offset as a function of load current. An increase in GBWP is advantageous because it results in a faster response and because the pole p 2 The fact of moving to higher frequencies without stability problems.

[0054] Figure 5 The DC-coupled loop illustrated in is intended to regulate the (DC) bias of the LDO, but its low-pass filter (R1, C1) limits the boost action that could in principle accelerate load transients.

[0055] Thus, one or more embodiments may additionally or alternatively include an AC coupling loop designed to improve the response of the LDO to fast load transients while avoiding oscillations of the regulated voltage.

[0056] Figure 6 is an exemplary circuit diagram of implementation details of such an AC coupling loop in the MCC LDO regulator 10' according to one or more embodiments of the present specification. In some embodiments, the LDO regulator 10' includes Figure 1 All circuit components of the conventional MCCLDO regulator 10 shown, plus the load current sensing circuit 50, and optionally including Figure 5 The DC coupling loop shown, plus the AC coupling loop. Therefore, it should be understood that one or more embodiments include Figure 5 and Figure 6 The circuits of both Figure 5 and Figure 6 The load current sensing circuit 50 is shown in two different figures for ease of illustration only, where the load current sensing circuit 50 may be the same for both the DC coupling loop and the AC coupling loop (i.e., may be instantiated only once in the LDO regulator 10') or may be duplicated for each of the DC coupling loop and the AC coupling loop (i.e., may be implemented twice in the LDO regulator 10'). It should also be understood that in some embodiments, there may be no Figure 5 The DC coupling loop only exists Figure 6 Here again, transistor N1 works as an input branch of multiple current mirrors, which are configured to convert the current I 50 The current I is mirrored into or from nodes 110 and 112 (possibly rescaled). 50 .

[0057] like Figure 6 As shown, the AC coupling loop includes a high pass filter placed between the input branch N1 and the output branch of the current mirror. The high pass filter may include, for example, a capacitive filter including a capacitor C2 coupled between the gate terminal of transistor N1 and node 610.

[0058] like Figure 6 As shown, the AC coupling loop includes an output branch of a first current mirror, which is configured to draw a current I from the compensation node 112. C EX (For example, with the current I drawn by generator G3 CFor example, the output branch of this first current mirror may include an n-channel MOS transistor N5 having a drain terminal coupled to node 112, a source terminal coupled to ground, and a gate terminal coupled to node 610, so that transistor N2 draws (e.g., scales) current I from node 112. 50 of the copy.

[0059] like Figure 6 As shown, the AC coupling loop includes an output branch of a second current mirror, which is configured to convert the current I C EX Provided to the control node 110 (eg, with the current I provided by the generator G2) C 6. The output branch of this second current mirror may include, for example, an n-channel MOS transistor N6 having a drain terminal coupled to the input of another p-channel current mirror at node 612, a source terminal coupled to ground, and a gate terminal coupled to node 610. The other p-channel current mirror is configured to mirror (and possibly rescale) the current drawn by transistor N6 such that current I C EX is injected into node 110. Specifically, another p-channel current mirror may include an input p-channel diode-connected MOS transistor P6 having a drain terminal coupled to node 612, a source terminal coupled to node 102, and a gate terminal coupled to its drain terminal, and an output p-channel MOS transistor P7 having a drain terminal coupled to node 110, a source terminal coupled to node 102, and a gate terminal coupled to the gate terminal of transistor P6. In summary, transistors N6, P6, and P7 are sized such that transistor P7 provides a current I to node 110 that is equal to the current I drawn by transistor N5 from node 112. C EX The same current I C EX For example, transistor N6 may have the same size (W / L) as transistor N5, and the mirror factor of current mirror P6-P7 may be equal to 1.

[0060] like Figure 6 As shown, the AC coupling loop includes a diode-connected n-channel MOS transistor N7 having a drain terminal biased by current generator G5, a source terminal coupled to ground, and a gate terminal coupled to node 610 via resistor R2. By doing so, transistors N5 and N6 can be weakly polarized under steady-state conditions, thereby ensuring minimum bias. From an AC point of view, resistor R2 provides appropriate biasing under DC conditions and implements a high-pass filter together with capacitor C2.

[0061] In DC, Figure 6The AC coupled loop illustrated in FIG. 1 is decoupled by capacitor C2. The AC behavior of the AC coupled loop is discussed below (at frequencies above the high pass pole frequency due to capacitor C2). Due to the additional pull-up current at node 110 and the fact that the current through transistor P7 passes through the additional current mirror, the current provided to node 110 by transistor P7 is less than the current drawn from node 112 by transistor N5 (e.g., it is less than I C EX ). Therefore, overall, current is drawn from node 110, which causes the AC gain of the loop to be positive. The positive AC gain of the loop accelerates the load transient response. As a design criterion, the AC gain of the AC-coupled loop can be less than -20 dB at any frequency.

[0062] Therefore, if Figure 6 The AC coupling loop shown (C2, N5, N6, P6, P7, R2, N7) has the effect of accelerating the load transient response, thereby immediately injecting additional current in the compensation path (increasing the transconductance g mC ). By doing this, oscillations during the transient response are limited or suppressed.

[0063] Since in different embodiments, the LDO regulator 10' may include only a DC-coupled loop, or only an AC-coupled loop, or both a DC-coupled loop and an AC-coupled loop, different architectures may be used for current sensing. In some embodiments as described above, a single current sensing circuit 50 and a single diode-connected transistor N1 are implemented, where the two loops (DC and AC) are coupled to the gate terminal of transistor N1. In this case, different sizes of current injected by the two loops may be achieved by using different sizes of current mirrors implemented in each loop. In other embodiments, some elements of the current sensing circuit may be replicated (e.g., instantiated twice). For example, the current flow line including transistors P2', P3, and N1 may be as shown in FIG. Figure 7 As shown in the example, two transistors P2' (eg, P2' A and p2′B) have their gate terminals coupled to the control node 110, and two transistors P3 (eg, P3 A and P3 B ) has its gate terminal coupled to the output terminal of the single transconductance amplifier 506, and a dedicated diode-connected transistor N1 (eg, N1 A and N1 B ) is coupled to a corresponding transistor P3 and a corresponding one of the loops (DC or AC). In some further embodiments, the amplifier 506 may also be replicated (eg, instantiated twice).

[0064] Figure 8is a Bode plot showing the magnitude ( ) of a simulated transfer function (frequency response) (horizontal axis: frequency, unit: [Hz], from 1 mHz to 100 MHz) of an MCC LDO regulator for OTA stability analysis according to one or more embodiments. Figure 8 The upper graph of the unit is [dB], with the vertical axis ranging from -120dB to 100dB) and the phase ( Figure 8 The simulation confirms the theoretical analysis: the peak of the compound pole pair is attenuated (a higher damping factor is obtained).

[0065] Fig. 9 Included are a number of graphs illustrating simulated transient responses of an MCC LDO regulator according to one or more embodiments in the event of a load current step. In particular: Fig. 9 The upper graph shows the output voltage V reg (Unit: [V], from 1.186V to 1.222V on the vertical axis), Fig. 9 The middle curve of shows the current injected by the AC coupling loop IAC and the current injected by the DC coupling loop IDC (unit: [μA], from 0.1 μA to 1.0 μA on the vertical axis), and Fig. 9 The lower graph shows the load current I L (Unit: [μA], from 50.0 μA to 500.0 μA on the vertical axis, current step size = 375 μA). Fig. 9 The horizontal axis of the curve shows time in [μs], from 8.0μs to 26.0μs.

[0066] Thus, one or more embodiments as illustrated herein may provide one or more of the following advantages: improved stability and bandwidth of an LDO regulator; and / or improved transient response of an LDO regulator.

[0067] Without prejudice to the essential principles, the details and embodiments may vary even significantly with respect to what has been described by way of example, without departing from the scope of protection.

[0068] The scope of protection is determined by the appended claims.

[0069] The claims are an integral part of the technical teaching provided here regarding the embodiments.

Claims

1. A low dropout voltage regulator circuit, comprising: an input node configured to receive an input voltage; an output node configured to generate a regulated output voltage; a pass device disposed between the input node and the output node and configured to receive a control signal from a control node, wherein conductivity of the pass device is controlled by the control signal; an error amplifier configured to generate the control signal according to a difference between the regulated output voltage and a reference voltage; A cascode stage, comprising: a first current generator configured to provide a compensation current to the control node; a cascode device having a conductive channel arranged between the control node and a compensation node; and a second current generator configured to draw the compensation current from the compensation node; a compensation capacitor disposed between the output node and the compensation node; a current sensing circuit configured to sense a load current flowing through the pass device and provide a feedback current to a first feedback node, the feedback current being proportional to the load current; and A current mirror circuit, comprising: an input branch formed by a conductive path arranged between the first feedback node and ground and configured to receive the feedback current; a low pass filter coupled between the control terminal of the input branch and the second feedback node; a first output branch coupled to the second feedback node, the first output branch being configured to draw a first additional compensation current from the compensation node, the first additional compensation current being proportional to the feedback current; a second output branch coupled to the second feedback node, the second output branch being configured to provide a second additional compensation current to the control node, the second additional compensation current being equal to the first additional compensation current; and A third output branch is coupled to the second feedback node, and the third output branch is configured to draw an additional bias current from the error amplifier, the additional bias current being proportional to the feedback current.

2. The circuit of claim 1 , wherein the input branch of the current mirror circuit comprises a diode-connected transistor having a conductive path arranged between the first feedback node and ground, and the low-pass filter is coupled between a control terminal of the diode-connected transistor and the second feedback node.

3. The circuit of claim 1 , wherein the current sensing circuit comprises: a replica device of the transfer device, arranged between the input node and the replica output node, and configured to receive the control signal from the control node; as well as A buffer circuit is configured to force the voltage at the replica output node to be equal to the regulated output voltage at the output node.

4. The circuit according to claim 1: wherein the error amplifier includes a transistor input differential pair having a common tail node coupled to a tail current generator; wherein the tail current generator is configured to draw a tail current from the common tail node; wherein the transistor input differential pair is loaded by a current mirror; and The third output branch of the current mirror circuit is configured to draw the additional bias current from the common tail node.

5. The circuit of claim 1, wherein the pass device comprises a p-channel MOS transistor having a source terminal coupled to the input node, a drain terminal coupled to the output node, and a gate terminal coupled to the control node.

6. The circuit of claim 1 , wherein the current mirror circuit further comprises: a high pass filter coupled between the control terminal of the input branch and a third feedback node; a fourth output branch coupled to the third feedback node, the fourth output branch being configured to draw a third additional compensation current from the compensation node, the third additional compensation current being proportional to the feedback current; as well as A fifth output branch is coupled to the third feedback node, and is configured to provide a fourth additional compensation current to the control node, wherein the fourth additional compensation current is equal to the third additional compensation current.

7. The circuit of claim 6, further comprising a diode-connected transistor having a conductive path arranged between the current generator and ground and a control terminal resistively coupled to the third feedback node.

8. A low dropout voltage regulator circuit, comprising: an input node configured to receive an input voltage; an output node configured to generate a regulated output voltage; a pass device disposed between the input node and the output node and configured to receive a control signal from a control node, wherein conductivity of the pass device is controlled by the control signal; an error amplifier configured to generate the control signal according to a difference between the regulated output voltage and a reference voltage; A cascode stage, comprising: a first current generator configured to provide a compensation current to the control node; a cascode device having a conductive channel arranged between the control node and a compensation node; and a second current generator configured to draw the compensation current from the compensation node; a compensation capacitor disposed between the output node and the compensation node; a current sensing circuit configured to sense a load current flowing through the pass device and provide a feedback current to a first feedback node, the feedback current being proportional to the load current; A current mirror circuit, comprising: an input branch formed by a conductive path arranged between the first feedback node and ground and configured to receive the feedback current; a high pass filter coupled between the control terminal of the input branch and the second feedback node; a first output branch coupled to the second feedback node, the first output branch being configured to draw a first additional compensation current from the compensation node, the first additional compensation current being proportional to the feedback current; and A second output branch is coupled to the second feedback node, and the second output branch is configured to provide a second additional compensation current to the control node, wherein the second additional compensation current is equal to the first additional compensation current.

9. The circuit of claim 8 , wherein the input branch of the current mirror circuit comprises a diode-connected transistor having a conductive path arranged between the first feedback node and ground, and the high-pass filter is coupled between a control terminal of the diode-connected transistor and the second feedback node.

10. The circuit of claim 8, wherein the current sensing circuit comprises: a replica device of the transfer device, arranged between the input node and the replica output node, and configured to receive the control signal from the control node; as well as A buffer circuit is configured to force the voltage at the replica output node to be equal to the regulated output voltage at the output node.

11. The circuit according to claim 8: The error amplifier comprises: a transistor input differential pair having a common tail node coupled to the tail current generator; wherein the tail current generator is configured to draw a tail current from the common tail node; wherein the transistor input differential pair is loaded by a current mirror; and The third output branch of the current mirror circuit is configured to draw the additional bias current from the common tail node.

12. The circuit of claim 8, wherein the pass device comprises a p-channel MOS transistor having a source terminal coupled to the input node, a drain terminal coupled to the output node, and a gate terminal coupled to the control node.

13. The circuit of claim 8, further comprising a diode-connected transistor having a conductive path disposed between the current generator and ground and a control terminal resistively coupled to the second feedback node.

14. A low dropout voltage regulator circuit, comprising: an input node configured to receive an input voltage; an output node configured to generate a regulated output voltage; a pass device disposed between the input node and the output node and configured to receive a control signal from a control node, wherein conductivity of the pass device is controlled by the control signal; an error amplifier configured to generate the control signal according to a difference between the regulated output voltage and a reference voltage; A cascode stage, comprising: a first current generator configured to provide a compensation current to the control node; a cascode device having a conductive channel arranged between the control node and a compensation node; and a second current generator configured to draw the compensation current from the compensation node; a compensation capacitor disposed between the output node and the compensation node; a first current sensing circuit configured to sense a load current flowing through the pass device and provide the load current to a first feedback node, the first feedback current being proportional to the load current; The first current mirror circuit comprises: a first input branch formed by a conductive path arranged between the first feedback node and ground and configured to receive the first feedback current; a low-pass filter coupled between a control terminal of the first input branch and a second feedback node; a first output branch coupled to the second feedback node, the first output branch being configured to draw a first additional compensation current from the compensation node, the first additional compensation current being proportional to the feedback current; a second output branch of the current mirror circuit, coupled to the second feedback node, the second output branch being configured to provide a second additional compensation current to the control node, the second additional compensation current being equal to the first additional compensation current; and a third output branch of the current mirror circuit, coupled to the second feedback node, the third output branch being configured to draw an additional bias current from the error amplifier, the additional bias current being proportional to the feedback current; a second current sensing circuit configured to sense a load current flowing through the pass device and provide a second feedback current to a third feedback node, the second feedback current being proportional to the load current; The second current mirror circuit comprises: a second input branch formed by a conductive path arranged between the third feedback node and ground and configured to receive the second feedback current; a high pass filter coupled between a control terminal of the second input branch and a fourth feedback node; a fourth output branch coupled to the fourth feedback node, the fourth output branch being configured to draw a third additional compensation current from the compensation node, the third additional compensation current being proportional to the other feedback current; and A fifth output branch is coupled to the fourth feedback node, and the fifth output branch is configured to provide a fourth additional compensation current to the control node, wherein the fourth additional compensation current is equal to the third additional compensation current.

15. The circuit of claim 14, further comprising a diode-connected transistor having a conductive path disposed between the current generator and ground and a control terminal resistively coupled to the fourth feedback node.

16. The circuit according to claim 14: The error amplifier comprises: a transistor input differential pair having a common tail node coupled to the tail current generator; wherein the tail current generator is configured to draw a tail current from the common tail node; wherein the transistor input differential pair is loaded by a current mirror; and The third output branch of the first current mirror circuit is configured to draw the additional bias current from the common tail node.

17. The circuit of claim 14, wherein the pass device comprises a p-channel MOS transistor having a source terminal coupled to the input node, a drain terminal coupled to the output node, and a gate terminal coupled to the control node.

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