Method for grouping storage blocks in memory, controller and memory

Abstract

The invention discloses a method for grouping storage blocks in a memory, a controller and the memory. The method comprises the following steps: based on a memory, calculating the minimum number of dies required to be contained when the maximum performance of a die combination under a single channel is greater than or equal to the preset performance of the single channel; and judging whether the minimum number of the dies is smaller than half of the number of the dies communicated with a single channel of the memory, and if so, grouping the memory blocks based on the minimum number of the dies. According to the method, the stability of the memory is improved by constructing a smaller super block on the basis of not influencing the performance.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage technology, and in particular to a method for grouping storage blocks in a memory, a controller, and a memory. Background Art

[0002] Solid State Drives (SSD) are storage hard disks made of solid-state electronic storage chips. The storage hard disk includes a controller and a storage medium. Currently, the most mainstream solid-state drives use flash memory chips (NAND flash) as storage media to store data.

[0003] As the capacity of NAND flash becomes larger and larger, the number of dies it contains becomes more and more. Generally, in SSD, when reading and writing, multiple different storage blocks on multiple dies belonging to the same super block are processed in parallel, but when garbage collection is performed, the entire super block is garbage collected, so the organization of the super block needs to take into account the overall performance of the system (including the performance of read and write operations and garbage collection). At the same time, the organization of the super block also has a great impact on the stability of the SSD. Specifically, when writing data to each storage block in a super block, the super block will not be closed until all storage blocks in the super block are written. Since the closed super block is more stable than the super block before closing, if the super block contains too many storage blocks, it will take a long time to write to the super block. During this period of time, each storage block in the super block is in an unstable state. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a method, a controller and a memory for grouping storage blocks in a memory, so as to improve the stability of the memory by constructing smaller super blocks without affecting the performance.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for grouping storage blocks in a memory is provided, wherein the memory includes a storage medium and a controller, wherein the storage medium is composed of a plurality of dies, each of which is divided into a plurality of planes, each of which is divided into a plurality of storage blocks, and the controller connects the plurality of dies through a plurality of channels, wherein the method is executed by the controller, and the method includes grouping the plurality of storage blocks to form a super block, wherein the grouping includes:

[0006] Based on the memory, calculating the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel; and

[0007] It is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to a single channel of the memory; if so, the memory blocks are grouped based on the minimum number of dies.

[0008] Optionally, the method further includes: if the minimum number of dies is greater than half of the number of dies connected to a single channel, grouping storage blocks according to the number of dies under each channel to form a super block.

[0009] Optionally, the preset performance of each channel is equal to a preset performance index of the memory divided by the number of the multiple channels.

[0010] Optionally, the minimum number of dies required to be included when calculating that the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of a single channel includes:

[0011] The sum of the transmission time of data transmitted by a single die and the writing time of the data from the single die to the storage block is multiplied by the preset performance of the single channel, and the obtained product is divided by the total transmission data volume of the single die to obtain the target number of dies;

[0012] The target number of dies is rounded up to obtain the minimum number of dies.

[0013] Optionally, the controller performs a write operation, a read operation, or garbage collection on the storage medium based on the super block.

[0014] Optionally, the same number of dies are selected in parallel from the dies connected to each channel according to the minimum number of dies to form a super block.

[0015] Optionally, grouping the storage blocks based on the minimum number of dies includes: if the number of dies connected to a single channel is an integer multiple of the minimum number of dies, evenly dividing the storage blocks in the same row contained in multiple dies of the minimum number of dies.

[0016] Optionally, the grouping of storage blocks based on the minimum number of dies includes: if the number of dies connected to the same channel is not an integer multiple of the minimum number of dies, first evenly dividing the number of storage blocks in the same row contained in multiple dies with the minimum number of dies, and then adding the remaining storage blocks to any group.

[0017] According to a second aspect of an embodiment of the present disclosure, a controller of a memory is provided, the memory comprising a storage medium and the controller, the storage medium being composed of a plurality of dies, each of which being divided into a plurality of planes, each of which being divided into a plurality of storage blocks, the controller connecting the plurality of dies via a plurality of channels, the controller executing the method described in the first aspect to group the storage blocks to form a super block.

[0018] According to a third aspect of an embodiment of the present disclosure, a memory is provided, comprising the above-mentioned controller and a storage medium.

[0019] The method for grouping storage blocks provided in the embodiments of the present disclosure constructs smaller super blocks without loss of performance, thereby reducing, for example, the unit time of garbage collection and the recovery time of system startup, saving the flash memory capacity occupied by the system, and improving the stability of the flash memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic block diagram of a solid state drive is shown;

[0022] Figure 2 is an example diagram for illustrating the relationship between a die, a plane, a storage block, and a super block;

[0023] Figure 3 and Figure 4 Describes the timing diagram of write operation in two different situations;

[0024] Figure 5 It is used to illustrate the embodiment of the present invention. Figure 2 The super block is redesigned based on the flash memory chip 230 shown;

[0025] Figure 6 is a flowchart of a method for operating a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0027] The following describes the embodiments of the present disclosure based on the embodiments, but the embodiments of the present disclosure are not limited to these embodiments. In the detailed description of the embodiments of the present disclosure below, some specific details are described in detail. For those skilled in the art, the embodiments of the present disclosure can be fully understood without the description of these details. In order to avoid confusing the essence of the embodiments of the present disclosure, well-known methods, processes, processes, components and circuits are not described in detail.

[0028] Unless the context clearly requires otherwise, the words "include", "comprising", and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the embodiments of the present disclosure, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0029] The specific implementation of the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. However, before describing in detail, it should be pointed out that the various embodiments of the present disclosure are applicable to both solid-state drives and other storage products such as UFS.

[0030] Figure 1 A schematic block diagram of a solid state drive according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, the computer system 100 includes a host 110 and a solid state drive, the solid state drive includes a controller 120 and a storage medium 130, the controller 120 is connected to the host 110, and is used to receive read and write commands from the host 110. The controller 120 is connected to the storage medium 130, and is used to read data from the storage medium 130 and write data to the storage medium 130. The controller 120 is also used to return the read data to the host 110 according to the read command, or receive data to be written to the storage medium 130 from the host 110.

[0032] The controller 120 includes a host interface 121, a processor 123, a cache unit 124 and a media controller 128. The host interface 121 of the controller 120 is connected to the host 110 to transmit data and read and write commands. The processor 123 is connected to the host interface 121, the cache unit 124 and the media controller 128, and the processor 123 parses the read and write commands and performs read and write operations. The cache unit 124 is, for example, an SRAM, which is used to store a mapping table. The processor 123 is also used to execute the core software layer of memory control, namely FTL (flash translation layer, flash conversion layer). The FTL consists of several programs. The processor 123 executes the program so that when receiving the read and write commands, the commands can be converted to complete the reading and writing of the storage medium 130, so that the file system and operating system of the host 110 can access the storage medium like accessing their own memory. The FTL also has the characteristics of supporting bad storage block management, wear leveling, garbage collection, power failure recovery, write balancing technology, etc.

[0033] The cache unit 124 may use SRAM and / or DRAM. In comparison, SRAM as a cache has a speed advantage, but is more expensive and has a smaller storage capacity per unit space. Accordingly, in order to improve the utilization of cache space, a DRAM-less solid-state drive (no DRAM) uses a two-level mapping table for address management, that is, the first-level mapping table is stored in the SRAM, and the second-level mapping table is stored in the storage medium 130.

[0034] The media controller 128 controls data transmission with the storage medium 130. When the storage medium 130 is, for example, a flash memory chip array, in order to improve data read and write performance, the media controller 128 can read and write the flash memory chips of the storage medium 130 in parallel via multiple channels (for example, CH0 and CH2), and each channel is connected to a group of flash memory chips.

[0035] Figure 2 is an example diagram for illustrating the relationship between the die, plane, storage block and super block. As shown in the figure, the flash memory chip 230 (corresponding to Figure 1The storage medium 130) includes 4 dies, which are marked as die 0 to die 3 in the figure. Each die is divided into four planes, which are marked as p0 to p3 in the figure. Each plane is divided into 10 storage blocks, which are marked as b0 to b9 in the figure. Therefore, each die in the figure is divided into 40 storage blocks. The size of a storage block is generally 4096 bytes. The figure shows the connection channels channel0 and channel1 between the controller 220 and the flash memory chip 230. The dies die0 and die1 share channel channel0, so the planes p0 to p3 of the dies die0 and die1 share channel channel0, and the dies die2 and die3 share channel channel1, so the planes p0 to p3 of the dies die0 and die1 share channel channel1. Relying on channels channel0 to channel1, the controller 220 (corresponding to Figure 1 The controller 120 of the flash memory chip 230 can access each storage block. Table 1 is related to Figure 2 Schematic diagram of the corresponding storage block.

[0036] Table 1

[0037]

[0038] In Table 1, a memory block is identified by using the channel, die, plane and memory block encoding, for example<channel0,die0,p0,b0> It indicates the memory block with the pattern on the diagram.

[0039] It should be understood that although Figure 2 The flash memory chip 230 is shown to include four dies and each die is divided into four planes, but this is only an example. Based on design and operation considerations, the number of dies in the flash memory chip 230 can be any appropriate number, and the number of planes in each die can also be the same. Figure 2 The number of planes shown is different, and the set or predetermined number of storage blocks in each plane may also be different.

[0040] Instead of dividing the memory blocks according to physical locations, the controller 220 may group the memory blocks divided by rows and manage the memory blocks in the same group as a super block.

[0041] refer to Figure 2As shown in Table 1, the 16 storage blocks indicated by rows are divided into the same super block. The figure shows an exemplary super block A1. Super block A1 includes 16 storage blocks, which are<channel0,die0,p0,b0> ,<channel0,die0,p1,b0> ,<channel0,die0,p2,b0> ,<channel0,die0,p3,b0> ,<channel0,die1,p0,b0> ,<channel0,die1,p1,b0> ,<channel0,die1,p2,b0> ,<channel0,die1,p3,b0> ,<channel1,die2,p0,b0> ,<channel1,die2,p1,b0> ,<channel1,die2,p2,b0> ,<channel1,die2,p3,b0> ,<channel1,die3,p0,b0> ,<channel1,die3,p1,b0> ,<channel1,die3,p2,b0> and<channel1,die3,p3,b0> The identified storage block.

[0042] based on Figure 2 When the controller 220 writes data to the flash memory chip 230, the data is written into each die, each plane, each storage block, and each page by row. For example, for super block A1, the super block can be in a stable state only after all the above 16 storage blocks are written.

[0043] In addition, in order to improve performance, when writing data to the above super block, it can be processed in parallel, for example, using channels channel0 and chanel1 for parallel transmission and parallel writing.<channel0,die0,p0,b0> and<channel1,die2,p0,b0> The data of the indicated storage block. The more channels, the more conducive to parallel processing. However, the number of channels does not increase with the increase in the number of dies. Generally, the number of channels is only 2, 4 or 8, which is less than the number of dies. Multiple dies need to share channels. Therefore, the parallel performance of multiple dies does not increase linearly with the increase in the number of dies. Moreover, as the capacity of flash memory chips becomes larger and larger, a flash memory chip (such as NAND Flash contains 32 or more dies), when the parallel processing of multiple dies can no longer improve the performance, the super block cannot gain performance benefits by adding dies. As the super block increases, the unfavorable factors become more obvious. For example, the garbage collection and write operation time of a super block will be particularly long, and the super block needs to take a long time to complete the write operation of all the storage blocks in it and then close the super block, causing the super block to be in an unstable state for a long time.

[0044] Based on this, the embodiment of the present invention proposes how to reduce the size of the super block without affecting the performance. The following calculation method can be used for performance calculation.

[0045] Assume that the transmission time of each plane is ts, there are m planes in each die, and after the data transmission of the entire die is completed, the time for the die to write the transmitted data to the storage medium (such as flash memory) is tprog,. The page size in each plane is represented by PAGE_SIZE (PAGE_SIZE is equal to 16k, for example). Assume that the number of channels of the entire flash memory chip is n, and the number of dies connected to each channel is u. Assume that the preset performance is V MB / S.

[0046] Figure 3 and Figure 4 The following diagram describes the timing diagram of write operation in two different situations. Figure 3 and 4 In the figure, u dies share one channel, and one channel shares one set of transmission signal lines. Therefore, when one of the u dies is transmitting data, the other dies cannot transmit data. Then, if the channel is always in working state, that is, the signal line is always transmitting data signals, the performance is the maximum value. The writing process of each die is divided into the data transmission stage and the programming stage, which are marked by ts*m and tprog respectively.

[0047] like Figure 3As shown in the figure, in the ts*m stage of die0, die0 transmits data, then enters the tprog stage of die0 and the ts*m stage of die1, then enters the tprog stage of die1 and the ts*m stage of die2, and when the ts*m stage of die 2 ends, die 0 has completed the tprog stage. In this example, one channel corresponds to three dies, which can keep the channel in working state. That is, in this example, the performance of one channel corresponding to three dies is the maximum value.

[0048] like Figure 4 As shown in the figure, when die(u-1) completes the ts*m stage, die0 has not yet completed the tprog stage. It needs to wait for die0 to complete the tprog stage before entering the ts*m stage. Therefore, in this example, the performance does not reach the maximum value when one channel corresponds to u dies. Figure 3 For example, the way to optimize the super block is to reduce the number of tube cores corresponding to a super block to 3 tube cores, which can achieve the purpose of reducing the size of the super block without affecting the speed. Figure 4 For example, if you want to increase the size of the superblock.

[0049] The size of the super block can be estimated using the following formula.

[0050] Assume that the total transmission data of T die is: T*m*PAGE_SIZE, where m is the number of planes contained in each die, and PAGE_SIZE is the amount of data transmitted on each plane. Because after a single channel transmits the data of T die, die0 needs to complete the tprog time before it can be transmitted again. Therefore, the total time for a single channel to use T die to write is the total time for die0 to complete: ts*m+trog. Then, the maximum performance of the die combination under a single channel can be obtained: (T*m*PAGE_SIZE) / (ts*m+trog). This performance unit is converted into M / S. Assuming that the performance requirement of T die is VM / S, the preset performance requirement of each channel is V / n. As long as the following inequality (1) holds, T is the number of die that does not affect performance:

[0051] V / n <= (T * m * PAGE_SIZE) / ( ts * m + tprog) Formula (1)

[0052] In some embodiments, the sum of the transmission time of data transmitted by a single die and the writing time of the data from a single die to a storage block is multiplied by the preset performance of a single channel, and the obtained product is divided by the total amount of data transmitted by the single die to obtain the target number of dies, and then the target number of dies is rounded up to obtain the minimum number of dies T. Refer to formula (2).

[0053] T>=V / n*(ts*m+tprog) / (m*PAGE_SIZE) formula (2)

[0054] T can only be an integer value, so the optimal solution for T should be a positive integer that is larger than V / n*(ts*m+tprog) / (T*m*PAGE_SIZE) and closest to V / n*(ts*m+tprog) / (T*m*PAGE_SIZE). In the above formula, the values ​​of tprog and ts can be obtained by experimental means, or by referring to the various indicators in the user manual provided by the manufacturer to obtain these two values.

[0055] Figure 5 It is used to illustrate the embodiment of the present invention. Figure 2 As shown in the figure, assuming that according to the above formula, the size of the super block is calculated to be greater than or equal to 1 tube core, the performance reaches the preset performance requirement, and 1 is equal to half of the number of tube cores 2 connected by a single channel, then the reference Figure 5 In one embodiment, the storage blocks corresponding to die0 and die2 are grouped into a super block (i.e., A3 in the figure) by row, and the storage blocks corresponding to die1 and die3 are grouped into a super block (not shown in the figure) by row. In another embodiment, the storage blocks corresponding to die0 and die3 are grouped into a super block (not shown in the figure) by row, and the storage blocks corresponding to die1 and die2 are grouped into a super block (not shown in the figure) by row. It should be understood that in the above embodiment, the super blocks in the same row of the same die must be allocated to the same super block.

[0056] The embodiment of the present invention also provides a method for operating a memory, the memory includes a storage medium and a controller, the storage medium is composed of multiple tube cores, each tube core is divided into multiple planes, each plane is divided into multiple storage blocks, the controller connects multiple tube cores through one or more channels, the memory method is executed by the controller, and includes grouping multiple storage blocks to form a super block, and performing various operations on the storage medium based on the super block, the various operations referred to here include but are not limited to read operations, write operations and garbage collection. In this method, if Figure 6 As shown, the operation of grouping multiple storage blocks to form a super block includes the following steps:

[0057] In step S601, the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the channel is calculated.

[0058] In step S602, it is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to the same channel. If so, step S603 is executed, otherwise, step S604 is executed.

[0059] In step S603, the memory blocks are grouped based on the minimum number of dies to form a super block.

[0060] In step S604, the storage blocks are grouped according to the number of dies under each channel to form a super block.

[0061] For step S601, the preset performance achieved by each channel can be obtained by calculating V / n, where V is a preset performance index of the memory, and the preset performance index V can be determined according to the protocol, for example, the preset performance index is determined to be 560MB / s based on the SATA protocol, or can be determined according to the received user performance instruction, and n is the number of channels of multiple dies used to connect the controller and the storage medium, and then the maximum performance of the die combination of T dies under a single channel is calculated, that is, the data volume of all storage blocks under the T dies is divided by the sum of the time required to transmit the data volume and the write time of a single storage block, and then the inequality is set: V / n<=maximum performance of the die combination of T dies under a single channel, and the minimum value T that satisfies the inequality is obtained by solving the inequality. Continuing to refer to formula (1), in some embodiments, the inequality is: V / n<=(T*m*PAGE_SIZE) / (ts*m+tprog), and the minimum positive integer T that satisfies the inequality is obtained by solving. The minimum value T is the minimum number of dies that must be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance. It should be understood that the maximum performance here corresponds to the performance value when the channel is always in a busy state.

[0062] For steps S603 to S604, refer to Figure 3 and Figure 4 , Figure 3 The example shows that when the performance of the die combination under a single channel meets the requirement of being greater than or equal to the preset performance, the minimum number of dies required is 3, and 3 is less than u / 2. Then the storage blocks under u dies can be grouped according to 3 to form a super block. Figure 4 The example shows that when the performance of the die combination under a single channel satisfies the preset performance, the minimum number of dies required to be included is greater than u, so all storage blocks in the same row of u dies are divided into the same group.

[0063] It should be understood that the grouping of storage blocks based on the minimum number of tube cores to form a super block in step S603 can select the same number of tube cores in parallel from the tube cores connected to each channel according to the minimum number of tube cores to form a super block. Specifically, X tube cores (T≤X≤u / 2) are selected in one channel, and the same number of tube cores, that is, X tube cores, are also selected in another channel, that is, the same number of tube cores are selected in parallel from each channel to form a super block in a parallel relationship; similarly, other Y tube cores (T≤Y≤u / 2, and X+Y≤u) can be selected in one channel, and other Y tube cores can be selected in another channel to form another super block. Using the above-mentioned super block for parallel write operation can shorten the time required for super block stabilization without affecting the preset performance requirements, make the flash memory more stable, and achieve a balance between performance and stability. It should be understood that it does not mean that the number of tube cores contained in each super block must be equal to the minimum number of tube cores; and the fact that the number of tube cores contained in each channel of a super block is the same does not mean that the number of tube cores contained in each super block must be the same, that is, X and Y are not necessarily equal, X can be equal to Y, or it can be different from Y, which is not limited here.

[0064] In some embodiments, if the number of dies connected to the same channel is an integer multiple of the minimum number of dies, the number of storage blocks in the same row contained in multiple dies with the minimum number of dies can be evenly divided. For example, if there are M channels and each channel has N dies, and N is a multiple of T, then T dies are selected from the N dies in each channel of the M channels to form a super block (for example Figure 5 ). However, if in this example, N is not a multiple of T, you can do this: repeat the operation of selecting T die from the N die in each channel of the M channels to form a super block until the remaining die in each channel is less than T, then add the remaining die in each channel to any of the formed super blocks. For example, if the number of channels is 4, there are 10 die in each channel, and the calculated T is 3, then the die are first allocated according to 3, then 3 die are selected in each channel to form a super block, thus forming 3 super blocks, and then the remaining 1 die in each channel is arbitrarily added to any of the 3 super blocks. It should be understood that although the size of the super blocks can be different, it is more convenient for the controller to operate them by forming super blocks in a way of the same size.

[0065] According to this embodiment, a smaller super block is constructed without loss of performance, thereby reducing, for example, the unit time of garbage collection and the recovery time of system startup, saving the flash memory capacity occupied by the system, and improving the stability of the flash memory chip. The disclosed embodiment is particularly suitable for large-capacity flash memory chips, that is, flash memory chips containing more dies.

[0066] It should be understood that in this embodiment and the above embodiments, it is mentioned that the inequality: V / n<=(T*m*PAGE_SIZE) / (ts*m+tprog) can be used to compare performance, but this embodiment is not limited to this. Other algorithms can be used to obtain the preset performance of each channel and the maximum performance of the die combination under a single channel, so as to estimate the minimum number of dies required to be included when the performance is greater than or equal to the preset performance. For example, data is obtained by conducting experiments on solid-state drives and calculations are performed to obtain the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance.

[0067] In addition, an embodiment of the present disclosure further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above embodiments when executing the computer program.

[0068] Furthermore, the embodiments of the present disclosure further provide a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above embodiments are implemented.

[0069] The embodiments according to the embodiments of the present disclosure are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present disclosure, so that those skilled in the art can make good use of the embodiments of the present disclosure and the modified use based on the embodiments of the present disclosure. The embodiments of the present disclosure are limited only by the claims and their full scope and equivalents.

Claims

1. A method for grouping storage blocks in a memory, the memory comprising a storage medium and a controller, the storage medium comprising a plurality of dies, each of which is divided into a plurality of planes, each of which is divided into a plurality of storage blocks, the controller connecting the plurality of dies via a plurality of channels, the method being executed by the controller, and comprising grouping the plurality of storage blocks to form a super block, the grouping comprising: Based on the memory, calculating the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of the single channel; as well as It is determined whether the minimum number of dies is less than or equal to half of the number of dies connected to a single channel of the memory; if so, the plurality of memory blocks are grouped based on the minimum number of dies.

2. The method according to claim 1, further comprising: If the minimum number of dies is greater than half of the number of dies connected to a single channel, the storage blocks are grouped according to the number of dies under each channel to form a super block.

3. The method according to claim 1, wherein: The preset performance of each channel is equal to the preset performance index of the memory divided by the number of the multiple channels.

4. The method according to claim 1, wherein the minimum number of dies required to be included when the maximum performance of the die combination under a single channel is greater than or equal to the preset performance of a single channel comprises: The sum of the transmission time of data transmitted by a single die and the writing time of the data from the single die to the storage block is multiplied by the preset performance of the single channel, and the obtained product is divided by the total transmission data volume of the single die to obtain the target number of dies; The target number of dies is rounded up to obtain the minimum number of dies.

5. The method according to claim 1, wherein: The controller performs a write operation, a read operation, or garbage collection on the storage medium based on the super block.

6. The method according to claim 1, wherein: The same number of dies is selected in parallel from the dies connected to each channel according to the minimum number of dies to form a super block.

7. The method according to claim 6, wherein: The grouping of the storage blocks based on the minimum number of dies includes: if the number of dies connected to a single channel is an integer multiple of the minimum number of dies, evenly dividing the number of storage blocks in the same row contained in multiple dies of the minimum number of dies.

8. The method according to claim 6, wherein: The grouping of storage blocks based on the minimum number of dies includes: if the number of dies connected to the same channel is not an integer multiple of the minimum number of dies, first evenly dividing the storage blocks in the same row contained in multiple dies of the minimum number of dies, and then adding the remaining storage blocks to any group.

9. A memory controller, the memory comprising a storage medium and the controller, the storage medium consisting of a plurality of dies, each of which is divided into a plurality of planes, each of which is divided into a plurality of storage blocks, the controller connecting the plurality of dies via a plurality of channels, the controller executing the method described in any one of claims 1 to 8 to group the storage blocks to form a super block.

10. A memory comprising the controller according to claim 9 and a storage medium.

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