Operational circuit, function calculation method, processor, chip and electronic device

Abstract

The invention discloses an operational circuit, a function calculation method, a processor, a chip and electronic equipment, and belongs to the field of chips. The operational circuit comprises a plurality of basic function units and at least one configuration switch; the input ends and the output ends of different basic function units in the plurality of basic function units are electrically connected through a plurality of connecting lines, and at least one configuration switch is arranged on the plurality of connecting lines; the at least one configuration switch is used for conducting the plurality of connecting lines into a first calculation path in the at least two calculation paths based on the configured switch state, and each calculation path in the at least two calculation paths corresponds to one function calculation. The operational circuit supports the function calculation on hardware by configuring the switching state of at least one configuration switch, and when the calculated function is changed, only the switching state of at least one configuration switch needs to be modified, and the circuit does not need to be rebuilt.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to an operation circuit, a function calculation method, a processor, a chip and an electronic device. Background Art

[0002] Transcendental functions refer to functions whose relationship between variables cannot be expressed by a finite number of addition, subtraction, multiplication, division, exponentiation, or square root operations, such as trigonometric functions, logarithmic functions, inverse trigonometric functions, exponential functions, etc.

[0003] In the related art, transcendental functions are implemented in hardware through iterative approximation algorithms. The related art will build a circuit based on a pre-designed iterative approximation algorithm.

[0004] However, in the related art, once the circuit is designed, it cannot be updated. When an algorithm is updated, the circuit needs to be rebuilt to meet the requirements for algorithm performance and accuracy. Summary of the invention

[0005] The present application provides an operation circuit, a function calculation method, a processor, a chip and an electronic device. The operation circuit provided by the present application supports the implementation of function calculation on hardware by configuring the switch state of at least one configuration switch. When the calculated function changes, it is only necessary to modify the switch state of at least one configuration switch without rebuilding the circuit.

[0006] According to one aspect of the present application, there is provided an operation circuit, the operation circuit comprising a plurality of basic function units and at least one configuration switch;

[0007] Input terminals and output terminals of different basic function units among the plurality of basic function units are electrically connected via a plurality of connection lines, and at least one configuration switch is arranged on the plurality of connection lines;

[0008] At least one configuration switch is used to switch the plurality of connection lines into a first computing path of at least two computing paths based on a configured switch state, and each computing path of the at least two computing paths corresponds to a function calculation.

[0009] According to one aspect of the present application, a function calculation method is provided, the method is used to control the above-mentioned operation circuit, the method comprising:

[0010] By configuring the switch state of at least one configuration switch, the plurality of connection lines are connected to form a first computing path;

[0011] Based on at least one basic function unit electrically connected to the first calculation path, a function calculation corresponding to the first calculation path is completed.

[0012] According to another aspect of the present application, a function calculation device is provided, the device is used to control the above-mentioned operation circuit, and the device includes:

[0013] A configuration module, configured to connect the plurality of connection lines to a first computing path by configuring a switch state of at least one configuration switch;

[0014] The calculation module is used to complete the function calculation corresponding to the first calculation path based on at least one basic function unit electrically connected to the first calculation path.

[0015] According to one aspect of the present application, a processor is provided, and the processor includes the above-mentioned operation circuit.

[0016] According to one aspect of the present application, a chip is provided, the chip includes a processor, and the processor includes the above-mentioned operation circuit.

[0017] According to one aspect of the present application, a server is provided, and the server includes the above-mentioned operation circuit.

[0018] According to one aspect of the present application, an electronic device is provided. The electronic device includes a processor, and the processor includes the above-mentioned operation circuit.

[0019] According to one aspect of the present application, an electronic device is provided, the electronic device comprising: a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-mentioned function calculation method.

[0020] According to one aspect of the present application, a computer-readable storage medium is provided, which stores a computer program, and the computer program is loaded and executed by a processor to implement the above-mentioned function calculation method.

[0021] According to one aspect of the present application, a computer program product is provided. The computer program product stores a computer program, and the computer program is loaded and executed by a processor to implement the above-mentioned function calculation method.

[0022] The beneficial effects brought about by the technical solution provided in the embodiments of the present application include at least the following.

[0023] A plurality of connection lines are preset on the operation circuit provided in the present application, and the plurality of connection lines are used to connect the input ends and output ends of different basic function units in the plurality of basic function units. When the operation circuit of the present application is applied, the plurality of connection lines can be connected as a first calculation path through at least one configuration switch, and the first calculation path corresponds to a function calculation, that is, the operation circuit provided in the present application supports hardware function calculation by configuring the switch state of at least one configuration switch. When the calculated function changes, it is only necessary to modify the switch state of at least one configuration switch without rebuilding the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a schematic diagram of an operation circuit and a control method of the operation circuit provided in one embodiment of the present application.

[0026] Figure 2 It is a schematic diagram of an operation circuit provided by an embodiment of the present application.

[0027] Figure 3 It is a schematic diagram of an operation circuit provided by an embodiment of the present application.

[0028] Figure 4 It is a schematic diagram of an operation circuit provided by an embodiment of the present application.

[0029] Figure 5 It is a flowchart of a function calculation method provided by an embodiment of the present application.

[0030] Figure 6 It is a schematic diagram of a switch configuration method for layer 1 iterative operation provided by an embodiment of the present application.

[0031] Figure 7 It is a schematic diagram of a switch configuration method for layer 2 iterative operation provided by an embodiment of the present application.

[0032] Figure 8 It is a schematic diagram of a switch configuration method for layer 3 iterative operation provided by an embodiment of the present application.

[0033] Fig. 9 It is a schematic diagram of a switch configuration method for layer 4 iterative operation provided by an embodiment of the present application.

[0034] Fig.10It is a structural block diagram of a function computing device provided by an embodiment of the present application.

[0035] Fig.11 It is a structural block diagram of an electronic device provided by an embodiment of the present application.

[0036] Fig.12 It is a schematic diagram of the structure of a server provided in one embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] First, some terms in the embodiments of the present application are introduced:

[0039] Transcendental function: refers to a function whose relationship between variables cannot be expressed by a finite number of addition, subtraction, multiplication, division, exponentiation, and square root operations, such as trigonometric functions, logarithmic functions, inverse trigonometric functions, exponential functions, etc.

[0040] Basic function unit: refers to a hardware unit used to implement simple function functions. Several basic function units together implement complex function functions. For example, a basic function unit can be any one of an addition function unit, a subtraction function unit, a multiplication function unit, a division function unit, a reciprocal function unit, a power function unit, a square root function unit, an exponential function unit, and a logarithmic function unit.

[0041] Figure 1 A schematic diagram of an operation circuit and a control method of the operation circuit provided by an exemplary embodiment of the present application is shown. Figure 1 A graphics processing unit (GPU) 100 is shown. The graphics processor 100 includes an operation circuit 110 and a scheduler 120 . The operation circuit 110 includes a plurality of basic function units 101 , at least one configuration switch 102 and a register 103 .

[0042] exist Figure 1 In the illustrated operation circuit 110, a plurality of basic function units 101 are electrically connected via a plurality of connection lines, and at least one configuration switch 102 is disposed on the plurality of connection lines. In one embodiment, input terminals and output terminals of different basic function units 101 in the plurality of basic function units 101 are electrically connected via a plurality of connection lines, and at least one configuration switch 102 is disposed on the plurality of connection lines.

[0043] After the scheduler 120 runs the program, it will obtain the register value of the register 103. The scheduler 120 writes the register value of the register 103 into the register 103. At least one configuration switch configures its own switch state based on the register value stored in the register 103. Then, at least one configuration switch 102 connects the multiple connection lines to the first calculation path of at least two calculation paths based on its configured switch state. Each calculation path of the at least two calculation paths corresponds to a function calculation. When executing the function calculation corresponding to the first calculation path, at least one basic function unit connected based on the first calculation path is used on the operation circuit 110 to complete the function calculation corresponding to the first calculation path.

[0044] In one embodiment, Figure 1 The operation circuit 110 located on the graphics processor 100 is shown. In fact, the operation circuit provided by the present application can also run on a processor such as a central processing unit (CPU), an AI processor (artificial intelligence processor), etc., and the present application does not limit this.

[0045] An embodiment of the present application provides an operation circuit, which includes multiple basic function units and at least one configuration switch; the input end and the output end of different basic function units in the multiple basic function units are electrically connected through multiple connection lines, and at least one configuration switch is set on the multiple connection lines; at least one configuration switch is used to conduct the multiple connection lines into a first calculation path of at least two calculation paths based on the configured switch state, and each calculation path of the at least two calculation paths corresponds to a function calculation.

[0046] Multiple basic function units include function units that support the implementation of at least two function calculations. Basic function units refer to hardware units used to implement simple function functions, and several basic function units jointly implement complex function functions. In one embodiment, multiple basic function units include function units that support the implementation of at least two iterative approximation algorithms for transcendental functions. Transcendental functions refer to functions whose relationship between variables cannot be expressed by a finite number of addition, subtraction, multiplication, division, exponentiation, and square root operations. Transcendental functions are often implemented through iterative approximation algorithms. Therefore, different iterative approximation algorithms require different basic function units. Multiple basic function units in the present application support the implementation of at least two iterative approximation algorithms.

[0047] In one embodiment, the plurality of basic function units include function units that support at least two precision algorithms for implementing common functions (functions that can be implemented through finite operations). For common functions, even if the true function value can be obtained through finite operations, in some scenarios where the calculation accuracy is not required, the hardware resources required for practical applications can be saved by implementing a low-precision function algorithm through a small number of basic function units.

[0048] In one embodiment, multiple basic function units include function units that support the implementation of different types of function calculations, such as sine functions and cosine functions. Through at least one configuration switch, the hardware circuit that originally implements the sine function can be changed to a hardware circuit that implements the cosine function.

[0049] In one embodiment, the plurality of basic function units include at least one of an addition function unit, a subtraction function unit, a multiplication function unit, a division function unit, a reciprocal function unit, a power function unit, a square root function unit, an exponential function unit, and a logarithmic function unit.

[0050] The addition function unit, subtraction function unit, multiplication function unit, and division function unit are hardware units for realizing addition function, subtraction function, multiplication function, and division function, respectively. Optionally, each of the four function units includes two unknown quantity input terminals and one calculation result output terminal.

[0051] The reciprocal function unit is a hardware unit for implementing the reciprocal function. Optionally, the reciprocal function unit includes an unknown quantity input terminal and a calculation result output terminal. The exponentiation function unit is a hardware unit for implementing the exponentiation function. Optionally, the exponentiation function unit includes an unknown quantity input terminal, a power value input terminal and a calculation result output terminal. The square root function unit is a hardware unit for implementing the square root function. Optionally, the square root function unit includes an unknown quantity input terminal, a square root value input terminal and a calculation result output terminal. The exponential function unit is a function unit for implementing the exponential calculation function. Optionally, the exponential function unit includes an unknown quantity input terminal, a base input terminal and a calculation result output terminal. The logarithmic function unit is a hardware unit for implementing the logarithmic calculation function. Optionally, the logarithmic function unit includes an unknown quantity input terminal, a base input terminal and a calculation result output terminal.

[0052] At least one configuration switch is arranged on a plurality of connection lines, and the plurality of connection lines electrically connect the input and output ends of different basic function units in a plurality of basic function units. A configuration switch refers to a switch whose switch state is configurable. Optionally, the switch state of the configuration switch is configured by a register value of a register. Optionally, the configuration of the register value of the register is implemented by a program, and the scheduler (also referred to as a processor) reads and runs the program and then writes the register value to the register. In the operation circuit provided in the present application, by configuring the switch state of at least one configuration switch, a plurality of connection lines can be conducted into a first calculation path, and at least one basic function unit connected to the first calculation path is used to complete the function calculation corresponding to the first calculation path.

[0053] In one embodiment, a configuration switch is provided on each input / output line, and the input / output line refers to the connection line between the input end and the output end of different basic function units. Optionally, a configuration switch is also provided on the external connection line between the input end and the output end of the same basic function unit.

[0054] In one embodiment, the input and output ends of different basic function units in a plurality of basic function units are electrically connected through a plurality of media lines. For example, the input end of basic function unit A is electrically connected to media line 1, and the output end of basic function unit B is also electrically connected to media line 1; the output end of basic function unit A is electrically connected to media line 2, and the input end of basic function unit B is also electrically connected to media line 2. At this time, media lines 1 and 2 act as intermediate media to electrically connect the input and output ends of different basic function units in the two basic function units. Optionally, a configuration switch is provided on each intermediate line, and the intermediate line refers to the connection line between the input or output end of the basic function unit and the media line.

[0055] In one embodiment, the multiple basic function units include multiple types, and the number of basic function units of each type preset on the operation circuit is determined based on the function calculation that requires the largest number of basic function units in at least two function calculations. For example, the at least two function calculations include a first function calculation and a second function calculation, the first function calculation requires 4 basic function units A and 2 basic function units B, and the second function calculation requires 2 basic function units A and 5 basic function units B, then the multiple basic function units preset on the operation circuit include 4 basic function units A and 5 basic function units B.

[0056] To summarize, the computing circuit provided by the present application is preset with multiple connection lines, multiple basic function units, and at least one configuration switch set on the multiple connection lines. The multiple connection lines are used to connect the input ends and output ends of different basic function units in the multiple basic function units. When the computing circuit of the present application is applied, the function calculation on the hardware can be realized by configuring the switching state of at least one configuration switch. When the calculated function changes, it is only necessary to modify the switching state of at least one configuration switch to change the first computing path of at least two computing paths to the second computing path without rebuilding the circuit.

[0057] Figure 2 FIG. 1 shows a schematic diagram of an operation circuit provided by an exemplary embodiment of the present application. Figure 2 The illustrated operation circuit includes a plurality of basic function units and a plurality of configuration switches, and the plurality of basic function units include a basic function unit 210 , a basic function unit 220 , and a basic function unit 230 .

[0058] exist Figure 2 In the figure, the input terminal 211 of the basic function unit 210 is electrically connected to the output terminal 222 of the basic function unit 220, the output terminal 232 of the basic function unit 230 and its own output terminal 212 through a connecting line; the input terminal 221 of the basic function unit 220 is electrically connected to the output terminal 212 of the basic function unit 210, the output terminal 232 of the basic function unit 230 and its own output terminal 222 through a connecting line; the input terminal 231 of the basic function unit 230 is electrically connected to the output terminal 212 of the basic function unit 210, the output terminal 222 of the basic function unit 220 and its own output terminal 232 through a connecting line.

[0059] from Figure 2 It can be seen that the input ends and output ends of different basic function units among the multiple basic function units are electrically connected through multiple connection lines, and the multiple configuration switches are configured on the multiple connection lines.

[0060] Assumptions Figure 2 The multiple basic function units support multiple iterative approximation algorithms for implementing transcendental functions. When the first iterative approximation algorithm is adopted, the basic function units 210 and 220 among the multiple basic function units need to be used, and when the second iterative approximation algorithm is adopted, the basic function units 210 to 230 need to be used. At this time, the calculation accuracy achieved when the first iterative approximation algorithm is adopted is less than the calculation accuracy achieved by the second iterative approximation algorithm, but the number of basic function units required to implement the first iterative approximation algorithm is less than the number of basic function units required to implement the second iterative approximation algorithm.

[0061] exist Figure 2By configuring the switch states of multiple configuration switches, multiple connection lines can be turned into a calculation path corresponding to the first iterative approximation algorithm, and the calculation path at this time is connected with the basic function unit 210 and the basic function unit 220. Similarly, by configuring the switch states of multiple configuration switches, multiple connection lines can be turned into a calculation path corresponding to the second iterative approximation algorithm, and the calculation path at this time is connected with the basic function units 220 to 230. It can be seen that by Figure 2 The operation circuit shown can quickly upgrade the first iterative approximation algorithm to the second iterative approximation algorithm in hardware, and the upgraded hardware circuit can be easily built by configuring the switch states of multiple configuration switches without modifying and adjusting the hardware.

[0062] In one embodiment, the plurality of basic function units include a first basic function unit and / or a second basic function unit, and the input end of the first basic function unit is electrically connected to the output ends of at least two other basic function units except the first basic function unit. In this case, the at least two other basic function units may be some or all other basic function units except the first basic function unit on the operation circuit. If the at least two other basic function units are some other basic function units except the first basic function unit, the plurality of basic function units preset on the operation circuit may be partially connected according to actual calculation needs;

[0063] The output end of the second basic function unit is electrically connected to the input ends of at least two other basic function units except the second basic function unit. At this time, the at least two other basic function units can be part or all of the other basic function units on the circuit except the second basic function unit. If the at least two other basic function units are part of the other basic function units except the second basic function unit, at this time, the multiple basic function units preset on the operation circuit can be partially connected according to the actual calculation needs.

[0064] Figure 3 Part (A) shows that the input terminal 311 of the first basic function unit 310 is electrically connected to the output terminals 321 of other basic function units 320 except the first basic function unit 310 and the output terminals 331 of other basic function units 330 .

[0065] At this time, at least one configuration switch is set on the connection line between the input end of the first basic function unit and the output end of other basic function units except the first basic function unit. By configuring the switching state of at least one configuration switch, the first calculation path can be turned on.

[0066] In one embodiment, the input terminal of the first basic function unit is electrically connected to the output terminals of all other basic function units except the first basic function unit. Figure 3 Part (A) shows this situation. Optionally, the input terminal of the first basic function unit is electrically connected to at least one external input terminal of the operation circuit. Optionally, at least one external input terminal of the operation circuit is electrically connected to the peripheral circuit. Optionally, the external input terminal of the operation circuit communicates with the peripheral circuit through a valid-enable handshake protocol. Optionally, at least one external input terminal of the operation circuit is used to input constants and / or variables required for function calculation. Optionally, an external input terminal of an operation circuit is used to input multiple constants and / or variables. Optionally, an external input terminal of an operation circuit is used to input a constant or variable.

[0067] Figure 3 Part (B) shows that the output terminal 341 of the second basic function unit 340 is electrically connected to the input terminal 351 of other basic function units 350 except the second basic function unit 340 and the input terminal 361 of other basic function units 360 .

[0068] At this time, at least one configuration switch is set on the connection line between the output end of the second basic function unit and the input end of other basic function units except the second basic function unit. By configuring the switching state of at least one configuration switch, the first calculation path can be turned on.

[0069] In one embodiment, the output terminal of the second basic function unit is electrically connected to the input terminals of all other basic function units except the second basic function unit. Figure 3 Part (B) shows this situation. Optionally, the output terminal of the second basic function unit is electrically connected to at least one output terminal of the operation circuit, and optionally, at least one output terminal of the operation circuit is electrically connected to the peripheral circuit. Optionally, the output terminal of the operation circuit communicates with the peripheral circuit via a valid-enable handshake protocol. Optionally, at least one output terminal of the operation circuit is used to output the function value obtained by executing the function calculation.

[0070] Register configuration:

[0071] In one embodiment, the switch state of at least one configuration switch is configured by a register. Optionally, a register is further provided on the operation circuit, and a register value of the register is used to configure the switch state of at least one configuration switch. Optionally, the number of registers is at least one, and there is a one-to-one relationship and / or a one-to-many relationship between at least one register and at least one configuration switch.

[0072] In one embodiment, each register in the at least one register corresponds to one configuration switch in the at least one configuration switch; or, the at least one register simultaneously includes a register corresponding to only one configuration switch and a register corresponding to multiple configuration switches; or, the number of the at least one register is one, and the register simultaneously corresponds to all configuration switches in the at least one configuration switch.

[0073] In the case where there is a one-to-one relationship between at least one register and at least one configuration switch, the configuration switch corresponding to the register configured as the first value is in the off state (conducting the line), and the configuration switch corresponding to the register configured as the second value is in the on state (disconnecting the line). Schematically, the configuration switch corresponding to the register configured as 1 is in the off state, that is, the connecting line is turned on, and the configuration switch corresponding to the register configured as 0 is in the on state, that is, the line is disconnected. At this time, the switch state of a configuration switch is configured by a register. When a register fails, it will only affect the single configuration switch corresponding to the register, thereby effectively reducing the coverage of the fault. At this time, only the configuration switch corresponding to another similar basic function unit needs to be started to ensure the normal execution of the function calculation, and the fault tolerance rate is high.

[0074] In the case where there is a one-to-many relationship between at least one register and at least one configuration switch, the switch states of the multiple configuration switches are configured according to the first bit sequence configured by the register, the first bit sequence includes multiple bits corresponding to the multiple configuration switches one by one, and schematically, the first bit sequence is 1010, then the configuration switches A, B, C, and D are configured to be off, on, off, and on, respectively. At this time, configuring the switch states of multiple configuration switches through one register can save the use of registers, and using fewer registers is more friendly to the layout and routing of the circuit, effectively reducing the hardware density of the circuit.

[0075] In one embodiment, the register value of the register is configured by the scheduler according to the program running result, and each configuration switch will read the register value from the register to configure its own switch state.

[0076] In the above embodiment, by configuring the switch state of at least one configuration switch through the configuration register, multiple connection lines can be connected to the first calculation path without changing the hardware. Then, when the calculated function changes, the at least one configuration switch can be configured through the configuration register to modify the first calculation path to the second calculation path, so as to realize the function calculation corresponding to the second calculation path without changing the hardware.

[0077] N-layer iterative operation:

[0078] In one embodiment, the first calculation path includes n layers of iterative operations, and the output end of the basic function unit for implementing the i-th layer of iterative operations is electrically connected to the input end of the basic function unit for implementing the i+1-th layer of iterative operations, wherein n is a positive integer greater than 1, and i is a positive integer. When the function calculation corresponding to the first calculation path is executed by the operation circuit, it is not that another basic function unit can be executed only after one basic function unit is executed, but multiple basic function units may be executed in parallel. Therefore, the first function calculation corresponding to the first calculation path will include n layers of iterative operations, and one or more basic function units may be executed simultaneously when executing each layer of iterative operations.

[0079] In an embodiment of the present application, by configuring the switching state of at least one configuration switch, the output end of the basic function unit used to implement the i-th layer iterative operation in the n-th layer iterative operation will be electrically connected to the output end of the basic function unit used to implement the i+1-th layer iterative operation.

[0080] Examples:

[0081] Figure 4 FIG. 2 shows an operation circuit provided by an exemplary embodiment of the present application. Figure 4 The implementation of the tanh function (a transcendental function) is used as an example. The tanh function has a variety of iterative approximation algorithms. Figure 4 In this paper, an iterative approximation algorithm will be implemented through a computational circuit:

[0082] f(x)=A+B*(x-x0)+C*(x-x0)*(x-x0);

[0083] Before executing a specific function calculation, the switch state of the relevant configuration switches on the operation circuit provided in the present application is configured to be in the off state (conducting), and the switch state of the remaining configuration switches is configured to be in the on state (disconnected). Figure 4 In the figure, a “black dot” indicates that the corresponding configuration switch is configured to be in the off state.

[0084] When executing a specific function calculation, the constants A, B, C, and x0 required to implement the above-mentioned iterative approximation algorithm are input into the operation circuit through the external input terminal (input) of the operation circuit, and the variable x required for the above-mentioned iterative approximation algorithm is input into the operation circuit through the external input terminal of another operation circuit.

[0085] During the first layer of iterative operations, the value of x-x0 is calculated through the addition function unit;

[0086] During the second-level iterative operation, the value of (x-x0)*(x-x0) is calculated by one multiplication function unit, and the value of B*(x-x0) is calculated by another multiplication function unit, and the two multiplication function units operate synchronously.

[0087] During the third-level iterative operation, the value of A+B*(x-x0) is calculated through an addition function unit, and the value of C*(x-x0)*(x-x0) is calculated through a multiplication function unit, and the two function units run synchronously.

[0088] During the fourth layer of iterative operations, an addition function unit is used to calculate the value of A+B*(x-x0)+C*(x-x0)*(x-x0), thereby obtaining the value of tanh(x).

[0089] pass Figure 4 The iterative approximation algorithm implemented by the operation circuit shown only needs to configure the switch state of the relevant configuration switch to conduct the calculation path of the iterative approximation algorithm. Assuming that the iterative approximation algorithm is updated and upgraded at this time to achieve more accurate calculation of the tanh function, through the operation circuit provided by the present application, it is only necessary to reconfigure the switch state of at least one configuration switch on the operation circuit without modifying the hardware.

[0090] Next, the function calculation method based on the above-mentioned operation circuit will be introduced.

[0091] Figure 5 A flow chart of a function calculation method provided by an exemplary embodiment of the present application is shown, and the method is illustrated by an example in which the method is executed by an electronic device. Optionally, the electronic device that implements the function calculation and the electronic device on which the above-mentioned operation circuit is built are the same device or different devices. The function calculation method of the present application includes:

[0092] Step 520, connecting the plurality of connection lines to a first computing path by configuring a switch state of at least one configuration switch;

[0093] The first calculation path is any one of at least two calculation paths. The first calculation path is a conduction mode of multiple connection lines, and the multiple connection lines support the conduction modes corresponding to at least two calculation paths. The operation circuit provided in the present application can be implemented as any one of at least two calculation paths. In the operation circuit provided in the present application, at least one configuration switch is set on the multiple connection lines, and the multiple connection lines are used to electrically connect the input and output ends of different basic function units in the multiple basic function units.

[0094] In one embodiment, the switch state of at least one configuration switch is configured by configuring the register value of the configuration register, so that the multiple connection lines are connected to form a first computing path. Optionally, the switch state of at least one configuration switch is configured by configuring the register value of at least one register; wherein there is a one-to-one relationship or a one-to-many relationship between at least one register and at least one configuration switch.

[0095] In the case where there is a one-to-one relationship between at least one register and at least one configuration switch, for a first register in the at least one register, by configuring the register value of the first register to be a first value, the configuration switch corresponding to the first register is configured to be in an off state (conducting the circuit); and / or, for a second register in the at least one register, by configuring the register value of the second register to be a second value, the configuration switch corresponding to the second register is configured to be in an on state (disconnecting the circuit).

[0096] Illustratively, by configuring the register value of the first register to 1, the configuration switch corresponding to the first register will be in an off state. By configuring the register value of the second register to 0, the configuration switch corresponding to the second register will be in an on state. By configuring the first register and / or the second register, multiple connection lines can be connected to form a first computing path.

[0097] In the case where there is a one-to-many relationship between at least one register and at least one configuration switch, the switch state of at least one configuration switch is configured to be an off state by configuring the register value of the third register to be a third value, and / or the switch state of at least one configuration switch is configured to be an on state by configuring the register value of the fourth register to be a fourth value.

[0098] Schematically, by configuring the register value of the third register to "1111", at least one configuration switch is configured to be in an off state; schematically, by configuring the register value of the fourth register to "0000", at least one configuration switch is configured to be in an on state. By configuring the third register and / or the fourth register, multiple connection lines can be connected to form a first computing path.

[0099] Step 540: Complete the function calculation corresponding to the first calculation path based on at least one basic function unit electrically connected to the first calculation path.

[0100] In the computing circuit provided in the present application, multiple connection lines can be turned on as a first computing path by configuring at least one configuration switch, and then, at least one basic function unit electrically connected based on the first computing path can complete the function calculation corresponding to the first computing path.

[0101] To summarize, a plurality of connection lines are preset on the operation circuit provided in the present application, and the plurality of connection lines are used to connect the input ends and output ends of different basic function units in a plurality of basic function units. When the operation circuit of the present application is applied, the plurality of connection lines are conducted as a first calculation path through at least one configuration switch, and the first calculation path corresponds to a function calculation, that is, the operation circuit provided in the present application supports hardware function calculation by configuring the switch state of at least one configuration switch. When the calculated function changes, it is only necessary to modify the switch state of at least one configuration switch without rebuilding the circuit.

[0102] In one embodiment, the first computation path includes n layers of iterative operations, and the first computation path is obtained by configuring the switch state of at least one configuration switch to conduct the connection line between the output end of the basic function unit for implementing the i-th layer of iterative operations and the input end of the basic function unit for implementing the i+1-th layer of iterative operations in multiple connection lines, where n is a positive integer greater than 1, and i is a positive integer. When the function operation corresponding to the first computation path is executed, the configuration switches corresponding to the n-layer iterative operations are not necessarily configured to be in the off state (conducting lines) at the same time. For example, the configuration switches corresponding to the i+1-layer iterative operations (or the i+2-layer iterative operations, the i+3-layer iterative operations, etc.) may be configured to be in the off state when the i-layer iterative operations are executed. It is also possible that the configuration switches corresponding to all the n-layer iterative operations have been configured before the function calculation is executed. At this time, the configuration timing of the configuration switches has a specific role in some scenarios.

[0103] Configuration opportunity 1:

[0104] By configuring the switch state of the configuration switch corresponding to each layer of iterative operation in the n layers of iterative operation before executing the n layers of iterative operation, and then connecting the connection line between the output end of the basic function unit for implementing the i-th layer of iterative operation and the input end of the basic function unit for implementing the i+1-th layer of iterative operation in multiple connection lines, the first calculation path is obtained.

[0105] Indicative, with reference Figure 4 According to the above analysis, Figure 4 The tanh function calculation shown includes four layers of iterative operations. Before executing the tanh function calculation, the switch state of the configuration switch corresponding to each layer of iterative operation in the four layers of iterative operations is configured to obtain a first calculation path, that is, Figure 4 The configuration switches corresponding to all the "black dots" in the figure are configured to be in the off state.

[0106] At this time, the switch status of all configuration switches that need to be configured is configured before executing the function calculation, which can avoid changing the configuration switches within a short period of time during the function calculation, ensuring the stability of the function calculation process and the accuracy of the calculation results. Changing the configuration switches within a short period of time requires high time control.

[0107] Configuration opportunity 2:

[0108] By configuring the switch state of the configuration switch corresponding to the i+1th layer iterative operation during the execution of the i-th layer iterative operation, and then connecting the connection line between the output end of the basic function unit for implementing the i-th layer iterative operation and the input end of the basic function unit for implementing the i+1th layer iterative operation in multiple connection lines, the first calculation path is obtained.

[0109] Combined with reference Figure 6 , Figure 6 The schematic diagram shows the configuration switch for configuring the first layer of iterative operation. Before starting to execute the function calculation, configure Figure 6 The configuration switches corresponding to the two “black dots” in the figure are turned on, and then the first layer of iteration is performed. When the first layer of iteration is performed, x and x0 are input and x-x0 is output.

[0110] Combined with reference Figure 7 , Figure 7 A schematic diagram of a configuration switch for configuring a second-layer iteration operation is shown. During the execution of the first-layer iteration operation, the configuration Figure 7 The configuration switches corresponding to the four “black dots” in FIG. When performing the second-level iterative operation, two (x-x0) are input into a multiplication function unit to obtain (x-x0)*(x-x0), and (x-x0) and B are input into another multiplication function unit to obtain B*(x-x0).

[0111] Combined with reference Figure 8 , Figure 8 A schematic diagram of a configuration switch for configuring a layer 3 iteration operation is shown. During the execution of a layer 2 iteration operation, the configuration Figure 8 The configuration switches corresponding to the four “black dots” in the figure. When performing the third-level iterative operation, (x-x0)*(x-x0) and C are input into a multiplication function unit to obtain C*(x-x0)*(x-x0), and B*(x-x0) and A are input into an addition function unit to obtain A+B*(x-x0).

[0112] Combined with reference Fig. 9 , Fig. 9 A schematic diagram of a configuration switch for configuring a layer 4 iteration operation is shown. During the execution of a layer 3 iteration operation, the configuration Fig. 9The three “black dots” in the figure correspond to the configuration switches. When executing the 4th layer iterative operation, C*(x-x0)*(x-x0) and A+B*(x-x0) are input into an addition function unit, and A+B*(x-x0)+C*(x-x0)*(x-x0) is output. Finally, A+B*(x-x0)+C*(x-x0)*(x-x0) is output to the external output terminal through the operation circuit.

[0113] At this time, when executing the i-th layer iterative operation, the switch state of the configuration switch corresponding to the i+1-th layer iterative operation is configured, and the function calculation can be executed concurrently and quickly. In the present application, the scheduler reads and runs the program and then configures the register value and then configures the corresponding configuration switch. This process takes a certain amount of time. If the function calculation is executed only after all the configuration switches are configured, the waiting time is longer. Configuring the i+1-th layer iterative operation when executing the i-th layer iterative operation can allow the circuit to run earlier and reduce the waiting time.

[0114] Middle solution:

[0115] The two configuration timing schemes introduced above each have their own advantages and disadvantages. In some scenarios, by configuring the i+k-th layer iterative operation (k is a preset positive integer greater than 1) during the i-th layer iterative operation, the advantages of both configuration timing schemes can be taken, the implementation difficulty is reduced, and it can be applied to more scenarios.

[0116] Fig.10 The structure block diagram of a function calculation device provided by an exemplary embodiment of the present application is shown, and the function calculation device is used to control the operation circuit provided by the above embodiment, and the device includes:

[0117] A configuration module 1001, configured to connect a plurality of connection lines to a first computing path by configuring a switch state of at least one configuration switch;

[0118] The calculation module 1002 is configured to complete the function calculation corresponding to the first calculation path based on at least one basic function unit electrically connected to the first calculation path.

[0119] In an optional embodiment, the configuration module 1001 is further used to configure the switch state of at least one configuration switch through the register value of the configuration register, so that the multiple connection lines are connected to form a first computing path.

[0120] In an optional embodiment, the configuration module 1001 is further configured to configure a switch state of at least one configuration switch by configuring a register value of at least one register;

[0121] There is a one-to-one relationship or a one-to-many relationship between at least one register and at least one configuration switch.

[0122] In an optional embodiment, there is a one-to-one relationship between at least one register and at least one configuration switch; the configuration module 1001 is further configured to configure a configuration switch corresponding to a first register in the at least one register to be in an off state by configuring the register value of the first register to be a first value;

[0123] and / or,

[0124] For a second register in the at least one register, a configuration switch corresponding to the second register is configured to be in an on state by configuring the register value of the second register to be a second value.

[0125] In an optional embodiment, the first computing path of the at least two computing paths includes n layers of iterative operations, where n is a positive integer greater than 1. The configuration module 1001 is further used to connect the connection line between the output end of the basic function unit for implementing the i-th layer of iterative operations and the input end of the basic function unit for implementing the i+1-th layer of iterative operations in the multiple connection lines by configuring the switch state of at least one configuration switch, so as to obtain the first computing path, where i is a positive integer.

[0126] In an optional embodiment, the configuration module 1001 is also used to configure the switch state of the configuration switch corresponding to each layer of iterative operation in the n layers of iterative operation before executing the n layers of iterative operation, thereby connecting the connection line between the output end of the basic function unit for implementing the i-th layer of iterative operation and the input end of the basic function unit for implementing the i+1-th layer of iterative operation in multiple connection lines to obtain a first calculation path.

[0127] In an optional embodiment, the configuration module 1001 is also used to configure the switch state of the configuration switch corresponding to the i+1th layer iterative operation during the execution of the i-th layer iterative operation, thereby connecting the connection lines between the output end of the basic function unit for implementing the i-th layer iterative operation and the input end of the basic function unit for implementing the i+1th layer iterative operation in multiple connection lines to obtain the first calculation path.

[0128] To summarize, a plurality of connection lines are preset on the operation circuit provided in the present application, and the plurality of connection lines are used to connect the input ends and output ends of different basic function units in a plurality of basic function units. When the operation circuit of the present application is applied, the plurality of connection lines can be connected as a first calculation path through at least one configuration switch. The first calculation path corresponds to a function calculation, that is, the operation circuit provided in the present application supports hardware function calculation by configuring the switch state of at least one configuration switch. When the calculated function changes, it is only necessary to modify the switch state of at least one configuration switch without rebuilding the circuit.

[0129] Fig.11 The structure block diagram of an electronic device 1100 provided by an exemplary embodiment of the present application is shown. Optionally, the electronic device 1100 includes the operation circuit provided by the embodiment of the present application, and / or is used to execute the function calculation method provided by the present application.

[0130] Optionally, the electronic device may be a portable mobile terminal, such as a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer, or a desktop computer. The electronic device 1100 may also be referred to as a user device, a portable terminal, a laptop terminal, a desktop terminal, or other names. Typically, the electronic device 1100 includes a processor 1101 and a memory 1102.

[0131] The processor 1101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1101 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1101 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1101 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1101 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0132] The memory 1102 may include one or more computer-readable storage media, which may be non-transitory. The memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices.

[0133] In some embodiments, the electronic device 1100 may further include: a peripheral device interface 1103 and at least one peripheral device. Those skilled in the art will appreciate that Fig.11 The structure shown in the figure does not constitute a limitation on the electronic device 1100, and may include more or less components than those shown in the figure, or combine certain components, or adopt a different component arrangement.

[0134] The present application also provides a processor, which includes the operation circuit as described in the above embodiment.

[0135] The present application also provides a chip, the chip includes a processor, and the processor includes the computing circuit as described in the above embodiment.

[0136] The present application also provides a graphics card, which includes the computing circuit as described in the above embodiment.

[0137] The present application also provides a server, which includes the computing circuit as described in the above embodiment.

[0138] Fig.12 A schematic diagram of the structure of a server provided by an exemplary embodiment of the present application is shown. The server 1200 includes multiple graphics processors 1201. At least one of the multiple graphics processors 1201 integrates a computing circuit 1202 provided by the present application. Fig.12 The diagram shows a situation where each of the multiple graphics processors 1201 is integrated with a computing circuit 1202 .

[0139] The present application also provides a computer-readable storage medium, in which at least one instruction, at least one program, a code set or an instruction set is stored. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the function calculation method provided in the above method embodiment.

[0140] The present application provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes the function calculation method provided by the above method embodiment.

Claims

1. A computing circuit, characterized in that: The operation circuit includes a plurality of basic function units and at least one configuration switch; The input terminals and output terminals of different basic function units among the plurality of basic function units are electrically connected via a plurality of connection lines, and the at least one configuration switch is arranged on the plurality of connection lines; The at least one configuration switch is used to connect the plurality of connection lines to a first computing path of at least two computing paths based on a configured switch state, and each computing path of the at least two computing paths corresponds to a function calculation.

2. The operation circuit according to claim 1, characterized in that: The plurality of basic function units include a first basic function unit and / or a second basic function unit; An input terminal of the first basic function unit is electrically connected to output terminals of at least two other basic function units except the first basic function unit; An output terminal of the second basic function unit is electrically connected to input terminals of at least two other basic function units except the second basic function unit.

3. The operation circuit according to claim 2, characterized in that: The input end of the first basic function unit is electrically connected to the output ends of all other basic function units except the first basic function unit, and is electrically connected to at least one external input end of the operation circuit.

4. The operation circuit according to claim 2, characterized in that: The output terminal of the second basic function unit is electrically connected to the input terminals of all other basic function units except the second basic function unit, and is electrically connected to at least one output terminal of the operation circuit to the outside.

5. The operation circuit according to any one of claims 1 to 4, characterized in that: The first computation path includes n layers of iterative operations, where n is a positive integer greater than 1; The output end of the basic function unit for implementing the i-th layer iterative operation is electrically connected to the input end of the basic function unit for implementing the i+1-th layer iterative operation, and i is a positive integer.

6. The operation circuit according to any one of claims 1 to 4, characterized in that: The operation circuit further includes a register; a register value of the register is used to configure a switch state of the at least one configuration switch.

7. The operation circuit according to claim 6, characterized in that: The number of the register is at least one, and there is a one-to-one relationship and / or a one-to-many relationship between the at least one register and the at least one configuration switch.

8. The operation circuit according to claim 7, characterized in that: There is a one-to-one relationship between at least one of the registers and the at least one configuration switch; The configuration switch corresponding to the register configured to the first value is in the off state, and the configuration switch corresponding to the register configured to the second value is in the on state.

9. The operation circuit according to any one of claims 1 to 8, characterized in that: The multiple basic function units include at least one of an addition function unit, a subtraction function unit, a multiplication function unit, a division function unit, a reciprocal function unit, a power function unit, a square root function unit, an exponential function unit, and a logarithmic function unit.

10. A function calculation method, characterized in that: The method is used to control the operation circuit according to any one of claims 1 to 9, and the method comprises: By configuring the switch state of the at least one configuration switch, the plurality of connection lines are connected to form the first computing path; Based on at least one basic function unit electrically connected to the first calculation path, a function calculation corresponding to the first calculation path is completed.

11. The method according to claim 10, characterized in that The step of configuring the switch state of the at least one configuration switch to conduct the plurality of connection lines into the first computing path comprises: The switch state of the at least one configuration switch is configured by configuring the register value of the configuration register, so that the plurality of connection lines are connected to form the first computing path.

12. The method according to claim 11, characterized in that Configuring the switch state of the at least one configuration switch by using the register value of the configuration register includes: Configuring a switch state of the at least one configuration switch by configuring a register value of at least one of the registers; There is a one-to-one relationship or a one-to-many relationship between at least one of the registers and the at least one configuration switch.

13. The method according to claim 12, characterized in that There is a one-to-one relationship between at least one of the registers and the at least one configuration switch; Configuring the switch state of the at least one configuration switch by configuring the register value of at least one of the registers includes: For a first register of at least one of the registers, configuring a register value of the first register to be a first value, so that a configuration switch corresponding to the first register is in an off state; and / or, For a second register in at least one of the registers, by configuring the register value of the second register to be a second value, a configuration switch corresponding to the second register is configured to be in an on state.

14. The method according to claim 10, characterized in that The first computing path of the at least two computing paths includes n layers of iterative operations, where n is a positive integer greater than 1; The step of configuring the switch state of the at least one configuration switch to conduct the plurality of connection lines into the first computing path comprises: By configuring the switching state of the at least one configuration switch, the connection line between the output end of the basic function unit for implementing the i-th layer iterative operation and the input end of the basic function unit for implementing the i+1-th layer iterative operation in the multiple connection lines is turned on to obtain the first calculation path, where i is a positive integer.

15. The method according to claim 14, characterized in that The step of configuring the switch state of the at least one configuration switch to conduct the connection line between the output end of the basic function unit for implementing the i-th layer iterative operation and the input end of the basic function unit for implementing the i+1-th layer iterative operation in the plurality of connection lines to obtain the first calculation path includes: The first calculation path is obtained by configuring the switching state of the configuration switch corresponding to each layer of iterative operation in the n layers of iterative operation before executing the n layers of iterative operation, and connecting the output end of the basic function unit used to implement the i-th layer of iterative operation and the input end of the basic function unit used to implement the i+1-th layer of iterative operation in the multiple connection lines.

16. The method according to claim 14, characterized in that The step of configuring the switch state of the at least one configuration switch to conduct the connection line between the output end of the basic function unit for implementing the i-th layer iterative operation and the input end of the basic function unit for implementing the i+1-th layer iterative operation in the plurality of connection lines to obtain the first calculation path includes: By configuring the switching state of the configuration switch corresponding to the i+1th layer iterative operation during the execution of the i-th layer iterative operation, the connection line between the output end of the basic function unit used to implement the i-th layer iterative operation and the input end of the basic function unit used to implement the i+1th layer iterative operation in the multiple connection lines is turned on, thereby obtaining the first calculation path.

17. A function computing device, characterized in that: The device is used to control the operation circuit according to any one of claims 1 to 9, and the device comprises: A configuration module, configured to connect the plurality of connection lines to the first computing path by configuring a switch state of the at least one configuration switch; The calculation module is used to complete the function calculation corresponding to the first calculation path based on at least one basic function unit electrically connected to the first calculation path.

18. A processor, characterized in that: The processor comprises the computing circuit as claimed in any one of claims 1 to 9.

19. A chip, characterized in that: The chip includes a processor, and the processor includes the computing circuit as described in any one of claims 1 to 9.

20. A server, characterized in that: The server comprises the computing circuit as claimed in any one of claims 1 to 9.

21. An electronic device, characterized in that: The electronic device comprises a processor, and the processor comprises the computing circuit as claimed in any one of claims 1 to 9.

22. An electronic device, characterized in that: The electronic device comprises: a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the function calculation method as described in any one of claims 10 to 16.

23. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the function calculation method as described in any one of claims 10 to 16.

24. A computer program product, characterized in that The computer program product stores a computer program, and the computer program is loaded and executed by a processor to implement the function calculation method according to any one of claims 10 to 16.

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