System calling method, processing device, chip and electronic equipment

Abstract

The embodiment of the invention discloses a system calling method, a processing device, a chip and electronic equipment, relates to the field of computers, and solves the problems of relatively low running efficiency and relatively high running cost of a processor when the processor switches a running state to access resources corresponding to different programs in the prior art. According to the specific scheme, the system calling method is provided and comprises the steps that a processor obtains a first instruction part of a block instruction under a first privilege level, the first instruction part is used for indicating a second instruction part of the block instruction and a specified register, and the specified register is a register used when the second instruction part is executed; the first instruction part comprises instructions of a first privilege level, the second instruction part comprises instructions of a second privilege level, the first privilege level is lower than the second privilege level, and the specified register is a part of the global registers in the plurality of global registers. In accordance with the first instruction portion, a second instruction portion is executed, and the specified register is used when the second instruction portion is executed.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular to a system call method, a processing device, a chip, and an electronic device. Background Art

[0002] The processor performs very complex computing and control tasks. For example, the processor needs to run multiple applications and also run the operating system (OS) that manages the multiple applications. The operating system can also be called a computer management control program. In order to limit the scope of resources accessed by the processor when running different programs, protect resources such as memory, input / output (I / O), and avoid security issues such as operating system crashes, the processor includes multiple operating states (or privilege levels). The operating system assigns a privilege level to each program and allocates corresponding resources. For example, the operating state of the processor includes kernel state (or operating system privilege level) and user state (or application privilege level). The operating system assigns an operating system privilege level to the operating system kernel and an application privilege level to each application. By switching the operating state, the processor can run different programs and access the resources corresponding to the programs without unlimited access to resources.

[0003] However, in the prior art, when the processor switches the running state to access resources corresponding to different programs, the running efficiency of the processor will be low and the running cost will be high. Summary of the invention

[0004] The embodiments of the present application provide a system call method, a processing device, a chip and an electronic device, which solve the problem in the prior art that when the processor switches the operating state to access resources corresponding to different programs, the processor has low operating efficiency and high operating cost.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In a first aspect of an embodiment of the present application, a system call method is provided, which is applied to an electronic device including a processor, the processor is used to execute a block instruction, the processor includes multiple global registers, the method includes: the processor obtains a first instruction part of the block instruction at a first privilege level, the first instruction part is used to indicate a second instruction part of the block instruction and a designated register, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the global registers among the multiple global registers. According to the first instruction part, the second instruction part is executed, and the designated register is used when executing the second instruction part.

[0007] The above-mentioned block instruction refers to an instruction set including a first instruction part and a second instruction part. The first instruction part corresponds to the second instruction part. The first instruction part can also be called a block header, and the second instruction part can also be called a block body. The first instruction part includes instructions of the first privilege level, and the second instruction part includes instructions of the second privilege level.

[0008] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, etc., and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, etc. The embodiments of the present application are not limited to this.

[0009] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0010] Optionally, taking the example of a processor including M global registers, the above-mentioned designated register may include 1 global register, or may include N global registers out of the M global registers, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0011] Optionally, when the designated register includes multiple global registers, some of the multiple global registers can be used to obtain the second instruction part, and other global registers can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers can be used to obtain the second instruction part and store the result after the second instruction part is executed. The embodiments of the present application are not limited to this.

[0012] Based on this scheme, the processor first obtains the first instruction part of the block instruction at the first privilege level, and the first instruction part is used to indicate the second instruction part of the block instruction and the designated register used when executing the second instruction part. Among them, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, and the designated register is a part of the global registers of the multiple global registers included in the processor. Then, the processor executes the second instruction part according to the first instruction part, and uses the designated register when executing the second instruction part. Compared with the prior art, in which the application switches the operating state of the processor through system calls, saves the context, and then obtains and executes the instructions of the privilege level of the operating system through all global registers, the processor adopts the system call method provided by the embodiment of the present application, and can access the resources corresponding to the program of the second privilege level through the designated register without switching the operating state, saving the context, and executing the second instruction part of the second privilege level to realize the function of the second privilege level, so as to improve the operating efficiency of the processor and reduce the operating cost.

[0013] In combination with the first aspect, in one implementation, the second instruction portion includes at least one instruction, and the method further includes: storing the execution result of the at least one instruction in a designated register. Alternatively, the processor further includes a dedicated register, storing the first execution result of the at least one instruction in the dedicated register, and storing the second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

[0014] Based on this solution, by storing the first execution result of at least one instruction in a dedicated register and the second execution result in a global register, more instructions can be scheduled for calculation compared to the pipeline technology in the prior art, thereby improving the scheduling efficiency and the performance of the processor.

[0015] In conjunction with the first aspect, in one implementation, the first instruction portion is obtained by the processor during the process of running a program of the first privilege level, and the program of the first privilege level includes the first instruction portion. The second instruction portion is executed by the processor during the process of running the program of the first privilege level.

[0016] Based on this solution, when the processor runs a program of the first privilege level, the processor obtains the first instruction part, and the program of the first privilege level includes the first instruction part. When the processor runs the program of the first privilege level, the second instruction part is executed according to the first instruction part, so that the program of the first privilege level realizes the function of the second privilege level. Therefore, the processor can access the resources corresponding to the program of the second privilege level without switching the running state and saving the context, and execute the second instruction part of the second privilege level to realize the function of the second privilege level, thereby improving the operating efficiency of the processor and reducing the operating cost.

[0017] In combination with the first aspect, in one implementation, the first instruction part includes address information, the address information is used to indicate the address of the second instruction part, and executing the second instruction part according to the first instruction part includes: executing the second instruction part according to the address information.

[0018] Based on this solution, the first instruction part includes address information, and the address information is used to indicate the address of the second instruction part, so that the processor can execute the second instruction part according to the first instruction part. The processor can access the resources corresponding to the program of the second privilege level without switching the running state and saving the context, and execute the second instruction part of the second privilege level to implement the function of the second privilege level, thereby improving the operating efficiency of the processor and reducing the operating cost.

[0019] In combination with the first aspect, in one implementation, the second instruction part includes authentication information, and before executing the second instruction part according to the address information, the method further includes: determining whether the second instruction part is legal according to the authentication information.

[0020] Based on this solution, the second instruction part includes authentication information, and the processor determines that the second instruction part is legal based on the authentication information, thereby avoiding the execution of the second instruction part that affects the security and reliability of the operating system. Therefore, the security and reliability of the system call method provided in the embodiment of the present application can be improved.

[0021] In combination with the first aspect, in one implementation, the first instruction part includes indication information, there is a corresponding relationship between the indication information and the second instruction part, and the second instruction part is executed according to the first instruction part, including: determining and executing the second instruction part corresponding to the indication information according to the indication information and the corresponding relationship.

[0022] Based on this solution, the first instruction part includes indication information, and there is a corresponding relationship between the indication information and the second instruction part. The processor determines and executes the second instruction part according to the indication information and the corresponding relationship, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system according to the first instruction part. Therefore, the security and reliability of the system call method provided in the embodiment of the present application can be improved.

[0023] In combination with the first aspect, in one implementation, the first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

[0024] In a second aspect of an embodiment of the present application, a processing device is provided, the processing device is used to execute a block instruction, the processing device includes a global engine, and a block engine coupled to the global engine and a plurality of global registers. The global engine is used to obtain a first instruction part of a block instruction when the processing device is running at a first privilege level, the first instruction part is used to indicate a second instruction part of the block instruction and a designated register, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of a first privilege level, the second instruction part includes instructions of a second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the global registers among the plurality of global registers. The global engine is also used to schedule the block engine to execute the second instruction part according to the first instruction part, and use the designated register when executing the second instruction part.

[0025] In conjunction with the second aspect, in one implementation, the second instruction portion includes at least one instruction. The block engine is used to store the execution result of the at least one instruction in a designated register. Alternatively, the block engine includes a dedicated register, the block engine is used to store the first execution result of the at least one instruction in the dedicated register, and store the second execution result in the dedicated register in the designated register, and the first execution result includes the second execution result.

[0026] In conjunction with the second aspect, in one implementation, the first instruction portion is acquired by the processing device during the process of running a program of the first privilege level, and the program of the first privilege level includes the first instruction portion. The second instruction portion is executed by the processing device during the process of running the program of the first privilege level.

[0027] In combination with the second aspect, in one implementation, the first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. The global engine is specifically used to schedule the block engine to execute the second instruction part according to the address information.

[0028] In combination with the second aspect, in one implementation, the second instruction part includes authentication information, and the global engine is further used to determine the legitimacy of the second instruction part based on the authentication information before the global engine schedules the block engine to execute the second instruction part based on the address information.

[0029] In conjunction with the second aspect, in one implementation, the first instruction part includes indication information, and there is a corresponding relationship between the indication information and the second instruction part. The global engine is specifically used to determine the second instruction part corresponding to the indication information according to the indication information and the corresponding relationship, and the scheduling block engine executes the second instruction part.

[0030] In conjunction with the second aspect, in one implementation, the first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

[0031] In a third aspect of the embodiments of the present application, a system call device is provided, the system call device is used to implement the system call method described in the first aspect or any possible implementation of the first aspect, the system call device includes an acquisition module and a processing module. Exemplarily, the acquisition module is used to support the acquisition operation of the system call device, such as acquiring the first instruction part. The processing module is used to control and manage the actions of the system call device, and is used to execute the processing operation performed by the system call device in the above embodiment, such as executing the second instruction part.

[0032] According to a fourth aspect of an embodiment of the present application, a chip is provided, which includes a cache memory and a processing device coupled to the cache memory, wherein the processing device is the processing device described in the second aspect or any possible implementation of the second aspect.

[0033] Optionally, the chip may be a processor, which may be a central processing unit, or a micro control unit, which may also be called a single-chip microcomputer, and the embodiments of the present application are not limited to this.

[0034] According to a fifth aspect of an embodiment of the present application, an electronic device is provided. The electronic device includes a memory and a chip coupled to the memory, wherein the chip is the chip described in the fourth aspect or any possible implementation of the fourth aspect.

[0035] Optionally, the above-mentioned storage device may be a memory, or may be a hard disk, which is not limited in the embodiments of the present application.

[0036] Optionally, the type of the electronic device may include a computer, a laptop computer, a smart watch, a smart bracelet, a smart phone, a smart car machine, a drone, etc. The embodiments of the present application do not limit the specific type of the electronic device.

[0037] In a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program runs on a processor, the processor executes the steps in the system call method as described in the first aspect or any possible implementation of the first aspect.

[0038] In a seventh aspect of the embodiments of the present application, a computer program product is provided. When the computer program product runs on a processor, the processor executes the steps in the system call method as described in the first aspect or any possible implementation of the first aspect.

[0039] The descriptions of the second to seventh aspects of the present application can refer to the detailed description of the first aspect; and the beneficial effects described in the second to seventh aspects can refer to the beneficial effect analysis of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a process of executing instructions by a processor;

[0041] Figure 2 A schematic diagram of a process in which a processor uses pipeline technology to execute instructions;

[0042] Figure 3 A schematic diagram of a process of executing instructions using a processor using block instruction technology;

[0043] Figure 4 A schematic diagram of the relationship between a program and a privilege level;

[0044] Figure 5 A flowchart of a system calling method provided in an embodiment of the present application;

[0045] Figure 6 A schematic diagram of a process for executing instructions using block instruction technology by a processor provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the relationship between a program and a privilege level provided in an embodiment of the present application;

[0047] Figure 8A flowchart of another system calling method provided in an embodiment of the present application;

[0048] Fig. 9 A schematic diagram of the structure of a system calling device provided in an embodiment of the present application;

[0049] Fig.10 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0050] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided by this application can be implemented in a variety of specific environments. The specific embodiments discussed are only illustrative of specific ways to implement and use this description and this technology, and do not limit the scope of this application.

[0052] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0053] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when the specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuits that perform an operation, etc.

[0054] The technical scheme in the embodiment of the present application will be described below in conjunction with the accompanying drawings in the embodiment of the present application. In the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiment of the present application, the words "first", "second" and the like do not limit the quantity and order.

[0055] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0056] Before introducing the embodiments of the present application, the technical terms and background technologies involved in the present application are first introduced.

[0057] Operating system kernel: The operating system kernel is the core part of the operating system, responsible for the system's memory management, hardware device management, file system management, and application management. The operating system kernel provides a set of services that allow applications to interact with computer hardware. The operating system kernel and applications are interdependent. The operating system kernel is responsible for managing the computer's resources, while applications perform user operations by calling the services provided by the operating system kernel.

[0058] Privilege level: A term used in computer operating systems to refer to a special level of user-mode processes or threads. The purpose of privilege level division is to ensure the security and stability of the system. By assigning different operations and resources to different privilege levels, the operating system can ensure that sensitive operations can only be performed by processes or threads with sufficient permissions, thereby preventing accidental or malicious behavior from affecting the system.

[0059] Context: refers to the values ​​of the processor's internal registers and program counter, as well as the address of the program counter, and also includes some other data stored inside the processor.

[0060] like Figure 1 As shown, it is a schematic diagram of the process of a processor 110 executing instructions. The processor 110 is coupled to the memory 120, and the processor 110 includes a computing unit 111 and an internal memory (also referred to as a register) 112 coupled to each other. The memory 120 stores an instruction sequence, and the instruction sequence includes at least one instruction arranged in an execution order. When the processor 110 executes an instruction, the processor 110 first obtains an instruction from the instruction sequence in the execution order and stores it in the internal memory 112. Then the computing unit 111 obtains the instruction from the internal memory 112 to complete the calculation, and returns the calculation result to the internal memory 112. Finally, the processor 110 stores the calculation result in the internal memory 120 to the memory 120 or the hard disk to complete the calculation of the instruction. The processor 110 continuously obtains instructions from the instruction sequence in the execution order to complete the calculation of the instruction sequence.

[0061] In order to improve the performance of the processor 110, the processor 110 may use pipeline technology. Figure 2 As shown, it is a schematic diagram of a process of the processor 110 executing instructions using pipeline technology. The processor 110 can start executing the next instruction when one instruction is not completed, thereby improving the performance of the processor 110. For example, taking the example that the processor 110 needs time t to execute each instruction, the processor 110 can start executing the next instruction when the time to execute one instruction does not reach t, ​​thereby improving the efficiency and performance of the processor 110.

[0062] However, when there is a dependency between instructions in the instruction sequence, the computational efficiency and performance of the processor 110 will be reduced. For example, when the computation of the third instruction in the instruction sequence requires the execution result of the second instruction to complete the computation, the third instruction can only be executed after the execution of the second instruction is completed, which will reduce the efficiency and performance of the processor 110.

[0063] In order to solve this problem, the processor 110 can use superscalar technology. For example, taking the case where the first instruction and the second instruction in the instruction sequence have a dependency relationship, and the calculation of the second instruction requires the calculation result of the first instruction, the processor 110 can first guess the calculation result of the first instruction in the process of processing the first instruction and the second instruction, and calculate the second instruction according to the guessed result. If the guessed result is the same as the calculation result of the first instruction, the calculation result of the second instruction can be used directly. If the guessed result is different from the calculation result of the first instruction, the second instruction is recalculated, thereby improving the computing efficiency and performance of the processor 110. In some instruction execution scenarios that require fewer guessed results, such as instruction execution scenarios such as conditional judgment, the processor 110 can use this superscalar technology.

[0064] In order to improve the performance of the processor 110, the processor 110 may also use block instruction technology. Figure 3 As shown, it is a schematic diagram of a process of executing instructions using a block instruction technology by a processor 110. At this time, the processor 110 includes a global engine 113, and at least one global register 114 and at least one block engine 115 coupled to the global engine 113. Each global register 114 and each block engine 115 can be coupled under the control of the global engine 113 to transmit instructions or calculation results. Each block engine 115 includes a dedicated register 1151. The memory 120 stores a first instruction partial sequence and a second instruction partial sequence. Each instruction in the first instruction partial sequence is used to indicate at least one instruction in the second instruction partial sequence, as well as the global register 114 used by the processor 110 when executing the at least one instruction. The second instruction partial sequence includes at least one instruction.

[0065] Among them, each instruction in the first instruction sequence can be called a "block header", and at least one instruction in the second instruction sequence indicated by the block header can be called a "block body", and each block header and the block body corresponding to the block header constitute a block instruction. The global engine 113 is used to obtain and schedule the block header in the first instruction sequence, determine the global register 114 used in the corresponding block body calculation process according to the block header, and allocate the block engine 115 used when calculating the block body. The global register 114 is used to obtain the block body corresponding to the block header and transmit it to the block engine 115. The block engine 115 is used to complete the calculation of the block body. The result of the block body calculation process can be stored in the dedicated register 1151, and the result after the block body calculation is completed is transmitted to the global register 114. The global register 114 transmits the calculation result of the block body to the memory 120 to complete the calculation of the block instruction. The processor 110 executes instructions by adopting block instruction technology. Compared with the above-mentioned pipeline technology, it can schedule more instructions for calculation, thereby improving scheduling efficiency and improving the performance of the processor 110. It can also improve the single-thread execution performance of the processor 110 by setting multiple block engines 115.

[0066] For example, an instruction sequence includes 5 instructions, and there are dependencies between the 5 instructions. The processor 110 can construct a block instruction, which includes a block header and a block body. The block header is used to indicate the 5 instructions and the global register 114 used to execute the 5 instructions, and the block body includes the 5 instructions. When the processor 110 executes the block instruction, the global engine 113 obtains the block header of the block instruction, determines the global register 114 used when calculating the block body of the block instruction, and allocates the block engine 115 used to calculate the block body to complete the calculation of the block instruction. The specific process can refer to the above description and will not be repeated here.

[0067] The processor 110 handles increasingly complex computing and control tasks. For example, the processor 110 needs to run multiple applications and also run an operating system that manages the multiple applications. In order to limit the scope of resources accessed by the processor 110 when running different programs, protect resources such as memory, input / output, and avoid security issues such as operating system crashes, the processor 110 includes multiple running states. The operating system assigns a privilege level to each program and allocates corresponding resources. For example, the running state of the processor includes kernel state and user state. The operating system assigns an operating system privilege level to the operating system kernel and an application privilege level to each application. When the processor runs a program at the application privilege level, it can be said that the processor is at the application privilege level, or that the running state of the processor is user state. When the processor runs a program at the operating system privilege level, it can be said that the processor is at the operating system privilege level, or that the running state of the processor is kernel state. By switching the running state, the processor 110 can run different programs and access the resources corresponding to the programs without unlimited access to resources.

[0068] For example, Figure 4 , which is a schematic diagram of the relationship between a program and a privilege level. The operating state of the processor 110 includes an operating system privilege level (also referred to as a supervisor privilege level) and an application privilege level (also referred to as a user privilege level). The operating system can assign an operating system privilege level to the operating system kernel, assign an application privilege level to each application, and allocate corresponding resources. Each application can be referred to as an "instance" of an application privilege level.

[0069] Among them, the running state of the processor 110 can be switched under the control of the operating system, so that it runs at different privilege levels at different times. When the processor 110 is at the operating system privilege level, the processor 110 can run the operating system kernel and access resources managed by the operating system kernel, such as memory, I / O and other resources. When the processor 110 is at the application privilege level, the processor 110 can run the application program and access the resources corresponding to the application program. When the application program running by the processor 110 requires the operating system kernel to provide services or resources, such as reading files, creating processes, accessing the hardware and software resources of the operating system, etc., the application program can issue a system call (syscall), which can also be called a system service request, requesting the operating system to switch the running state of the processor 110 to the operating system privilege level and execute the corresponding instructions to complete the corresponding operation. Thereby, the scope of the processor 110 accessing resources when running the program can be limited, and the processor 110 cannot access all resources at will, which can avoid security issues such as operating system crashes.

[0070] Since the storage resources (e.g., global registers 114) in the processor 110 are limited, the processor 110 needs to use the storage resources when executing the instructions of each application program. Therefore, the processor 110 needs to save the context and release the storage resources when switching the running state. Specifically, each time the running state of the processor 110 switches from the application privilege level to the operating system privilege level, the value of the register used by the application program needs to be saved, and then the instructions of the operating system privilege level are executed. This process is called "saving the user process context", or it can be called "saving the context".

[0071] For example, Figure 4 As shown, the processor 110 is at the application privilege level, and the first application program running needs to access the resources of the operating system. Figure 4 As shown in (1), the processor 110 can save the context according to the system call instruction in the first application program, for example, the context can be saved in the memory 120, and the running state of the processor 110 can be switched to the operating system privilege level, the operating system kernel can be restored to control the processor 110, and the instructions specified by the operating system can be executed. Figure 4 As shown in (2), after the processor 110 executes the instructions specified by the operating system, the running state can be switched to the application privilege level, and the instructions of the first application can be resumed according to the saved context to continue running the first application.

[0072] However, when the processor 110 switches the running state and saves the context to access the resources corresponding to different programs, the running efficiency of the processor 110 will be low and the running cost will be high.

[0073] For example, the processor 110 is an advanced RISC machine (ARM) V8 architecture processor, including 32 global registers 114, and the processor 110 executes a word processing (Microsoft Word, Word) application program, and the Word program requires the operating system kernel to provide a file reading service, and the operating state of the processor 110 needs to be switched from the application privilege level to the operating system privilege level. Before switching the operating state, the 32 global registers 114 store the data of the Word program. First, the processor 110 needs to store the data in the 32 global registers 114 in the memory 120, and then store the instructions corresponding to the file reading service in the operating system kernel in the 32 global registers 114, and then execute the instructions corresponding to the file reading service. However, storing the data of the Word program in the 32 global registers 114 in the memory 120 requires occupying the storage space in the memory 120 and consumes a lot of time. Storing the instructions corresponding to the file reading service in the operating system kernel in the 32 global registers 114 also requires a lot of time, which will lead to a reduction in the operating efficiency of the processor 110 and a high operating cost.

[0074] In order to solve the problem that the processor 110 has low operating efficiency and high operating cost when switching operating states to access resources corresponding to different programs. The embodiment of the present application provides a system call method, which can improve the operating efficiency of the processor 110 and reduce the operating cost. The system call method provided in the embodiment of the present application can be applied to physical computers, virtual machines, and various types of operating systems, and the embodiment of the present application is not limited to this.

[0075] like Figure 5 As shown, it is a flowchart of a system call method provided by an embodiment of the present application, and the method includes steps S501-S502. The system call method is applied to an electronic device including a processor, and the processor includes multiple global registers, and the processor is used to execute block instructions. The block instruction refers to an instruction set including a first instruction part and a second instruction part, the first instruction part corresponds to the second instruction part, the first instruction part can also be called a block header, and the second instruction part can also be called a block body, the first instruction part includes instructions of a first privilege level, and the second instruction part includes instructions of a second privilege level.

[0076] For example, the electronic device may be a computer, and the processor may be the above-mentioned Figure 3 The processor 110 shown in FIG. 1 may be the global register 114 described above. The system call method in the embodiment of the present application is applied to the following example: Figure 3 The processor 110 shown is taken as an example for exemplary description, and the description of each component in the above processor 110 can be referred to in the following embodiments.

[0077] S501. The processor 110 obtains a first instruction part of a block instruction at a first privilege level, where the first instruction part is used to indicate a second instruction part of the block instruction and a designated register, where the designated register is a register used when executing the second instruction part. The first instruction part includes instructions of a first privilege level, and the second instruction part includes instructions of a second privilege level. The first privilege level is lower than the second privilege level, and the designated register is a part of global registers 114 among a plurality of global registers 114.

[0078] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, etc., and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, etc. The embodiments of the present application are not limited to this.

[0079] Exemplarily, the first privilege level may be an application privilege level, and the second privilege level may be an operating system privilege level. The following embodiments of the present application take the first privilege level as an application privilege level and the second privilege level as an operating system privilege level as an example for exemplary description.

[0080] In a possible embodiment, the first instruction part includes instructions of the application privilege level, and the first instruction part may include instructions generated by the compiler according to the program of the application privilege level. The second instruction part includes instructions of the operating system privilege level, and the second instruction part may include instructions generated by the compiler according to the program of the operating system privilege level. The embodiment of the present application does not limit the specific type of the application privilege level program.

[0081] Optionally, the compiler for compiling the application privileged level program and the compiler for compiling the operating system privileged level program may be the same compiler or different compilers, which is not limited in the embodiments of the present application.

[0082] For example, taking the application privilege level program as a Word program, the operating system privilege level program as an operating system kernel, and using different compilers for compilation as an example, the first instruction part may include instructions generated by the application compiler based on the compilation of the Word program, and the second instruction part may include instructions generated by the operating system compiler based on the compilation of the operating system kernel.

[0083] In a possible embodiment, Figure 6 As shown, the processor 110 is coupled to the memory 120. Since the first instruction part includes instructions of the application privilege level, the first instruction part can be stored in the storage area of ​​the application privilege level in the memory 120, and the second instruction part includes instructions of the operating system privilege level, the second instruction part can be stored in the storage area of ​​the operating system privilege level in the memory.

[0084] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0085] In a possible embodiment, the above-mentioned processor 110 obtains the first instruction part of the block instruction at the first privilege level, including: when the processor 110 runs at the application privilege level, the global engine 113 in the processor 110 can control the global register 114 to obtain the first instruction part of the block instruction from the storage area of ​​the application privilege level in the memory 120.

[0086] Optionally, taking the example that the processor 110 includes M global registers 114, the above-mentioned designated registers may include 1 global register 114, or may include N global registers 114 out of the M global registers 114, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0087] For example, taking the example that the processor 110 includes 32 global registers 114 , the designated registers may include 3 global registers 114 .

[0088] Optionally, when the designated register includes multiple global registers 114, some of the multiple global registers 114 can be used to obtain the second instruction part, and other global registers 114 can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers 114 can be used to obtain the second instruction part and store the result after the second instruction part is executed. The embodiments of the present application are not limited to this.

[0089] For example, taking the case where the designated register includes three global registers 114, two of the global registers 114 can be used to obtain the second instruction part, and the other global register 114 can be used to store the result after the second instruction part is executed. Alternatively, one of the global registers 114 can be used to obtain the second instruction part, and the other two global registers 114 can be used to store the result after the second instruction part is executed. Alternatively, the three global registers 114 can be used to obtain the second instruction part, and can also be used to store the result after the second instruction part is executed.

[0090] In a possible embodiment, the first instruction portion is obtained by the processor 110 during the process of executing a program of a first privilege level, and the program of the first privilege level includes the first instruction portion.

[0091] For example, during the process of the processor 110 running a Word program at an application privilege level, the processor 110 obtains a first instruction portion, and the Word program includes the first instruction portion.

[0092] In a possible embodiment, the processor 110 may be a central processing unit (CPU), which is not limited in the embodiment of the present application.

[0093] S502: The processor 110 executes the second instruction part according to the first instruction part, and uses a designated register when executing the second instruction part.

[0094] In a possible embodiment, the first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. For example, the address information can be a pointer. The processor 110 executes the second instruction part according to the first instruction part, including: the processor 110 executes the second instruction part according to the address information.

[0095] In a possible embodiment, the second instruction part includes at least one instruction, and the processor 110 executes the second instruction part, including: storing the execution result of the at least one instruction in a designated register. Alternatively, the processor 110 includes a special register 1151, storing the first execution result of the at least one instruction in the special register 1151, and storing the second execution result in the special register 1151 in the designated register, and the first execution result includes the second execution result.

[0096] Wherein, when the second instruction part includes one instruction, the first execution result includes the execution result of the instruction, and the execution result of the instruction is the second execution result. When the second instruction part includes multiple instructions, the first execution result includes the result after each instruction is executed, and the result after the last instruction of the multiple instructions is executed is the second execution result.

[0097] For example, Figure 6As shown, the processor 110 also includes a block engine 115, and the block engine 115 includes the above-mentioned dedicated register 1151. Taking the second instruction part including two instructions and the designated register including one global register 114 as an example, the above-mentioned processor 110 executes the second instruction part, specifically including: first, the block engine 115 obtains and executes the first instruction of the two instructions from the global register 114, and stores the result of the execution of the first instruction in the dedicated register 1151. Then, the block engine 115 obtains the second instruction of the two instructions from the designated register, executes the second instruction according to the execution result of the first instruction, and stores the result of the execution of the second instruction in the dedicated register 1151. Finally, the execution result of the second instruction part is stored in the global register 114 to complete the execution of the two instructions. It can be understood that the first execution result includes the execution result of the first instruction and the execution result of the second instruction, and the second execution result is the execution result of the second instruction. By storing the first execution result of the two instructions in the dedicated register 1151 and the second execution result in the global register 114, compared with the above-mentioned pipeline technology, more instructions can be scheduled for calculation, thereby improving the scheduling efficiency and the performance of the processor 110. The single-thread execution performance of the processor 110 can also be improved by setting multiple block engines 115.

[0098] In a possible embodiment, the second instruction portion is executed by the processor 110 during the process of running a program of the first privilege level. When the processor 110 executes the second instruction portion, the program of the first privilege level implements the function of the second privilege level.

[0099] Optionally, the functions of the second privilege level include: creating a new process, executing a system call, managing memory, accessing a file system, etc., which is not limited to the embodiments of the present application.

[0100] For example, taking the program of the first privilege level as a Word program and the function of the second privilege level as accessing the file system as an example, when the block engine 115 in the processor 110 executes the second instruction part, the Word program can implement the function of accessing the file system.

[0101] To facilitate understanding of the system call method provided by the present application, an example is given below in which the processor 110 runs a Word program.

[0102] like Figure 7As shown, it is a schematic diagram of the relationship between a program and a privilege level. For example, the operating state of the processor 110 includes an application privilege level and an operating system privilege level. The operating system grants the Word program and other application programs an application privilege level, and grants the operating system kernel an operating system privilege level. The instructions compiled by the Word program include a third instruction, a first instruction part, and a fourth instruction. The instructions compiled by the operating system kernel include a second instruction part, and the second instruction part is used to implement the function of accessing system files. When the processor 110 runs at the application privilege level and runs the Word program, the processor 110 can execute the third instruction compiled and generated by the Word program in sequence. When a user uses the Word program to input text, and the Word program needs to implement the function of accessing system files, such as Figure 7 As shown in (1), the processor 110 can obtain the first instruction part, obtain and execute the second instruction part through the specified register according to the first instruction part, so as to realize the function of accessing the system file. When the processor 110 completes the execution of the second instruction part, it can continue to execute the fourth instruction. It can be understood that by adopting the system call method provided in the embodiment of the present application, in the process of the Word program realizing the function of accessing the system file, the processor 110 does not need to save the context, does not need to wait for the data in the global register 114 to be stored in the memory 120, and then executes the second instruction part, so the operating efficiency of the processor 110 can be improved and the operating cost can be reduced.

[0103] In a possible embodiment, when the processor 110 executes a program of the first privilege level to implement the function of the second privilege level, it needs to execute a large number of instructions, and it takes a lot of time to obtain and execute instructions through designated registers. In this case, the system call method provided in the embodiment of the present application may not be adopted. The compiler may generate system call instructions based on the compilation of the program of the first privilege level. The processor 110 switches the running state according to the system call instructions, saves the context, and uses all global registers 114 in the processor 110 to obtain and execute instructions, thereby improving the running efficiency of the processor.

[0104] In the system call method provided in the embodiment of the present application, the processor 110 first obtains the first instruction part of the block instruction at the first privilege level, and the first instruction part is used to indicate the second instruction part of the block instruction and the designated register used when executing the second instruction part. Among them, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, and the designated register is a part of the global registers 114 of the multiple global registers 114 included in the processor 110. Then, the processor 110 executes the second instruction part according to the first instruction part, and uses the designated register when executing the second instruction part. Compared with the prior art, in which the application switches the operating state of the processor through the system call, saves the context, and then obtains and executes the instructions of the privilege level of the operating system through all global registers, the processor 110 can access the resources corresponding to the program of the second privilege level through the designated register without switching the operating state and saving the context, and execute the second instruction part of the second privilege level to realize the function of the second privilege level, thereby improving the operating efficiency of the processor 110 and reducing the operating cost.

[0105] In a possible embodiment, in order to improve the security and reliability of the system call method provided in the embodiment of the present application, the first instruction part and / or the second instruction part may be restricted to prevent the processor 110 from obtaining the second instruction part that affects the security and reliability of the operating system according to the first instruction part. For example, the first instruction part includes address information. If the first instruction part is not restricted, the address information may point to the second instruction part of the access password, which will result in lower security and reliability of the operating system. Various implementation methods are illustrated below.

[0106] like Figure 8 As shown, in a possible embodiment, the above-mentioned second instruction part may include authentication information. The system call method provided in the embodiment of the present application also includes step S503 before the processor 110 executes the second instruction part according to the address information in the above-mentioned step S502.

[0107] S503: The processor 110 determines, based on the authentication information, that the second instruction portion is legal.

[0108] Specifically, the global engine 113 in the processor 110 can determine whether the second instruction part is legal based on the authentication information in the second instruction part after acquiring the second instruction part and before executing the second instruction part. When it is determined that the second instruction part is legal, the processor 110 executes the second instruction part, thereby avoiding the execution of the second instruction part that affects the security and reliability of the operating system.

[0109] In a possible embodiment, the authentication information may include at least one special character, and the global engine 113 may determine whether the second instruction part is legal based on the at least one special character.

[0110] In a possible embodiment, the special characters in the above-mentioned authentication information can be generated by the compiler according to the compilation of the program of the second privilege level, and the global engine 113 can determine whether the second instruction part is legal according to whether the authentication information includes special characters and whether the format of the authentication information is correct.

[0111] In the system call method provided in the embodiment of the present application, the second instruction part includes authentication information, and the processor 110 determines that the second instruction part is legal based on the authentication information, thereby avoiding the execution of the second instruction part that affects the security and reliability of the operating system, thereby improving the security and reliability of the system call method provided in the embodiment of the present application.

[0112] In a possible embodiment, the first instruction part may include indication information, and there is a corresponding relationship between the indication information and the second instruction part. The above step S502 includes: the processor 110 determines and executes the second instruction part corresponding to the indication information according to the indication information and the corresponding relationship.

[0113] Specifically, the global engine 113 in the processor 110 can determine the second instruction part corresponding to the indication information based on the indication information and the correspondence between the indication information and the second instruction part, and obtain the second instruction part through a designated register, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system based on the first instruction part.

[0114] In a possible embodiment, the correspondence between the above-mentioned indication information and the second instruction part can be stored in a register in the processor 110 in the form of a table, or stored in the memory 120, and the global engine 113 can query the table according to the indication information to determine the second instruction part corresponding to the indication information.

[0115] Exemplarily, the indication information may be characters. The embodiment of the present application takes the characters as numbers, and different numbers correspond to different second instruction parts as an example for illustrative explanation.

[0116] For example, when the indication information is a number "1", the indication information "1" corresponds to two instructions, and the two instructions are the second instruction part. When the indication information is a number "2", the indication information "2" corresponds to three instructions, and the three instructions are the second instruction part.

[0117] In the system call method provided in the embodiment of the present application, the first instruction part includes indication information, and there is a corresponding relationship between the indication information and the second instruction part. The processor 110 determines the second instruction part based on the indication information and the corresponding relationship, thereby avoiding obtaining the second instruction part that affects the security and reliability of the operating system based on the first instruction part, thereby improving the security and reliability of the system call method provided in the embodiment of the present application.

[0118] Based on this, the embodiment of the present application also provides a processing device, which is used to execute a block instruction. The block instruction refers to an instruction set including a first instruction part and a second instruction part. The first instruction part corresponds to the second instruction part. The first instruction part can also be called a block header, and the second instruction part can also be called a block body. The first instruction part includes instructions of a first privilege level, and the second instruction part includes instructions of a second privilege level. The processing device can be a processor. The embodiment of the present application uses the processing device as Figure 6 The processor 110 is taken as an example for exemplary description. The processor 110 includes a global engine 113 , a block engine 115 coupled to the global engine 113 , and a plurality of global registers 114 .

[0119] The global engine 113 is used to obtain the first instruction part of the block instruction when the processor 110 runs at the first privilege level. The first instruction part is used to indicate the second instruction part of the block instruction and the designated register, and the designated register is the register used when executing the second instruction part. The first instruction part includes instructions of the first privilege level, and the second instruction part includes instructions of the second privilege level. The first privilege level is lower than the second privilege level. The designated register is some global registers 114 among multiple global registers 114.

[0120] The global engine 113 is further configured to schedule the block engine 115 to execute the second instruction portion according to the first instruction portion, and to use the designated register when executing the second instruction portion.

[0121] Optionally, the first privilege level may include one of a hypervisor privilege level, an operating system privilege level, an application privilege level, etc., and the second privilege level may include one of a security privilege level, a hypervisor privilege level, an operating system privilege level, etc., which is not limited in the embodiments of the present application. The following embodiments of the present application take the first privilege level as the application privilege level and the second privilege level as the operating system privilege level as an example for exemplary description.

[0122] Optionally, the second instruction part may include one instruction, or may include multiple instructions. The embodiment of the present application does not limit the specific number of instructions included in the second instruction part.

[0123] Optionally, taking the example that the processor 110 includes M global registers 114, the above-mentioned designated registers may include 1 global register 114, or may include N global registers 114 out of the M global registers 114, where M is a positive integer and N is a positive integer greater than 1 and less than M. The embodiments of the present application do not limit the specific values ​​of M and N.

[0124] Optionally, when the designated register includes multiple global registers 114, some of the multiple global registers 114 can be used to obtain the second instruction part, and other global registers 114 can be used to store the result after the second instruction part is executed. Alternatively, all of the multiple global registers 114 can be used to obtain the second instruction part and store the result after the second instruction part is executed. The embodiments of the present application are not limited to this.

[0125] Optionally, the processor 110 may include at least one block engine 115 , and the at least one block engine 115 and a plurality of global registers 114 are coupled to the global engine 113 . The embodiment of the present application does not limit the specific number of block engines 115 included in the processor 110 .

[0126] like Figure 6 As shown, in a possible embodiment, the second instruction portion includes at least one instruction. The block engine 115 is used to store the execution result of the at least one instruction in a designated register. Alternatively, the block engine 115 includes a dedicated register 1151, and the block engine 115 is used to store the first execution result of the at least one instruction in the dedicated register, and store the second execution result in the dedicated register in the designated register, and the first execution result includes the second execution result.

[0127] In a possible embodiment, the first instruction portion is obtained by the processor 110 (processing device) during the process of running a program of the first privilege level, and the program of the first privilege level includes the first instruction portion. The second instruction portion is executed by the processor 110 during the process of running the program of the first privilege level, and when the processor 110 executes the second instruction portion, the program of the first privilege level implements the function of the second privilege level.

[0128] In a possible embodiment, the first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. The global engine 113 is specifically used to schedule the block engine to execute the second instruction part according to the address information.

[0129] In a possible embodiment, the second instruction part includes authentication information. Before the global engine 113 schedules the block engine to execute the second instruction part based on the address information, the global engine 113 is further configured to determine whether the second instruction part is legal based on the authentication information.

[0130] In a possible embodiment, the first instruction part includes indication information, and there is a corresponding relationship between the indication information and the second instruction part. The global engine 113 is specifically used to determine the second instruction part corresponding to the indication information based on the indication information and the corresponding relationship, and the scheduling block engine executes the second instruction part.

[0131] The processor 110 (processing device) provided in the embodiment of the present application first obtains the first instruction part of the block instruction at the first privilege level, and the first instruction part is used to indicate the second instruction part of the block instruction and the designated register used when executing the second instruction part. Among them, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, and the designated register is a part of the global registers of the multiple global registers included in the processor. Then, the global engine 113 schedules the block engine 115 to execute the second instruction part according to the first instruction part, and uses the designated register when executing the second instruction part. Compared with the prior art, in which the application switches the operating state of the processor through system calls, saves the context, and then obtains and executes the instructions of the privilege level of the operating system through all global registers, the processor 110 adopts the system call method provided in the embodiment of the present application, and can access the resources corresponding to the program of the second privilege level through designated registers without switching the operating state and saving the context, and execute the second instruction part of the second privilege level to realize the function of the second privilege level, so that the operating efficiency of the processor 110 can be improved and the operating cost can be reduced.

[0132] like Fig. 9 As shown, an embodiment of the present application further provides a system call device 900, which may be the processor 110 in the above embodiment, and the system call device 900 may be used to implement the system call method of any of the above embodiments.

[0133] The system call device 900 includes: an acquisition module 901 and a processing module 902. Exemplarily, the acquisition module 901 is used to support the acquisition operation of the system call device 900, such as acquiring the first instruction part. The processing module 902 is used to control and manage the actions of the system call device 900, and to execute the processing operations performed by the system call device 900 in the above embodiment, such as executing the second instruction part. Optionally, if the system call device 900 includes a storage unit, the processing module 902 can also execute the program or instruction stored in the memory, so that the system call device 900 implements the method and function involved in any of the above embodiments.

[0134] Exemplarily, the processing module 902 may be used to execute, for example Figure 5 , and / or other processes for the technology described herein. The acquisition module 901 can be used to perform, for example, Figure 5Step S501 in the embodiment, and / or other processes for the technology described herein. Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0135] Exemplarily, in hardware implementation, the functions of the acquisition module 901 may be performed by a transceiver (transmitter / receiver) and / or a communication interface, and the functions of the processing module 902 may be performed by an accelerator, wherein the processing module 902 may be embedded in or independent of the processor of the system call device 900 in the form of hardware, or may be stored in the memory of the system call device 900 in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned functional units.

[0136] like Fig.10 As shown, the embodiment of the present application further provides a chip 1000, the chip 1000 includes a cache memory 1001, and a processing device 1002 coupled to the cache memory 1001, the structure of the processing device 1002 is as follows Figure 6 The structure of processor 110 is shown.

[0137] Optionally, the chip 1000 may be a central processing unit, or may be a microcontroller unit (MCU), which may also be called a single-chip microcomputer, but the embodiments of the present application are not limited thereto.

[0138] like Fig.11 As shown, the embodiment of the present application further provides an electronic device 1100, which includes a memory 1101 and a chip 1000 coupled to the memory 1101. The structure of the chip 1000 is as follows Fig.10 The structure of chip 1000 is shown.

[0139] Optionally, the memory 1101 may be a memory, or may be a hard disk, which is not limited in the embodiment of the present application.

[0140] Optionally, the type of the electronic device 1100 may include a computer, a laptop computer, a smart watch, a smart bracelet, a smart phone, a smart car machine, a drone, etc. The embodiment of the present application does not limit the specific type of the electronic device 1100.

[0141] The embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the following Figure 5 or Figure 8 The steps in the system call method are shown.

[0142] The embodiment of the present application further provides a computer program product. When at least one processor of the electronic device 1100 runs the computer program product, the processor executes the following Figure 5 or Figure 8 The steps in the system call method are shown.

[0143] The above detailed description of the system call method and the analysis of beneficial effects can all be correspondingly referred to the processor 110, the system call device 900, the chip 1000, the electronic device 1100, the computer-readable storage medium and the computer program product, and the embodiments of the present application will not be repeated here.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A system call method, characterized in that: Applied in an electronic device including a processor, the processor is used to execute a block instruction, the processor includes a plurality of global registers, and the method includes: The processor obtains a first instruction part of the block instruction at a first privilege level, the first instruction part is used to indicate a second instruction part and a designated register of the block instruction, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of the first privilege level, the second instruction part includes instructions of the second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the global registers among the multiple global registers; The second instruction portion is executed according to the first instruction portion, and the designated register is used when executing the second instruction portion.

2. The method according to claim 1, characterized in that The second instruction part includes at least one instruction, and the method further includes: storing the execution result of the at least one instruction in the designated register; Alternatively, the processor further comprises a dedicated register; A first execution result of the at least one instruction is stored in the dedicated register, and a second execution result in the dedicated register is stored in the designated register, wherein the first execution result includes the second execution result.

3. The method according to claim 1 or 2, characterized in that: The first instruction portion is obtained by the processor during the process of running the program of the first privilege level, and the program of the first privilege level includes the first instruction portion; The second instruction portion is executed by the processor during the process of running the program at the first privilege level.

4. The method according to any one of claims 1 to 3, characterized in that The first instruction part includes address information, and the address information is used to indicate the address of the second instruction part. The executing the second instruction part according to the first instruction part includes: The second instruction portion is executed according to the address information.

5. The method according to any one of claims 1 to 4, characterized in that The second instruction part includes authentication information, and the method further includes: The legality of the second instruction portion is determined according to the authentication information.

6. The method according to any one of claims 1 to 3, characterized in that The first instruction part includes instruction information, and there is a corresponding relationship between the instruction information and the second instruction part. The executing the second instruction part according to the first instruction part includes: According to the indication information and the corresponding relationship, the second instruction part corresponding to the indication information is determined and executed.

7. The method according to any one of claims 1 to 6, characterized in that The first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

8. A processing device, characterized in that: The processing device is used to execute block instructions, and the processing device includes a global engine, a block engine coupled to the global engine, and a plurality of global registers; The global engine is used to obtain a first instruction part of the block instruction when the processing device runs at a first privilege level, the first instruction part is used to indicate a second instruction part of the block instruction and a designated register, the designated register is a register used when executing the second instruction part, the first instruction part includes instructions of a first privilege level, the second instruction part includes instructions of a second privilege level, the first privilege level is lower than the second privilege level, and the designated register is a part of the multiple global registers; The global engine is further configured to schedule the block engine to execute the second instruction part according to the first instruction part, and use the designated register when executing the second instruction part.

9. The processing device according to claim 8, characterized in that The second instruction portion includes at least one instruction; The block engine is configured to store the execution result of the at least one instruction in the designated register; Alternatively, the block engine includes dedicated registers; The block engine is used to store a first execution result of the at least one instruction in the dedicated register, and store a second execution result in the dedicated register in the designated register, wherein the first execution result includes the second execution result.

10. The processing device according to claim 8 or 9, characterized in that: The first instruction portion is obtained by the processing device during the process of running the program of the first privilege level, and the program of the first privilege level includes the first instruction portion; The second instruction portion is executed by the processing device during the process of running the program of the first privilege level.

11. The processing device according to any one of claims 8 to 10, characterized in that: The first instruction part includes address information, and the address information is used to indicate the address of the second instruction part; The global engine is specifically configured to schedule the block engine to execute the second instruction portion according to the address information.

12. The processing device according to any one of claims 8 to 11, characterized in that: The second instruction portion includes authentication information; The global engine is further used to determine whether the second instruction part is legal according to the authentication information.

13. The processing device according to any one of claims 8 to 10, characterized in that: The first instruction part includes instruction information, and there is a corresponding relationship between the instruction information and the second instruction part; The global engine is specifically configured to determine the second instruction portion corresponding to the indication information according to the indication information and the corresponding relationship, and schedule the block engine to execute the second instruction portion.

14. The processing device according to any one of claims 8 to 13, characterized in that: The first privilege level is an application privilege level, and the second privilege level is an operating system privilege level.

15. A chip, characterized in that: The chip includes a cache memory and a processing device coupled to the cache memory, wherein the processing device is the processing device according to any one of claims 8 to 14.

16. An electronic device, characterized in that: The electronic device comprises a memory and a chip coupled to the memory, wherein the chip is the chip as claimed in claim 15.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on a processor, the processor is enabled to execute the system call method according to any one of claims 1 to 7.

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