Asynchronous bridge and asynchronous bridging method
By introducing an instruction receiver and an instruction prefetcher into the asynchronous bridge of a single-chip system, the problem of out-of-synchronization of the DSP and CPU operating clocks is solved and the system performance is significantly improved.
Patent Information
- Application Number
- CN202410197508.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-18
- Filing Date
- 2024-02-22
- Publication Date
- 2025-01-21
AI Technical Summary
In a single chip system, the operation time pulses of the digital signal processor and the central processing unit are not synchronized, resulting in low performance of the asynchronous bridge and difficult to effectively handle asynchronous communication.
An asynchronous bridge is designed, which includes an instruction receiver and an instruction prefetcher. It optimizes the asynchronous processing process by prefetching the second instruction before the first instruction is completed and responding immediately when the second instruction is officially received.
Significantly improves system performance, reduces asynchronous processing time through prefetch technology, and improves communication efficiency between DSP and CPU.
Smart Images
Figure CN119336678A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of asynchronous communication. Background Art
[0002] The functional blocks on a single-chip system (SoC) often operate at different frequencies. For example, on an SoC, the operating clock of the digital signal processor (DSP) may be as high as 300MHz, while the operating clock of the central processing unit (CPU) may be only 200MHz. The DSP and the CPU are asynchronous. If the DSP wants to obtain data from the CPU, an asynchronous bridge (such as the AHB-to-AHB bridge of the on-chip bus technology) is required to handle the asynchronous situation between the DSP and the CPU.
[0003] How to improve the performance of asynchronous bridges is an important issue in the technical field. Summary of the invention
[0004] An asynchronous bridge implemented according to one embodiment of the present invention includes an instruction receiver and an instruction prefetcher. The instruction receiver receives a first instruction from a first clock operation device to operate a second clock operation device. Before the first instruction is executed and responded to the first clock operation device, the instruction prefetcher prefetches a second instruction from the first clock operation device. When the instruction receiver receives the second instruction from the first clock operation device, the second clock operation device operates according to the second instruction. The system performance is significantly improved.
[0005] In one embodiment, the asynchronous bridge further includes a pre-fetch cache and an instruction processor. The instruction processor receives a pre-fetch request from the instruction pre-fetcher corresponding to the second instruction, reads a pre-fetch data from the second clock operation device, and caches the pre-fetch data in the pre-fetch cache, and responds to the first clock operation device when the instruction receiver receives the second instruction.
[0006] In one embodiment, the pre-fetch cache is managed by a pre-fetch index. In response to the instruction processor, the pre-fetch data is cached in the pre-fetch cache, and the instruction pre-fetcher causes the pre-fetch index to mark the second instruction.
[0007] In one embodiment, when the instruction receiver receives the second instruction, it queries the prefetch index, reads the prefetch data from the prefetch cache according to the annotation of the prefetch index on the second instruction, and responds to the first clock operation device.
[0008] In one embodiment, the asynchronous bridge further includes a read cache for asynchronously processing by the first clock computing device the non-prefetched read instructions issued by the second clock computing device.
[0009] In one embodiment, the first instruction is a read instruction. When the instruction receiver receives the first instruction and confirms that the prefetch index does not mark the first instruction, it issues a read request to the instruction processor. In response to the read request, the instruction processor obtains a read data from the second clock computing device and caches the read data in the read cache to respond to the first clock computing device.
[0010] In one implementation, the instruction processor prioritizes the read request over the prefetch request.
[0011] In one embodiment, when a second instruction different from the first instruction appears in a direct memory access module on the first clock computing device, the instruction prefetcher loads the second instruction from the direct memory access module and sends the prefetch request to the instruction processor, which instructs the second clock computing device to supply the read data and then supply the prefetch data without interruption. In this way, the second instruction is completed by taking advantage of the first instruction, significantly improving system performance.
[0012] The above concepts are more used to implement asynchronous bridge methods.
[0013] An asynchronous bridging method implemented according to one embodiment of the present case includes: receiving a first instruction from a first clock computing device to operate a second clock computing device; and before the first instruction is executed and responded to the first clock computing device, pre-fetching a second instruction from the first clock computing device, and when the second instruction is formally received from the first clock computing device, the second clock computing device operates according to the second instruction.
[0014] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A computer system 100 is illustrated according to one embodiment of the present invention;
[0016] Figure 2 For example, the computer system 100 is a single chip (SoC) system 200;
[0017] Figure 3 is a flow chart illustrating the workflow of the instruction receiver 220 according to one embodiment of the present invention;
[0018] Figure 4 is a flow chart illustrating the working process of the instruction prefetcher 222 according to one embodiment of the present invention;
[0019] Figure 5 is a flow chart illustrating the workflow of the instruction processor 224 according to one embodiment of the present invention; and
[0020] Figure 6 2 is a waveform diagram illustrating signal waveforms of the DSP system 202 and the CPU system 204 according to one embodiment of the present invention.
[0021] Figure Number:
[0022] 100: Computer Systems
[0023] 102: First clock computing device
[0024] 104: Second clock computing device
[0025] 106:Asynchronous Bridge
[0026] 108, 220: Command receiver
[0027] 110, 222: instruction prefetcher
[0028] 200: System on a Chip (SoC)
[0029] 202: Digital Signal Processor (DSP) System
[0030] 204: Central Processing Unit (CPU) System
[0031] 206:Asynchronous Bridge
[0032] 208: Digital Signal Processor (DSP)
[0033] 210: Direct Memory Access Module (DMA)
[0034] 212: Instruction Memory (ITCM)
[0035] 214: Data memory (DTCM)
[0036] 216: Advanced High-Performance Bus Master (AHBM)
[0037] 218: DSP Bus Array
[0038] 224: Instruction Processor
[0039] 226: Read cache
[0040] 228: Prefetch Cache
[0041] 230: Write cache
[0042] 232: Prefetch Index
[0043] 602, 604: Arrows, indicating the causal relationship of events
[0044] S302...S324, S402...S414, S502...S522: Steps
[0045] A0, A0+4, A0+8, A0+C, B0, B0+4, B0+8, and B0+C: each is a single data. B0_bust_4_read: four data starting from B0
[0046] burst: multiple data
[0047] DSP_DMA_next: DSP system 202 end signal
[0048] HCLK_CPU, HCLK_DSP: operation clock
[0049] HTRANS_CPU, HADDR_CPU, HBURST_CPU, HSIZE_CPU, HWRITE_CPU, HRDATA_CPU, and HREADY_CPU: CPU system 204 terminal signals
[0050] IDLE: Idle
[0051] seq, nseq: continuous, discontinuous marking
[0052] word:
[0053] X: No data transmitted DETAILED DESCRIPTION
[0054] The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims.
[0055] Figure 1 According to one embodiment of the present invention, a computer system 100 is illustrated, which includes two computing devices running at different clock speeds: a first clock computing device 102 and a second clock computing device 104. The first clock computing device 102 and the second clock computing device 104 communicate with each other via an asynchronous bridge 106.
[0056] The asynchronous bridge 106 includes not only a command receiver 108 but also a command prefetcher 110. The asynchronous bridge 106 receives a first command from the first clock computing device 102 through the command receiver 108 and performs asynchronous processing, so that the second clock computing device 104 can act accordingly and execute the first command. After the first command is executed and responded to the first clock computing device 102, the asynchronous bridge 106 receives a second command from the first clock computing device 102 through the command receiver 108.
[0057] In particular, the asynchronous bridge 106 has already pre-fetched the second instruction from the first clock computing device 102 by the instruction pre-fetcher 110 long before the instruction receiver 108 receives the second instruction from the first clock computing device 102. The asynchronous bridge 106 can complete the asynchronous processing of the second instruction before the first instruction is executed and responded to the first clock computing device 102, and even make the second clock computing device 104 act in accordance with the second instruction. In this way, when the asynchronous bridge 106 formally receives the second instruction from the first clock computing device 102 via the instruction receiver 108, it can respond to the first clock computing device 102 immediately. The system operation performance is greatly improved.
[0058] The computer system 100 may have various variations, for example, a computer system, a consumer electronic product system, or a single chip system (System on a Chip, abbreviated as SoC).
[0059] Figure 2 For example, the computer system 100 is a single chip (SoC) system 200. A digital signal processor (DSP) system 202 is arranged on the SoC system 200. Figure 1 The first clock computing device 102 can have an operating clock of up to 300 MHz. The SoC system 200 also has a central processing unit (CPU) system 204, i.e. Figure 1 The second clock computing device 104 may have an operating clock of 200 MHz, which is different from the operating clock of the DSP system 202. The asynchronous bridge 206 may use an on-chip bus technology, such as an AHB-to-AHB bridge; AHB is the abbreviation of Advanced High-Performance Bus.
[0060] The DSP system 202 includes a digital signal processor (DSP) 208 , a direct memory access module (DMA) 210 , an instruction memory (ITCM) 212 , a data memory (DTCM) 214 , and an advance high-performance bus master (AHBM) 216 , which communicate with each other through a DSP bus matrix 218 .
[0061] The asynchronous processing between the first clock and the second clock is handled by the asynchronous bridge 206. The instruction receiver 220 used by the asynchronous bridge 206 cooperates with the AHBM technology and is responsible for processing the read and write instructions provided by the DSP system 202 through the AHBM 216. The instruction prefetcher 222 prefetches instructions from the DMA 210. The asynchronous bridge 206 also includes an instruction processor 224, a read cache 226, a prefetch cache 228, and a write cache 230. The prefetch cache 228 can be managed by a prefetch index 232. The read cache 226, the prefetch cache 228, and the write cache 230 can adopt a first-in-first-out (FIFO) technology.
[0062] In response to the read instruction that has not been pre-fetched, the instruction receiver 220 issues a read request to the instruction processor 224, so that the instruction processor 224 reads the CPU system 204. The instruction processor 224 caches the read data responded by the CPU system 204 into the read cache 226. The instruction receiver 220 responds to the DSP system 202 whose clock is different from that of the CPU system 204 by reading the contents of the cache 226.
[0063] In response to the write command requested by the DSP system 202, the command receiver 220 issues a write request to the command processor 224. The write data issued by the DSP system 202 is cached in the write cache 230. According to the write request, the command processor 224 obtains the write data from the write cache 230 and fills it into the CPU system 204. In this way, the DSP system 202 can request to write data to the CPU system 204 even if the clock frequency is different from that of the CPU system 204.
[0064] As for the read instructions pre-fetched by the instruction pre-fetcher 222 from the DSP system 202, the operation is as follows. Regarding the read instructions pre-fetched from the DSP system 202, the instruction pre-fetcher 222 sends a pre-fetch request to the instruction processor 224, so that the instruction processor 224 pre-fetches the CPU system 204. The instruction processor 224 caches the pre-fetched data responded by the CPU system 204 into the pre-fetch buffer 228, and the instruction pre-fetcher 222 will mark the pre-fetch index 232 as the pre-fetched read instruction. The read instruction to be pre-fetched is later formally received by the instruction receiver 220, and the instruction receiver 220 can identify from the pre-fetch index 232 that there is already pre-fetched data, and the time-consuming asynchronous processing can be omitted. The instruction receiver 220 responds to the DSP system 202 with the content of the pre-fetch buffer 228.
[0065] In particular, the instruction processor 224 prioritizes read requests over prefetch requests. Prefetching does not slow down the system.
[0066] The prefetch effect is particularly effective when two consecutive read instructions are executed. In one embodiment, after the instruction receiver 220 receives a first read instruction, the instruction prefetcher 222 loads the second read instruction from the DMA 210 when a second read instruction different from the first read instruction appears in the DMA 210, and sends the prefetch request to the instruction processor 224. After the instruction processor 224 returns the first read data (corresponding to the first read instruction), the second read data (corresponding to the prefetched second read instruction) is continuously supplied.
[0067] The following is a detailed explanation of the working process of the instruction receiver 220 , the instruction prefetcher 222 , and the instruction processor 224 .
[0068] Figure 3 FIG. 2 is a flow chart illustrating the workflow of the instruction receiver 220 according to one embodiment of the present invention. The DSP system 202 transmits a write instruction or a read instruction to the instruction receiver 220 in the asynchronous bridge 206 through the DSP bus array 218 and the AHBM 216 by the DSP 208 (or DMA 210). After receiving the instruction, the instruction receiver 220 will Figure 3 Process work.
[0069] In step S302, the instruction receiver 220 determines whether the received instruction is a write instruction. If so, the process proceeds to step S304, caching the write data to the write cache 230, until step S306 determines that the cache of the write data is completed. In step S308, the instruction receiver 220 generates a write request and inputs it into the instruction processor 224, so that the instruction processor 224 writes the content of the write cache 230 into the CPU system 204.
[0070] If the received instruction is determined to be a non-write instruction in step S302, the instruction receiver 220 will further determine whether it is a read instruction in step S310. If so, the instruction receiver 220 will further proceed to step S312 to determine whether the currently received read instruction has been marked in the prefetch index 232. For the read instruction that is not marked in the prefetch index 232, the instruction receiver 220 generates a read request to the instruction processor 224 in step S314, and the instruction processor 224 obtains the read data from the CPU system 204 and fills it into the read buffer 226. The instruction receiver 220 monitors whether the read buffer 226 is still empty in step S316. Once it is determined that the read buffer 226 has been filled with data, in step S318, the instruction receiver 220 responds to the DSP system 202 with the content of the read buffer 226 until step S320 determines that the read data has been completed and returned to the DSP system 202.
[0071] If step S312 determines that the read instruction currently received by the instruction receiver 220 has been marked in the prefetch index 232, the instruction receiver 220 executes step S322 to read the prefetch buffer 228 and respond to the DSP system 202 with the content of the prefetch buffer 228 until step S324 determines that the prefetch data has been completed and returned to the DSP system 202.
[0072] Compared with the processing procedures for the read instructions that have not been prefetched (S314-S320), the processing procedures for the read instructions that have been prefetched (S322 and S324) simply respond to the DSP system 202 with the content of the prefetch buffer 228. The time-consuming operation of the instruction processor 224 and the reading of the CPU system 204 have already been completed. The system performance is greatly improved.
[0073] Figure 4 The flowchart illustrates the working process of the instruction prefetcher 222 according to one embodiment of the present invention. In one embodiment, the instruction prefetcher 222 utilizes the idle period of the AHBM 216 (no instruction is transmitted to the instruction receiver 220) to prefetch the next instruction to be transmitted by the DMA 210. In particular, the prefetching of the read instruction. The read instruction may include the read address, the read size, and the number of read data (burst number). Since the prefetched read instruction is provided by the DMA 210, it is quite accurate. Such instruction prefetching technology is particularly beneficial for optimizing the operation of writing to the DSP system 202 (e.g., writing to the DMA 210 or the DSP 208).
[0074] In step S402, the instruction prefetcher 222 determines whether the DMA 210 is active (DMA active). If so, the instruction prefetcher 222 determines in step S404 whether a read instruction required by the DMA 210 has been delivered to the instruction receiver 220. If not, the process proceeds to step S406, and the instruction prefetcher 222 prefetches the read instruction from the DMA 210. In step S408, the instruction prefetcher 222 generates a prefetch request and delivers it to the instruction processor 224. In step S410, it is confirmed whether the CPU system 204 allows prefetching data. If the CPU system 204 allows prefetching data, the process proceeds to step S412, and the prefetched read instruction is marked in the prefetch index 232; accordingly, the instruction processor 224 prefetches data from the CPU system 204 and fills it into the prefetch buffer 228, until step S414 determines that the prefetch is completed.
[0075] Figure 5 2 is a flow chart illustrating the workflow of the instruction processor 224 according to one embodiment of the present invention.
[0076] In step S502, the command processor 224 determines whether a write request is received from the command receiver 220. If so, the process proceeds to step S504, where the command processor 224 obtains the write data from the write buffer 230 and writes it into the CPU system 204 until step S506 determines that the write is complete.
[0077] If step S502 determines that no write request is received from the instruction receiver 220, the process proceeds to step S508. The instruction processor 224 determines whether a read request is received from the instruction receiver 220. If so, the process proceeds to step S510, and the instruction processor 224 reads the read data from the CPU system 204. Then, according to step S512, the instruction processor 224 fills the read data into the read buffer 226. Steps S510 and S512 are repeatedly executed until step S514 determines that the read is completed.
[0078] If step S508 determines that no read request is received from the instruction receiver 220, the process proceeds to step S516. The instruction processor 224 determines whether a prefetch request is received from the instruction prefetcher 222. If so, the process proceeds to step S518, and the instruction processor 224 prefetches data from the CPU system 204. Then, according to step S520, the instruction processor 224 fills the prefetched data into the prefetch cache 228. Steps S518 and S520 are repeatedly executed until step S522 determines that the prefetch is completed.
[0079] Figure 5The flow shows that the priority of the command processor 224 operation is from high to low: write request sent by the command receiver 220; read request sent by the command receiver 220; pre-fetch request sent by the command pre-fetcher 222.
[0080] Figure 6 2 is a waveform diagram illustrating the signal waveforms of the DSP system 202 and the CPU system 204 according to one embodiment of the present invention. The CPU system 204 is designed to provide four adjacent (seq marked, combined into word marked with burst) data each time.
[0081] The DSP system 202 uses an operating clock HCLK_DSP, which is faster than the operating clock HCLK_CPU of the CPU system 204. As shown by the signal DSP_DMA_next, the DMA 210 on the DSP system 202 not only requests to read A0, but also requests to read four data B0_bust_4_read starting from B0. The signals of the CPU system 204 include: HTRANS_CPU, HADDR_CPU, HBURST_CPU, HSIZE_CPU, HWRITE_CPU, HRDATA_CPU, and HREADY_CPU. After being idle, in response to the A0 read requested by the DSP system 202, the CPU system 204 will respond with A0, A0+4, A0+8, and A0+C. Referring to HCLK_DSP timing 8, before the four data A0, A0+4, A0+8, and A0+C related to A0 are completely returned, the instruction prefetcher 222 of the asynchronous bridge 206 prefetches the read instruction B0_bust_4_read from the DSP system 202. The asynchronous bridge 206 can omit the synchronous processing of the B0_bust_4_read read instruction, so that it can take advantage of the A0 read instruction, so that the CPU system 204 can immediately supply the prefetch data B0, B0+4, B0+8, and B0+C (arrow 602) after the four data A0, A0+4, A0+8, and A0+C. Arrow 604 shows that the four prefetch data B0, B0+4, B0+8, and B0+C are successfully prefetched to the prefetch buffer 228, and can be returned to the DSP system 202 after the read data A0. Figure 6 The waveform shows that even if the B0 data is not continuous with A0+C (B0 is marked as nseq), it will be spit out by the CPU system 204 immediately after the A0 data.
[0082] Any asynchronous bridging technology implemented by instruction prefetching should be protected by this case.
[0083] The above concept can further realize an asynchronous bridge method, including: receiving a first instruction from a first clock computing device (102 / 202) to enable a second clock computing device (104 / 204) to operate; and, before the first instruction is executed and responded to the first clock computing device (102 / 202), pre-fetching a second instruction from the first clock computing device (102 / 202), and waiting for the second instruction to be formally received from the first clock computing device (102 / 202), the second clock computing device (104 / 204) operates according to the second instruction. In addition, the second clock computing device (104 / 204) has prepared data to be transmitted back to the first clock computing device (102 / 202) in a cache on the asynchronous bridge (106 / 206), so as to respond to the formally received second instruction in real time.
[0084] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the claims.
Claims
1. An asynchronous bridge, characterized in that: include: a command receiver, receiving a first command from a first clock computing device to operate a second clock computing device; and an instruction prefetcher, which prefetches a second instruction from the first clock computing device before the first instruction is executed and responded to the first clock computing device; When the instruction receiver receives the second instruction from the first clock operation device, the second clock operation device operates according to the second instruction.
2. The asynchronous bridge according to claim 1, characterized in that: Also includes: a pre-fetch cache; and An instruction processor receives a pre-fetch request from the instruction pre-fetcher corresponding to the second instruction, reads a pre-fetch data from the second clock operation device, and caches the pre-fetch data to the pre-fetch cache, and responds to the first clock operation device when the instruction receiver receives the second instruction.
3. The asynchronous bridge according to claim 2, characterized in that: The prefetch cache is managed by a prefetch index; and Corresponding to the instruction processor, the pre-fetch data is cached in the pre-fetch cache, and the instruction pre-fetcher causes the pre-fetch index to mark the second instruction.
4. The asynchronous bridge according to claim 3, characterized in that: When the instruction receiver receives the second instruction, it queries the pre-fetch index, reads the pre-fetch data from the pre-fetch cache according to the mark of the pre-fetch index on the second instruction, and responds to the first clock operation device.
5. The asynchronous bridge according to claim 4, characterized in that: Also includes: A read cache is used for the first clock computing device to asynchronously process the non-prefetched read instructions issued by the second clock computing device.
6. The asynchronous bridge according to claim 5, characterized in that: The first instruction is a read instruction; The instruction receiver receives the first instruction and issues a read request to the instruction processor when confirming that the prefetch index does not mark the first instruction; and In response to the read request, the instruction processor obtains a read data from the second clock computing device and caches the read data in the read cache to respond to the first clock computing device.
7. The asynchronous bridge according to claim 6, characterized in that: Also includes: A write cache is used for the first clock computing device to asynchronously process the write instruction issued by the second clock computing device.
8. The asynchronous bridge according to claim 7, characterized in that: When the command receiver receives a third command which is a write command from the first clock operation device, the command receiver caches a write data into the write cache and issues a write request to the command processor; and In response to the write request, the instruction processor obtains the write data from the write cache and supplies it to the second clock computing device.
9. The asynchronous bridge according to claim 6, characterized in that: The instruction processor prioritizes the read request over the prefetch request.
10. The asynchronous bridge according to claim 6, characterized in that: When a second instruction different from the first instruction appears in a direct memory access module on the first clock computing device, the instruction prefetcher loads the second instruction from the direct memory access module and sends the prefetch request to the instruction processor. After the instruction processor instructs the second clock computing device to supply the read data, the prefetch data is supplied uninterruptedly.
11. An asynchronous bridging method, characterized in that: include: receiving a first instruction from a first clock computing device to operate a second clock computing device; and Before the first instruction is executed and responded to the first clock computing device, a second instruction is pre-fetched from the first clock computing device. After the second instruction is formally received from the first clock computing device, the second clock computing device operates according to the second instruction.
12. The asynchronous bridging method according to claim 11, characterized in that: Also includes: Providing a pre-fetch cache; generating a prefetch request corresponding to the prefetch of the second instruction; In response to the pre-fetch request, a pre-fetch data is read from the second clock computing device; and The pre-fetch data is cached in the pre-fetch cache, and when the second instruction is formally received from the first clock computing device, the pre-fetch data is responded to the first clock computing device.
13. The asynchronous bridging method according to claim 12, characterized in that: Also includes: Managing the prefetch buffer with a prefetch index; and The corresponding pre-fetch data is cached in the pre-fetch cache, and the pre-fetch index marks the second instruction.
14. The asynchronous bridging method according to claim 13, characterized in that: Also includes: When the second instruction is formally received from the first clock computing device, the pre-fetch index is queried, and the pre-fetch data is read from the pre-fetch cache according to the mark of the second instruction in the pre-fetch index, and the pre-fetch data is responded to the first clock computing device.
15. The asynchronous bridging method according to claim 14, characterized in that: Also includes: A read cache is provided for asynchronously processing the non-prefetched read instructions issued by the second clock computing device by the first clock computing device.
16. The asynchronous bridging method according to claim 15, characterized in that: Also includes: When receiving the first instruction as a read instruction and confirming that the prefetch index does not mark the first instruction, generating a read request; and In response to the read request, a read data is obtained from the second clock computing device, and the read data is cached in the read cache to respond to the first clock computing device.
17. The asynchronous bridging method according to claim 16, wherein: Also includes: A write cache is provided for the asynchronous processing of the write instruction issued by the second clock computing device by the first clock computing device.
18. The asynchronous bridging method according to claim 17, characterized in that: Also includes: When a third instruction that is a write instruction is received from the first clock computing device, a write data is cached in the write cache and a write request is generated; and In response to the write request, the write data is obtained from the write cache and supplied to the second clock computing device.
19. The asynchronous bridging method according to claim 16, wherein: The read request has a higher priority than the pre-fetch request.
20. The asynchronous bridging method according to claim 16, wherein: Also includes: When a second instruction different from the first instruction appears in a direct memory access module on the first clock computing device, the second instruction is loaded from the direct memory access module to generate the pre-fetch request, so that the second clock computing device supplies the read data and then supplies the pre-fetch data continuously.