Display device

Abstract

Provided is a display device capable of achieving high definition. A display device includes an array substrate, a plurality of signal lines, a signal line selection circuit, and a driver IC. The driver IC is mounted on the array substrate along the signal line selection circuit. The selection control signal is output from snubber circuits provided at both ends of the driver IC in the first direction. The signal line selection circuit is provided with a plurality of switching circuits for selecting one of a plurality of signal lines on an array substrate in a Dx direction. A wiring for supplying a selection control signal to a signal line selection circuit includes: a first wiring to which a plurality of switching circuits are connected in a Dx direction; a second wiring provided substantially parallel to the first wiring and having both end portions connected to the snubber circuit; and a plurality of third wirings connected to the second wirings at a plurality of locations including at least both end portions and a center portion of the first wirings.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] Conventionally, there is a disclosed structure in which, in a display device of a signal line selection drive method, for example, a control line is wired at a central position of a substrate in order to reduce wiring resistance of a control signal to an analog switch circuit (signal line selection circuit) (for example, Patent Document 1). In addition, there is a disclosed structure in which a plurality of distribution circuits (signal line selection circuits) are provided, and a control signal is supplied to both ends of each distribution circuit, thereby blunting and reducing the waveform of the control signal (for example, Patent Document 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-192928

[0006] Patent Document 2: Japanese Patent Application Publication No. 2009-216997 Summary of the invention

[0007] In Patent Document 1, since the control line at the center is wired to extend toward both ends, the wiring resistance increases toward both ends, and thus, the voltage drop and control signal delay and attenuation caused by the wiring resistance may not be sufficiently suppressed.

[0008] In addition, in recent years, for example, in structures that use lenses to magnify and display display images, such as VR (Virtual Reality), AR (Augmented Reality), and MR (Mixed Reality), further high-definition display panels are pursued. In the above-mentioned patent document 2, since control signal lines are connected to both ends of each distribution circuit, the number of control signal lines wired between the distribution circuits increases. Therefore, the interval between the distribution circuits is larger than the pixel interval, and there is a possibility that multiple areas of the display panel divided by the distribution circuits can be visually recognized.

[0009] An object of the present invention is to provide a display device capable of achieving high definition.

[0010] A display device according to one embodiment of the present disclosure comprises: a substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction; a plurality of scan lines connected to the pixels arranged in the first direction; a plurality of signal lines connected to the pixels arranged in the second direction; a gate driver that supplies a scan signal to the scan line during a selection period of the scan line; a signal line selection circuit that supplies a pixel signal to the signal line during a selection period of the signal line; and a driver IC that generates a plurality of image signals obtained by time-division multiplexing the pixel signals respectively supplied to the plurality of signal lines and supplies the signals to the signal line selection circuit, and transmits a selection control signal of the signal line to the signal line selection circuit. The signal line selection circuit is provided along the first direction, the driver IC is mounted on the substrate along the signal line selection circuit, the selection control signal is output from the buffer circuits provided at the two ends of the driver IC in the first direction, the signal line selection circuit is provided with a plurality of switch circuits for selecting one of a plurality of signal lines arranged along the first direction on the substrate, and the wiring for supplying the selection control signal to the signal line selection circuit includes: a first wiring, to which the plurality of switch circuits are connected in the first direction; a second wiring, which is provided approximately parallel to the first wiring and has its two ends connected to the buffer circuits, respectively; and a plurality of third wirings, which are connected to the second wiring at a plurality of locations including at least the two ends and a central portion of the first wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing an example of a schematic structure of a display device.

[0012] Figure 2 This is a diagram showing an example of a pixel arrangement in a display area.

[0013] Figure 3 It is a cross-sectional view showing a schematic cross-sectional structure of a display device.

[0014] Figure 4 It is a top view showing a structural example of a pixel.

[0015] Figure 5A It means along Figure 4 A diagram of a first example of a cross section taken along line A1-A2.

[0016] Figure 5B It means along Figure 4 FIG. 2 is a diagram of a second example of a cross section taken along line A1-A2 of FIG.

[0017] Figure 6 This is a diagram showing an example of a driving circuit configuration.

[0018] Figure 71 is a schematic diagram of a substrate showing a connection example of selection control lines in a conventional example.

[0019] Figure 8 1 is a schematic diagram of a substrate showing a connection example of selection control lines according to an embodiment.

[0020] Fig. 9 It is along Figure 8 A schematic cross-sectional view of the B1-B2 line.

[0021] Fig.10 Yes means Figure 7 A diagram showing an example of a selection control signal waveform in the connection example shown.

[0022] Fig.11 Yes means Figure 8 A diagram showing an example of a selection control signal waveform in the connection example shown.

[0023] Fig.12 It is a schematic diagram of a substrate showing a connection example of selection control lines according to a modification of the embodiment.

[0024] Fig.13 Yes means Fig.12 A diagram showing an example of a selection control signal waveform in the connection example shown.

[0025] Description of Reference Numerals

[0026] 1: Display device

[0027] 4: Driver IC

[0028] 11: Display Panel

[0029] 12: Power supply unit

[0030] 13: Control device

[0031] 40: Driving circuit

[0032] 42: Gate Driver

[0033] 43: Signal line selection circuit

[0034] 44: Display control circuit

[0035] 51: Gate line layer (2nd metal layer)

[0036] 53: Signal line layer (1st metal layer)

[0037] AA: Display Area

[0038] ASW: Switching Circuit

[0039] COML: Common Electrode

[0040] CS: Holding Capacitor

[0041] DTL: Signal Line

[0042] ENB: scan line drive signal

[0043] GATE: Scan signal (gate signal)

[0044] MUX, MUX1, MUX2, xMUX1, xMUX2: Select control signal

[0045] Pix, Pix(n,m), Pix(n+1,m): pixels

[0046] PSIG1: 1st power supply voltage signal

[0047] PSIG2: Second power supply voltage signal

[0048] PX: Pixel electrode

[0049] SCL: scan line (gate line)

[0050] SIG: Pixel Signal

[0051] SWL: Select Control Line

[0052] Tr: Pixel transistor

[0053] Trn1, Trn2, Trp1, Trp2: switching transistors

[0054] VCOM: common potential

[0055] VGH: 1st potential

[0056] VGL: Second potential

[0057] Vsig: Image signal

[0058] VsigL: Image signal line DETAILED DESCRIPTION

[0059] The method (implementation method) for implementing the invention is described in detail with reference to the accompanying drawings. The present invention is not limited by the contents described in the following embodiments. In addition, the constituent elements described below include constituent elements that can be easily thought of by a person skilled in the art and substantially the same constituent elements. In addition, the constituent elements described below can be appropriately combined. In addition, the disclosed content is only an example, and the scheme that is more easily thought of by a person skilled in the art for appropriate changes that retain the main purpose of the invention is of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes schematically represent the width, thickness, shape, etc. of each part compared to the actual form, but it is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, sometimes the same elements as those described in the drawings that have appeared are marked with the same figure numbers and the detailed description is appropriately omitted.

[0060] Figure 1 This is a diagram showing an example of a schematic structure of a display device. Figure 2 This is a diagram showing an example of a pixel arrangement in a display area.

[0061] The display device 1 of this embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present disclosure, the display device 1 can adopt, for example, a column inversion drive method or a frame inversion method as a driving method. The driving method in the display device 1 is not limited to the inversion drive method and the frame inversion method.

[0062] The display device 1 includes a display area AA on a display panel 11 , and a drive circuit 40 is provided in a peripheral area of ​​the display area AA. The display device 1 is supplied with power from a power supply device 12 .

[0063] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral area of ​​the display area AA. The display control circuit 44 is included in a driver IC 4 installed in the peripheral area of ​​the display area AA. The driver IC 4 is connected to the control device 13 via a relay substrate composed of, for example, a flexible printed circuit (FPC: Flexible Printed Circuit).

[0064] The control device 13 controls the power supply from the power supply device 12 to the display device 1. The control device 13 also controls power on and power off of the display device 1. The power supply device 12 and the control device 13 are mounted on, for example, a device (not shown) on which the display device 1 is mounted.

[0065] A plurality of pixels Pix arranged in the Dx direction (first direction) and the Dy direction (second direction) are provided in the display area AA. In addition, a scanning line (gate line) SCL for supplying a scanning signal (gate signal) GATE to the pixel Pix, a signal line DTL for supplying a pixel signal SIG to the pixel Pix, and a common electrode COML for supplying a common potential VCOM to the pixel Pix are provided in the display area AA. In the present embodiment, the scanning line SCL is provided to extend in the Dx direction (first direction). In addition, in the present embodiment, the signal line DTL is provided to extend in the Dy direction (second direction).

[0066] like Figure 2 As shown, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is composed of a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to the signal line DTL, the gate is connected to the scanning line (gate line) SCL, and the drain is connected to the pixel electrode PX. A holding capacitor CS is formed between the pixel electrode PX and the common electrode COML.

[0067] The gates of the pixel transistors Tr of the pixels Pix arranged in the Dx direction (the first direction) are supplied with scanning signals (gate signals) GATE (1, 2, ···, m, ···, M) via scanning lines (gate lines) SCL, and the sources of the pixel transistors Tr of the pixels Pix arranged in the Dy direction (the second direction) are supplied with pixel signals SIG (1, 2, ···, n, ···N) via signal lines DTL. Figure 2 , an example is shown in which N pixels Pix are arranged in the Dx direction (first direction) and M pixels Pix are arranged in the Dy direction (second direction), but the present invention is not limited thereto. Hereinafter, a row in which pixels Pix are arranged in the Dx direction (first direction) is also referred to as a pixel row. In addition, a column in which pixels Pix are arranged in the Dy direction (second direction) is also referred to as a pixel column.

[0068] In the present disclosure, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). As a pixel arrangement, for example, a strip arrangement in which pixels of RGB are arranged in the Dx direction (first direction) is exemplified, but the pixel arrangement is not limited to the strip arrangement of RGB. Specifically, for example, a white pixel for displaying white (W) may be configured as a pixel Pix, or a strip arrangement in an inclined direction having a predetermined angle relative to the Dx direction (first direction) or the Dy direction (second direction) may be configured, or a plurality of pixel groups displaying different colors may be arranged periodically in both the Dx direction (first direction) and the Dy direction (second direction).

[0069] The power supply device 12 generates a positive first power supply voltage signal PSIG1 and a negative second power supply voltage signal PSIG2 supplied to the display device 1. The first power supply voltage signal PSIG1 is controlled to be a first potential VGH. The second power supply voltage signal PSIG2 is controlled to be a second potential VGL which is lower than the first potential VGH. The first potential VGH is set to, for example, 6V. The second potential VGL is set to, for example, -6V. The first potential VGH is not limited to 6V. In addition, the second potential VGL is not limited to -6V.

[0070] The control device 13 transmits an image signal, which is an original signal of an image displayed on the display device 1, to the display device 1. In addition, the control device 13 transmits a control signal for controlling the display device 1 to the display device 1. In addition, the control device 13 transmits a control signal for controlling the power supply from the power supply device 12 to the display device 1 to the power supply device 12.

[0071] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. The control device 13 can realize the display function of the display device 1 by executing a program using hardware resources such as the CPU and the storage device. The control device 13 controls the driver IC 4 so that the image to be displayed on the display device 1 can be processed as information of the image input grayscale according to the execution result of the program.

[0072] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives the image signal and various control signals from the control device 13. In addition, the display control circuit 44 converts the image signal from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing the pixel signal SIG corresponding to the pixel arrangement of RGB. In addition, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0073] In addition, the display control circuit 44 has a function as an interface (I / F) between the signal line selection circuit 43 and the control device 13 and a timing generator.

[0074] Next, refer to Figures 3 to 5B A schematic structure of the display device 1 according to the embodiment will be described. Figure 3 It is a cross-sectional view showing a schematic cross-sectional structure of a display device. Figure 4 It is a top view showing a structural example of a pixel. Figure 5A It means along Figure 4 The first example of the cross section of the A1-A2 line. Figure 5A In the first example shown, an example in which a bottom-gate transistor is used as the pixel transistor Tr is shown. Figure 5B It means along Figure 4 The second example of the cross section of the A1-A2 line. Figure 5B In the second example shown, an example in which a top-gate transistor is used as the pixel transistor Tr is shown.

[0075] The array substrate 2 includes a first substrate 21 formed of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX from the common electrode COML. The plurality of pixel electrodes PX are arranged in rows and columns (matrix) on the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0076] The pixel electrode PX is provided corresponding to each pixel Pix. The pixel signal SIG for performing the display operation is supplied from the signal line selection circuit 43 to the pixel electrode PX via the signal line DTL and the pixel transistor Tr. In addition, during the display operation, the common potential VCOM for display as a voltage signal is supplied from the driver IC4 to the common electrode COML. The common potential VCOM is preferably a potential different from the GND potential, for example, set to about -0.7V. The setting value of the common potential VCOM is set to an optimal value that does not produce flicker in a driving method such as a column inversion driving method or a frame inversion driving method. In addition, the common potential VCOM is preferably a fixed potential, but it can also be a structure having a waveform composed of an AC rectangular wave.

[0077] The pixel electrode PX and the common electrode COML are made of a light-transmitting conductive material such as ITO (Indium Tin Oxide) etc. A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0078] The counter substrate 3 includes a second substrate 31 formed of glass or transparent resin, and a color filter 32 and a light shielding layer (not shown) formed on one surface of the second substrate 31. A polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0079] The array substrate 2 and the counter substrate 3 are arranged relative to each other with a predetermined interval (cell gap) set. A liquid crystal layer 6 as a display function layer is provided in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 changes the orientation state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML, thereby modulating the light passing through the liquid crystal layer 6. In this embodiment, a liquid crystal of a transverse electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) is used.

[0080] The array substrate 2 includes wiring such as a pixel transistor Tr of each pixel Pix, a signal line DTL for supplying a pixel signal SIG to each pixel electrode PX, and a scanning line (gate line) SCL for supplying a gate signal GATE for driving each pixel transistor Tr. The signal line DTL and the scanning line (gate line) SCL extend on a plane parallel to the surface of the first substrate 21.

[0081] like Figure 4 As shown in FIG. 1 , a region surrounded by a scanning line (gate line) SCL and a signal line DTL is a pixel Pix. The pixel electrode PX includes a plurality of strip-shaped electrodes 22a and a connecting portion 22b.

[0082] like Figure 4 As shown, the pixel transistor Tr includes a semiconductor 61 , a source electrode 62 , a drain electrode 63 and a gate electrode 64 .

[0083] like Figure 5A As shown, in a structure using a bottom-gate transistor as a pixel transistor Tr, a gate line layer 51 is provided on the first substrate 21. A gate electrode 64 (scanning line (gate line) SCL) is provided on the gate line layer 51. An insulating layer 58a (second insulating layer) covers the gate electrode 64 and is provided on the first substrate 21. A semiconductor layer 52 is provided on the insulating layer 58a. A semiconductor 61 is provided on the semiconductor layer 52. A signal line layer 53 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c (first insulating layer).

[0084] like Figure 5BAs shown, in a structure using a top-gate transistor as a pixel transistor Tr, a light shield LS is provided on the first substrate 21. A semiconductor layer 52 is provided on the light shield LS via an insulating layer 58f. A semiconductor 61 is provided on the semiconductor layer 52. A gate line layer 51 is provided on the upper side of the semiconductor layer 52 via an insulating layer 58c. A gate electrode 64 is provided on the gate line layer 51. An insulating layer 58a covers the gate electrode 64 and is provided on the insulating layer 58c. A signal line layer 53 is provided on the upper side of the gate line layer 51 via an insulating layer 58a.

[0085] A drain electrode 63 and a source electrode 62 (signal line DTL) are provided on the signal line layer 53. An auxiliary wiring layer 54 is provided on the upper side of the drain electrode 63 and the source electrode 62 (signal line DTL) via an insulating layer 58d (third insulating layer). A common electrode layer 55 is provided on the upper side of the auxiliary wiring layer 54 via an insulating layer 58e. A common electrode COML is provided on the common electrode layer 55. In addition, a structure in which the auxiliary wiring layer overlaps the common electrode layer without an insulating layer can also be adopted. A pixel electrode PX is provided on the upper side of the common electrode layer 55 via an insulating layer 24.

[0086] like Figure 4 and Figure 5A (or Figure 5B ), the pixel electrode PX is connected to the drain electrode 63 of the pixel transistor Tr via the contact hole H11. The drain electrode 63 is connected to the semiconductor 61 via the contact hole H12. The semiconductor 61 intersects with the gate electrode 64 in a plan view. The gate electrode 64 is connected to the scanning line (gate line) SCL and is protruded from one side of the scanning line (gate line) SCL. The semiconductor 61 extends to a position overlapping with the source electrode 62 and is electrically connected to the source electrode 62 via the contact hole H13. The source electrode 62 is connected to the signal line DTL and protrudes from one side of the signal line DTL.

[0087] As the material of the semiconductor 61, a known material such as polycrystalline silicon or an oxide semiconductor can be used. For example, by using TAOS (Transparent Amorphous Oxide Semiconductor), the ability to maintain the voltage for image display for a long time (retention rate) is good, and the display quality can be improved. In addition, in an oxide semiconductor including TAOS, the leakage current when the pixel transistor Tr is turned off is small.

[0088] The gate electrode 64 (scanning line (gate line) SCL) is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo) or an alloy thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are made of, for example, titanium aluminum (TiAl) which is an alloy of titanium and aluminum.

[0089] As the material of the insulating layers 24, 58a, 58c, 58d, 58e, and 58f, a known insulating material can be used. For example, as the material of the insulating layer 58b, TEOS (Tetra Ethyl Ortho Silicate) can be used. In addition, as the material of the insulating layer 58c, for example, a silicon oxide film (SiO 2 As the material of the insulating layer 58d, an organic insulating film such as acrylic resin is used. Thus, the surface on which the common electrode COML is provided is flattened.

[0090] As with the gate electrode 64 (scanning line (gate line) SCL), the auxiliary wiring layer 54 is made of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof.

[0091] Figure 6 FIG. 1 is a diagram showing an example of a drive circuit configuration. Figure 6 FIG. 1 shows an example of a circuit configuration corresponding to pixels Pix(n, m) and Pix(n+1, m). Figure 2 The pixel arrangement shown in FIG. 1 shows the nth pixel Pix from the left in the figure arranged in the Dx direction (first direction) and the mth pixel Pix from the top in the figure arranged in the Dy direction (second direction). Figure 2 The pixel arrangement shown shows the n+1th pixel from the left in the figure among the pixels Pix arranged in the Dx direction (first direction) and the mth pixel Pix from the top in the figure among the pixels Pix arranged in the Dy direction (second direction).

[0092] Each circuit element constituting the driving circuit 40 is operated by being supplied with the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 from the power supply device 12. The potential of the first power supply voltage signal PSIG1 (first potential VGH) is set to the high potential of the scanning signal (gate signal) GATE(m) supplied to the gate of the pixel transistor Tr. In addition, the potential of the second power supply voltage signal PSIG2 (second potential VGL) is set to the low potential of the scanning signal GATE(m) supplied to the gate of the pixel transistor Tr.

[0093] The display control circuit 44 (driver IC4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 (driver IC4) supplies the synchronization signal such as the start pulse STV and the shift clock CKV or the scanning line drive signal ENB to the gate driver 42. In addition, the display control circuit 44 (driver IC4) supplies the selection control signal MUX to the signal line selection circuit 43. The potential of the first power supply voltage signal PSIG1 (the first potential VGH) is, for example, set to the high potential of the selection control signal MUX. In addition, the potential of the second power supply voltage signal PSIG2 (the second potential VGL) is, for example, set to the low potential of the selection control signal MUX. The present disclosure is not limited by the potential of the selection control signal MUX.

[0094] The gate driver 42 is a circuit that generates a scanning signal GATE(m) to be supplied to the gate of the pixel transistor Tr based on the start pulse STV, the shift clock CKV, and the scanning line drive signal ENB output from the display control circuit 44 (driver IC4 ).

[0095] Specifically, during the selection period of the scanning line SCL connected to the m-th pixel row, the scanning signal GATE(m) is set to a high potential (first potential VGH), thereby turning on the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0096] In addition, during the non-selection period of the scanning line SCL connected to the m-th pixel row, the scanning signal GATE(m) is set to a low potential (second potential VGL), thereby turning off the pixel transistors Tr of the pixels Pix(n,m) and Pix(n+1,m).

[0097] The signal line selection circuit 43 includes a switch circuit ASW which divides the time during which the scanning line SCL connected to the m-th pixel row is selected, supplies a pixel signal SIG(n) to the pixel Pix(n,m), and supplies a pixel signal SIG(n+1) to the pixel Pix(n+1,m). Figure 6 In the example shown, the switch circuit ASW includes switching transistors Trn1 and Trn2 formed of n-type TFTs and switching transistors Trp1 and Trp2 formed of p-type TFTs.

[0098] The signal line selection circuit 43 includes a plurality of switch circuits ASW arranged in parallel along the Dx direction (first direction) on the array substrate 2. Figure 6The following example is shown: the selection period of the scan line SCL connected to the m-th pixel row is divided into two parts, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during the selection periods of the pixel Pix(n,m) and the pixel Pix(n+1,m). In this structure, the total number of switch circuits ASW arranged in the Dx direction (first direction) is N / 2.

[0099] Specifically, during the selection period of the signal line DTL connected to the pixel Pix(n,m), the selection control signal MUX1 is set to a high potential (first potential VGH), and the selection control signal xMUX1 is set to a low potential (second potential VGL). As a result, the switching transistors Trn1 and Trp1 are turned on and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n).

[0100] In addition, during the selection period of the signal line DTL connected to the pixel Pix(n+1,m), the selection control signal MUX2 is set to a high potential (first potential VGH), and the selection control signal xMUX2 is set to a low potential (second potential VGL). As a result, the switching transistors Trn2 and Trp2 are turned on and the image signal Vsig output from the display control circuit 44 (driver IC4) is selectively output as the pixel signal SIG(n+1).

[0101] In addition, Figure 6 Although the switch circuit ASW of CMOS structure is illustrated in the figure, it is not limited to this. For example, the switch circuit ASW may be formed of only n-type TFTs or only p-type TFTs.

[0102] In addition, Figure 6 The following example is illustrated: the selection period of the scan line SCL connected to the m-th row of pixels is divided into two parts, and the corresponding pixel signals SIG(n) and SIG(n+1) are selectively output during the selection periods of the pixels Pix(n, m) and the pixels Pix(n+1, m), but the present invention is not limited thereto. For example, the following example may be used: the selection period of the scan line SCL connected to the m-th row of pixels is divided into a plurality of periods of three or more parts, and the corresponding pixel signals SIG are selectively output during the selection periods of the pixels Pix.

[0103] Figure 7 1 is a schematic diagram of a substrate showing a connection example of a selection control line in a conventional example. In the following description, for convenience of description, a plurality of wirings that transmit selection control signals MUX1, xMUX1, MUX2, and xMUX2 are simplified as selection control lines SWL.

[0104] exist Figure 7 In the figure, the wiring (signal line DTL, image signal line VsigL, and selection control line SWL) in the signal line layer 53 (first metal layer) on the array substrate 2 is shown by solid lines, and the wiring (image signal line VsigL and selection control line SWL) in the gate line layer 51 (second metal layer) on the array substrate 2 is shown by dotted lines. The wiring on the signal line layer 53 (first metal layer) and the wiring on the gate line layer 51 (second metal layer) are connected by contact holes represented by black dots. In addition, the scanning line (gate line) SCL is omitted.

[0105] like Figure 7 As shown, the driver IC 4 is mounted on the array substrate 2 along the signal line selection circuit 43. The output buffer circuit Buf for selecting the control signal is usually provided at both ends of the driver IC 4 in the length direction.

[0106] exist Figure 7 In the connection example of the conventional example shown, the selection control lines SWL are connected to both ends of the signal line selection circuit 43 in the Dx direction (first direction).

[0107] Figure 8 1 is a schematic diagram of a substrate showing a connection example of selection control lines according to an embodiment. Fig. 9 It is along Figure 8 A schematic cross-sectional view of the B1-B2 line. Fig. 9 , examples are given with Figure 5A The pixel cross section shown has the same layer structure as the first example.

[0108] exist Figure 8 and Fig. 9 In the connection example of the selection control line of the embodiment shown, the selection control line includes: the first wiring SWL1, which connects a plurality of switch circuits ASW of the signal line selection circuit 43 arranged along the Dx direction (first direction) on the array substrate 2; the second wiring SWL2, which is arranged approximately parallel to the first wiring SWL1, and the two ends are respectively connected to the output buffer circuit Buf of the selection control signal arranged at the two ends of the driver IC4 in the Dx direction (first direction); and the third wiring SWL3, which is connected to the second wiring SWL2 at the two ends and the center of the first wiring SWL1. In addition, Figure 8 In the illustrated connection example, the video signal lines include: a first video signal line VsigL1 intersecting the second wiring SWL2 ; and a second video signal line VsigL2 connected to each of the switch circuits of the signal line selection circuit 43 .

[0109] exist Figure 8 In the connection example of the illustrated embodiment, the first wiring SWL1 , the second wiring SWL2 , and the third wiring SWL3 are provided on the signal line layer 53 (first metal layer) on the array substrate 2 .

[0110] exist Figure 8 In the connection example of the embodiment shown in FIG. Fig. 9 As shown, the two ends in the Dx direction (first direction) are connected to the output buffer circuit Buf of the selection control signal provided at the two ends in the Dx direction (first direction) of the driver IC4 via the contact holes H21 and H22 and the wiring provided in the gate line layer 51 (second metal layer). Fig. 9 As shown, the second wiring SWL2 intersects the first video signal line VsigL1 provided in the gate line layer 51 (second metal layer) via the insulating layers 58 a and 58 c .

[0111] The layer where the first wiring SWL1, the second wiring SWL2, and the third wiring SWL3 are provided is not limited to the signal line layer 53 (first metal layer). The first wiring SWL1, the second wiring SWL2, and the third wiring SWL3 may be provided in a metal layer different from the gate line layer 51 (second metal layer).

[0112] Fig.10 Yes means Figure 7 A diagram showing an example of a selection control signal waveform in the connection example shown. Fig.11 Yes means Figure 8 A diagram showing an example of a selection control signal waveform in the connection example shown.

[0113] The conduction timing of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2 varies according to the potential of the pixel signals SIG(n) and SIG(n+1). Fig.10 and Fig.11 , an example is shown in which the switching transistors Trn1 and Trp1 and the switching transistors Trn2 and Trp2 are turned on in a region where the selection control signal MUX (MUX1, xMUX1, MUX2, xMUX2) is equal to or higher than the potential indicated by the single-dot chain line.

[0114] Since the turn-on time and the turn-off time are generated due to the impedance of the selection control line SWL, the conduction period of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2 becomes longer than the selection period of the pixel Pix (n, m) (the high level period under the control of the selection control signal MUX1 and the low level period under the control of the selection control signal xMUX1) and the selection period of the pixel Pix (n+1, m) (the high level period under the control of the selection control signal MUX2 and the low level period under the control of the selection control signal xMUX2). Therefore, it is necessary to set an interval time Int between the selection period of the pixel Pix (n, m) and the selection period of the pixel Pix (n+1, m) so that the conduction period of the switching transistors Trn1, Trp1 does not overlap with the conduction period of the switching transistors Trn2, Trp2.

[0115] like Fig.10 As shown, in Figure 7 In the connection example shown, the impedance of the selection control line SWL becomes larger, and the on-time and off-time of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2 become longer. As a result, the actual on-time of the switching transistors Trn1 and Trp1 becomes longer relative to the selection period of the pixel Pix (n, m) (the high level period under the control of the selection control signal MUX1 and the low level period under the control of the selection control signal xMUX1). In addition, the actual on-time of the switching transistors Trn2 and Trp2 becomes longer relative to the selection period of the pixel Pix (n+1, m) (the high level period under the control of the selection control signal MUX2 and the low level period under the control of the selection control signal xMUX2). As a result, it is necessary to set the interval time Int set between the selection period of the pixel Pix (n, m) and the selection period of the pixel Pix (n+1, m) to be longer.

[0116] In the embodiment, the connection example of the selection control line SWL ( Figure 8 ), by increasing the supply point P of the selection control signal to the signal line selection circuit 43, the impedance of the selection control line SWL is different from that of the conventional example ( Figure 7 ) is lower than that of Fig.11 As shown, Fig.10Compared with the conventional example shown, the on time and off time of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2 can be shortened. As a result, the actual on time of the switching transistors Trn1, Trp1 relative to the selection period of the pixel Pix (n, m), and the actual on time of the switching transistors Trn2, Trp2 relative to the selection period of the pixel Pix (n+1, m) are shortened. As a result, the interval time Int set between the selection period of the pixel Pix (n, m) and the selection period of the pixel Pix (n+1, m) can be shortened. In addition, by shortening the on time of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2, the selection period of the pixel Pix (n, m) (the high level period under the control of the selection control signal MUX1 and the low level period under the control of the selection control signal xMUX1) and the selection period of the pixel Pix (n+1, m) (the high level period under the control of the selection control signal MUX2 and the low level period under the control of the selection control signal xMUX2) can be shortened. As a result, the selection period (1 horizontal period = 1H period) of the scanning line SCL connected to the m-th pixel row is shortened, and higher-definition display than in the conventional example can be realized at the same frame rate.

[0117] (Variation Example)

[0118] Fig.12 It is a schematic diagram of a substrate showing a connection example of selection control lines according to a modification of the embodiment. Fig.13 Yes means Fig.12 A diagram showing an example of a selection control signal waveform in the connection example shown.

[0119] exist Fig.12 In the variation shown, Figure 8 The number of supply points P of the selection control signal to the signal line selection circuit 43 is further increased. Fig.12 In the connection example of the selection control line of the modification of the embodiment shown, the selection control line includes the third wiring SWL3 connected to the second wiring SWL2 at a plurality of locations including both ends and the center of the first wiring SWL1.

[0120] Therefore, if Fig.13 As shown, Fig.11Compared with the connection example of the embodiment shown, the on time and off time of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2 can be further shortened. As a result, the actual on period of the switching transistors Trn1, Trp1 relative to the selection period of the pixel Pix (n, m) and the actual on period of the switching transistors Trn2, Trp2 relative to the selection period of the pixel Pix (n+1, m) are further shortened, and as a result, the interval time Int set between the selection period of the pixel Pix (n, m) and the selection period of the pixel Pix (n+1, m) can be further shortened. In addition, by further shortening the on time of the switching transistors Trn1, Trp1 and the switching transistors Trn2, Trp2, the selection period of the pixel Pix (n, m) and the selection period of the pixel Pix (n+1, m) can be further shortened. As a result, the selection period (1 horizontal period = 1H period) of the scanning line SCL connected to the m-th row of pixels is further shortened, and a higher-definition display can be achieved with the same array.

[0121] The position of the supply point P of the selection control signal to the signal line selection circuit 43 and the layer of the third wiring SWL3 extending from the second wiring SWL2 to the signal line selection circuit 43 can be appropriately set according to the configuration and wiring conditions of the display control circuit 44 (driver IC4) and the signal line selection circuit 43. Specifically, for example, Fig.12 In the connection example shown, the supply point P of the selection control signal to the signal line selection circuit 43 is preferably set at a position where the wiring direction changes between adjacent image signal lines VsigL. This can prevent the width between the signal line selection circuit 43 and the driver IC 4 in the Dy direction (second direction) from increasing.

[0122] It should be noted that the display device 1 is not limited to a liquid crystal display device, and may be, for example, an organic EL device using an organic light emitting diode (OLED: Organic Light Emitting Diode) as a display element. In addition, the display device 1 may also be an inorganic EL device using an inorganic light emitting diode (micro LED) as a display element. In addition, the display device 1 may also be an electrophoretic device (EPD: Electrophoretic Display), or a transparent device that displays an image on a transmissive display surface.

[0123] The preferred embodiments of the present disclosure are described above, but the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are only examples, and various changes can be made within the scope of the main purpose of the present disclosure. Appropriate changes made within the scope of the main purpose of the present disclosure are of course within the technical scope of the present disclosure.

Claims

1. A display device, characterized in that: have: A substrate having a display area in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction; A plurality of scanning lines connected to pixels arranged in the first direction; a plurality of signal lines connected to pixels arranged in the second direction; a gate driver for supplying a scanning signal to the scanning line during a selection period of the scanning line; a signal line selection circuit that supplies a pixel signal to the signal line during a selection period of the signal line; as well as a driver IC that generates a plurality of image signals obtained by time-division multiplexing pixel signals supplied to a plurality of signal lines and supplies the signals to the signal line selection circuit, and supplies a selection control signal of the signal line to the signal line selection circuit, The driver IC is mounted on the substrate along the signal line selection circuit. The selection control signal is output from buffer circuits provided at both ends of the driver IC in the first direction. The signal line selection circuit includes a plurality of switch circuits arranged along the first direction on the substrate for selecting one of the plurality of signal lines. The wiring for supplying the selection control signal to the signal line selection circuit includes: a first wiring to which a plurality of the switch circuits are connected in the first direction; a second wiring provided substantially in parallel with the first wiring and having both ends connected to the buffer circuit; and A plurality of third wirings are connected to the second wiring at a plurality of locations including at least both end portions and a central portion of the first wiring.

2. The display device according to claim 1, characterized in that The substrate has: a first metal layer having the signal line; and a second metal layer different from the first metal layer, The first wiring, the second wiring, and the third wiring are provided in the first metal layer. The wiring for supplying the image signal to the signal line selection circuit includes: a first image signal line provided in the second metal layer and intersecting the second wiring; and A second video signal line is provided in the first metal layer and connected to the switch circuit.

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