Error rate based voltage scaling

Abstract

The invention relates to voltage scaling based on error rate. A method includes generating parity information by circuitry residing on a memory device; attaching parity information to data read from the memory device to generate a bit string including the data read from the memory device and the parity information; transmitting, via a channel, the bit string from the memory device to a physical input / output PHY I / O device coupleable to the memory device; calculating a parity mismatch value based on a comparison between the received memory parity information and the calculated PHY I / O parity information; determining a target parity check mismatch value; comparing the calculated parity mismatch value with the determined target parity mismatch value; and adjusting a voltage in response to the comparison between the calculated even check mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to error rate based voltage scaling. Background Art

[0002] The memory system may include a memory subsystem, which may include one or more memory devices that store data, digital logic, and associated voltage controls. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices, and the voltage controls may change the voltage during operation of the digital logic. Summary of the invention

[0003] In one aspect, the present disclosure relates to a method for error rate-based voltage scaling, comprising: reading data from a memory device in response to a read operation; generating parity information by a circuit system residing on the memory device; appending the parity information to the data read from the memory device by the circuit system to generate a bit string including the data read from the memory device and the parity information; and transmitting the bit string from the memory device to a physical input / output (PHY I / O) device that can be coupled to the memory device via a channel.

[0004] On the other hand, the present disclosure relates to an apparatus for error rate-based voltage scaling, comprising: a plurality of memory dies; and a circuit system residing on at least one of the plurality of memory dies, wherein the circuit system is configured to: generate parity information; concatenate the parity information to a codeword read from one of the plurality of memory dies to generate a bit string including the codeword and the concatenated parity information; and cause the bit string to be transmitted to a circuit system outside the plurality of memory dies.

[0005] On the other hand, the present disclosure relates to a system comprising: a memory device comprising a plurality of memory dies, wherein the memory device is configured to: generate parity information by a circuit system residing on at least one of the plurality of memory dies; append the parity information to data read from one of the plurality of memory dies by the circuit system to generate a bit string, the bit string comprising the data read from the one of the plurality of memory dies and the parity information; and transmit the bit string from the memory device to a physical input / output (PHY I / O) device that can be coupled to the memory device via a channel; and the PHY I / O device coupled to a processing device, wherein the processing device is configured to: receive the bit string provided from the memory device through the channel; and determine the bit values ​​contained within the received bit string.

[0006] On the other hand, the present disclosure relates to an apparatus for error rate-based voltage scaling, comprising: a physical input / output (PHY I / O) device configured to receive a bit string including parity information provided from a memory device over a channel; and a processing device coupled to the PHY I / O device, wherein the processing device is configured to: calculate a parity mismatch value based on a comparison between memory parity information and calculated PHY I / O parity information determined by the processing device circuit system; determine an actual channel error rate based on the calculated parity mismatch value; and adjust a voltage in response to the determined channel error rate.

[0007] In another aspect, the present disclosure relates to a system for error rate-based voltage scaling, comprising: a memory device comprising a plurality of memory dies, wherein circuitry residing on at least one of the memory dies is configured to: write data received from a physical input / output (PHY I / O) device coupled to the memory device to the one of the plurality of memory dies; read data from the one of the plurality of memory dies; append parity information generated by the circuitry to the data read from the one of the plurality of memory dies to generate a first bit string including the read data and the parity information; and transmit the first bit string to the PHY I / O device via a channel; wherein the PHY I / O device is configured to: transmit data to the memory device; and receive the first bit string transmitted from the memory device via the channel including the read data and the memory parity information; and a processing device coupled to the PHY I / O device, wherein the processing device is configured to: compare the received memory parity information with a PHY I / O device calculated by the processing device The invention relates to a method for comparing the received memory parity information with the calculated PHY I / O parity information; calculating a parity mismatch value based on the comparison between the received memory parity information and the calculated PHY I / O parity information; determining an actual channel error rate based on the calculated parity mismatch value; and adjusting a voltage in response to the calculated parity mismatch value. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0010] Figure 2 An example apparatus for determining a parity mismatch value according to some embodiments of the present disclosure is described.

[0011] Figure 3 An example apparatus for error rate based voltage scaling according to some embodiments of the present disclosure is described.

[0012] Figure 4 A diagram illustrating an example method for determining a parity mismatch value according to some embodiments of the present disclosure.

[0013] Figure 5 A diagram illustrating an example method for error rate based voltage scaling according to some embodiments of the present disclosure.

[0014] Figure 6An example system including a memory device and a PHY I / O according to some embodiments of the present disclosure is described.

[0015] Figure 7 An example system including a memory device and a PHY I / O according to some embodiments of the present disclosure is described.

[0016] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure relate to voltage scaling based on error rates, and in particular, to a memory subsystem that includes circuitry (e.g., voltage scaling circuitry) for performing voltage scaling based on error rates. Voltage scaling can be used to match system power consumption to desired performance. Error rates associated with a system (e.g., a computing system) can be monitored to determine the setting of voltage values. Dynamic voltage scaling is a technique for reducing the power consumption of a system by dynamically adjusting the voltage of the system. This can take advantage of the fact that systems typically have nominal voltage settings. Dynamic voltage scaling that increases voltage can be referred to as overvoltage, while dynamic voltage scaling that decreases voltage can be referred to as undervoltage. Undervoltage can be performed to save power, particularly in computing systems such as laptops and other mobile devices where energy comes from a battery and is therefore limited, or in some cases, to increase the reliability of the computing system.

[0018] During operation of a computing system, data may incur errors while being transmitted to and / or from devices and / or due to inherent characteristics of the devices. For example, a fiber optic receiver or radio delivering data to a controller may transmit a certain percentage of corrupted data. In one embodiment, a memory device including a memory subsystem may experience data corruption on a certain percentage of the transmitted data. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid state drive (SSD). Figure 1 Examples of storage devices and memory modules are described in and elsewhere. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0019] During operation, data written to the memory subsystem may incur errors when being transferred to and from the memory device (e.g., when being written to or read from the memory device) and / or due to inherent characteristics of the memory device. For example, NAND memory devices tend to introduce errors (e.g., flipped bits) to the data stored therein due to inherent behaviors of NAND memory devices, such as voltage drift, read / write disturbances, and / or memory cell degradation. As a result, the execution of a read operation may return a bit from a memory cell (e.g., a NAND memory cell) that is different from the bit written to the memory cell. For example, a logic "0" written to a memory cell may be read as a logic "1" and vice versa. The error rate caused by the memory device (e.g., the bit error rate of the memory device and / or the signal-to-noise ratio of the memory device) may fluctuate over time due to factors such as temperature, age of the memory device, usage of the memory device, or workload. For example, because current is used to provide power to the memory subsystem, the memory subsystem may exhibit temperature fluctuations during operation. Such fluctuations may become more significant based on the type of workload to which the memory subsystem is subjected. For example, some types of workloads that may be characterized by a high volume of operations may cause greater temperature fluctuations within the memory subsystem, resulting in higher memory device error rates, than workloads characterized by a low volume of operations. Furthermore, the memory subsystem may experience temperature fluctuations based on the environment in which the memory subsystem is deployed. Additionally, over time and use, the quality of the memory subsystem may degrade, resulting in higher error rates and greater susceptibility to temperature and workload changes.

[0020] In addition, when the memory subsystem interacts with the host system via a channel (or other interface, communication bus, etc.), errors (e.g., bit error rate of the channel, signal-to-noise ratio (SNR) of the channel) may be encountered on the channel. Channel errors may depend on, but are not limited to, temperature, aging, voltage stability, and / or frequency (e.g., speed) changes of the memory subsystem and / or environment. As an example, as a general rule, the faster the channel, the higher the bit error rate (BER), and correspondingly, the slower the channel, the lower the BER. In addition, tolerances within the system may affect the channel error rate. For example, as a non-limiting example, on-die and off-die terminations, set I / O slopes and drive strengths, internal PLL / DLL jitter requirements, tolerances within internal analog and digital power supplies may affect the channel error rate. Therefore, the system may experience a total error rate of a combination between the error rate of the memory device (e.g., errors introduced during operation of the memory device) and the error rate encountered via the channel (e.g., errors introduced due to data traversing the channel). When the error rate of the memory device is minimal, the margins described above may be widened or the voltage of the system may be reduced, thereby allowing more errors to be encountered across the channel, resulting in lower precision required within the components utilized in the system, reducing resources and reducing costs. However, the error rate of the memory device may sometimes be significant, requiring mitigation of the error rate of the channel.

[0021] The error rate of a channel can be mitigated in several non-limiting ways (e.g., tighter tolerances of the system, manipulation of I / O conversion rates, termination, internal biasing, reducing speed or adjusting drive strength, pull-up / pull-down, attenuation / gain, clocking frequency and rate, etc.). In one example, the channel error rate can be mitigated by operating the channel at a specific voltage value or at a voltage value above a specific voltage value, which can be referred to as the "nominal voltage value" of the channel (or interface, bus, etc.). For example, the error rate associated with the channel can vary depending on the voltage value supplied to the system. For example, the greater the voltage supplied to the system (e.g., to the channel), the lower the channel error rate. Given a sufficiently high voltage, the total error rate experienced between the memory device and the channel may be sufficient to fully operate the system. For example, at such a voltage, the system may operate above or better than a target error rate level. Thus, some methods employ a system that can utilize a voltage level (e.g., a nominal voltage level) that operates the system above a target error rate level, resulting in a decrease in the overall efficiency of the system, an increase in power consumption, and / or an increase in the thermal load experienced by the memory subsystem or its components.

[0022] Aspects of the present disclosure address the above and other deficiencies by determining whether a system is operating above a target error rate level, the total error rate of the system being a memory device error rate and a channel error rate, for example, appending a parity check to data read from a memory device to produce a bit string, transmitting the bit string to a host device via a channel, determining the bit error rates of the memory device and the channel, comparing an actual total bit error rate (BER) to a target total bit error rate (BER), and adjusting a voltage of the system in response to the comparison to scale the voltage to a level that increases the efficiency of the system and continues to produce an acceptable total error rate.

[0023] For example, embodiments herein may allow for dynamic control of the bit BER tolerated by a channel (e.g., a PHY I / O channel, such as an Open NAND Flash Interface (ONFI) channel) to reduce power consumption within a memory subsystem without negatively impacting the performance of a memory device (e.g., a NAND memory device) utilized by the memory subsystem. As will be described in greater detail herein, these and other aspects of the present disclosure may be achieved by appending a parity check at the memory die level to data read from a memory device and comparing this parity check to a parity check generated by circuitry coupled to the channel (e.g., by circuitry associated with an ONFI interface). These parity checks may be compared to determine the BER of the channel. When the actual total error rate mentioned above is less than or greater than the target total error rate, the amount of power provided to the various components of the memory subsystem may be adjusted, thereby changing the actual BER of the channel, and in turn changing the actual total error rate, thereby improving efficiency when operating within an acceptable target total error rate.

[0024] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a memory device, a memory module, or a mixture of a memory device and a memory module. Examples of memory devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other vehicles), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like.

[0028] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120, for example, uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0029] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] One of the memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages that may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130 and / or the memory device 140.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] Memory subsystem 110 may include voltage scaling circuitry 113. Although not described herein, Figure 11 to avoid obscuring the diagram, but the voltage scaling circuitry 113 may include various circuitry to facilitate adjusting the voltage in response to a parity mismatch value between the parity information generated by the parity logic 129 of the memory device 130 (memory parity information) and the parity information calculated by the parity logic 126 of the PHY I / O. As used herein, the term "parity mismatch value" generally refers to a condition in which one or more parity bits appended to the bit string and received from the memory device do not match the parity bits calculated by the parity logic 126 of the PHY I / O (PHY I / O parity information). The parity mismatch value may indicate that one or more bits in the bit string may be in error. As will be appreciated, the PHY I / O may generally be an input / output (I / O) device of the physical (PHY) layer of the OSI being calculated. In some embodiments, the PHY I / O may be an ONFI interface, but embodiments are not so limited. The parity logic 126 may reside on the PHY I / O. As described in further detail below, the term "residing on" refers to something that is physically located on a particular component.

[0041] In some embodiments, voltage scaling circuitry 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that may allow voltage scaling circuitry 113 to program and / or execute operations to selectively perform regulation of voltage.

[0042] In some embodiments, the memory subsystem controller 115 includes at least a portion of the voltage scaling circuitry 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the voltage scaling circuitry 113 is part of the host system 110, an application, or an operating system.

[0043] In a non-limiting example, a device (e.g., computing system 100) may include memory subsystem voltage scaling circuitry 113. Memory subsystem voltage scaling circuitry 113 may reside on memory subsystem 110. As used herein, the term "resides on" refers to something that is physically located on a particular component. For example, memory subsystem voltage scaling circuitry 113 "resides" on memory subsystem 110 refers to a condition in which the hardware circuitry including memory subsystem voltage scaling circuitry 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "deployed on" or "located on".

[0044] The memory subsystem voltage scaling circuitry 113 may be configured to adjust the voltage and / or control the adjustment of the voltage. Parity information may be generated by the parity logic 129 of the memory device 130 and appended to data read from the memory components of the memory subsystem 110. As described above, the memory components may be memory dies (e.g., Figure 2 130) and / or a memory package forming at least a portion of the memory device 130. To further elaborate, the parity information generated by the parity logic 129 of the memory device 130 may be appended to the data read from the memory device 130 to generate a bit string including the data read from the memory device 130 and the parity information generated by the parity logic 129. The bit string including the generated memory parity information and the data read from the memory device 130 may be received by the PHY I / O over the channel and compared to the parity information calculated by the parity logic 126 of the PHY I / O. The memory subsystem voltage scaling circuitry 113 may adjust the voltage in response to a parity mismatch value between the received memory parity information and the calculated PHY I / O parity information.

[0045] The memory subsystem controller 115 may control the transmission of the bit string generated by the memory device 130 to the PHY I / O 123 of the memory subsystem 110. The PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be configured to calculate a parity mismatch value, for example, using the parity check logic 126. For example, the PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be configured to compare the memory parity information received from the memory device 130 with the PHY I / O parity information calculated by the parity check logic 126 to calculate the parity mismatch value. The PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be further configured to determine an actual BER of a channel across which the bit string is transmitted, wherein the actual BER of the channel is based on the calculated parity mismatch value. In addition, as will be described in further detail below, the PHY I / O 123 can be configured to determine the actual BER of at least one of the memory components based on a difference between the actual total BER of the system and the actual BER of the channel. In some embodiments, the actual BER of at least one of the memory components and the actual BER of the channel (as the actual total BER of the system) can be compared to a target total BER to determine whether the actual total BER is below the target total BER, above the target total BER, or at the target total BER. Thus, the voltage can be scaled (i.e., altered to increase or decrease the voltage value) in response to the comparison between the actual total BER of the system and the target total BER.

[0046] For example, in some embodiments, the PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be configured to determine the memory components and channels (e.g., the processing unit 121 coupled to the PHY I / O 123) based on the memory components and channels (e.g., the processing unit 121 coupled to the PHY I / O 123). Figure 2 and Figure 3 224 / 324 illustrated in FIG. 224 / 324) is below a threshold of a target total BER. In some embodiments, the PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be configured to scale the voltage value up based on determining that the actual total BER of at least one of the memory component and the channel is above a threshold of the target total BER. In some embodiments, the PHY I / O 123 (e.g., the processing unit 121 coupled to the PHY I / O 123) may be configured to maintain (i.e., keep the voltage value unchanged) based on determining that the actual total BER of at least one of the memory component and the channel is within a threshold of the target total BER.

[0047] By determining a comparison between the actual overall BER and the target overall BER and scaling the voltage supplied to the system based on the comparison, the channel error rate can be adjusted to achieve an overall adjustment of the actual overall BER. Adjusting the channel error rate can allow the system to operate at an acceptable error rate while supplying a minimum voltage, thereby improving the efficiency of the system and thereby providing an improvement in the overall functionality of a computing system in which aspects of the present disclosure are employed.

[0048] Figure 2 An example apparatus 200 for calculating parity mismatch values ​​according to some embodiments of the present disclosure is illustrated. The apparatus may include a memory subsystem 210 including parity logic 229. The memory subsystem 210 may include a plurality of memory dies 228-1 to 228-M (collectively referred to as "memory dies 228"). In contrast to previous approaches, the parity logic 229 may reside on at least one of the plurality of memory dies 228. Alternatively, the parity logic 229 may reside on a memory device outside of the plurality of memory dies 228 (e.g., such as Figure 1 229). Parity logic 229 may include hardware (e.g., circuitry) configured to generate and / or append parity bits (e.g., concatenated parity information) on a string of bits read from memory device 130 and, therefore, from memory die 228. In some examples, multiple memory dies 228 may reside on NAND memory device 130, and / or parity logic 229 may reside on one or more of the memory dies 228.

[0049] In some embodiments, parity logic 229 residing on the memory subsystem 210, the memory device 130, and / or the memory die 228 of the memory device 130 may be configured to generate parity information. As mentioned above, the parity logic 229 may be further configured to concatenate the parity information generated by the parity logic 229 to a codeword read from one of the plurality of memory dies 228 to generate a bit string. The codeword may include host data (e.g., user data, etc.) and / or elements of an error correction code. In general, a "codeword" refers to a bit string containing a predetermined number of bits, which may include data (e.g., payload), error correction bits (e.g., parity), a header (e.g., one or more bits describing the purpose of the bit string), and / or an address locator (e.g., an address to which the bit string will be written or from which the bit string will be retrieved). The bit string may include the codeword and the concatenated parity information. The parity logic 229 may be configured to further cause the bit string to be transmitted to a circuit system external to the plurality of memory dies 228. For example, circuitry external to the plurality of memory dies 228 may include a physical input / output (PHY I / O) 223 device that may be coupled to the plurality of memory dies 228 via a channel 224. The PHY I / O 223 may receive a bit string from the memory device 130 via the channel 224. As mentioned above, the channel 224 may be a channel of an interface, such as an ONFI interface, a bus, or a similar collection of channels configured to facilitate the transfer of data (e.g., a bit string) between the PHY I / O 223 and the memory device 130.

[0050] The decoder 225 may be coupled to the PHY I / O 223 and / or the memory device 130. The decoder 225 may be a low density parity check (LDPC) decoder 225 configured to decode a codeword, which may include firmware and / or hardware. Decoding the codeword may be part of a read operation. The decoded data generated by decoding the codeword may be used to determine the actual total number of errors received from the memory device 130. For example, the execution of a read operation may return a different bit from the bit written to the memory cell from a memory cell (e.g., a NAND memory cell). For example, a logical "0" written to a memory cell may be read as a logical "1" and vice versa. In addition, during the transmission of data between the memory device 130 and the PHY I / O 223, the channel 224 through which the bit string is transmitted may cause errors. Therefore, in addition to the actual BER of the channel, the actual total BER of the system may also include the actual BER of the memory die. As discussed above, the actual BER of the channel may be determined based on the calculated parity mismatch value.

[0051] For example, PHY I / O 223 (e.g., processing unit 221 coupled to PHY I / O 223) may be configured to calculate PHY I / O parity information using, for example, parity logic 226. PHY I / O 223 (e.g., processing unit 221 coupled to PHY I / O 223) may be further configured to receive a bit string including memory parity information from memory device 130 (and data read from memory device 130), and compare the calculated PHY I / O parity information with the received memory parity information to calculate a parity mismatch value based on the bit values ​​included in the received bit string. PHY I / O 223 may then be used to determine the actual BER of the channel based on the calculated parity mismatch value.

[0052] Figure 3 An example device 300 for error rate based voltage scaling according to some embodiments of the present disclosure is illustrated. The device 300 may be similar to Figure 2 , and therefore, Figure 3 The Figure 2 Elements with similar names to the elements in the figure may be similar to each other. The apparatus may include a physical input / output (PHY I / O) device 323 including parity check logic 326. The PHY I / O may be coupled to a decoder 325 (e.g., a low density parity check (LDPC) decoder), a processing unit 321, and / or a voltage regulator 327.

[0053] In some embodiments, a processing unit 321 coupled to a PHY I / O device 323 and utilizing parity logic 326 of the PHY I / O device 323 may receive memory parity information corresponding to a bit string received by the PHY I / O device 323. The bit string may be received via a channel 324. In a less limiting example, the bit string may be received via a channel 324 associated with an Open NAND Flash Interface (ONFI) interface or other type of bus.

[0054] The processing unit 321 may be configured to calculate PHY I / O parity information using the parity logic 326 of the PHY I / O device 323. The calculated PHY I / O parity information may be compared to the memory parity information generated by the parity logic 329 and appended to the bit string. The processing unit 321 may be further configured to calculate a parity mismatch value based on a comparison between the calculated PHY I / O parity information and the received memory parity information. Due to errors encountered when transmitting and receiving data through the channel 324, the calculated PHY I / O parity information may be different from the received memory parity information. The difference between the calculated PHY I / O parity information and the received memory parity information generated and transmitted from the memory device 130 is the calculated parity mismatch value. The processing unit 321 may be configured to determine an actual channel error rate based on the calculated parity mismatch value, and adjust the voltage in response to the actual channel error rate and the target channel error rate.

[0055] For example, the processing unit 321 may be configured to determine a target parity mismatch value. The target parity mismatch value may indicate a target channel error rate. The target parity mismatch value may be determined based on subtracting the actual memory device error rate from a target or threshold total target error rate (e.g., an acceptable performance level of the memory device) determined by the processing unit 321. The processing unit 321 may be configured to calculate the actual memory device error rate. For example, the processing unit 321 may utilize a decoder 325 coupled to the PHY I / O 323 and the processing unit 321 to determine the actual total BER of data received from the memory device 130 (e.g., the actual error rate of the memory device and the actual error rate encountered via the channel). The parity check logic 326 of the PHY I / O 323 may be used to determine the actual BER of data read from the memory device 130 encountered by the channel. The processing unit 321 may further calculate the difference between the actual total BER determined using the decoder 325 and the actual channel BER determined using the parity check logic 326 to determine the actual BER of the memory device 130. Thus, the processing unit 321 may calculate a target parity mismatch value according to the difference between the target total error rate or the threshold total error rate and the actual BER of the memory device 130 .

[0056] The target parity mismatch value may be dynamic based on the actual BER encountered by the memory device 130. When the actual BER of the memory device 130 has few errors (i.e., a low error rate), the voltage may be reduced, thereby allowing a higher error rate across the channel. Thus, as the memory device 130 degrades over time, the error rate of the memory device 130 may increase. Thus, as the actual BER of the memory device 130 increases closer to a target or threshold total error rate (i.e., toward a high error rate), the voltage may be increased to minimize the actual BER encountered on the channel. In this way, the actual total BER may be maintained at or near a target or threshold total error rate.

[0057] Furthermore, the BER of the memory device 130 fluctuates during the life of the memory device 130 due to various circumstances, such as fluctuations in temperature, the type of workload, and degradation of the quality of the memory subsystem, but the examples are not so limited. Thus, the actual total BER (e.g., the actual BER of the channel combined with the actual BER of the memory device) will fluctuate due to the changing number of errors exhibited from the memory device 130 throughout the life and operation of the memory device 130. Thus, the difference between the target total error rate or threshold total error rate and the actual BER of the memory device will change depending on various aspects of the operation within the storage subsystem 310. In order to adapt to these changes in order to maintain optimal efficiency and produce an acceptable total error rate, the processing unit 321 may be configured to determine changes in the target parity mismatch value (e.g., the acceptable BER of the channel). In this manner, the target parity mismatch value may be a roaming or dynamic parity mismatch value.

[0058] The PHY I / O device 323 may be further coupled to a voltage regulator 327. The processing unit 321 may be configured to utilize the voltage regulator 327 to adjust the voltage by changing the voltage value from a first voltage value to a second voltage value in response to a comparison between the calculated parity mismatch value and the target parity mismatch value. As described above, the target parity mismatch value may change as the actual BER of the memory device 130 fluctuates over time and as the memory subsystem 130 operates. Therefore, the processing unit 321 may be configured to further change the voltage value in response to a comparison between the calculated parity mismatch value and the roaming parity mismatch value. In other words, the voltage may depend on the actual total error rate and may be adjusted as the actual total error rate fluctuates in order to produce an optimal BER for the channel.

[0059] For example, in an embodiment where channel 324 is provided as part of an ONFI bus (e.g., an interface), the ONFI bus may operate at a nominal voltage associated with the ONFI bus. This nominal voltage may produce a minimum channel error rate, however, as discussed herein, the nominal voltage value may be greater than necessary to operate the memory subsystem 310 while maintaining an actual total BER within an acceptable error threshold. In the case where the calculated parity mismatch value is lower than the target parity mismatch value, the system operates at a desired state that is higher or "better than" that required to maintain an acceptable BER. Reducing the voltage may increase the actual channel error rate. However, in this example, since the calculated parity mismatch value is lower than the target parity mismatch value, the increase in the actual channel error rate is acceptable. The voltage value may be reduced, thereby reducing power consumption and adverse thermal effects on the memory subsystem 310 while increasing the efficiency of the memory subsystem 310.

[0060] For example, the first voltage value may be a nominal voltage associated with the ONFI bus, and the second voltage value may be less than the first voltage value. In the case where the calculated parity mismatch value is lower than the target parity mismatch value, the processing unit 321 may be configured to cause the voltage regulator 327 to adjust the voltage from the first voltage value (the nominal ONFI bus voltage value) to the second voltage value (less than the nominal voltage value). In the case where the calculated parity mismatch value is still lower than the target parity mismatch value after the voltage has been adjusted from the first voltage value to the second voltage value, the processing unit 321 may be configured to cause the voltage regulator 327 to adjust the voltage by changing the voltage value from the second voltage value to a third voltage value, the third voltage value being less than the first voltage value and less than the second voltage value.

[0061] In the event that the calculated parity mismatch value is equal to or within the determined threshold range of the target parity mismatch value, the processing unit 321 may be configured to cause the voltage regulator 327 to maintain the voltage value. Although three voltage values ​​are described, the scope of the present disclosure further contemplates the use of more than three voltage values ​​to provide additional fine tuning of the voltage value selected during operation of the memory subsystem 310. Furthermore, it is contemplated within the scope of the present disclosure to dynamically change the voltage value based on the real-time calculated parity mismatch value by, for example, increasing the voltage value from the third voltage value to the second voltage value, increasing the voltage value from the second voltage value to the nominal voltage value, and so on.

[0062] In an illustrative non-limiting example, when it is determined that the actual total BER of the channel 324 and the memory device 130 is greater than 6×10 -3, the nominal voltage can be used to minimize the errors introduced by channel 324. This is because memory device 130 is introducing so many errors that any reduction in the amount of errors introduced by channel 324 will help ensure accurate data retrieval. In contrast, if the actual combined BER of channel 324 and memory device 130 is less than 4×10 -3 , then the lowest voltage (e.g., the third voltage value) may be applied to PHY I / O 323 to save resources within storage subsystem 310 and improve the efficiency of storage subsystem 310. This is because memory device 130 is introducing an amount of errors below the threshold error rate (e.g., memory device 130 generally provides data with a minimum number of errors associated therewith), and thus some additional errors introduced by channel 324 are acceptable, particularly due to the benefits of reduced power consumption, higher or “better” thermal performance, etc., that may be experienced by memory subsystem 310 due to the reduction in voltage applied to PHY I / O 323. Continuing with this example, if the actual total BER of channel 324 and memory device 130 is between 4×10 -3 With 6×10 -3 , then a reduced voltage (e.g., a second voltage) may be applied to PHY I / O 323. This may allow for saving resources such as power compared to applying a nominal voltage, while still providing data that does not suffer from a large number of errors. It should be appreciated that the foregoing numerical examples are merely illustrative and should not be considered to limit the scope of the present disclosure to these particular enumerated values. Furthermore, while three zones are described, more or fewer zones are contemplated within the scope of the present disclosure, the zones may be divided differently, and / or the zones may be completely adjacent.

[0063] Figure 4 An example method diagram 440 for calculating a parity mismatch value according to some embodiments of the present disclosure is illustrated. The method 440 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 440 is performed by Figure 2 The memory subsystem circuit system 210 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] At operation 441, data may be read from the memory device. Data may be read from the memory device in response to a read operation.

[0065] At operation 442, parity information may be generated by circuitry resident on the memory device. The circuitry resident on the memory device may reside outside or within a memory die associated with the memory device. For example, the parity information may be generated by the circuitry resident on the memory device. Figure 2 and Figure 3 The parity logic 229 / 329 described in the above generates parity information on the memory die. In some embodiments, the parity information may be generated without enabling the memory device (e.g., Figures 1 to 3 130) of a memory controller (e.g., Figure 1 Parity information is generated in the case of a storage subsystem controller 115).

[0066] At operation 443, parity information may be appended to the data read from the memory device to generate a bit string. The bit string may consist of the data read from the memory device and the parity information. Figure 2 and Figure 3 The parity check logic 229 / 329 illustrated in appends parity check information to data read from a memory device. For example, the parity check information may be appended to data read from a memory device to generate a bit string without enabling a memory controller coupled to the memory device.

[0067] In some embodiments, the data read from the memory device may include a codeword. The codeword may include host data (e.g., user data, etc.) and / or elements of an error correction code. In general, a "codeword" refers to a bit string containing a predetermined number of bits, which may include data (e.g., a payload), error correction bits (e.g., parity), a header (e.g., one or more bits describing the purpose of the bit string) and / or an address locator (e.g., an address to which the bit string will be written or from which the bit string will be retrieved). In addition, the data read from the memory device may include multiple codewords (e.g., 5, 10, etc.). In some embodiments, appending parity information to the data read from the memory device may include appending corresponding parity information to multiple corresponding data read from the memory device to generate multiple bit strings including parity information. That is, multiple bit strings may include corresponding data read from the memory device and corresponding parity information. Figure 2 and 3 The parity logic 229 / 329 illustrated in appends corresponding parity information to a plurality of corresponding data read from the memory device. In some embodiments, the parity information may be concatenated on the data to produce a bit string read from the memory device.

[0068] At operation 445, a bit string (or multiple bit strings) may be transmitted (eg, read) from a memory device. The bit string may be transmitted via a channel (eg, as described above in conjunction with Figure 2 and Figure 3 The channel described herein) is transmitted to a physical input / output (PHY I / O) device that can be coupled to the memory device. The circuit system residing on the PHY I / O device (e.g., Figures 2 to 3 The parity check logic 226 / 326 described in the embodiment of the present invention may calculate a parity mismatch value based on the bit values ​​contained in the bit string. The actual BER associated with the channel may be determined by the circuitry and processing unit resident on the PHY I / O device based on the calculated parity mismatch value. The actual BER associated with the memory device may be determined by the circuitry, PHY I / O device, and processing unit resident on the decoder based on the total decoding error rate and the actual BER of the channel (e.g., the calculated parity mismatch value).

[0069] Figure 5 An example method diagram 550 for error rate based voltage scaling according to some embodiments of the present disclosure is illustrated. The method 550 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 550 is performed by Figure 1 The physical input / output (PHY I / O) device 123 is executed, for example, by Figure 2 and Figure 3 The processing units 221 and 321 of the embodiment of the present invention are executed. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] The PHY I / O device receives parity information corresponding to the bit string at operation 551. The bit string may be received (eg, read) from a memory device coupled to the PHY I / O device via an Open NAND Flash Interface (ONFI) channel.

[0071] At operation 553, a parity mismatch value may be calculated based on a comparison between received memory parity information (e.g., parity information generated by a memory device including any errors encountered by a channel) and calculated PHY I / O parity information (e.g., parity information calculated by a PHY I / O). The received memory parity information (and / or received data) typically includes errors introduced by the channel. The calculated parity mismatch value is equal to or based on the difference between the calculated PHY I / O parity information and the received memory parity information. Using the calculated parity mismatch value, an actual channel error rate may be determined. Furthermore, using the calculated parity mismatch value, an actual memory device error rate may be determined. For example, a decoder coupled to a PHY I / O and / or a memory device may be used to decode a codeword received (e.g., read) from a memory device to determine an actual total error rate of a memory subsystem. The actual memory device error rate may be calculated based on the difference between the actual total memory subsystem error rate and the actual channel error rate.

[0072] At operation 555, a target parity mismatch value may be determined. The target parity mismatch value may be associated with an acceptable number or acceptable range of errors or BER encountered when transmitting data over the channel.

[0073] At operation 557, the calculated parity mismatch value may be compared to the determined target parity mismatch value. For example, the calculated parity mismatch value may be determined to be higher than the target parity mismatch value. Correspondingly, the target parity mismatch value may be determined to be higher than the calculated parity mismatch value. Alternatively, the calculated parity mismatch value may be within an acceptable error range for the target parity mismatch value.

[0074] At operation 559, the voltage may be adjusted in response to a comparison between the calculated parity mismatch value and the target parity mismatch value. For example, in response to the calculated parity mismatch value being higher than the target parity mismatch value by a first threshold amount, the voltage may be adjusted by increasing the voltage. Increasing the voltage may result in a lower actual BER of the channel, thereby reducing the actual total error in the system, and reducing the parity mismatch value between the received memory parity information and the calculated PHY I / O parity information. Correspondingly, in response to the target parity mismatch value being higher than the calculated parity mismatch value by a second threshold amount, the voltage may be adjusted by reducing the voltage. Reducing the voltage may result in a higher actual BER of the channel, thereby increasing the actual total error in the system and increasing the parity mismatch value between the received memory parity information and the calculated PHY I / O parity information. In addition, reducing the voltage may result in a reduction in resources and a higher efficiency of the system.

[0075] In some embodiments, the calculated parity mismatch value may be within a threshold range of a target parity mismatch value. In this example, in response to the calculated parity mismatch value being within the threshold range of the target parity mismatch value, adjusting the voltage may include maintaining a current voltage value. The first threshold amount, the second threshold amount, and the threshold range may be predetermined and configured by a processing device coupled to the PHY I / O device.

[0076] Figure 6 An example system 660 is illustrated that includes a memory device 630 and a PHY I / O 623 in accordance with some embodiments of the present disclosure. The memory device 630 may be coupled to a physical input / output (PHY I / O) device 623 and a processing device 621 via a channel and may include multiple memory dies.

[0077] At operation 661 of system 660, memory device 630 may be configured to generate parity information. Parity information may be generated by circuitry residing on at least one of a plurality of memory dies (e.g., in one of the dies, in a plurality of dies, or per die) of memory device 630. In some embodiments, parity information may be generated without enabling a memory controller coupled to memory device 630.

[0078] At operation 663 of system 660, the generated parity information may be appended to data read from one or more of the plurality of memory dies to generate a bit string. Figures 2 to 3 630) to append parity information. The circuitry may reside on one or more of the plurality of memory dies and may be appended to data read from one or more of the plurality of memory dies to generate a bit string without enabling a memory controller coupled to the memory device 630. The generated bit string may include data read from one or more of the plurality of memory dies and the generated parity information. In some embodiments, the parity information may be concatenated to a codeword read from one or more of the plurality of memory dies, and the generated bit string may further include the codeword.

[0079] At operation 665 of system 660, a bit string including data and parity information read from one or more of the plurality of memory dies may be transmitted from memory device 630 to PHY I / O device 623 via a channel. In some embodiments, the channel may be an Open NAND Flash Interface (ONFI) bus.

[0080] At operation 667 of the system 660, the bit string transmitted from the memory device 630 may be received by the PHY I / O device 623. The PHY I / O device 623 may be coupled to a processing device 621 configured to receive the bit string through a channel (ONFI bus). The PHY I / O device 623 may receive a codeword included in the bit string and decode the codeword using a decoder coupled to the PHY I / O device 623.

[0081] At operation 669 of system 660, processing device 621 coupled to PHY I / O device 623 may be configured to determine bit values ​​included in the bit string. Based on the bit values ​​determined to be included in the bit string, processing device 621 may be further configured to calculate a parity mismatch value. Calculating the parity mismatch value may include comparing the bit values ​​within parity information (e.g., memory parity information) included in the bit string with the bit values ​​generated by circuitry (e.g., in the memory). Figures 2 to 3 In addition, the processing device 621 can be configured with a decoder to decode the codewords received by the PHY I / O 623 from the memory device 630 to determine the actual total error rate of the system 660.

[0082] Using the calculated parity mismatch value, processing device 621 can be configured to determine an actual BER associated with the channel based on the calculated parity mismatch value. In addition, processing device 621 can be configured to calculate the difference between the actual total error rate of system 660 and the actual BER of the channel to determine the actual BER associated with the plurality of memory dies.

[0083] Figure 7 An example system 770 is illustrated that includes a memory device 730 and a PHY I / O 723, in accordance with some embodiments of the present disclosure. The memory device 730 may be coupled to a physical input / output (PHY I / O) device 723 via a channel and may include multiple memory dies.

[0084] At operation 771 of system 770, processing device 721 coupled to PHY I / O device 723 may be configured to transmit data from PHY I / O device 723 to memory device 730 included in system 770. Memory device 730 may store data for later use by PHY I / O device 723 or another device that may be coupled to memory device 730 and / or system 770.

[0085] At operation 773 of system 770, circuitry resident on at least one of the memory dies of memory device 730 may be configured to write data received from PHY I / O device 723 to one of the plurality of memory dies. The data may be stored in memory device 730 for later use by PHY I / O device 723 or another device that may be coupled to memory device 730 and / or system 770. The data written to the memory die may be partially corrupted and may include errors introduced to the data by the memory die.

[0086] At operation 774 of system 770, system 770 may be configured to read data from one of the plurality of memory dies.

[0087] At operation 775 of system 770, circuitry resident on at least one of the memory dies may be configured to append parity information generated by the circuitry to data read from one of the plurality of memory dies to generate a first bit string. The first bit string may include the read data and the parity information appended to the data. In some embodiments, memory device 730 may be a NAND memory device. In this example, the NAND memory device may append parity information to the bit string. In some embodiments, the bit string may include at least one codeword.

[0088] At operation 777 of system 770, circuitry resident on at least one of the memory dies may be configured to transmit the first bit string via a channel to PHY I / O device 723. The channel may comprise an Open NAND Flash Interface (ONFI) bus, but examples are not so limited.

[0089] At operation 779 of the system 770, the PHY I / O device 723 may receive a first bit string from the memory device 730 via a channel. The first bit string may include data previously transmitted from the PHY I / O device 723 to the memory device 730 at operation 771. The first bit string may further include memory parity information appended to the data and transmitted from the memory device 730 to the PHY I / O device 723 of the system 770.

[0090] At operation 781 of system 770, processing device 721 resident on system 770 and coupled to PHY I / O device 723 may be configured to calculate PHY I / O parity information. Processing device 721 may be further configured to receive memory parity information and compare the memory parity information with the calculated PHY I / O parity information.

[0091] At operation 783 of system 770, processing device 721 resident on system 770 and coupled to PHY I / O device 723 may be configured to calculate a parity mismatch value based on a comparison between the memory parity information and the calculated PHY I / O parity information.

[0092] At operation 785 of system 770, processing device 721 resident on system 770 and coupled to PHY I / O device 723 may be configured to determine an actual channel error rate based on the calculated parity mismatch value. As further described below, the actual channel error rate may be adjusted according to the voltage supplied to the system. The greater the voltage utilized, the lower the actual channel error rate, and vice versa.

[0093] In addition, as in Figure 2 and Figure 3 , the PHY I / O device 723 may be coupled to a decoder resident on the system 770. In some examples, the decoder may be a low density parity check (LDPC) decoder. The LDPC decoder may be utilized to configure the processing device 721 to decode codewords received from the memory device 730 over the channel to determine an actual total error rate for the system 770. For example, the received data may include information about data previously written to and read (e.g., received) from the memory device 730, including any partially damaged data and errors introduced to the data by the memory die. In addition, the received data may include errors introduced into the data and into the system 770 as the data is transmitted from the memory device 730 to the PHY I / O device 723 over the channel. The processing device 721 may be further configured to calculate an actual memory device error rate based on a difference between the actual total error rate and the actual channel error rate.

[0094] In some embodiments, processing device 721 may be further configured to determine a target parity mismatch value (e.g., an acceptable error rate). The target parity mismatch value calculated by processing device 721 may be associated with a difference between a target overall BER for system 770 that allows system 770 to operate at the highest or best efficiency and still produce an acceptable overall BER and the calculated memory device error rate.

[0095] At operation 787 of system 770, processing device 721 resident in system 770 and coupled to PHY I / O device 723 may be configured to adjust a voltage in response to the calculated parity mismatch value. For example, PHY I / O device 723 may be coupled to Figure 3, and the processing device 721 may be configured to compare the target parity mismatch value with the calculated parity mismatch value, and in response to the comparison, utilize the voltage regulator to change the supplied voltage. Changing the voltage may result in changing the actual BER of the channel. For example, increasing the voltage may reduce the errors encountered by the channel, and reducing the voltage may increase the errors encountered by the channel. If the calculated parity mismatch value is higher than the target parity mismatch value by a specified amount, or for example by a first threshold amount, then the processing device 721 may be configured to cause the voltage regulator to increase the voltage. Correspondingly, if the target parity mismatch value is higher than the calculated parity mismatch value by a specified amount, or for example by a second threshold amount, then the processing device 721 may be configured to cause the voltage regulator to reduce the voltage. Reducing the voltage may minimize resources and improve the efficiency of the system, thereby providing an improvement in the overall functionality of the computing system.

[0096] In some embodiments, the supplied voltage may start from a nominal voltage value. For example, the voltage may be a nominal voltage value associated with an open NAND flash interface (ONFI) bus. Adjusting the voltage may include changing the voltage from the nominal voltage to a second voltage that is lower than the nominal voltage value. The voltage value may be changed to the second voltage value in response to the target parity mismatch value being higher than the calculated parity mismatch value by at least a second threshold amount. When the voltage is changed to the second voltage value, a second bit string may be transmitted from the memory device 730 to the PHY I / O device 723. The processing device 721 may be configured to calculate a parity mismatch value between the received second bit string and the calculated second parity value associated with the second bit string. Thus, the processing device 721 may be configured to adjust the voltage to change the actual channel error rate, changing the parity mismatch value between the parity information received by the PHY I / O device 723 from the second bit string transmitted from the memory device 730.

[0097] In some examples, the calculated parity mismatch value may exceed or be higher than a target parity mismatch value. If the calculated parity mismatch value is higher than the target parity mismatch value by at least a first threshold amount, the voltage may be changed back from the second voltage value to the nominal voltage value, thereby increasing the supplied voltage. Increasing the voltage may reduce the actual BER of the channel and reduce the total error rate or the parity mismatch value between the calculated PHY I / O parity information and the received memory parity information. In some embodiments, in response to the calculated parity mismatch value being within a threshold range and not higher than a first threshold or a second threshold of the target parity mismatch value, the processing device 721 may be configured to adjust the voltage by maintaining the voltage value. Therefore, the PHY I / O device 723 voltage may be dynamically controlled to improve the power / performance combination.

[0098] Figure 88 is a block diagram of an example computer system 800 in which embodiments of the present disclosure may operate. For example, Figure 8 An example machine illustrating a computer system 800 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, to execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The computer may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0099] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0100] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0101] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 for communicating over a network 820.

[0102] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 826 by the computer system 800, the instructions 826 may also reside, in whole or in part, within the main memory 804 and / or within the processing device 802, which also constitute machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1 Memory subsystem 110.

[0103] In one embodiment, instructions 826 include implementing circuitry corresponding to voltage scaling and PHY I / O devices (e.g., Figure 1 The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0104] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0105] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into physical quantities similarly represented as within the computer system's memories or registers or other such information storage systems.

[0106] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0107] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0108] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0109] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for error rate based voltage scaling, comprising: reading data from a memory device (130) in response to a read operation; By a circuit system (129; 229； 339) generating parity information; appending, by the circuit system, the parity information to the data read from the memory device to produce a bit string including the data read from the memory device and the parity information; as well as The bit string is transmitted from the memory device via a channel (224; 324) to a physical input / output (PHYI / O) device (123; 223; 323) that may be coupled to the memory device.

2. The method according to claim 1, wherein: The circuitry residing on the memory device resides on a memory die associated with the memory device, and The circuitry generates the parity information on the memory die.

3. The method of claim 1 , further comprising appending, by the circuit system, respective parity information to a plurality of respective data read from the memory device to generate a plurality of bit strings comprising the respective data read from the memory device and the respective parity information.

4. The method of claim 1, further comprising generating the parity information, and appending the parity information to the data read from the memory device to generate the bit string without enabling a memory controller coupled to the memory device.

5. The method according to claim 1, further comprising: calculating, with circuitry resident on a processing unit coupled to the PHY I / O, a parity mismatch value based on bit values ​​contained within the bit string, wherein the parity mismatch value is indicative of an actual bit error rate, BER, associated with the channel; as well as utilizing circuitry resident on the processing unit to: decoding a codeword received in the bit string to determine an actual BER associated with a total error rate; and An actual BER associated with the memory device is calculated based on a difference between the actual BER associated with the total error rate and the actual BER associated with the channel.

6. An apparatus for error rate based voltage scaling, comprising: A plurality of memory dies (228-1, ..., 228-M; 328)； and circuitry (229; 329) residing on at least one of the plurality of memory dies, wherein the circuitry is configured to: Generate parity information; concatenating the parity information to a codeword read from one of the plurality of memory dies to produce a bit string including the codeword and the concatenated parity information; as well as Circuitry (223; 323) causes the bit string to be transmitted to external to the plurality of memory dies.

7. The apparatus of claim 6, wherein the circuitry external to the plurality of memory dies comprises a physical input / output (PHYI / O) device that is coupleable to the plurality of memory dies via a channel.

8. The apparatus of claim 7, wherein circuitry resident on the PHY I / O is to calculate a parity mismatch value based on bit values ​​contained within the bit string, wherein the PHY / IO is coupled to a processing unit, and the circuitry resident on the processing unit is to determine an actual bit error rate (BER) associated with the channel based on the calculated parity mismatch value, and wherein the circuitry resident on the processing unit is configured to: decoding the codeword received in the bit string to determine an actual BER associated with a total error rate; and An actual BER associated with the plurality of memory dies is calculated based on a difference between the actual BER associated with the total error rate and the actual BER associated with the channel.

9. A system comprising: A memory device comprising a plurality of memory dies, wherein the memory device is configured to: generating, by circuitry resident on at least one of the plurality of memory dies, parity information; appending, by the circuitry, the parity information to data read from one of the plurality of memory dies to produce a bit string comprising the data read from the one of the plurality of memory dies and the parity information; as well as transmitting the bit string from the memory device to a physical input / output (PHY) I / O device (123; 223; 323) that can be coupled to the memory device via a channel; and The PHY I / O device is coupled to a processing device, wherein the processing device is configured to: receiving the bit string provided from the memory device through the channel; as well as Bit values ​​contained within the received bit string are determined.

10. The system of claim 9, wherein the processing device is further configured to calculate a parity mismatch value based on the bit values ​​included in the received bit string, and wherein calculating the parity mismatch value comprises comparing the bit values ​​within the parity information included in the received bit string with parity information calculated by circuitry on the PHY I / O device.

11. The system of claim 9, wherein the processing device is further configured to: calculating a parity mismatch value based on the bit values ​​contained in the received bit string; determining an actual bit error rate, BER, associated with the channel based on the calculated parity mismatch value; decoding data in a codeword received in the bit string using a decoder coupled to the processing device; determining an actual BER associated with the actual total error rate based on the data in the codeword; as well as An actual BER associated with the plurality of memory dies is calculated based on a difference between the actual BER associated with the total error rate and the actual BER associated with the channel.

12. An apparatus for error rate based voltage scaling, comprising: a physical input / output (PHY) I / O device (123; 223; 323) configured to receive a bit string including parity information provided from a memory device (130) through a channel (224; 324); and a processing device (121; 221; 321) coupled to the PHY I / O device, wherein the processing device is configured to: calculating a parity mismatch value based on a comparison between memory parity information and calculated PHY I / O parity information determined by the processing device circuitry; determining an actual channel error rate based on the calculated parity mismatch value; as well as A voltage is adjusted in response to the determined channel error rate.

13. The apparatus of claim 12, wherein the processing device is further configured to: determining a target parity mismatch value; and The voltage is adjusted by changing a voltage value from a first voltage value to a second voltage value in response to a comparison between the calculated parity mismatch value and the target parity mismatch value.

14. The apparatus of claim 13, wherein the processing device is further configured to adjust the voltage by changing the voltage value from the second voltage value to a third voltage value, wherein the third voltage value is less than the first voltage value and less than the second voltage value.

15. The apparatus of claim 12, wherein the processing device is further configured to: determining a target parity mismatch value; comparing the target parity mismatch value to the calculated parity mismatch value; and In response to the calculated parity mismatch value being within a threshold range of the target parity mismatch value, the voltage is adjusted by maintaining a voltage value.

16. A system for error rate based voltage scaling, comprising: A memory device (130) comprising a plurality of memory dies (228-1, ..., 228-M; 328), wherein circuitry (129; 229; 339) resident on at least one of the memory dies is configured to: writing data received from a physical input / output (PHY) I / O device (123; 223; 323) coupled to the memory device to the one of the plurality of memory dies; reading data from said one of said plurality of memory dies; appending parity information generated by the circuitry to the data read from the one of the plurality of memory dies to generate a first bit string including the read data and the parity information; as well as transmitting the first bit string to the PHY I / O device via a channel (224; 324); Wherein the PHY I / O device is configured to: transferring data to the memory device; and receiving the first bit string including the read data and the memory parity information transmitted from the memory device via the channel; and a processing device (121; 221; 321) coupled to the PHY I / O device, wherein the processing device is configured to: comparing the received memory parity information with PHY I / O parity information calculated by the processing device; calculating a parity mismatch value based on the comparison between the received memory parity information and the calculated PHY I / O parity information; determining an actual channel error rate based on the calculated parity mismatch value; as well as A voltage is adjusted in response to the calculated parity mismatch value.

17. The system of claim 16, wherein the processing device is further configured to: decoding data in a codeword received in the bit string using a decoder coupled to the processing device; determining an actual total error rate based on the data in the codeword; as well as An actual memory device error rate is calculated based on a difference between the actual total error rate and the actual channel error rate.

18. The system of claim 16, wherein the processing device is further configured to: determining a target parity mismatch value; comparing the target parity mismatch value to the calculated parity mismatch value; and The voltage is adjusted to change the actual channel error rate, wherein changing the actual channel error rate changes a parity mismatch value between memory parity information received by the PHY I / O from a second bit string transmitted by the memory device.

19. The system of claim 18, wherein adjusting the voltage comprises: increasing the voltage in response to the calculated parity mismatch value being higher than the target parity mismatch value by a first threshold amount; as well as The voltage is reduced in response to the target parity mismatch value being higher than the calculated parity mismatch value by a second threshold amount.

20. The system of claim 18, wherein the processing device is further configured to: comparing the target parity mismatch value to the calculated parity mismatch value; and In response to the calculated parity mismatch value being within a threshold range of the target parity mismatch value, the voltage is adjusted by maintaining a voltage value.

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