Universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and prototype verification or hardware simulation acceleration platform

Abstract

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and in particular to a USB2.0 host speed reduction bridge based on a bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform. BACKGROUND

[0002] As a widely used external bus standard, USB is formulated and maintained by USB-IF, the official standard association of USB. From the beginning, USB has successively released multiple versions such as USB1.1, USB2.0, USB3.0, USB3.1 and USB3.2, and the new versions are forward compatible with the old versions, playing a key role in connecting and communicating of numerous electronic devices. However, in the chip prototype verification and hardware simulation acceleration scenarios, its high-speed characteristics bring many challenges. With the continuous improvement of chip scale, the demand for prototype verification and hardware simulation acceleration is also increasing. How to perform system-level functional verification on USB-related high-speed interfaces on the prototype verification and hardware simulation acceleration platform has become an important issue restricting the system-level verification of the whole chip.

[0003] Prototype verification and simulation accelerator is one of the most commonly used EDA tools in large-scale chip development. By mapping the logic of the chip to be tested into the FPGA or customized ASIC chip system based on multiple chips, it supports software and hardware co-development, can maximize the correctness of the chip function, and is thousands or even millions of times faster than traditional software simulation. According to different chip scales, the speed of prototype verification and simulation accelerator can reach 1M-100MHz, while the speed of traditional software simulation is usually only 1Hz-100Hz. Prototype verification and simulation accelerator can effectively shorten the development cycle of the chip and reduce the development cost, and is widely used in the development of GPU, CPU, GPGPU, AI chip, etc. With the increasing scale of chips, the requirements for prototype verification and simulation accelerator are becoming higher and higher, and the demand for high-capacity and high-speed prototype verification and simulation accelerator is increasing,

[0004] Prototype verification and simulation accelerator can accelerate the chip design simulation process, reduce verification time, improve development efficiency, and also provide powerful debugging and analysis functions. However, compared with the real running rate of the chip, its speed still has a gap. Taking the USB3.0 16bit data bit width PHY interface as an example, the clock frequency used by the PHY interface is 250MHz. Since the speed of the prototype verification and simulation accelerator is only 1M-100MHz, the speed cannot be directly matched, so it cannot be directly connected to the external PHY chip through the PHY interface, and therefore a speed reduction bridge is needed to balance the speed difference between the two sides, to realize the communication between the internal logic to be tested of the prototype verification and simulation accelerator and the external real-speed USB device, and further realize the system and verification of the USB-related functions of the chip to be tested.

[0005] For different high-speed interface protocols, a corresponding speed reduction bridge needs to be designed and implemented according to the protocol. Since the USB2.0 protocol has strict requirements for bus turn around time and cannot be closed, the traditional full-transmission type speed reduction bridge will cause the external real device data transmission to fail due to the protocol bus turn around timeout, so that the chip system-level verification of the USB2.0 related chip on the prototype verification or hardware simulation acceleration platform is in a dilemma. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a USB2.0 host speed reduction bridge prototype verification or hardware simulation acceleration platform based on bidirectional protocol handshake, and a prototype verification or hardware simulation acceleration platform, which are used to solve the technical problems that the internal running rate is too low to directly match the real external device and cannot meet the strict transmission timeout mechanism of USB2.0 in the chip prototype verification and hardware simulation acceleration platform of the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a USB2.0 host speed reduction bridge based on bidirectional protocol handshake, comprising: a slow side module for realizing the protocol layer and the physical link layer functions of the USB protocol under a slow clock frequency, and communicating with a USB2.0 host controller in a DUT; an original speed side module for realizing the protocol layer and the physical link layer functions of the USB protocol under an original clock frequency, and communicating with an external real USB2.0 slave device through a USB2.0 PHY; a data buffer RAM connected with the slow side module and the original speed side module respectively, for buffering and synchronizing the data exchanged between the original speed side module and the slow side module; and a bridge control module connected with the slow side module and the original speed side module respectively, for planning and controlling the independent handshake of the USB2.0 protocol layer of the original speed side and the slow side under the original clock frequency.

[0008] In an embodiment of the present application, the slow side module comprises: a slow side protocol layer module for realizing the protocol layer function of the USB protocol under a slow clock frequency; a slow side physical link layer module for realizing the physical link layer function of the USB protocol under a slow clock frequency; and a UTMI-UTMI interface conversion module for connecting the physical link layer of the USB protocol of the slow side and the USB2.0 host controller in the tested logic.

[0009] In an embodiment of the present application, the original-speed side module comprises: an original-speed side protocol layer module, configured to implement the function of the USB protocol layer at the original clock frequency; and an original-speed side physical link layer module, configured to implement the function of the physical link layer of the USB protocol at the original clock frequency, and communicate with the external real USB2.0 slave device through the USB2.0 PHY.

[0010] In an embodiment of the present application, the reduced-speed bridge buffers the OUT Token sent by the USB2.0 host controller after receiving the OUT Token, buffers the Data packet sent by the USB2.0 host controller after receiving the Data packet, forwards the buffered OUT Token and the Data packet to the real USB2.0 slave device in sequence, and forwards the handshake packet returned by the real USB2.0 slave device to the USB2.0 host controller.

[0011] In an embodiment of the present application, the reduced-speed bridge buffers the OUT Token sent by the USB2.0 host controller after receiving the OUT Token, buffers the Data packet sent by the USB2.0 host controller after receiving the Data packet, forwards the buffered OUT Token and the Data packet to the real USB2.0 slave device in sequence, and forwards the handshake packet returned by the real USB2.0 slave device to the USB2.0 host controller.

[0012] In an embodiment of the present application, the reduced-speed bridge forwards the IN Token to the real USB2.0 slave device after receiving the IN Token sent by the USB2.0 host controller, forwards the handshake packet or the complete data packet to the USB2.0 host controller after receiving the handshake packet or the data packet returned by the real USB2.0 slave device, buffers the handshake packet after receiving the handshake packet returned by the USB2.0 host controller, forwards the handshake packet to the real USB2.0 slave device directly when it is judged that the bus turnaround time corresponding to the IN transmission on the original-speed side does not time out, retransmits the buffered IN Token to the real USB2.0 slave device when it is judged that the bus turnaround time corresponding to the IN transmission on the original-speed side times out, and forwards the previously buffered handshake packet to the real USB2.0 slave device after the real USB2.0 slave device returns the data packet again.

[0013] In an embodiment of the present application, after the slow side module receives the IN token sent by the USB2.0 host controller, the bridge control module controls the IN token to be forwarded to the real USB2.0 slave device through the original speed side module; if the original speed side module receives the handshake packet replied by the real USB2.0 slave device, the bridge control module controls the handshake packet to be directly forwarded to the USB2.0 host controller through the slow side module; if the original speed side module receives the data packet replied by the real USB2.0 slave device, the bridge control module controls the data packet to be temporarily stored in the data cache RAM, and after the complete data packet is received by the original speed side module and cached in the data cache RAM, the bridge control module controls the complete data packet to be forwarded to the USB2.0 host controller through the slow side module; after the slow side module receives the handshake packet replied by the USB2.0 host controller, the bridge control module controls the handshake packet to be cached in the data cache RAM; when it is judged that the bus turn around time corresponding to the IN transmission of the original speed side does not time out, the bridge control module controls the handshake packet to be directly forwarded to the real USB2.0 slave device through the original speed side module; when it is judged that the bus turn around time corresponding to the IN transmission of the original speed side times out, the bridge control module controls the slow side module to resend the IN token cached before to the real USB2.0 slave device, and after the slow side module receives the data packet returned again by the real USB2.0 slave device, the bridge control module controls the handshake packet received by the original speed side module before to be forwarded to the real USB2.0 slave device.

[0014] In an embodiment of the present application, the slow bridge receives the PING token sent by the USB2.0 host controller, and forwards the PING token to the real USB2.0 slave device; after receiving the handshake packet replied by the real USB2.0 slave device, the handshake packet is forwarded to the USB2.0 host controller.

[0015] In an embodiment of the present application, after the slow side module receives the PING token sent by the USB2.0 host controller, the bridge control module controls the PING token received by the original speed side module to be forwarded to the real USB2.0 slave device; after the handshake packet replied by the real USB2.0 slave device is received through the original speed side module, the bridge control module controls the handshake packet to be forwarded to the USB2.0 host controller through the slow side module.

[0016] To achieve the above object and other related objects, the present application provides a prototype verification or hardware simulation acceleration platform, which comprises a USB2.0 host slow bridge based on a bidirectional protocol handshake.

[0017] As described above, the application is a USB2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification and hardware simulation acceleration platform, which has the following beneficial effects: the slow side module of the application runs at a slow clock frequency, is responsible for implementing the protocol layer of the USB protocol and the physical link layer function of the USB protocol, and communicates with the USB2.0 host controller in the chip design under test (DUT); the original speed side module works at the original clock frequency, achieves the protocol layer of the USB protocol and the physical link layer logic of the USB protocol, and communicates with the external real USB2.0 slave device through the USB2.0 PHY. The data buffer RAM realizes data buffering and synchronization; the bridge control module coordinates the whole process, and accurately controls the independent handshake of the USB2.0 protocol layer on both sides at the original clock frequency. Through the bidirectional protocol handshake of the speed reduction bridge on both sides, the application realizes that the slow chip design under test (DUT) in the chip prototype verification platform communicates with the external standard speed real USB slave device through the speed reduction bridge. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The structure schematic diagram of the USB2.0 host speed reduction bridge based on bidirectional protocol handshake in an embodiment of the application is shown.

[0019] Figure 2 The structure schematic diagram of the USB2.0 host speed reduction bridge based on bidirectional protocol handshake in an embodiment of the application is shown.

[0020] Figure 3 The USB2.0 data transmission flowchart in an embodiment of the application is shown. DETAILED DESCRIPTION

[0021] The embodiments of the application are described below through specific concrete examples, and those skilled in the art can easily understand other advantages and effects of the application from the content disclosed in the specification. The application can also be implemented or applied through other different specific embodiments, and each detail in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0022] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting, unless the above context clearly dictates otherwise. Spatially relative terms, such as "upper," "lower," "left," "right," "below," "above," "bottom," "top," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be further understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in use, a relative physical property previously described as on the bottom surface can now be said to be on the top surface, which is now the new bottom surface.

[0023] Throughout this specification, when it is said that a certain part is "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" in which other elements are interposed therebetween. In addition, when it is said that a certain part "includes" a certain constituent element, other constituent elements are not excluded unless specifically stated to the contrary, and it means that other constituent elements can also be included.

[0024] The terms first, second, third, etc. that are mentioned herein are used to describe various parts, components, regions, layers and / or sections, but are not limited thereto. These terms are used only to distinguish a certain part, component, region, layer or section from another part, component, region, layer or section. Thus, a first part, component, region, layer or section described below can be referred to as a second part, component, region, layer or section within the scope of the present application.

[0025] Further, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" when used herein, specify the presence of stated features, operations, elements, components, items, and / or objects, but do not preclude the presence or addition of one or more other features, operations, elements, components, items, and / or objects. As used herein, the term "or" and "and / or" is construed to be inclusive, or means one and any combination of the items. Thus, "A, B or C" or "A, B and / or C" means any of the following: A; B; C; A and B; A and C; B and C; A, B and C. This definition applies regardless of the lack of any occurring items, combinations of items, and / or the possibility of rearrangement of an item combination, in certain instances.

[0026] The application provides a USB2.0 host speed reduction bridge based on bidirectional protocol handshake, a slow side module runs at a slow clock frequency, is responsible for realizing protocol layer of USB protocol and physical link layer function of USB protocol, and communicates with a USB2.0 host controller in a chip design under test (DUT); a normal speed side module works at an original clock frequency, realizes protocol layer of USB protocol and physical link layer logic of USB protocol, and communicates with an external real USB2.0 slave device by means of USB2.0 PHY. Data buffer RAM realizes data buffering and synchronization; a bridge control module is in charge of the whole situation, accurately controls independent handshake of USB2.0 protocol layers on both sides at the original clock frequency. The application realizes data communication between a slow chip design under test (DUT) in a chip prototype verification platform and an external standard speed real USB slave device through a speed reduction bridge by means of bidirectional protocol handshake on both sides of the speed reduction bridge; the application is suitable for different types of USB transmission, is also suitable for a device under test being a USB2.0 host, and can be connected with different types of USB2.0 slave devices.

[0027] The embodiments of the application are described in detail below with reference to the drawings, so that those skilled in the art of the technical field to which the application pertains can easily implement the application. The application can be embodied in various different forms, and is not limited to the embodiments described herein.

[0028] As Figure 1 A structure schematic diagram of a USB2.0 host speed reduction bridge based on bidirectional protocol handshake in an embodiment of the application is shown.

[0029] Comprise:

[0030] The slow side module is used for realizing protocol layer and physical link layer function of USB protocol at a slow clock frequency, and communicating with a USB2.0 host controller in a DUT; specifically, the slow side module runs at a slow clock frequency environment, undertakes the task of realizing protocol layer and physical link layer function of USB protocol. And it can accurately analyze and generate signal and data format conforming to USB protocol specification, and ensure that communication between the slow side module and the USB2.0 host controller in the DUT conforms to the protocol standard.

[0031] The native-speed side module implements the protocol layer and physical link layer functions of the USB protocol at the native clock frequency, and communicates with external USB 2.0 slave devices via the USB 2.0 PHY. Specifically, the native-speed side module operates at the native clock frequency and is responsible for implementing the protocol layer and physical link layer functions of the USB protocol. It communicates with external USB 2.0 slave devices via the USB 2.0 PHY. The USB 2.0 PHY, as the physical layer interface, is responsible for converting the digital signals generated by the native-speed side module into analog signals suitable for transmission over the USB cable, and converting the received analog signals from the USB cable into digital signals for processing by the native-speed side module. The native-speed side module utilizes the physical connection provided by the USB 2.0 PHY to establish a communication link with the external USB 2.0 slave device, enabling bidirectional data transmission.

[0032] The data cache RAM is connected to both the slow-side module and the original-speed module, and is used to cache and synchronize the data exchanged between the original-speed module and the slow-side module. Since the slow-side module and the original-speed module operate at different clock frequencies and have different data transmission rates, the data cache RAM can temporarily store the data sent by one module and wait for the other module to read and process it at an appropriate time, thereby avoiding data loss or conflict.

[0033] The bridge control module, connected to both the slow-side module and the original-speed side module, coordinates and controls the independent handshakes of the USB 2.0 protocol layer between the original-speed and slow-speed sides at the original clock frequency. It manages the communication flow between the slow-side and original-speed side modules, ensuring that they interact according to predetermined protocol specifications.

[0034] In one embodiment, in a USB 2.0 host speed-down bridge based on a bidirectional protocol handshake, the slow-side module is a key component connecting the USB 2.0 host controller in the design under test (DUT). Operating at a slow clock frequency, it undertakes the crucial task of adapting the operations and data of the USB 2.0 host controller in the DUT to ensure smooth transmission and interaction within the speed-down bridge system. This lays the foundation for the entire speed-down bridge to enable communication between the slow DUT and external standard-speed devices.

[0035] like Figure 2 The slow-side module includes:

[0036] The slow-side protocol layer module is used to implement the protocol layer functions of the USB protocol at a slow clock frequency. Specifically, this module strictly adheres to the USB protocol specification and accurately implements the core functions of the USB protocol layer at a slow clock frequency. According to the USB protocol specification, the slow-side protocol layer module parses the data from the USB 2.0 host controller in the DUT and extracts key information. The slow-side protocol layer module also encapsulates the data from the original-speed side's actual USB 2.0 slave device according to the communication protocol requirements of the slow side.

[0037] The slow-side physical link layer module implements the physical link layer functions of the USB protocol at a slow clock frequency. Specifically, this module implements the physical link layer functions of the USB protocol at a slow clock frequency. It is primarily responsible for handling operations related to the physical transmission medium, including signal encoding and decoding, and link state machine control. This module also performs physical layer error detection. It further parses data from the USB 2.0 host controller in the DUT; and further encapsulates data from the native-side USB 2.0 slave device according to the communication protocol requirements of the slow side.

[0038] The UTMI-UTMI interface conversion module is used to interface the physical link layer of the USB protocol on the slow side and the USB 2.0 host controller in the logic under test. Specifically, this module operates at a slow clock frequency, and its main function is to achieve seamless interfacing between the physical link layer of the USB protocol on the slow side and the USB 2.0 host controller in the logic under test. UTMI (Universal Transceiver Macrocell Interface) is a commonly used USB transceiver interface standard. Different devices or modules may use different versions of the UTMI interface or have specific implementations of the UTMI interface. This conversion module can understand and handle these differences, completing the conversion and adaptation of interface signals. In the entire communication process, the UTMI-UTMI interface conversion module acts as a bridge between the physical link layer of the USB protocol on the slow side and the USB 2.0 host controller in the logic under test, playing a crucial role in signal relay and adaptation. It monitors the signal status of both interfaces in real time and performs timely conversion and transmission based on signal changes.

[0039] In one embodiment, in a USB 2.0 host speed-down bridge based on a bidirectional handshake protocol, the native speed-side module is the key hub connecting the speed-down bridge internally with the actual USB 2.0 slave device. It operates at the native clock frequency, i.e., the standard USB 2.0 operating clock frequency, enabling it to interact with external devices at a normal speed. This ensures that the speed-down bridge can be compatible with and accurately process various data and commands from the actual USB 2.0 slave device, achieving stable and efficient data communication between the speed-down bridge and the external device.

[0040] like Figure 2 The original velocity side module includes:

[0041] The native-speed protocol layer module implements the functions of the USB protocol layer at the native clock frequency. Specifically, this module strictly adheres to the USB protocol specification, accurately parsing protocol commands transmitted from the actual USB 2.0 slave device via the USB 2.0 PHY at the native clock frequency. Based on the parsed command information, the native-speed protocol layer module is responsible for organizing and encapsulating the data to be sent to the actual USB 2.0 slave device according to the format specified by the USB protocol. The native-speed protocol layer module also performs format checks on the data from the actual USB 2.0 slave device according to the USB protocol specifications.

[0042] The native-speed physical link layer module implements the physical link layer function of the USB protocol at the native clock frequency, communicating with external USB 2.0 slave devices via the USB 2.0 PHY. Specifically, before sending data to the external USB 2.0 slave device, it converts and adapts the signals according to the interface requirements of the USB 2.0 PHY, and then sends the data to the external USB 2.0 slave device via the USB 2.0 PHY. When data is returned from the external USB 2.0 slave device, it performs preliminary parsing and forwards it to the native-speed protocol layer module for subsequent verification and processing.

[0043] According to the protocol requirements, the time elapsed from the sender completing the transmission of a data packet to the start of receiving a response data packet must be less than the bus turn-around time specified in the protocol. If the timeout occurs, the sender will consider the transmission to have failed. To ensure that the transmission on the original speed side of the speed reduction bridge does not time out, the speed reduction bridge design scheme in this invention processes the transmission according to the following rules without violating the protocol.

[0044] In one embodiment, the USB 2.0 speed-reducing bridge coordinates data interaction between the slow-speed host and the original-speed USB slave device in OUT transmission scenarios. By caching OUT tokens and data packets and accurately forwarding handshake packets, stable communication between devices with different speeds is achieved, ensuring the integrity and reliability of data transmission.

[0045] like Figure 3The speed-reducing bridge buffers the OUT token sent by the USB 2.0 host controller. After receiving the data packet sent by the USB 2.0 host controller, it forwards the buffered OUT token and data packet to the actual USB 2.0 slave device in turn, and then forwards the handshake packet (ACK, NAK, NYET or STALL) it replies to to the USB 2.0 host controller.

[0046] In one specific embodiment, the slow-side module receives an OUT Token from the USB 2.0 host controller. The OUT Token contains crucial information such as the target device's address and endpoint number, which is essential for subsequent data forwarding. After capturing the OUT Token, the slow-side module parses and verifies its accuracy before writing it into a pre-allocated cache RAM. When the slow-side module receives a data packet from the USB 2.0 host controller, it sends a signal to the bridge control module after confirming the data packet reception is successful. After confirming that all aspects are normal, the bridge control module sends a forwarding command to the original-speed module. Upon receiving the forwarding command, the original-speed module reads the previously cached OUT Token and data packet from RAM and, according to its clock frequency and electrical characteristics, sends them to the actual USB 2.0 slave device via the USB 2.0 PHY. Upon receiving the OUT Token and data packet, the actual USB 2.0 slave device returns a corresponding handshake packet based on its processing capabilities and data reception status. The handshake packet is transmitted to the native-speed side module via the USB 2.0 PHY. After the native-speed side module receives the handshake packet from the actual USB 2.0 slave device via the USB 2.0 PHY, it notifies the bridge control module that the handshake packet has been received successfully. Then, the bridge control module sends a forwarding command to the slow-speed side module. Upon receiving the forwarding command from the bridge control module, the slow-speed side module encapsulates and converts the handshake packet according to the communication protocol and format of the slow-speed host, and then sends the handshake packet to the USB 2.0 host controller via the USB 2.0 bus.

[0047] In one embodiment, the USB 2.0 speed-down bridge is responsible for accurately and efficiently forwarding IN tokens, data packets, and handshake packets between two parties at different speeds in IN transmission scenarios, while handling possible abnormal situations such as bus turn-around timeouts, to ensure the integrity and reliability of data transmission.

[0048] like Figure 3When the speed-reducing bridge receives an IN token from the USB 2.0 host controller, it forwards the IN token to the actual USB 2.0 slave device. If it receives a handshake packet (NAK, STALL) from the actual USB 2.0 slave device, it forwards the handshake packet to the USB 2.0 host controller via the slow side. If it receives a data packet from the actual USB 2.0 slave device, it caches the data packet in RAM and forwards it to the USB 2.0 host controller via the slow side after receiving all the data packets. After receiving a handshake packet (ACK) from the USB 2.0 host controller, it caches the data packet. If it determines that the IN transmission on the original speed side has not exceeded the bus turn-around time, it directly forwards the handshake packet (ACK) to the actual USB 2.0 slave device. If it determines that the IN transmission on the original speed side has exceeded the bus turn-around time, it retransmits the cached IN token to the actual USB 2.0 slave device. After the actual USB 2.0 slave device returns a data packet again, it forwards the previously cached handshake packet (ACK) to the actual USB 2.0 slave device via the original speed side.

[0049] In one specific embodiment, after receiving the IN token from the USB 2.0 host controller via the slow-side module, the signal is transmitted to the bridge control module. The bridge control module parses the IN token, extracting information such as the device address and endpoint number, and uses this information to determine the target real USB 2.0 slave device. Then, the bridge control module sends a forwarding command to the original-speed side module, requesting it to send the IN token to the real USB 2.0 slave device. Upon receiving the forwarding command from the bridge control module, the original-speed side module converts and adjusts the IN token signal according to its clock frequency and electrical characteristics to ensure the signal meets the reception requirements of the real USB 2.0 slave device. After receiving the IN token, the real USB 2.0 slave device returns a corresponding response based on its data readiness. After the original-speed side module receives the handshake packet from the real USB 2.0 slave device, the bridge control module controls the forwarding of the handshake packet directly to the USB 2.0 host controller via the slow-side module; if the real USB 2.0 slave device has data to send, it returns a data packet. When the original speed module receives the data packet from the actual USB 2.0 slave device, the bridge control module temporarily stores the data packet in the data buffer RAM. After the original speed module receives the complete data packet and buffers it in the data buffer RAM, the bridge control module sends a forwarding command to the slow speed module, requesting the slow speed module to send the complete data packet to the USB 2.0 host controller. The slow speed module encapsulates and converts the data packet according to the slow speed side's communication protocol and format, and then sends it to the USB 2.0 host controller, completing the data packet forwarding process.

[0050] If it is determined that there is no bus turn-around timeout for the IN transmission on the original speed side, the bridge control module controls the original speed side module to directly handle the handshake packet and forward it to the real USB 2.0 slave device. The original speed side module encapsulates and converts the handshake packet according to the original speed side's communication protocol and format, and then sends it to the real USB 2.0 slave device to confirm successful data transmission. The IN transmission is then complete.

[0051] When the IN transmission bus turn-around time corresponding to the original speed side expires, the bridge control module controls the slow-speed side module to retransmit the cached IN token to the real USB 2.0 slave device. The real USB 2.0 slave device will prepare data again and return a data packet. After the slow-speed side module receives the data packet returned by the real USB 2.0 slave device, the bridge control module controls the forwarding of the handshake packet previously cached by the original speed side module to the real USB 2.0 slave device, completing this IN transmission.

[0052] In one embodiment, in a PING transmission scenario of a USB 2.0 speed-down bridge, the USB 2.0 host controller, as the initiator of the transmission, sends a PING token to query the status of the slave device; the speed-down bridge, as an intermediate bridge, is responsible for the conversion and forwarding of signals and data between the two sides at different speeds; the original speed USB slave device returns the corresponding handshake packet according to its own status to respond to the host's query.

[0053] like Figure 3 The slow-down bridge receives a PING token from the USB 2.0 host controller and forwards it to the actual USB 2.0 slave device. After receiving a handshake packet (ACK, NAK, or STALL) from the actual USB 2.0 slave device, it forwards the handshake packet to the USB 2.0 host controller through the slow side.

[0054] In one embodiment, after receiving the PING token from the USB 2.0 host controller via the slow-side module, the slow-side module performs preliminary parsing of the PING token, extracting key information such as the device address and endpoint number, and formats this information into a format suitable for processing by the bridge control module before transmitting it to the bridge control module. Upon receiving the PING token and its key information from the slow-side module, the bridge control module performs detailed analysis and processing. Then, the bridge control module sends a forwarding command to the original-speed side module, requesting it to forward the PING token to the corresponding actual USB 2.0 slave device. Upon receiving the forwarding command from the bridge control module, the original-speed side module parses the command, converts and adjusts the PING token signal, and then sends the adjusted PING token signal to the corresponding actual USB 2.0 slave device, completing the PING token forwarding process.

[0055] After receiving the PING token, the actual USB 2.0 slave device will return a corresponding handshake packet based on its own status. Once the native-side module receives the handshake packet from the actual USB 2.0 slave device, it will perform initial parsing. Then, the bridge control module will send a forwarding command to the slow-side module. Upon receiving the forwarding command from the bridge control module, the slow-side module will parse the command to obtain the specific content and type information of the handshake packet. According to the slow-side's communication protocol and format, the slow-side module will encapsulate and convert the handshake packet. After conversion, the slow-side module will send the encapsulated handshake packet signal to the USB 2.0 host controller, completing the handshake packet forwarding process. At this point, the PING transmission is complete.

[0056] Similar to the principles of the above embodiments, the present invention provides a prototype verification or hardware simulation acceleration platform.

[0057] like Figure 2 The prototype verification or hardware simulation acceleration platform includes: the USB 2.0 host speed-down bridge based on bidirectional protocol handshake described in the above embodiments, and the design logic of the chip under test including a USB 2.0 host controller.

[0058] The USB 2.0 host speed-down bridge based on bidirectional protocol handshake includes: a slow-side module, used to implement the protocol layer and physical link layer functions of the USB protocol at a slow clock frequency, and communicate with the USB 2.0 host controller in the DUT; a native-speed side module, used to implement the protocol layer and physical link layer functions of the USB protocol at the native clock frequency, and communicate with external real USB 2.0 slave devices through the USB 2.0 PHY; a data buffer RAM, connected to both the slow-side and native-speed side modules, used to buffer and synchronize the data exchanged between the native-speed and slow-side modules; and a bridge control module, connected to both the slow-side and native-speed side modules, used to coordinate and control the independent handshake of the USB 2.0 protocol layer on both the native-speed and slow-speed sides at the native clock frequency.

[0059] Since the implementation principle of the prototype verification or hardware simulation acceleration platform has been described in the foregoing embodiments, it will not be repeated here.

[0060] In summary, the USB 2.0 host speed-down bridge and prototyping or hardware simulation acceleration platform based on bidirectional protocol handshake of this invention features a slow-speed side module that operates at a slow clock frequency. This module is responsible for implementing the USB protocol's protocol layer and physical link layer functions, and communicating with the USB 2.0 host controller in the design under test (DUT). The original-speed side module operates at the original clock frequency, implementing the USB protocol's protocol layer and physical link layer logic, and communicating with external real USB 2.0 slave devices via the USB 2.0 PHY. A data buffer RAM handles data caching and synchronization. The bridge control module oversees the entire process, precisely controlling the independent handshake of the USB 2.0 protocol layers on both sides at the original clock frequency. This invention, through bidirectional protocol handshake on both sides of the speed-down bridge, enables the slow-speed DUT within the chip prototyping platform to communicate with external standard-speed real USB slave devices via the speed-down bridge. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0061] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A USB 2.0 host speed-reducing bridge based on bidirectional protocol handshake, characterized in that, include: The slow-side module is used to implement the protocol layer and physical link layer functions of the USB protocol at a slow clock frequency and to communicate with the USB 2.0 host controller in the DUT. The original clock frequency module is used to implement the protocol layer and physical link layer functions of the USB protocol at the original clock frequency, and communicate with external real USB 2.0 slave devices through the USB 2.0 PHY; The data cache RAM is connected to the slow-speed side module and the original-speed side module respectively, and is used to cache and synchronize the data exchanged between the original-speed side module and the slow-speed side module. The bridge control module is connected to the slow-side module and the original-speed side module respectively, and is used to coordinate and control the independent handshake of the USB 2.0 protocol layer of the original-speed side and the slow-speed side at the original clock frequency.

2. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 1, characterized in that, The slow-speed side module includes: The slow-side protocol layer module is used to implement the protocol layer functions of the USB protocol at slow clock frequencies. The slow-side physical link layer module is used to implement the physical link layer function of the USB protocol at slow clock frequencies. The UTMI-UTMI interface conversion module is used to interface the physical link layer of the USB protocol on the slow side and the USB 2.0 host controller in the logic under test.

3. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 2, characterized in that, The original velocity side module includes: The original clock frequency protocol layer module is used to implement the functions of the USB protocol layer at the original clock frequency. The native-speed physical link layer module is used to implement the physical link layer function of the USB protocol at the native clock frequency, and communicates with external real USB 2.0 slave devices through the USB 2.0 PHY.

4. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 3, characterized in that, After receiving the OUT Token sent by the USB 2.0 host controller, the speed-reducing bridge caches it. After receiving the Data packet sent by the USB 2.0 host controller, it forwards the cached OUT token and Data packet to the actual USB 2.0 slave device in turn, and then forwards the handshake packet it replies to to the USB 2.0 host controller.

5. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 4, characterized in that, The slow-side module receives the OUT Token sent by the USB 2.0 host controller and writes it into the data buffer RAM. When the slow-side module receives the data packet sent by the USB 2.0 host controller, the bridge control module controls the forwarding of the buffered OUT Token and data packet to the actual USB 2.0 slave device through the original-speed side module. After the original speed side module receives the handshake packet from the real USB 2.0 slave device through the USB 2.0 PHY, the bridge control module controls the forwarding of the reply handshake packet to the USB 2.0 host controller through the slow speed side module.

6. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 3, characterized in that, When the speed-reducing bridge receives an IN token from the USB 2.0 host controller, it forwards the IN token to the actual USB 2.0 slave device. After receiving a handshake packet or data packet from the actual USB 2.0 slave device, it forwards the handshake packet or complete data packet to the USB 2.0 host controller. Cache the handshake packet received in response from the USB 2.0 host controller; If the IN transmission corresponding to the original speed side does not have a bus turn-around timeout, the handshake packet is directly forwarded to the real USB 2.0 slave device. If the IN transmission corresponding to the original speed side has a bus turn-around timeout, the cached IN token is resent to the real USB 2.0 slave device. After waiting for the real USB 2.0 slave device to return the data packet again, the previously cached handshake packet is forwarded to the real USB 2.0 slave device.

7. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 6, characterized in that, After receiving the IN token sent by the USB 2.0 host controller through the slow-side module, the bridge control module controls the forwarding of the IN token to the actual USB 2.0 slave device through the original-speed side module; If the original speed side module receives a handshake packet from a real USB 2.0 slave device, the bridge control module will control the forwarding of the handshake packet directly to the USB 2.0 host controller through the slow speed side module. If the native-speed module receives a data packet from the actual USB 2.0 slave device, the bridge control module temporarily stores the data packet in the data buffer RAM. After the native-speed module receives the complete data packet and caches it in the data buffer RAM, the bridge control module forwards the complete data packet to the USB 2.0 host controller through the slow-speed module. After the slow-speed module receives the handshake packet from the USB 2.0 host controller, the bridge control module caches it in the data buffer RAM. If it is determined that the IN transmission corresponding to the native-speed module has not exceeded the bus turn-around time, the bridge control module directly forwards the handshake packet to the actual USB 2.0 slave device through the native-speed module. If it is determined that the IN transmission corresponding to the native-speed module has exceeded the bus turn-around time, the bridge control module controls the slow-speed module to retransmit the previously cached IN token to the actual USB 2.0 slave device. After the slow-speed module receives the data packet returned by the actual USB 2.0 slave device, the bridge control module forwards the previously cached handshake packet received by the native-speed module to the actual USB 2.0 slave device.

8. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 3, characterized in that, The speed-reducing bridge receives a PING token from the USB 2.0 host controller and forwards it to the actual USB 2.0 slave device. After receiving a handshake packet from the actual USB 2.0 slave device, it forwards the handshake packet to the USB 2.0 host controller.

9. The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in claim 8, characterized in that, After receiving the PING token from the USB 2.0 host controller via the slow-side module, the bridge control module controls the forwarding of the PING token received by the slow-side module to the actual USB 2.0 slave device. After receiving the handshake packet from the actual USB 2.0 slave device via the original speed side module, the bridge control module controls the forwarding of the handshake packet to the USB 2.0 host controller via the slow speed side module.

10. A prototype verification or hardware simulation acceleration platform, characterized in that, The platform includes: The USB 2.0 host speed-down bridge based on bidirectional protocol handshake as described in any one of claims 1 to 9.

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