Long-distance port expansion device based on multi-port PHY chip

By replacing the switch with a multi-port PHY chip, low-cost, low-latency long-distance data transmission is achieved, solving the problems of high cost and high latency of remote switches. It is suitable for industrial control and real-time data acquisition, and has hardware redundancy and rapid fault recovery capabilities.

CN121690876APending Publication Date: 2026-03-17KUNGAO XINXIN MICROELECTRONICS (JIANGSU) CO LTD
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Patent Information

Application Number
CN202511929198.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-19
Publication Date
2026-03-17

AI Technical Summary

Technical Problem

In traditional network communication systems, remote switching equipment is expensive and has high latency, making it difficult to meet the needs of industrial control and real-time data acquisition.

Method used

A multi-port PHY chip is used to directly replace the switch, enabling long-distance data transmission via fiber optic cable or shielded twisted pair cable. Automatic switching for link failures is implemented on the PHY chip, creating redundant transmission paths and eliminating the need for switching chips and processor modules.

Benefits of technology

It reduces hardware costs, decreases network latency, improves equipment reliability and fault recovery speed, adapts to the limited space and low power consumption requirements of industrial sites, and is compatible with existing Ethernet terminals.

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Abstract

The invention discloses a long-distance port expansion device based on a multi-port PHY chip, and the device comprises a near-end device which is integrated with a multi-channel serial interface supporting a multi-port protocol; the remote equipment comprises at least one PHY (Physical Layer) chip, and the PHY chip is provided with an uplink multi-channel protocol interface supporting a multi-port protocol and is provided with a plurality of downlink network ports; and the multi-channel serial interface of the near-end equipment is connected with the uplink multi-channel protocol interface of the PHY chip through a long-distance transmission medium. According to the invention, the port access and data forwarding functions of a traditional switch (including a switch realized by a switch chip or a processor) are directly replaced by the far-end multi-port PHY, and the method is suitable for various network communication scenes sensitive to network cost, time delay and architecture complexity.
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Description

Technical Field

[0001] This invention relates to the field of Ethernet technology, and in particular to a long-distance port expansion device based on a multi-port PHY chip. Background Technology

[0002] In port expansion applications of network communication systems (such as industrial field device access, edge node terminal expansion, etc.), such as Figure 1 As shown, traditional solutions typically employ a "near-end aggregation + remote-end switch" architecture to achieve multi-port access. The remote end requires the deployment of a separate switch device, which is often based on a switching chip or processor. A typical example is an integrated switch containing multiple access ports and uplink ports. It establishes a connection with the near-end device through wired transmission media (such as network cables or optical fibers), thereby enabling centralized access and data forwarding for multiple terminal devices.

[0003] However, traditional technical solutions are costly. Remote switches need to integrate switching chips, processors, power management modules, and the hardware cost of the switching chips themselves is high. In addition, network latency is significant. Data from terminal devices needs to go through a multi-level forwarding path of "terminal → remote switch → near-end device". The forwarding processing of the switching chip and the protocol interaction between the switch and the near-end device all introduce additional latency, affecting latency-sensitive applications such as industrial control and real-time data acquisition. Summary of the Invention

[0004] To address the aforementioned technical issues, this invention provides a low-latency, low-cost long-distance port extension technology solution. Its core purpose is to enable long-distance centralized access and data transmission for multiple terminal devices without the need to deploy remote switches. It directly replaces the port access and data forwarding functions of traditional switches (including switches implemented with switching chips or processors) through a remote multi-port PHY, adapting to various network communication scenarios that are sensitive to network cost, latency, and architectural complexity.

[0005] To achieve the above objectives, the present invention provides a long-distance port expansion device based on a multi-port PHY chip, comprising: a near-end device integrating a multi-channel serial interface supporting a multi-port protocol; and a far-end device including at least one PHY chip, wherein the PHY chip has an uplink multi-channel protocol interface supporting a multi-port protocol and multiple downlink network ports; the multi-channel serial interface of the near-end device and the uplink multi-channel protocol interface of the PHY chip are connected through a long-distance transmission medium.

[0006] Furthermore, two long-distance transmission media are provided between the near-end device and the PHY chip to form a redundant transmission path.

[0007] Furthermore, the PHY chip has two mutually protected uplink multi-channel protocol interfaces. When the PHY chip detects a link failure on one uplink multi-channel protocol interface, it automatically switches to the link on the other uplink multi-channel protocol interface. The automatic switching function is triggered by the PHY chip by detecting the link signal status of the uplink multi-channel protocol interface.

[0008] Furthermore, the long-distance transmission medium is optical fiber or shielded twisted pair cable.

[0009] Furthermore, the PHY chip is an eight-port PHY chip that supports the USGMII protocol, used to realize data transmission through eight Gigabit Ethernet ports.

[0010] Furthermore, the PHY chip is a four-port PHY chip that supports the QSGMII protocol, used to realize data transmission through four Gigabit Ethernet ports.

[0011] Furthermore, the PHY chip is a four-port PHY chip that supports the USXGMII protocol, used to realize data transmission through four 2.5G Ethernet ports. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the port expansion architecture of existing technology;

[0014] Figure 2 This is a schematic diagram of the architecture of the long-distance port expansion device of the present invention;

[0015] Figure 3 This is a schematic diagram of the long-distance port extension device of the present invention;

[0016] Figure 4 This is a schematic diagram of the remote port expansion using two optical fibers for protected transmission according to the present invention.

[0017] Figure 5 This is a schematic diagram of an eight-port PHY with two mutually protected USGMII interfaces according to the present invention.

[0018] Figure 6 These are example diagrams of the three multiport protocols USGMII / QSGMII / USXGMII of this invention;

[0019] Figure 7 This is a schematic diagram of the remote port expansion with two PHY chips according to the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention provides a low-latency, low-cost long-distance port expansion technology solution. Its core purpose is to enable long-distance centralized access and data transmission for multiple terminal devices without the need to deploy remote switches. It directly replaces the port access and data forwarding functions of traditional switches (including switches implemented with switching chips or processors) through a remote multi-port PHY, adapting to various network communication scenarios that are sensitive to network cost, latency, and architectural complexity.

[0022] This invention innovates by using multi-channel protocols such as USGMII / QSGMII as the core of transmission and directly replacing traditional switching chips with multi-port PHY chips to transform both remote and near-end equipment. The remote end deploys a multi-port PHY chip supporting multiple channel protocol interfaces such as USGMII / QSGMII, replacing the traditional switching chip. A single chip enables multi-terminal access and data aggregation, eliminating redundant hardware in the remote switching chip. The near-end equipment integrates multiple channel protocol interfaces such as USGMII / QSGMII, configured as fiber optic serial interfaces, transmitting multi-port data to the remote multi-port PHY via a single USGMII / QSGMII link. The overall solution eliminates high-cost components such as the forwarding engine and buffer module of the remote equipment's switching chip, retaining only the PHY chip, protocol interface circuitry, and basic power supply module, reducing hardware costs, size, and power consumption.

[0023] like Figure 2 The diagram shown illustrates a remote port extension based on a USGMII link, including:

[0024] The near-end equipment uses a USGMII protocol interface to connect to the optical fiber, which is then connected to the USGMII protocol interface of the far-end PHY.

[0025] The remote PHY uses a USGMII protocol interface to connect to the optical fiber, which in turn connects to the USGMII protocol interface of the near-end device.

[0026] The remote PHY has eight downstream interfaces for access ports of remote devices.

[0027] In specific examples, the USGMII protocol PHY can use the KG7108 model. The USGMII PHY connection mode is as follows: Figure 3 As shown, the PHY connects to the MAC via USGMII, and divides the USGMII data into 8 ports. In USGMII encoding, each data packet has a corresponding egress ID, such as 0-7. In the sending direction, the PHY uses this ID to transmit the data packet through the corresponding port. Conversely, data packets received through the corresponding port are sent to the MAC with their corresponding ID, allowing the MAC to distinguish which port the data originated from.

[0028] For near-end devices, USGMII Serdes (serializers or serial interfaces) need to be integrated into the switching chip. The Serdes are on the chip and provide external connections through the chip's pins. Interface devices, such as optical cages, can be connected to the PCB board by soldering.

[0029] Figure 4 This is a schematic diagram of a remote port expansion using two optical fibers for protected transmission. Figure 2 Based on this, the near-end equipment and the far-end PHY are connected by two optical fibers, with the optical fiber links providing redundancy protection for each other.

[0030] Figure 5 This diagram illustrates an eight-port PHY with two mutually protective USGMII interfaces. The eight ports are internally connected to one of the USGMII interfaces. If this USGMII connection is lost or an error occurs, the PHY automatically switches to the other USGMII. The redundancy switching function is implemented on the PHY itself, which detects the link status (link up or down) by monitoring the USGMII signals. If a link down is detected, the PHY immediately switches to the backup USGMII.

[0031] Figure 6 This is an example of three multi-port protocols: USGMII, QSGMII, and USXGMII, in a non-redundant configuration. The USGMII protocol supports 8 Gigabit ports. To provide 9-16 ports, more USGMII PHYs can be connected, or two 8-port PHYs can be installed in the device. The QSGMII protocol supports 4 Gigabit ports, and the USXGMII protocol supports 4 2.5G ports.

[0032] In the multi-rate adaptation embodiment, a four-port PHY chip supporting the QSGMII protocol is used to enable a single link to carry four 1G terminal accesses, which can adapt to access scenarios with smaller ports; a multi-port PHY chip supporting 2.5G / 5G rates is used, which can work with the USXGMII protocol to enable a single link to carry four 2.5G or two 5G terminal accesses, adapting to high-definition video surveillance scenarios.

[0033] In the port expansion embodiment, a 16-port / 24-port PHY chip can be used to enable 24-port terminal access through the multi-channel USGMII protocol, and the near-end device connects to the PHY through the multi-channel USGMII.

[0034] In addition, the aforementioned optical fibers are generally suitable for transmission distances of more than 100m. In the transmission medium extension embodiment, the optical fiber can be replaced with shielded twisted pair (STP) cable and USGMII-over-Copper technology can be used to adapt to short-distance, low-cost scenarios within 100m.

[0035] The number of optical fibers corresponds to the number of SerDes. For a 16-port PHY, typically two uplink USGMIIs are needed, requiring two optical fibers. If redundancy is required, four USGMIIs are needed, which is four optical fibers. Figure 7 As shown.

[0036] In an embodiment of the present invention, a long-distance port expansion device based on a multi-port PHY chip is provided, comprising: a near-end device integrating a multi-channel serial interface supporting a multi-port protocol; and a far-end device including at least one PHY chip, wherein the PHY chip has an uplink multi-channel protocol interface supporting a multi-port protocol and multiple downlink network ports; the multi-channel serial interface of the near-end device and the uplink multi-channel protocol interface of the PHY chip are connected through a long-distance transmission medium.

[0037] Furthermore, two long-distance transmission media are provided between the near-end device and the PHY chip to form a redundant transmission path.

[0038] Furthermore, the PHY chip has two mutually protected uplink multi-channel protocol interfaces. When the PHY chip detects a link failure on one uplink multi-channel protocol interface, it automatically switches to the link on the other uplink multi-channel protocol interface. The automatic switching function is triggered by the PHY chip by detecting the link signal status of the uplink multi-channel protocol interface.

[0039] Furthermore, the long-distance transmission medium is optical fiber or shielded twisted pair cable.

[0040] Furthermore, the PHY chip is an eight-port PHY chip that supports the USGMII protocol, used to realize data transmission through eight Gigabit Ethernet ports.

[0041] Furthermore, the PHY chip is a four-port PHY chip that supports the QSGMII protocol, used to realize data transmission through four Gigabit Ethernet ports.

[0042] Furthermore, the PHY chip is a four-port PHY chip that supports the USXGMII protocol, used to realize data transmission through four 2.5G Ethernet ports.

[0043] Compared to the traditional "near-end aggregation device + remote independent switch" solution, this invention has significant technical advantages: In terms of cost control, it directly replaces the high-priced switching chip with a multi-port PHY chip, eliminating redundant forwarding engines, processors, and cache modules, thus reducing the hardware cost of the remote device and eliminating the need for additional software development costs; in terms of real-time performance, it eliminates the multi-level forwarding path of "terminal → remote switch → near-end device," simplifying it to a direct "terminal → near-end device" approach, resulting in end-to-end latency far superior to traditional solutions, meeting the requirements of industrial hard real-time protocols and avoiding closed-loop control. Inaccuracy and data acquisition lag are addressed; in terms of reliability design, hardware-level redundancy is constructed using dual fiber optic links and dual USGMII interfaces, significantly reducing link switching latency and improving fault recovery speed compared to traditional solutions; in terms of deployment adaptability, the power consumption and size of remote equipment are reduced, making it suitable for the needs of confined spaces, low power consumption, and harsh operating conditions in industrial environments; in terms of compatibility, it supports 10 / 100 / 1000M rate adaptive switching, seamlessly compatible with existing Ethernet terminals, and can access existing networks without equipment modification, making it widely adaptable to various transmission scenarios such as industrial IoT and smart grids.

[0044] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A long-distance port expansion device based on multi-port PHY chips, characterized in that, The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip.

2. The apparatus of claim 1, wherein, The application relates to a serial interface device and a PHY chip.

3. The apparatus of claim 2, wherein, The application relates to a serial interface device and a PHY chip.

4. The apparatus of any one of claims 1-3, wherein, The application relates to a serial interface device and a PHY chip.

5. The apparatus of any one of claims 1-3, wherein, The application relates to a serial interface device and a PHY chip.

6. The apparatus of any one of claims 1-3, wherein, The application relates to a serial interface device and a PHY chip.

7. The apparatus of any one of claims 1-3, wherein, The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a serial interface device and a PHY chip. The application relates to a

Citation Information

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