Read static noise margin measurement method of static random access memory, computing device and storage medium

Abstract

The present invention discloses a method for measuring the read static noise margin of a static random access memory, a computing device and a storage medium. The present invention obtains test data of a static random access memory, extracts the test voltage of each chip; then performs format conversion on the test voltage; obtains a first fitting curve and a second fitting curve by using curve fitting interpolation for the test voltage after format conversion, obtains the intersection of the first fitting curve and the second fitting curve, and then calculates the maximum square side length on the curve on the left and right sides of the intersection, thereby determining the read static noise margin of the static random access memory. The present invention utilizes curve fitting interpolation and interpolation operations to more accurately determine RSNML and RSNMR values, reduce dependence on engineer experience, and reduce valuation errors. The present invention has significant improvements in automation, accuracy, efficiency and reliability, and provides a new and efficient tool for the field of SRAM design and testing.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a read static noise margin measurement method of a static random access memory, a computing device and a storage medium. Background Art

[0002] With the development of integrated circuit technology, static random access memory (SRAM) is increasingly used in electronic devices. The stability and reliability of SRAM are critical to the performance of the entire system. In order to evaluate the performance of SRAM cells under different read conditions, existing technologies usually use simulation software or drawing tools to graphically process test data (rawdata). Specifically, these techniques involve drawing the largest possible square on the graph and measuring the lengths of the sides of the squares on the left and right sides as the RSNML (Read Static Noise Margin Left) value and RSNMR (Read Static Noise Margin Right) value of the SRAM, respectively. These values ​​reflect the stability performance of the SRAM cell under different read conditions, which is of great significance for optimizing the design and improving the reliability of the SRAM.

[0003] However, the process of manually drawing a square and measuring the side length using simulation software or drawing tools is time-consuming, labor-intensive, and inefficient, and is not suitable for large-scale or fast-iteration design verification processes. Engineers also need to rely on experience to estimate the side length of the square. This highly subjective evaluation method can easily lead to inaccurate results, affecting the optimization of SRAM design and the improvement of reliability.

[0004] Therefore, the main challenges faced when dealing with SRAM RSNM (Read Static Noise Margin) evaluation include improving the efficiency of drawing and measuring and improving the accuracy of evaluation results. To overcome these challenges, a new method or system is needed that can automatically and accurately extract RSNM values ​​from test data, reduce human errors, and improve the efficiency and accuracy of the overall evaluation process. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a method for measuring the read static noise margin of a static random access memory, a computing device and a storage medium.

[0006] The present invention is implemented in this way. In a first aspect, the present invention provides a method for measuring read static noise margin of a static random access memory, the method comprising the following steps:

[0007] Step S1, acquiring the test data of the static random access memory, extracting the test voltage of each chip; and then converting the format of the test voltage;

[0008] Step S2: Obtain a smooth fitting curve by using curve fitting interpolation for the test voltage after format conversion, specifically:

[0009] S2-1, based on the test voltage after format conversion, extract the forward input terminal voltage and the reverse input terminal voltage of each chip, and perform arithmetic function processing respectively to obtain two sets of arithmetic progressions x1 and x2;

[0010] S2-2, performing cubic spline interpolation operations on the two sets of arithmetic progressions x1 and x2, respectively, to obtain two sets of interpolated progressions y1 and y2;

[0011] S2-3, using the arithmetic sequence x1 as the horizontal coordinate and the sequence y1 as the vertical coordinate to obtain a smooth first fitting curve; using the arithmetic sequence x2 as the horizontal coordinate and the sequence y2 as the vertical coordinate to obtain a smooth second fitting curve;

[0012] Step S3, obtaining the intersection of the first fitting curve and the second fitting curve, and then calculating the maximum square side lengths on the left and right curves of the intersection, the maximum square side length on the left curve of the intersection is the RSNML parameter, and the maximum square side length on the right curve of the intersection is the RSNMR parameter;

[0013] Step S4: determining the read static noise margin of the static random access memory according to the RSNML parameter and the RSNMR parameter.

[0014] Preferably, the test data includes wafer batch, wafer number, physical coordinates of each chip in the wafer, and test voltage values ​​collected during testing.

[0015] Preferably, the format conversion in step S1 is to group the test voltage values ​​of the same chip according to the input voltage and the output voltage, and redefine the coordinates of each parameter value according to the input voltage group and the output voltage group of the same chip.

[0016] Preferably, the test condition of the static random access memory in step S1 is to apply different input voltage values ​​to the input terminal and collect the output voltage value of the corresponding output terminal.

[0017] Preferably, in step S2-1, the multiples of the two groups of arithmetic progressions x1 and x2 are the same.

[0018] Preferably, step S3 specifically includes:

[0019] S3-1, obtaining the intersection of the first fitting curve and the second fitting curve, and obtaining the coordinates of the intersection;

[0020] S3-2, respectively searching for the corresponding test voltage index positions p1 and p2 that coincide with the intersection coordinates in the arithmetic progression x1 and x2;

[0021] S3-3. According to the intersection and index positions p1 and p2, the maximum square side lengths on the left and right curves of the intersection of each chip are calculated. The maximum square side length on the left curve of the intersection is the RSNML parameter, and the maximum square side length on the right curve of the intersection is the RSNMR parameter.

[0022] Preferably, the calculation process of the RSNML parameters in step S3-3 is specifically:

[0023] In the first fitting curve, the corresponding array differences of the elements before the index position p1 in the arithmetic sequence x1 are calculated and sorted in reverse order to obtain the first array a_p1;

[0024] Take the negative value of each element of the array a_p1, and then further perform cumulative summation to obtain the second array b_p1;

[0025] The second array b_p1 is traversed, and the offset function of the 45-degree straight line is used to solve the problem. The 45-degree straight line scan is used to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve before the index position p1, and finally the maximum side length of the square is further obtained.

[0026] Preferably, the calculation process of the RSNMR parameters in step S3-3 is specifically:

[0027] In the second fitting curve, the corresponding array differences of the elements after the index position p2 in the arithmetic sequence x2 are calculated and sorted in reverse order to obtain the third array a_p2;

[0028] Take the negative value of each element of the array a_p2, and then further perform cumulative summation to obtain the fourth array b_p2;

[0029] The fourth array b_p2 is traversed, and the offset function of the 45-degree straight line is used to solve the problem. The 45-degree straight line scan is used to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve after the index position p2, and finally the maximum side length of the square is further obtained.

[0030] In a second aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method described.

[0031] In a third aspect, the present invention provides a computing device, comprising a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method described in the right is implemented.

[0032] The present invention provides a SRAM RSNM (Read Static Noise Margin) measurement method, which has the following significant beneficial effects compared with the prior art:

[0033] 1) The method of the present invention replaces the traditional manual drawing and estimation method, greatly improves the efficiency of obtaining SRAM RSNM values, reduces the interference of human factors, and ensures the consistency and repeatability of operations.

[0034] 2) The present invention utilizes curve fitting interpolation and interpolation operations to more accurately determine the RSNML and RSNMR values ​​of the SRAM cell, thereby reducing reliance on engineer experience and reducing estimation errors.

[0035] 3) The present invention does not require manual drawing, which significantly reduces the time consumption of the drawing process, thereby speeding up the entire SRAM RSNM value acquisition process. This not only saves human resources, but also shortens the project cycle. At the same time, it also reduces the errors that may occur in manual operations, such as inaccurate drawing, data entry errors, etc., thereby improving the reliability of the measurement results.

[0036] 4) The measurement method provided by the present invention can provide more reliable data support and help design more stable SRAM cells. Accurate RSNM value is crucial for optimizing SRAM design and improving its reliability.

[0037] The method of the present invention can be promoted as a standard operating procedure in actual work, so that the operating results between different engineers or different projects have better comparability, and further improve work efficiency and consistency of results.

[0038] The method of the present invention is not only applicable to current SRAM test data, but also can adapt to data formats and measurement requirements that may change in the future, and has good flexibility and expansibility.

[0039] In summary, the SRAM RSNM measurement method of the present invention has significant improvements in automation, accuracy, efficiency and reliability, and provides a new and efficient tool for the SRAM design and testing field. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1The present invention provides a flow chart of a method for measuring the static noise margin of an SRAM read. DETAILED DESCRIPTION

[0042] As can be seen from the background technology, the SRAM read static noise margin measurement method in the prior art mainly uses simulation software or drawing tools to draw manually, which is time-consuming and labor-intensive, inefficient, and not suitable for large-scale or fast-iteration design verification processes. In addition, the experience of engineers is also highly subjective, which can easily lead to inaccurate results and affect the optimization of SRAM design and the improvement of reliability.

[0043] In order to solve the technical problem, the present invention provides a novel read static noise margin measurement method of a static random access memory, comprising:

[0044] Acquire the test data of the static random access memory and extract the test voltage of each chip; then convert the format of the test voltage;

[0045] The test voltage after format conversion is interpolated by curve fitting to obtain a smooth fitting curve, specifically:

[0046] Based on the test voltage after format conversion, the forward input terminal voltage and the reverse input terminal voltage of each chip are extracted, and arithmetic function processing is performed respectively to obtain two sets of arithmetic progressions x1 and x2;

[0047] Perform cubic spline interpolation operations on the above two sets of arithmetic progressions x1 and x2 respectively to obtain two sets of interpolated progressions y1 and y2;

[0048] With the arithmetic sequence x1 as the horizontal coordinate and the sequence y1 as the vertical coordinate, a smooth first fitting curve is obtained; with the arithmetic sequence x2 as the horizontal coordinate and the sequence y2 as the vertical coordinate, a smooth second fitting curve is obtained;

[0049] Obtain the intersection of the first fitting curve and the second fitting curve, and then calculate the maximum square side lengths on the curves on the left and right sides of the intersection, the maximum square side length on the curve on the left side of the intersection is the RSNML parameter, and the maximum square side length on the curve on the right side of the intersection is the RSNMR parameter;

[0050] The read static noise margin of the static random access memory is determined according to the RSNML parameter and the RSNMR parameter.

[0051] The technical solution of the present invention utilizes curve fitting interpolation and interpolation operation to more accurately determine the RSNML and RSNMR values ​​of the SRAM cell, reducing the reliance on engineer experience and reducing the estimation error. The method of the present invention is not only applicable to current SRAM test data, but also can adapt to data formats and measurement requirements that may change in the future, and has good flexibility and scalability. The SRAM RSNM measurement method of the present invention has significant improvements in automation, accuracy, efficiency and reliability, and provides a new and efficient tool for the field of SRAM design and testing.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] refer to Figure 1 , shows a flow chart of an embodiment of a method for measuring read static noise margin of a static random access memory of the present invention.

[0054] The method for measuring read static noise margin of a static random access memory in this embodiment includes the following steps:

[0055] Step S1, acquiring test data of a static random access memory, extracting a test voltage (value) of each chip (die); and then performing format conversion on the test voltage.

[0056] Specifically, the test data includes wafer batch, wafer number, physical coordinates of each chip in the wafer, and test voltage values ​​collected during the test. For example, the test data may be presented in a format similar to an Excel file, which records in detail various relevant information of each chip (die) on a specific wafer (wafer) and the corresponding test voltage (value).

[0057] Specifically, the format conversion is to group the test voltage values ​​of the same chip according to the input voltage and the output voltage, and redefine the coordinates of each parameter value according to the input voltage group and the output voltage group of the same chip.

[0058] In this process, it should be noted that the test condition of the static random access memory is to apply different input voltage values ​​to the input terminal and collect the output voltage value of the corresponding output terminal.

[0059] Step S2: Obtain a smooth fitting curve by using curve fitting interpolation for the test voltage after format conversion, specifically:

[0060] S2-1. Based on the test voltage after format conversion, extract the forward input terminal voltage and the reverse input terminal voltage for each chip (die), and perform arithmetic function processing on them respectively to obtain two groups of arithmetic progressions x1 and x2, that is, one group of arithmetic progressions x1 is the forward input terminal voltage group, and the other group of arithmetic progressions x2 is the reverse input terminal voltage group.

[0061] The two sets of arithmetic progressions x1 and x2 are both n-multiples, that is, the intervals between the values ​​in the sequence are uniform, and each value is n times the previous value. n is set manually according to actual needs, and can be 10, 100, 1000, 10000, etc. These sequences have the same multiples, ensuring the consistency of the data.

[0062] Specifically, the arithmetic sequence extraction technology of this embodiment uses the linspace function in the NumPy library.

[0063] S2-2, respectively perform cubic spline interpolation operations (i.e., one-dimensional interpolation) on the above two sets of arithmetic progressions x1 and x2 to obtain two sets of interpolated progressions y1 and y2. Cubic spline interpolation is a smooth interpolation method that can create a continuous curve that passes through all data points or between data points.

[0064] Specifically, the one-dimensional interpolation operation in this embodiment uses the interp1d function in the SciPy library.

[0065] S2-3, using the arithmetic sequence x1 as the horizontal coordinate and the sequence y1 as the vertical coordinate, a smooth first fitting curve is obtained; using the arithmetic sequence x2 as the horizontal coordinate and the sequence y2 as the vertical coordinate, a smooth second fitting curve is obtained. The first fitting curve and the second fitting curve describe the performance characteristics of the SRAM.

[0066] Step S3, obtaining the intersection of the first fitting curve and the second fitting curve, and then calculating the maximum square side lengths on the curves on the left and right sides of the intersection, the maximum square side length on the curve on the left side of the intersection is the RSNML parameter, and the maximum square side length on the curve on the right side of the intersection is the RSNMR parameter, specifically:

[0067] S3-1. Obtain the intersection of the first fitting curve and the second fitting curve, and obtain the coordinates of the intersection.

[0068] Specifically, this embodiment uses the intersect method of the Curve object in the bezier library to extract the intersection point.

[0069] S3-2, respectively searching for the corresponding test voltage index positions p1 and p2 that coincide with the intersection coordinates in the arithmetic progression x1 and x2;

[0070] Specifically, this embodiment searches for the searchsorted function using the NumPy library.

[0071] S3-3. According to the intersection, the maximum side length of the square on the left and right curves of the intersection of each chip is calculated. The maximum side length of the square on the left curve of the intersection is the RSNML value, and the maximum side length of the square on the right curve of the intersection is the RSNMR value; specifically:

[0072] S3-3-1. Calculate the SRAM RSNML parameters, specifically:

[0073] S3-3-1-1. In the first fitting curve, calculate the corresponding array differences of the elements before the index position p1 in the arithmetic difference data x1 and sort them in reverse order to obtain the first array a_p1.

[0074] S3-3-1-2. Take a negative value for each element of the array a_p1, and then further perform cumulative summation to obtain a second array b_p1.

[0075] S3-3-1-3, traverse the second array b_p1, and use the 45-degree straight line offset f(x)-(x+b)=0 to solve, and scan the 45-degree straight line to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve before the index position p1, and finally further obtain the maximum square side length, that is, the SRAM RSNML parameter.

[0076] S3-3-2. Calculate the SRAM RSNMR parameters, specifically:

[0077] S3-3-2-1. In the second fitting curve, calculate the corresponding array differences of the elements after the index position p2 in the arithmetic difference data x2 and sort them in reverse order to obtain a third array a_p2.

[0078] S3-3-2-2. Take a negative value for each element of the array a_p2, and then further perform cumulative summation to obtain a fourth array b_p2.

[0079] S3-3-2-3, traverse the fourth array b_p2, and use the 45-degree straight line offset f(x)-(x+b)=0 to solve, and use the 45-degree straight line scan to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve after the index position p2, and finally further obtain the maximum square side length, that is, the SRAM RSNMR parameter.

[0080] Step S4: According to the calculated RSNML parameters and RSNMR parameters, the read static noise margin of the static random access memory is determined. By analyzing these parameters, the stability performance of the SRAM under different read conditions can be deeply understood, thereby providing a key basis for optimizing the design and improving the reliability.

[0081] The method of the present invention abandons the traditional manual drawing and estimation methods and realizes automatic processing. A series of operations such as data format conversion, curve fitting interpolation, intersection calculation and maximum square side length calculation are automatically performed by the program, which greatly shortens the time for obtaining the SRAM RSNM value and significantly improves the operation efficiency. This enables the performance of the SRAM unit to be evaluated more quickly in the large-scale or fast-iteration design verification process, saving valuable time and human resources and accelerating the progress of the project. By using curve fitting interpolation and interpolation operations, the present invention can more accurately determine the RSNML and RSNMR values ​​of the SRAM unit. Compared with the subjective method of estimating the side length of the square by engineers based on experience, the present invention is based on mathematical algorithms and precise data processing, which reduces the error of human judgment and improves the accuracy of the valuation. Accurate RSNM values ​​are crucial for optimizing SRAM design and improving its reliability, and can provide designers with more reliable data support, which helps to design more stable and better-performing SRAM units. Since there is no need to draw graphics manually, the present invention avoids various errors that may occur in manual operations, such as inaccurate drawing and data entry errors. This not only improves the accuracy of the measurement results, but also enhances the reliability of the entire evaluation process. The improved reliability of the measurement results helps to reduce design decision errors caused by erroneous data, improves the quality of SRAM design and testing, and reduces product development risks. The measurement method provided by the present invention can generate more reliable RSNM data, which provides a strong basis for the design optimization of SRAM units. Designers can deeply analyze the performance of SRAM under different reading conditions based on accurate RSNM values, adjust design parameters in a targeted manner, and improve circuit structure, thereby improving the stability and reliability of SRAM, extending the service life of the product, and improving the overall system performance. The method of the present invention has good promotion value and can be promoted and applied as a standard operating procedure in actual work. The same method is used for measurement between different engineers or different projects, which can ensure that the operation results have better comparability, improve work efficiency and consistency of results. In addition, the method of the present invention is not only applicable to the current SRAM test data format, but also has good flexibility and scalability, and can adapt to data formats and measurement requirements that may change in the future, providing a solid technical foundation for the sustainable development of SRAM technology.

[0082] An embodiment of the present invention further provides a computing device. Specifically, the computing device includes a memory and a processor. The memory stores executable code. When the processor executes the executable code, the method described in any one of the implementation modes is implemented.

[0083] The memory may include high-speed random access memory (RAM), and may also include non-volatile memory (Non-volatile Memory), such as at least one disk storage. The communication connection between the system network element and at least one other network element is realized through at least one communication interface (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0084] The bus may be an ISA bus, a PCI bus or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.

[0085] Among them, the memory is used to store the program, and the processor executes the program after receiving the execution instruction. The method executed by the device for flow process definition disclosed in any embodiment of the above-mentioned embodiment of the present invention can be applied to the processor or implemented by the processor.

[0086] The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0087] The computer program product of the readable storage medium provided in the embodiment of the present invention includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the methods described in the previous method embodiments. The specific implementation can be referred to the previous method embodiments, which will not be repeated here.

[0088] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0089] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for measuring read static noise margin of a static random access memory, characterized in that: The method comprises the following steps: Step S1, acquiring the test data of the static random access memory, extracting the test voltage of each chip; and then converting the format of the test voltage; Step S2: Obtain a smooth fitting curve by using curve fitting interpolation for the test voltage after format conversion, specifically: S2-1, based on the test voltage after format conversion, extract the forward input terminal voltage and the reverse input terminal voltage of each chip, and perform arithmetic function processing respectively to obtain two sets of arithmetic progressions x1 and x2; S2-2, performing cubic spline interpolation operations on the two sets of arithmetic progressions x1 and x2, respectively, to obtain two sets of interpolated progressions y1 and y2; S2-3, using the arithmetic sequence x1 as the horizontal coordinate and the sequence y1 as the vertical coordinate to obtain a smooth first fitting curve; using the arithmetic sequence x2 as the horizontal coordinate and the sequence y2 as the vertical coordinate to obtain a smooth second fitting curve; Step S3, obtaining the intersection of the first fitting curve and the second fitting curve, and then calculating the maximum square side lengths on the left and right curves of the intersection, the maximum square side length on the left curve of the intersection is the RSNML parameter, and the maximum square side length on the right curve of the intersection is the RSNMR parameter; specifically: S3-1, obtaining the intersection of the first fitting curve and the second fitting curve, and obtaining the coordinates of the intersection; S3-2, respectively searching for the corresponding test voltage index positions p1 and p2 that coincide with the intersection coordinates in the arithmetic progression x1 and x2; S3-3. According to the intersection and index positions p1 and p2, the maximum side length of the square on the left and right curves of the intersection of each chip is calculated. The maximum side length of the square on the left curve of the intersection is the RSNML parameter, and the maximum side length of the square on the right curve of the intersection is the RSNMR parameter. The calculation process of the RSNML parameters in step S3-3 is specifically as follows: In the first fitting curve, the corresponding array difference of the elements before the index position p1 in the arithmetic difference data x1 is calculated and sorted in reverse order to obtain the first array a_p1; Take the negative value of each element of the array a_p1, and then further perform cumulative summation to obtain the second array b_p1; Traverse the second array b_p1, and use the 45-degree straight line offset to solve, and scan the 45-degree straight line to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve before the index position p1, and finally further obtain the maximum square side length; The calculation process of the RSNMR parameters in step S3-3 is specifically as follows: In the second fitting curve, the corresponding array difference of the elements after the index position p2 in the arithmetic difference data x2 is calculated and sorted in reverse order to obtain the third array a_p2; Take the negative value of each element of the array a_p2, and then further perform cumulative summation to obtain the fourth array b_p2; Traverse the fourth array b_p2, and use the offset of the 45-degree straight line to solve the 45-degree straight line scan to obtain the maximum diagonal length of the square in the closed curve formed by the first fitting curve and the second fitting curve after the index position p2, and finally further obtain the maximum square side length; Step S4: determining the read static noise margin of the static random access memory according to the RSNML parameter and the RSNMR parameter.

2. The method for measuring read static noise margin of a static random access memory according to claim 1, characterized in that: The test data includes wafer batch, wafer number, physical coordinates of each chip in the wafer, and test voltage values ​​collected during the test.

3. The method for measuring read static noise margin of a static random access memory according to claim 1, characterized in that: The format conversion in step S1 is to group the test voltage values ​​of the same chip according to the input voltage and the output voltage, and redefine the coordinates of each parameter value according to the input voltage group and the output voltage group of the same chip.

4. The method for measuring read static noise margin of a static random access memory according to claim 1, characterized in that: The test condition of the static random access memory in step S1 is to apply different input voltage values ​​to the input terminal and collect the output voltage value of the corresponding output terminal.

5. The method for measuring read static noise margin of a static random access memory according to claim 1, characterized in that: In step S2-1, the multiples of the two groups of arithmetic progressions x1 and x2 are the same.

6. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 5.

7. A computing device, comprising a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, the method according to any one of claims 1 to 5 is implemented.

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