A three-dimensional integration process method without bump interface

Abstract

The present application discloses a three-dimensional integration process method without a bump interface, which constructs a bump-free three-dimensional integrated structure based on a silicon adapter plate, eliminates micro-bumps and their heterogeneous interfaces, avoids many problems existing in the bump bonding process, enables the three-dimensional stacking to obtain better electrical and mechanical performance, and at the same time realizes a more compact device layout, which is conducive to reducing the device size. It solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The use of copper pillar bumps has high manufacturing costs, requires precise process control, and faces reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a three-dimensional integration process method without a bump interface. Background Art

[0002] Silicon interposer technology is a key technology developed to achieve high-density interconnection between chips, primarily used in advanced packaging and 3D integration. It allows multiple chips to be stacked vertically and interconnected through TSVs (Through-Silicon Vias), facilitating high-speed signal transmission and electrical interconnection, improving system performance and reliability.

[0003] In recent years, with the increasing demand for high-density interconnects, bump bonding technology in silicon interposers has been moving towards finer pitches. As the bump pitch decreases, the need for solder decreases, and solder can even be eliminated entirely to avoid the risk of bridging between bumps during solder melting.

[0004] There are two main existing technical methods:

[0005] One method uses tin or a tin alloy to form tiny solder balls, or bumps, which are then heated and pressed against corresponding pads to achieve electrical connections. However, this method can lead to solder joint fatigue, increased resistance, or electromigration when faced with challenges such as large temperature fluctuations and high current density, thus affecting reliability and performance stability.

[0006] Another method uses copper as the bump material, forming tiny copper pillars on the chip or substrate through electroplating or other processing methods, and then connecting them through welding or pressing. Although this method can meet the needs of high-density and high-speed interconnection, it has high manufacturing costs, requires precise process control (such as controlling pressure and temperature), and faces reliability issues such as bond breakage, pressure reduction, or electrical performance degradation. Summary of the Invention

[0007] The present application provides a three-dimensional integration process method without a bump interface, which solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The manufacturing cost of copper pillar bumps is high, precise process control is required, and there are reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

[0008] In view of this, the present application provides a three-dimensional integration process method without a bump interface, the method comprising:

[0009] Step S1, preparing an insulating layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate containing the TSV;

[0010] Step S2: preparing a mask barrier layer of a target pattern on the front and back surfaces of the silicon adapter plate and the front surface of the corresponding substrate based on a lift-off process and a photolithography process;

[0011] Step S3, sequentially preparing a barrier layer and a metal seed layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate;

[0012] Step S4, aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process;

[0013] Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

[0014] Optionally, step S2 specifically includes:

[0015] Bonding the silicon wafer to the front and back surfaces of the silicon adapter plate simultaneously by using temporary bonding adhesive;

[0016] Spin-coating photoresist on the front and back surfaces of the silicon adapter plate by a spin coater;

[0017] After the silicon adapter plate and the silicon wafer are debonded by thermal slip, the silicon adapter plate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process, and a development process to prepare a mask barrier layer of a target image on the front and back surfaces of the silicon adapter plate.

[0018] Optionally, step S2 further includes:

[0019] temporarily bonding the silicon wafer to the front surface of the substrate by using a temporary bonding adhesive;

[0020] Spin coating photoresist on the front side of the substrate by a spin coater;

[0021] After the substrate and the silicon wafer are debonded by thermal slip, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process, and a development process to prepare a mask barrier layer of a target image on the front side of the substrate.

[0022] Optionally, step S3 specifically includes:

[0023] Depositing a barrier layer on the front side, the back side and the TSV corresponding side of the silicon adapter by metal physical vapor deposition;

[0024] A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

[0025] Optionally, step S3 further includes:

[0026] A metal seed layer is deposited on the front surface of the substrate by metal physical vapor deposition.

[0027] Optionally, after step S3, the following steps are further included:

[0028] The mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate are removed by using a degumming solution.

[0029] Optionally, after removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by using a degumming liquid, the method further comprises:

[0030] A bonding pattern of a target pattern is prepared on the substrate by using a permanent bonding adhesive through an overlay process.

[0031] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0032] In this application, a three-dimensional integration process method with a bump-free interface is provided, in which a bump-free three-dimensional integrated structure is constructed based on a silicon adapter plate, micro-bumps and their heterogeneous interfaces are eliminated, and many problems existing in the bump bonding process are avoided, so that the three-dimensional stacking can obtain better electrical and mechanical performance, while realizing a more compact device layout, which is conducive to reducing the device size, and solving the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The use of copper pillar bumps has a high manufacturing cost, requires precise process control, and faces reliability problems such as bond breakage, pressure reduction or electrical performance degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a flow chart of a three-dimensional integration process method without a bump interface in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0035] This application designs a three-dimensional integration process method without a bump interface, which solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The manufacturing cost of copper pillar bumps is high, precise process control is required, and there are reliability issues such as bond breakage, pressure reduction or electrical performance degradation.

[0036] For easier understanding, see Figure 1 , Figure 1 This is a flow chart of a three-dimensional integration process method without a bump interface in an embodiment of the present application. Figure 1 As shown, specifically:

[0037] Step S1, preparing an insulating layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate containing the TSV;

[0038] It should be noted that insulating layers are prepared on the front and back surfaces of the silicon adapter board and the surface corresponding to the TSV (Through-Silicon Via) to prevent electrical short circuits and provide mechanical support.

[0039] Insulating materials such as silicon dioxide (SiO2) or polyimide (PI) are typically deposited on designated areas of the silicon interposer using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques.

[0040] Step S2: preparing a mask barrier layer of the target pattern on the front and back surfaces of the silicon adapter and the front surface of the corresponding substrate based on a lift-off process and a photolithography process;

[0041] It should be noted that a mask barrier layer of a target pattern is prepared on the front and back sides of the silicon adapter and the front side of the corresponding substrate to control the subsequent metal deposition and form the required circuit pattern.

[0042] Lift-off process: First, a layer of photosensitive resin (photoresist) is coated on the surface of the silicon adapter plate and the substrate, and then the desired pattern is formed through exposure through a mask. The unexposed part is removed during the development process, leaving the desired pattern.

[0043] Photolithography process: Use a photolithography machine to transfer the pattern on the mask to the photoresist layer on the silicon adapter and substrate, and then use a developer to remove the unexposed photoresist to form a mask barrier layer.

[0044] Step S3: sequentially preparing a barrier layer and a metal seed layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate;

[0045] It should be noted that the barrier layer and the metal seed layer are sequentially prepared on the front side, the back side and the TSV corresponding side of the silicon adapter plate to achieve good metal filling and electrical connection.

[0046] Barrier layer: A thin layer of metal or metal alloy, such as titanium (Ti) or tantalum (Ta), is deposited on the insulating layer, usually using PVD or CVD technology, to prevent the reaction between the metal and silicon.

[0047] Metal seed layer: A metal seed layer, such as copper (Cu) or nickel (Ni), is deposited on the barrier layer to provide conductivity for the subsequent electroplating process.

[0048] Step S4: aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process;

[0049] It should be noted that the silicon adapter plate and the substrate are aligned and bonded to the target pattern through a permanent bonding process to achieve precise inter-layer alignment.

[0050] Using heat-activated or UV-activated bonding technology, the silicon interposer is tightly attached to the corresponding surface of the substrate to form a stable physical connection.

[0051] Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

[0052] It should be noted that metal interconnection is achieved between the silicon adapter plate and the substrate through an electroplating process to complete three-dimensional integration.

[0053] The silicon interposer and substrate are placed in an electroplating tank, and metal is deposited on the metal seed layer through an electrochemical process to form the required circuit connections.

[0054] After electroplating is complete, excess metal and photoresist are removed, leaving behind a precise metal interconnect structure.

[0055] Furthermore, step S2 specifically includes:

[0056] The silicon wafer is bonded to the front and back surfaces of the silicon interposer simultaneously by using a temporary bonding adhesive;

[0057] Spin-coat photoresist on the front and back surfaces of the silicon adapter plate using a coating machine;

[0058] After the silicon adapter plate and the silicon wafer are debonded by hot sliding, the silicon adapter plate is subjected to a pre-baking process, an exposure process, a post-baking process and a development process in sequence to prepare a mask barrier layer of the target image on the front and back sides of the silicon adapter plate.

[0059] It should be noted that step S2 is a key step in the bumpless interface 3D integration process, involving temporary bonding of the silicon interposer and the silicon wafer, coating of photoresist, and preparation of mask barrier layers on the front and back surfaces of the silicon interposer through exposure and development processes. The following is a detailed description of this step:

[0060] Temporary Bonding: First, a temporary bonding adhesive is used to temporarily bond the silicon wafer to the front and back surfaces of the silicon interposer. This step provides necessary support and protection for the silicon interposer during subsequent processing. The temporary bonding adhesive must possess excellent bond strength and controllable debonding properties to ensure smooth debonding without damaging the silicon interposer or the silicon wafer.

[0061] Spin-coating photoresist: Next, a spin coater is used to spin-coat photoresist onto both the front and back surfaces of the silicon interposer. Spin coating is a common photoresist coating method that uses centrifugal force to evenly coat the surface of the silicon interposer. During the spin coating process, factors such as the viscosity of the photoresist, the centrifugal speed, and the ambient temperature and humidity all affect the uniformity and thickness of the film.

[0062] Hot-slip debonding: After the silicon interposer and silicon wafer are bonded using a temporary bonding adhesive, they are debonded using a hot-slip debonding process. This step frees the silicon wafer for subsequent processing. Hot-slip debonding is a common debonding method that softens the bonding material under specific temperature conditions, enabling debonding.

[0063] Pre-bake: After photoresist coating, a pre-bake is performed. The purpose of the pre-bake is to remove the solvent from the photoresist, making it drier and tougher. The pre-bake requires precise control of temperature and time to ensure the photoresist reaches its optimal state.

[0064] Exposure process: After pre-baking, the exposure process is carried out. Exposure uses a light source to transfer the pattern on the mask to the photoresist on the surface of the silicon adapter. During the exposure process, the photosensitivity of the photoresist changes, forming a pattern corresponding to the mask.

[0065] Post-baking process: After exposure, the post-baking process is carried out. The purpose of post-baking is to further solidify the photoresist, improve the chemical resistance and thermal stability of the photoresist, and prepare for the subsequent development process.

[0066] Development: Finally, the development process takes place. This involves using a developer solution to dissolve the portions of the photoresist that have changed due to exposure, thereby forming the desired pattern. The development process requires precise control of the developer solution concentration, temperature, and development time to ensure accurate pattern transfer.

[0067] Through the above steps, a mask barrier layer with a target image can be prepared on the front and back sides of the silicon adapter, laying the foundation for subsequent metal interconnection and three-dimensional integration.

[0068] Furthermore, step S2 further includes:

[0069] Temporarily bonding the silicon wafer to the front side of the substrate using a temporary bonding adhesive;

[0070] Spin-coat photoresist on the front side of the substrate using a spin coater;

[0071] After the substrate and the silicon wafer are debonded by hot sliding, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process, and a development process to prepare a mask barrier layer of the target image on the front side of the substrate.

[0072] Furthermore, step S3 specifically includes:

[0073] Depositing barrier layers on the front and back surfaces of the silicon interposer and the TSV corresponding surface by metal physical vapor deposition;

[0074] A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

[0075] It should be noted that step S3 is a key step in the bumpless interface 3D integration process, which involves depositing barrier layers and metal seed layers on the front and back sides of the silicon adapter and the corresponding surfaces of the TSV (Through-Silicon Via). The following is a detailed description of this step:

[0076] Deposition barrier layer:

[0077] Purpose: The main function of the barrier layer is to prevent metal from diffusing into the dielectric layer at high temperatures, so it must have high stability and good adhesion to the copper and dielectric layers.

[0078] Method: Barrier layers are deposited on the front and back surfaces of the silicon interposer and on the TSV-corresponding surfaces using metal physical vapor deposition (PVD). The PVD process generally includes three steps: (1) vaporization of the coating: This involves evaporating, sublimating, or sputtering the coating through a vaporization source; (2) migration of the coating atoms, molecules, or ions: This involves collisions between atoms, molecules, or ions from the vaporization source, which then produce various reactions; and (3) deposition of the coating atoms, molecules, or ions on the substrate. In through-silicon via (TSV) 3D packaging technology, technologies for depositing barrier layers, such as Ti-TiN, Ti-TiW, and Ta-TaN, follow the manufacturing techniques of integrated circuits.

[0079] Depositing the metal seed layer:

[0080] Purpose: The main function of the metal seed layer is to provide a starting point for metal deposition in the subsequent electroplating process and ensure the uniform growth of the metal layer.

[0081] Method: A metal seed layer is deposited on the barrier layer using physical vapor deposition (PVD). TiC or TiN is typically deposited. Argon (Ar) is filled in a vacuum and glow-discharged at high voltage, ionizing the Ar atoms into Ar ions (Ar+). Under the influence of the electric field, the Ar ions are accelerated and bombarded with a cathode target made of a plating material. The target material is sputtered and deposited onto the workpiece surface. For copper-filled TSVs, the seed layer is typically made of copper to achieve good electroplating results.

[0082] In practice, physical vapor deposition (PVD) is a thin film deposition technology that physically transforms a material into a vapor phase in a vacuum environment and deposits it on a substrate. Throughout the process, the vacuum environment reduces interference from gas molecules, ensuring the quality and uniformity of the film. This method offers advantages such as low deposition temperatures and high deposition rates, making it suitable for large-scale industrial production.

[0083] Furthermore, physical vapor deposition (PVD) technology offers advantages in high purity, uniformity, and excellent adhesion in the production of high-quality thin films. Its vacuum deposition process effectively reduces impurities, improves material purity, and enables precise thickness control and uniform distribution, ensuring consistent film deposition across large substrate areas. The strong adhesion of PVD films reduces the risk of delamination and damage, making them particularly suitable for the production of copper conductive and diffusion barrier layers, possessing significant application value.

[0084] Furthermore, step S3 further includes:

[0085] A metal seed layer is deposited on the front side of the substrate by metal physical vapor deposition.

[0086] Furthermore, after step S3, the following steps are further included:

[0087] The mask blocking layer, excess barrier layer and metal seed layer on the silicon adapter and substrate are removed by using a degumming solution.

[0088] It should be noted that in the semiconductor packaging process, debonding is a key step, which involves removing the mask barrier layer, excess barrier layer, and metal seed layer on the silicon interposer and substrate. The following is a detailed description of this process:

[0089] A photoresist stripper (also known as a stripping solution) is a solvent or solution used to remove photoresist. The choice of stripper depends on the type of photoresist and the chemical stability of the substrate material. Common strippers include acetone, NMP (1-methyl-2-pyrrolidone), NEP (nitroethylpyrrolidone), and DMSO (dimethyl sulfoxide).

[0090] Glue removal process:

[0091] Wet stripping: Photoresist is removed using either an organic solvent or an alkaline solution. Organic solvent stripping removes the photoresist by dissolving it, while alkaline solutions remove it chemically. For example, a 4% KOH solution can quickly remove phenolic resin-based photoresists.

[0092] Dry stripping: Use plasma to remove the photoresist. This method can remove the photoresist without contact with solvents, but there may be contamination problems caused by reaction residues.

[0093] Treatment after degumming:

[0094] After stripping, the silicon interposer and substrate typically need to be cleaned to remove any residual photoresist and stripping solution. This step is crucial to ensure the quality of subsequent processes and avoid contamination.

[0095] Furthermore, after removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by using a degumming liquid, the following steps are also included:

[0096] A bonding pattern of the target pattern is prepared on a substrate using a permanent bonding adhesive through an overlay process.

[0097] It's important to note that after stripping, a permanent bonding adhesive is applied to the substrate through an overlay process to create a bond pattern corresponding to the target pattern. Overlay is a precision alignment technique that ensures the bond pattern matches the design drawing precisely. This process typically involves using photolithography to create a pattern of permanent bonding adhesive on the substrate. The adhesive is then cured through heat treatment or UV light exposure to form the desired bonding pattern.

[0098] Choice of permanent bonding adhesive:

[0099] Permanent bonding adhesives must have good thermal and chemical stability to withstand subsequent high-temperature and chemical processes. In addition, the bonding adhesive should have good fluidity and adhesion strength to ensure the precise formation of the bonding pattern and a strong bond to the substrate.

[0100] Through the above steps, the mask blocking layer, excess barrier layer and metal seed layer on the silicon adapter and substrate can be effectively removed, and a precise bonding pattern can be formed on the substrate, laying the foundation for subsequent three-dimensional integration process.

[0101] In an embodiment of the present application, a three-dimensional integration process method with a bump-free interface is provided, in which a bump-free three-dimensional integrated structure is constructed based on a silicon adapter plate, micro-bumps and their heterogeneous interfaces are eliminated, and many problems existing in the bump bonding process are avoided, so that the three-dimensional stacking can obtain better electrical and mechanical performance, while realizing a more compact device layout, which is conducive to reducing the device size, and solves the problem that the use of tin ball bumps will cause solder joint fatigue, increased resistance or electromigration when facing challenges such as large temperature changes and high current density, thereby affecting reliability and performance stability. The use of copper pillar bumps has a high manufacturing cost, requires precise process control, and faces reliability problems such as bond breakage, pressure reduction or electrical performance degradation.

[0102] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0103] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0104] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0106] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0107] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0108] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English full name: Read-Only Memory, English abbreviation: ROM), random access memory (English full name: Random Access Memory, English abbreviation: RAM), magnetic disk or optical disk and other media that can store program code.

[0109] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A three-dimensional integration process method without a bump interface, characterized in that: include: Step S1, preparing an insulating layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate containing the TSV; Step S2: preparing a mask barrier layer of a target pattern on the front and back surfaces of the silicon adapter plate and the front surface of the corresponding substrate based on a lift-off process and a photolithography process; Step S3, sequentially preparing a barrier layer and a metal seed layer on the front side, the back side, and the TSV corresponding side of the silicon adapter plate; Step S4, aligning and bonding the silicon adapter plate and the substrate to the target pattern through a permanent bonding process; Step S5: achieving metal interconnection between the silicon adapter plate and the substrate through an electroplating process.

2. The three-dimensional integration process method without bump interface according to claim 1, characterized in that: The step S2 specifically includes: Bonding the silicon wafer to the front and back surfaces of the silicon adapter plate simultaneously by using temporary bonding adhesive; Spin-coating photoresist on the front and back surfaces of the silicon adapter plate by a spin coater; After the silicon adapter plate and the silicon wafer are debonded by thermal slip, the silicon adapter plate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process, and a development process to prepare a mask barrier layer of a target image on the front and back surfaces of the silicon adapter plate.

3. The three-dimensional integration process method without bump interface according to claim 2, characterized in that: The step S2 further includes: temporarily bonding the silicon wafer to the front surface of the substrate by using a temporary bonding adhesive; Spin coating photoresist on the front side of the substrate by a spin coater; After the substrate and the silicon wafer are debonded by thermal slip, the substrate is sequentially subjected to a pre-baking process, an exposure process, a post-baking process, and a development process to prepare a mask barrier layer of a target image on the front side of the substrate.

4. The three-dimensional integration process method without bump interface according to claim 1, characterized in that: The step S3 specifically includes: Depositing a barrier layer on the front side, the back side and the TSV corresponding side of the silicon adapter by metal physical vapor deposition; A metal seed layer is deposited on the barrier layer by metal physical vapor deposition.

5. The three-dimensional integration process method without bump interface according to claim 4, characterized in that: The step S3 further includes: A metal seed layer is deposited on the front surface of the substrate by metal physical vapor deposition.

6. The three-dimensional integration process method without bump interface according to claim 5, characterized in that: After step S3, the following steps are also included: The mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate are removed by using a degumming solution.

7. The three-dimensional integration process method without bump interface according to claim 6, characterized in that: After removing the mask blocking layer, the redundant barrier layer and the metal seed layer on the silicon adapter plate and the substrate by using the degumming liquid, the method further includes: A bonding pattern of a target pattern is prepared on the substrate by using a permanent bonding adhesive through an overlay process.

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