Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate; a plurality of layers of first electrode layers on the substrate, each of the first electrode layers having edges with a plurality of first electrode layer openings, sidewalls of the first electrode layer openings being recessed relative to sidewalls of the edges of the first electrode layers; at least one layer of second electrode layers, each of the second electrode layers being between two adjacent layers of the first electrode layers and insulated from the first electrode layers, each of the second electrode layers having edges opposite to the edges of the first electrode layers with a plurality of second electrode layer openings, sidewalls of the second electrode layer openings being recessed relative to sidewalls of the edges of the second electrode layers; a plurality of first conductive plugs through the edges of the second electrode layers, each of the first conductive plugs through the first electrode layer openings in the plurality of layers of the first electrode layers; and a plurality of second conductive plugs through the edges of the first electrode layers, each of the second conductive plugs through the second electrode layer openings in the plurality of layers of the second electrode layers, to improve electrical performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Capacitors are commonly used passive components in very large-scale integrated circuits. They mainly include polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors, and metal-insulator-metal (MIM) capacitors.

[0003] With the rapid development of wireless communication technology, there is a strong demand to embed high-performance decoupling and bypass capacitors suitable for System-on-Chip (SoC) into the copper interconnect terminals of integrated circuits to obtain powerful RF systems. This further requires the embedded capacitors to have high capacitance density, ideal voltage linearity, precise capacitance control, and high reliability: traditional PIP, MIS, and MOS structures are no longer sufficient to meet these performance requirements. Because MIM capacitors cause less interference to transistors and can provide better linearity and symmetry, the use of MIM capacitors will be a development trend in RF and analog / mixed-signal integrated circuits.

[0004] However, the electrical performance of MIM capacitors produced by existing technologies needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate; a plurality of overlapping first electrode layers on the substrate, each first electrode layer having a plurality of first electrode layer openings at its edge, the projected patterns of the first electrode layer openings in different first electrode layers overlapping, and the sidewalls of the first electrode layer openings recessed relative to the sidewalls of the first electrode layer edges; at least one second electrode layer, each second electrode layer located between two adjacent first electrode layers and insulated from the first electrode layers, each second electrode layer having a plurality of second electrode layer openings at its edge opposite to the edge of the first electrode layer, the projected patterns of the second electrode layer openings in different second electrode layers overlapping, and the sidewalls of the second electrode layer openings recessed towards the sidewalls of the second electrode layer edges; a plurality of first conductive plugs penetrating the edges of the second electrode layers, each first conductive plug passing through a first electrode layer opening in the plurality of first electrode layers, the sidewalls of the first conductive plugs contacting the second electrode layers; and a plurality of second conductive plugs penetrating the edges of the first electrode layers, each second conductive plug passing through a second electrode layer opening in the plurality of second electrode layers, the sidewalls of the second conductive plugs contacting the first electrode layers.

[0007] Optionally, there is a first distance between the sidewall of the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

[0008] Optionally, there is a second distance between the sidewall of the second electrode layer opening and the sidewall of the second conductive plug, the dimension of the second distance being greater than 0.

[0009] Optionally, the opening of the first electrode layer includes a first side that is parallel to each other along a first direction and a second side that is connected to the first side, the second side extending along a second direction, and the first direction being perpendicular to the second direction.

[0010] Optionally, the opening of the second electrode layer includes a third side that is parallel to each other along the first direction and a fourth side that is connected to the third side, the fourth side extending along the second direction.

[0011] Optionally, it also includes: a third electrode layer opening, wherein the third electrode layer opening is located within each first electrode layer, and the projected patterns of the third electrode layer openings in different first electrode layers overlap.

[0012] Optionally, it also includes: a plurality of third conductive plugs penetrating the second electrode layer, each third conductive plug passing through an opening in the third electrode layer within a plurality of first electrode layers, the distance from the sidewall of the third electrode layer opening to the sidewall of the third conductive plug being greater than 0, and the sidewall of the third conductive plug being in contact with the second electrode layer.

[0013] Optionally, it also includes: a fourth electrode layer opening, which is located within each second electrode layer, and the projected patterns of the fourth electrode layer openings in different second electrode layers overlap.

[0014] Optionally, it also includes: a plurality of fourth conductive plugs penetrating the first electrode layer, each second conductive plug passing through an opening in the fourth electrode layer within the plurality of second electrode layers, the distance from the sidewall of the fourth electrode layer opening to the sidewall of the fourth conductive plug being greater than 0, and the sidewall of the fourth conductive plug being in contact with the first electrode layer.

[0015] Optionally, the material of the first electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0016] Optionally, the material of the second electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0017] Optionally, it may also include: a first conductive structure located on the first conductive plug, and a second conductive structure located on the second conductive plug.

[0018] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; forming a plurality of first electrode layer openings at the edges of each first electrode layer, wherein the projected patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the edges of the first electrode layers; forming at least one second electrode layer, each second electrode layer being located between two adjacent first electrode layers, and the second electrode layer being insulated from the first electrode layer; forming a plurality of second electrode layer openings at the edges of each second electrode layer opposite to the edges of the first electrode layers, wherein the projected patterns of the second electrode layer openings in different second electrode layers overlap, and the sidewalls of the second electrode layer openings are recessed towards the sidewalls of the edges of the second electrode layers; forming a plurality of first conductive plugs penetrating the second electrode layers, each first conductive plug passing through the first electrode layer openings in the plurality of first electrode layers, and the sidewalls of the first conductive plugs contacting the second electrode layers; forming a plurality of second conductive plugs penetrating the first electrode layers, each second conductive plug passing through the second electrode layer openings in the plurality of second electrode layers, and the sidewalls of the second conductive plugs contacting the first electrode layers.

[0019] Optionally, there is a first distance between the sidewall of the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

[0020] Optionally, there is a second distance between the sidewall of the second electrode layer opening and the sidewall of the second conductive plug, the dimension of the second distance being greater than 0.

[0021] Optionally, the opening of the first electrode layer includes a first side that is parallel to each other along a first direction and a second side that is connected to the first side, the second side extending along a second direction, and the first direction being perpendicular to the second direction.

[0022] Optionally, the opening of the second electrode layer includes a third side that is parallel to each other along the first direction and a fourth side that is connected to the third side, the fourth side extending along the second direction.

[0023] Optionally, it also includes forming a third electrode layer opening within the first electrode layer, wherein the projected patterns of the third electrode layer openings within different first electrode layers overlap.

[0024] Optionally, a plurality of third conductive plugs are formed that penetrate the second electrode layer. Each third conductive plug passes through an opening in the third electrode layer within a plurality of first electrode layers. The distance from the sidewall of the third electrode layer opening to the sidewall of the third conductive plug is greater than 0, and the sidewall of the third conductive plug is in contact with the second electrode layer.

[0025] Optionally, a fourth electrode layer opening is formed within each second electrode layer, and the projected patterns of the fourth electrode layer openings in different second electrode layers overlap.

[0026] Optionally, a plurality of fourth conductive plugs are formed that penetrate the first electrode layer. Each fourth conductive plug passes through an opening in the fourth electrode layer within a plurality of second electrode layers. The distance from the sidewall of the fourth electrode layer opening to the sidewall of the fourth conductive plug is greater than 0, and the sidewall of the fourth conductive plug is in contact with the first electrode layer.

[0027] Optionally, the material of the first electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0028] Optionally, the material of the second electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the semiconductor structure of the present invention, the edges of several overlapping first electrode layers on the substrate each have several first electrode layer openings. The projected patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the first electrode layer edges. A second electrode layer is provided between adjacent first electrode layers, and the edges of the second electrode layers opposite to the first electrode layers have several second electrode layer openings. The sidewalls of the second electrode layer openings are recessed towards the sidewalls of the second electrode layer edges. Several first conductive plugs penetrate the edges of the second electrode layers, each first conductive plug passing through a first electrode layer opening within several first electrode layers. Several second conductive plugs penetrate the edges of the first electrode layers. The conductive plugs, each second conductive plug, pass through the openings of the second electrode layers within several layers of second electrode layers. By utilizing the sidewall of the opening of the first electrode layer to be recessed relative to the sidewall of the edge of the first electrode layer, forming the first conductive plug at the edge of the first electrode layer is equivalent to losing half of the equivalent capacitance area of ​​the opening of the first electrode layer. Similarly, by utilizing the sidewall of the opening of the second electrode layer to be recessed towards the sidewall of the edge of the second electrode layer, forming the second conductive plug at the edge of the second electrode layer is equivalent to losing half of the equivalent capacitance area of ​​the opening of the second electrode layer. This helps to reduce the equivalent series resistance and improve the overall high-frequency characteristics of the semiconductor structure with a relatively small reduction in the effective area of ​​the first and second electrode layers. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a semiconductor structure;

[0032] Figures 2 to 18 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0033] As mentioned in the background section, the electrical performance of MIM capacitors produced by existing technologies needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of a semiconductor structure. To make the internal structure clearer, the electrode layer is made transparent and simply represented by different types of lines, while the insulating layer involved in the middle is omitted.

[0035] Please refer to Figure 1A semiconductor structure includes: a substrate (not shown); a first electrode layer 101 overlapping on the substrate, the first electrode layer 101 including first electrode layers 101a and 101b, the first electrode layer 101 having a first electrode layer opening 102; a second electrode layer 103 located between adjacent first electrode layers 101, the second electrode layer 103 having a second electrode layer opening 103a; a first conductive plug (not shown) penetrating the second electrode layer 103, the first conductive plug passing through the first electrode layer openings 102 within several layers of first electrode layers 101; a first conductive structure 103b located on the first conductive plug; several second conductive plugs (not shown) penetrating the first electrode layer 101, the second conductive plugs passing through the second electrode layer openings 103a within several layers of second electrode layers 103; a second conductive structure 104 located on the second conductive plugs; a first pin 105 located on the first conductive structure 103b; and a second pin 106 located on the second conductive structure 104.

[0036] The inventors discovered that the pattern projected onto the substrate by the opening 102 of the first electrode layer is a square, and the pattern projected onto the substrate by the opening 103a of the second electrode layer is also a square. Since a large part of the capacitor is occupied by the opening of the electrode layer, the reduction in the effective area ratio of the electrode layer will lead to a reduction in capacitance, which in turn affects the electrical performance of the final semiconductor structure.

[0037] Based on this, the present invention provides a semiconductor structure and its formation method. The edges of several overlapping first electrode layers on a substrate each have several first electrode layer openings. The projected patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the first electrode layer edges. A second electrode layer is provided between adjacent first electrode layers, and the edges of the second electrode layers opposite to the first electrode layers have several second electrode layer openings. The sidewalls of the second electrode layer openings are recessed towards the sidewalls of the second electrode layer edges. Several first conductive plugs penetrate the edges of the second electrode layers, each first conductive plug passing through a first electrode layer opening within the several first electrode layers. Several second conductive plugs are provided, each second conductive plug passing through an opening in a second electrode layer within several second electrode layers. By utilizing the recess of the sidewall of the first electrode layer opening relative to the sidewall of the first electrode layer edge, forming a first conductive plug at the edge of the first electrode layer is equivalent to losing half the equivalent capacitance area of ​​the first electrode layer opening. Similarly, by utilizing the recess of the sidewall of the second electrode layer opening towards the sidewall of the second electrode layer edge, forming a second conductive plug at the edge of the second electrode layer is equivalent to losing half the equivalent capacitance area of ​​the second electrode layer opening. This helps to reduce the equivalent series resistance and improve the overall high-frequency characteristics of the semiconductor structure while minimizing the reduction in the effective area of ​​the first and second electrode layers.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 18 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to the following first. Figure 2 and Figure 3 Provides a base of 200.

[0041] Figure 3 for Figure 2 In the cross-sectional view of AA Figure 2 for Figure 3 Top view.

[0042] In this embodiment, the substrate 200 has a first conductive layer 201 and a second conductive layer 202.

[0043] In this embodiment, the substrate 200 also has several device structures (not shown), and the first conductive layer 201 and the second conductive layer 202 are electrically connected to the several device structures respectively.

[0044] Please refer to Figure 4 A first electrode layer 203 with several overlapping layers is formed on the substrate 200.

[0045] Figure 4 View direction and Figure 2 The view orientation is consistent.

[0046] exist Figure 5 First, a first electrode layer 203 is formed on the substrate 200.

[0047] In this embodiment, the method for forming a first electrode layer 203 on a substrate 200 includes: forming a first electrode material layer (not shown) on the substrate 200; and performing a first patterning process on the first electrode material layer to form the first electrode layer 203.

[0048] The formation process of the first electrode material layer includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition.

[0049] In this embodiment, the first electrode material layer is formed using atomic layer deposition.

[0050] The material of the first electrode layer 203 includes one or more of the following: nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0051] In this embodiment, the first electrode layer 203 is made of titanium nitride.

[0052] Please refer to Figure 5 Several first electrode layer openings 203a are formed at the edge of each first electrode layer. The projection patterns of the first electrode layer openings 203a in different first electrode layers 203 overlap, and the sidewalls of the first electrode layer openings 203a are recessed relative to the sidewalls of the edge of the first electrode layer 203.

[0053] Figure 5 View direction and Figure 4 The view orientation is the same.

[0054] In this embodiment, a plurality of first electrode layer openings 203a are formed at the edge of the first electrode layer 203, and the sidewalls of the first electrode layer openings 203a are recessed relative to the sidewalls of the edge of the first electrode layer 203.

[0055] In this embodiment, the first electrode layer opening 203a includes a first side 203b that is parallel to each other along a first direction and a second side 203c that is connected to the first side 203b. The second side 203c extends along a second direction, and the first direction is perpendicular to the second direction.

[0056] In this embodiment, the first direction is the X direction and the second direction is the Y direction.

[0057] Please continue to refer to this. Figure 5 It also includes forming a third electrode layer opening 203d within the first electrode layer 203, and overlapping the projection patterns of the third electrode layer opening 203d within different layers of the first electrode layer 203.

[0058] In this embodiment, the projection of the third electrode layer opening 203d toward the substrate is square.

[0059] In other embodiments, the projection of the third electrode layer opening 203d toward the substrate may also be non-square.

[0060] Please refer to Figure 6 A first insulating layer 204 is formed on the substrate 200. The first insulating layer 204 covers the surface of the first electrode layer 203 and fills the openings 203a and 203d of the first electrode layer.

[0061] The material of the first insulating layer 204 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0062] In this embodiment, the first insulating layer 204 is made of hafnium oxide.

[0063] Please refer to Figure 7 A second electrode layer 205 is formed on the first insulating layer 204.

[0064] In this embodiment, the method for forming a second electrode layer 205 on the first insulating layer 204 includes: forming a second electrode material layer (not shown) on the first insulating layer 204; and performing a second patterning process on the second electrode material layer to form the second electrode layer 205.

[0065] The formation process of the second electrode material layer includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition.

[0066] In this embodiment, the second electrode material layer is formed using atomic layer deposition.

[0067] The material of the second electrode layer 205 includes one or more of the following: nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride, and tungsten.

[0068] In this embodiment, the material of the second electrode layer 205 is titanium nitride.

[0069] Please refer to Figure 8 A plurality of second electrode layer openings 205a are formed at the edge of each second electrode layer 205 opposite to the edge of the first electrode layer 203, and the sidewall of the second electrode layer opening 205a is recessed toward the sidewall of the edge of the second electrode layer 205.

[0070] In this embodiment, the projected patterns of the openings 205a in each second electrode layer overlap.

[0071] In this embodiment, the second electrode layer opening 205a includes a third side 205b that is parallel to each other along the first direction and a fourth side 205c that is connected to the third side 205b, and the fourth side 205c extends along the second direction.

[0072] In this embodiment, the first direction is the X direction and the second direction is the Y direction.

[0073] Please continue to refer to this. Figure 8 It also includes forming a fourth electrode layer opening in each second electrode layer 205, and the projected patterns of the fourth electrode layer openings in different second electrode layers 205 overlap.

[0074] In this embodiment, the projection of the opening of the fourth electrode layer toward the substrate is square.

[0075] In other embodiments, the projection of the fourth electrode layer opening toward the substrate may also be non-square.

[0076] Please refer to Figure 9 A second insulating layer 206 is formed on the first insulating layer 204, and the second insulating layer 206 covers the surface of the second electrode layer 205.

[0077] The material of the second insulating layer 206 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0078] In this embodiment, the material of the second insulating layer 206 is hafnium oxide.

[0079] Please refer to Figure 10 A first electrode layer 203 is then formed on the second insulating layer 206.

[0080] In this embodiment, the semiconductor structure only shows a first electrode layer 203 with two layers stacked, and a second electrode layer 205 is formed between the two first electrode layers 203.

[0081] In other embodiments, a second electrode layer 205 may be formed on the first electrode layer 203, and a first electrode layer 203 may be stacked on the second electrode layer 205. By continuously stacking in this manner, a multi-layered first electrode layer 203 is formed, and a second electrode layer 205 is formed between adjacent first electrode layers 203.

[0082] Please refer to Figure 11 A plurality of first electrode layer openings 203a are formed at the edge of the first electrode layer 203.

[0083] In this embodiment, the projected pattern of the first electrode layer opening 203a in the first electrode layer 203 overlaps with the projected pattern of the first electrode layer opening 203a in the first electrode layer 203 located at the bottom of the second electrode layer 205.

[0084] Please refer to Figure 12 A dielectric layer 207 is formed on a substrate 200, and the dielectric layer 207 covers a first electrode layer 203, a second electrode layer 205, a first insulating layer 204, and a second insulating layer 206.

[0085] In this embodiment, the dielectric layer 207 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0086] In this embodiment, after forming the dielectric layer 207, the method further includes forming a first through-hole and a second through-hole within the dielectric layer 207. For the specific formation process of the first through-hole and the second through-hole, please refer to [reference needed]. Figures 13 to 14 .

[0087] Please refer to Figures 13 to 14A first through hole 208 and a second through hole 209 are formed in the dielectric layer 207, respectively.

[0088] Figure 13 for Figure 14 Top view; Figure 14 for Figure 13 Cross-sectional view of AA.

[0089] In this embodiment, the first through hole 208 passes through the first electrode layer opening 203a in several layers of first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and extends to the part of the top surface of the first conductive layer 201 exposed in the substrate.

[0090] In this embodiment, each second through hole 209 passes through the second electrode layer opening 205a in several layers of second electrode layers 205, penetrates the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204 and extends to the part of the top surface of the second conductive layer 201 exposed in the substrate.

[0091] In this embodiment, a third through hole 210 is also formed in the dielectric layer 207. Each third through hole 210 passes through the third electrode layer opening 203d in several layers of first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and extends to the part of the top surface of the first conductive layer 201 exposed in the substrate.

[0092] In this embodiment, a fourth through hole 211 is also formed in the dielectric layer 207. Each fourth through hole 211 passes through the fourth electrode layer opening in several layers of second electrode layers 205, penetrates the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204 and extends to the part of the top surface of the second conductive layer 202 exposed in the substrate.

[0093] Please refer to Figures 15 to 17 A first conductive plug 212 is formed in the first through hole 208; a second conductive plug 213 is formed in the second through hole 209.

[0094] Figure 15 The view direction and Figure 14 The view orientation is consistent. Figure 16 and Figure 13 The view orientation is consistent. Figure 17 yes Figure 16 The relationship between the first electrode layer, the second electrode layer, and the opening of the first electrode layer at the middle edge. Figure 17 The first and second electrode layers are made transparent, while the insulating layer and dielectric layer are omitted.

[0095] In this embodiment, there is a first distance between the sidewall of the first electrode layer opening 203a and the sidewall of the first conductive plug 212, and the dimension of the first distance is greater than 0 (see reference). Figure 17 Furthermore, the sidewall of the first conductive plug 212 is in contact with the second electrode layer 205.

[0096] In this embodiment, there is a second distance between the sidewall of the second electrode layer opening 205a and the sidewall of the second conductive plug 213, and the dimension of the second distance is greater than 0 (see reference). Figure 17 Furthermore, the sidewall of the second conductive plug 213 is in contact with the first electrode layer 203.

[0097] In this embodiment, the first conductive plug 212 is equivalent to riding on the entire boundary of the first electrode layer 203. It is not surrounded by the opening 203a of the first electrode layer. Instead, the first conductive plug 212 is designed to be recessed towards the center of the first electrode layer 203 through the opening 203a of the first electrode layer, so that the first conductive plug 212 can help reduce the equivalent series resistance and improve the high frequency characteristics of the entire semiconductor structure with a smaller reduction in the effective area of ​​the first electrode layer 203.

[0098] In this embodiment, similarly, the second conductive plug 213 is equivalent to riding on the entire boundary of the second electrode layer 205. It is not surrounded by the second electrode layer opening 205a, but is designed to be recessed towards the center of the second electrode layer 205 through the second electrode layer opening 205a, so that the second conductive plug 213 is designed to be outside the edge of the second electrode layer 205. This second conductive plug 213 can help reduce the equivalent series resistance and improve the high frequency characteristics of the entire semiconductor structure with a smaller reduction in the effective area of ​​the second electrode layer 205.

[0099] In this embodiment, the first conductive plug 212 is electrically connected to the first conductive layer 201; the second conductive plug 213 is electrically connected to the second conductive layer 202.

[0100] In this embodiment, the method for forming the first conductive plug 212 and the second conductive plug 213 includes: forming a conductive plug material layer (not shown) in the first through hole 208, the second through hole 209 and the dielectric layer 207; and planarizing the conductive plug material layer until the top surface of the dielectric layer 207 is exposed, thereby forming the first conductive plug 212 and the second conductive plug 213.

[0101] The materials of the first conductive plug 212 include copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum; the materials of the second conductive plug 213 include copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0102] In this embodiment, before forming the first conductive plug 212, the method further includes: forming a first auxiliary layer on the bottom surface and sidewall of the first through hole 208; the first conductive plug 212 is located on the first auxiliary layer.

[0103] In this embodiment, before forming the second conductive plug 213, the method further includes: forming a second auxiliary layer on the bottom surface and sidewall of the second through hole; the second conductive plug 213 is located on the second auxiliary layer.

[0104] It should be noted that, in this embodiment, when the metal materials selected for the first conductive plug 212 and the second conductive plug 213 have strong metal activity, such as copper, the first auxiliary layer and the second auxiliary layer are barrier layers, which are used to prevent the metal diffusion of the first conductive plug 212 and the second conductive plug 213, thereby causing metal contamination; when the metal materials selected for the first conductive plug 212 and the second conductive plug 213 have poor adhesion, such as tungsten, the first auxiliary layer and the second auxiliary layer are adhesive layers, which are used to increase the adhesion between the first conductive plug 212 and the second conductive plug 213 and the dielectric layer.

[0105] Please continue to refer to this. Figure 16 A third conductive plug 214 is formed in the third through hole 210; a fourth conductive plug 215 is formed in the fourth through hole 211.

[0106] In this embodiment, the third conductive plug 214 is electrically connected to the first conductive layer 201; the fourth conductive plug 215 is electrically connected to the second conductive layer 202.

[0107] The materials of the third conductive plug 214 include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum; the materials of the fourth conductive plug 215 include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0108] Please refer to Figure 18 A first conductive structure 216 is formed on the first conductive plug 212, and a second conductive structure 217 is formed on the second conductive plug 213.

[0109] Figure 18 View direction and Figure 16 The view orientation is consistent.

[0110] In this embodiment, the first conductive structure 216 is also formed on the third conductive plug 216, and the second conductive structure 217 is formed on the fourth conductive plug.

[0111] Please continue to refer to this. Figure 18 A first pin 218 is formed on the first conductive structure 216, and a second pin 219 is formed on the second conductive structure 217.

[0112] Accordingly, the present invention also provides a semiconductor structure, including a substrate; a plurality of overlapping first electrode layers 203 located on the substrate, each first electrode layer 203 having a plurality of first electrode layer openings 203a at its edge, the projected patterns of the first electrode layer openings 203a in different first electrode layers 203 overlapping, and the sidewalls of the first electrode layer openings 203a being recessed relative to the sidewalls of the edges of the first electrode layers 203; at least one second electrode layer 205, each second electrode layer 205 being located between two adjacent first electrode layers 203, and the second electrode layer 205 being insulated from the first electrode layer 203, and the edges of each second electrode layer 205 being adjacent to the first electrode layer 203. The edge of the electrode layer has several second electrode layer openings 205a, and the sidewalls of the second electrode layer openings 205a are recessed towards the sidewalls of the edge of the second electrode layer 205; several first conductive plugs 212 penetrate the edge of the second electrode layer 205, and each first conductive plug 212 passes through the first electrode layer openings 203a within several layers of first electrode layers 203, and the sidewalls of the first conductive plugs 212 are in contact with the second electrode layer 205; several second conductive plugs 213 penetrate the edge of the first electrode layer 203, and each second conductive plug 213 passes through the second electrode layer openings 205a within several layers of second electrode layers 205, and the sidewalls of the second conductive plugs 213 are in contact with the first electrode layer 203.

[0113] In this embodiment, the edges of several overlapping first electrode layers 203 on the substrate each have several first electrode layer openings 203a. The projected patterns of the first electrode layer openings 203a in different layers of the first electrode layers 203 overlap, and the sidewalls of the first electrode layer openings 203a are recessed relative to the sidewalls of the edges of the first electrode layers 203. A second electrode layer 205 is provided between adjacent first electrode layers 203. The edges of the second electrode layers 205 opposite to the first electrode layers 203 have several second electrode layer openings 205a, and the sidewalls of the second electrode layer openings 205a are recessed towards the sidewalls of the edges of the second electrode layers 205. Several first conductive plugs 212 penetrate the edges of the second electrode layers 205, and each first conductive plug 212 passes through the first electrode layer openings 203a in several layers of the first electrode layers 203. Several first conductive plugs 212 penetrate the edges of the first electrode layers 203. Two conductive plugs 213, each passing through a second electrode layer opening 205a within several layers of second electrode layers 205; by utilizing the sidewall of the first electrode layer opening 203a recessed relative to the sidewall of the edge of the first electrode layer 203, forming a first conductive plug 212 at the edge of the first electrode layer 203 is equivalent to losing half the equivalent capacitance area of ​​the first electrode layer opening 203a; similarly, by utilizing the sidewall of the second electrode layer opening 205a recessed towards the sidewall of the edge of the second electrode layer 205, forming a second conductive plug 213 at the edge of the second electrode layer 205 is equivalent to losing half the equivalent capacitance area of ​​the second electrode layer opening 205a. This helps to reduce the equivalent series resistance and improve the overall high-frequency characteristics of the semiconductor structure with a relatively small reduction in the effective area of ​​the first electrode layer 203 and the second electrode layer 205.

[0114] In this embodiment, there is a first distance between the sidewall of the first electrode layer opening 203a and the sidewall of the first conductive plug 212, and the dimension of the first distance is greater than 0 (see reference). Figure 17 Furthermore, the sidewall of the first conductive plug 212 is in contact with the second electrode layer 205.

[0115] In this embodiment, there is a second distance between the sidewall of the second electrode layer opening 205a and the sidewall of the second conductive plug 213, and the dimension of the second distance is greater than 0 (see reference). Figure 17 Furthermore, the sidewall of the second conductive plug 213 is in contact with the first electrode layer 203.

[0116] In this embodiment, the first electrode layer opening 203a includes a first side 203b that is parallel to each other along a first direction and a second side 203c that is connected to the first side 203b. The second side 203c extends along a second direction, and the first direction is perpendicular to the second direction.

[0117] In this embodiment, the second electrode layer opening 205a includes a third side 205b that is parallel to each other along the first direction and a fourth side 205c that is connected to the third side 205b, and the fourth side 205c extends along the second direction.

[0118] In this embodiment, it also includes: a third electrode layer opening 203d, the third electrode layer opening 203d being located within each first electrode layer 203, and the projected patterns of the first electrode layer openings 203a within different first electrode layers 203 overlapping.

[0119] In this embodiment, it further includes: a plurality of first conductive plugs 212 penetrating the second electrode layer 205, each first conductive plug 212 passing through a third electrode layer opening 203d in a plurality of first electrode layers 203, the distance from the sidewall of the third electrode layer opening 203d to the sidewall of the first conductive plug 212 being greater than 0, and the sidewall of the first conductive plug 212 being in contact with the second electrode layer 205.

[0120] In this embodiment, it further includes: a fourth electrode layer opening, which is located within each second electrode layer 205, and the projected patterns of the fourth electrode layer openings in different second electrode layers 205 overlap.

[0121] In this embodiment, a plurality of second conductive plugs 213 penetrate the first electrode layer 203. Each second conductive plug 213 passes through an opening in a fourth electrode layer within a plurality of second electrode layers 205. The distance from the sidewall of the fourth electrode layer opening to the sidewall of the second conductive plug 213 is greater than 0, and the sidewall of the second conductive plug 213 is in contact with the first electrode layer 203.

[0122] In this embodiment, it also includes a first conductive structure 216 located on the first conductive plug 212 and a first pin 218 located on the first conductive structure 216.

[0123] In this embodiment, a second conductive structure 217 located on the second conductive plug 213 and a second pin 219 located on the second conductive structure 217 are also included.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; The substrate has several overlapping first electrode layers, each first electrode layer having several first electrode layer openings at its edge. The projected patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the first electrode layer edges. At least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer. Each second electrode layer has a plurality of second electrode layer openings at the edge opposite to the edge of the first electrode layer. The projected patterns of the second electrode layer openings in different layers of second electrode layers overlap, and the sidewalls of the second electrode layer openings are recessed toward the sidewalls of the edge of the second electrode layer. A plurality of first conductive plugs extending through the edge of the second electrode layer, each first conductive plug passing through an opening in the first electrode layer within a plurality of first electrode layers, the sidewall of the first conductive plug being in contact with the second electrode layer; A plurality of second conductive plugs are inserted through the edge of the first electrode layer, each second conductive plug passing through an opening in the second electrode layer within a plurality of second electrode layers, and the sidewall of the second conductive plug is in contact with the first electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, There is a first distance between the sidewall of the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

3. The semiconductor structure as described in claim 1, characterized in that, There is a second distance between the sidewall of the opening of the second electrode layer and the sidewall of the second conductive plug, and the dimension of the second distance is greater than 0.

4. The semiconductor structure as described in claim 1, characterized in that, The first electrode layer opening includes a first side that is parallel to each other along a first direction and a second side that is connected to the first side. The second side extends along a second direction, and the first direction is perpendicular to the second direction.

5. The semiconductor structure as described in claim 1, characterized in that, The second electrode layer opening includes a third side that is parallel to each other along a first direction and a fourth side that is connected to the third side, the fourth side extending along a second direction.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: The third electrode layer opening is located within each of the first electrode layers, and the projected patterns of the third electrode layer openings in different first electrode layers overlap.

7. The semiconductor structure as described in claim 6, characterized in that, Also includes: A plurality of third conductive plugs are inserted through the second electrode layer. Each third conductive plug passes through an opening in the third electrode layer within a plurality of first electrode layers. The distance from the sidewall of the third electrode layer opening to the sidewall of the third conductive plug is greater than 0, and the sidewall of the third conductive plug is in contact with the second electrode layer.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: The fourth electrode layer opening is located within each second electrode layer, and the projected patterns of the fourth electrode layer openings in different second electrode layers overlap.

9. The semiconductor structure as described in claim 8, characterized in that, Also includes: A plurality of fourth conductive plugs are inserted through the first electrode layer. Each fourth conductive plug passes through an opening in a fourth electrode layer within a plurality of second electrode layers. The distance from the sidewall of the fourth electrode layer opening to the sidewall of the fourth conductive plug is greater than 0, and the sidewall of the fourth conductive plug is in contact with the first electrode layer.

10. The semiconductor structure as claimed in claim 1, characterized in that, Also includes: A first conductive structure located on the first conductive plug, and a second conductive structure located on the second conductive plug.

11. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Several overlapping first electrode layers are formed on the substrate; A plurality of first electrode layer openings are formed at the edge of each first electrode layer, and the projected patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the first electrode layer edges. At least one second electrode layer is formed, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer; A plurality of second electrode layer openings are formed at the edge opposite to the edge of the first electrode layer in each second electrode layer. The projected patterns of the second electrode layer openings in different second electrode layers overlap, and the sidewalls of the second electrode layer openings are recessed toward the sidewalls of the edge of the second electrode layer. A plurality of first conductive plugs are formed that penetrate the second electrode layer, each first conductive plug passing through an opening in the first electrode layer within the plurality of first electrode layers, and the sidewall of the first conductive plug being in contact with the second electrode layer. A plurality of second conductive plugs are formed that penetrate the first electrode layer. Each second conductive plug passes through an opening in the second electrode layer within the plurality of second electrode layers, and the sidewall of the second conductive plug is in contact with the first electrode layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, There is a first distance between the sidewall of the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, There is a second distance between the sidewall of the opening of the second electrode layer and the sidewall of the second conductive plug, and the dimension of the second distance is greater than 0.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first electrode layer opening includes a first side that is parallel to each other along a first direction and a second side that is connected to the first side. The second side extends along a second direction, and the first direction is perpendicular to the second direction.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The second electrode layer opening includes a third side that is parallel to each other along a first direction and a fourth side that is connected to the third side, the fourth side extending along a second direction.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, It also includes forming a third electrode layer opening within the first electrode layer, with the projected patterns of the third electrode layer openings in different layers of the first electrode layer overlapping.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, A plurality of third conductive plugs are formed that penetrate the second electrode layer. Each third conductive plug passes through an opening in the third electrode layer within a plurality of first electrode layers. The distance from the sidewall of the third electrode layer opening to the sidewall of the third conductive plug is greater than 0, and the sidewall of the third conductive plug is in contact with the second electrode layer.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, A fourth electrode layer opening is formed within each second electrode layer, and the projected patterns of the fourth electrode layer openings within different second electrode layers overlap.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, A plurality of fourth conductive plugs are formed that penetrate the first electrode layer. Each fourth conductive plug passes through an opening in a fourth electrode layer within a plurality of second electrode layers. The distance from the sidewall of the fourth electrode layer opening to the sidewall of the second conductive plug is greater than 0, and the sidewall of the second conductive plug is in contact with the first electrode layer.

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