Integrated multi-beam feed network chip

Abstract

The application relates to an integrated multi-beam feed network chip in the technical field of satellite communication, and aims to solve the problems of high cost and low integration of a traditional multi-beam feed network. The integrated multi-beam feed network chip comprises a chip body, an input port, an output port and a signal layer. Based on the proposed integrated multi-beam feed network chip, a novel feed network wiring method is constructed by properly designing the wiring of different beam signals, so that the number of signal layers is reduced to the maximum extent, and the design cost of the feed network is reduced. The application can effectively solve the problems of large scale and high cost caused by the fact that the traditional multi-beam feed network spans multiple signal layers, provides a complete technical solution for the chip-level design of the multi-beam feed network, and can further meet the needs of low cost and miniaturization of the multi-beam phased array system.

Description

Technical Field

[0001] This invention relates to the field of satellite communication technology, and in particular to an integrated multi-beam feed network chip. Background Technology

[0002] The rapid development of phased array systems has led to an increasing demand for low cost and miniaturization. On the one hand, since the power supply networks in phased array systems are mostly implemented directly on the PCB circuit board using multi-layer signal layer connections, the required power supply networks are becoming more complex to meet the needs of large-scale phased arrays. However, these complex power supply networks increase the PCB area. Traditional multi-layer PCBs cannot meet the needs of low-cost phased array design.

[0003] On the other hand, traditional power supply networks occupy a large number of layers when routing through multiple layers. Due to miniaturization and integration requirements, the number of PCB trace layers needs to be reduced. However, reducing the number of PCB trace layers leads to signals crossing between different signal layers. Therefore, the loss in the power supply network crossing alternating traces is a bottleneck restricting its performance. In current phased array systems, there is a widespread requirement to minimize power supply network losses to reduce system design costs.

[0004] In summary, utilizing large-scale multi-beam phased arrays to achieve integrated multi-beam feeder network design with new architecture and methods has become an important solution to the bottleneck problem of traditional multi-beam feeder networks. Summary of the Invention

[0005] To address the technical problems existing in the prior art, the present invention aims to provide an integrated multi-beam feed network chip with a highly integrated and low-cost multi-beam feed network architecture. By connecting the chip, the number of trace layers in the feed network is reduced, thereby achieving a low-cost and highly integrated design of the feed network.

[0006] To achieve the above-mentioned objectives, the present invention provides an integrated multi-beam feed network chip, comprising a chip body and further comprising:

[0007] Several input port groups are used to access multi-beam input signals; each input port group includes several beam input ports;

[0008] Several output ports are used to output multi-beam output signals; the number of beam input ports and the number of output ports in each input port group are the same as the number of beams;

[0009] A plurality of signal layers are connected in sequence, each signal layer having a plurality of beamforming circuits, the number of beamforming circuits being the same as the number of beams; the beamforming circuits are used to perform pairwise beamforming of co-beam signals between a plurality of input port groups; the beamforming circuits of the first signal layer are connected to the beam input ports respectively, and the beamforming circuits of the last signal layer are connected to the output ports respectively;

[0010] The input port and the output port are arranged along the outer edge of the chip body.

[0011] According to one technical solution of the present invention, the chip body is rectangular, the output ports are distributed on the wide side of the chip body, and the input ports are distributed on the long side of the chip body.

[0012] According to one technical solution of the present invention, a plurality of input port groups and a plurality of output ports are uniformly distributed along the outer edge of the chip body, and the beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers.

[0013] According to one technical solution of the present invention, the beam numbering rule of the beam input port is as follows:

[0014] For several input port groups, group numbers are assigned sequentially along the long side of the chip body in alphabetical order, with a total of M group numbers.

[0015] The N beam input ports in each input port group are evenly distributed on the two long sides of the chip body, and beam numbers are assigned to the N beam input ports in numerical order.

[0016] For any of the aforementioned beam input ports, the beam number includes the group number and the beam number;

[0017] The total number of beam input ports is N*M, where the values ​​of M and N are both greater than or equal to 1.

[0018] According to one technical solution of the present invention, the internal structure of the chip is a passive architecture.

[0019] According to a technical solution of the present invention, the number of input port groups and the number of signal layers satisfy the following relationship:

[0020] log2(M) = γ

[0021] Where M represents the number of input port groups, M≥1, and M is an even number; γ represents the number of signal layers, and γ is an integer.

[0022] According to one technical solution of the present invention, a plurality of signal layers are stacked, and adjacent signal layers are connected by vias and vertical connection structures.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] This invention proposes an integrated multi-beam feed network chip that features a smaller size and significantly reduced inter-layer losses. This integrated multi-beam feed network chip overcomes the technical bottlenecks of large PCB trace size and high cost inherent in traditional multi-beam feed networks, thus providing a solution for low-cost, high-performance integrated design. This chip not only reduces the number of signal trace layers but also significantly reduces feed network losses, solving the problems of large PCB trace area and high losses inherent in traditional multi-beam feed networks. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0026] Figure 1 This schematic diagram illustrates the structure of an integrated multi-beam feed network chip provided in one embodiment of the present invention.

[0027] Figure 2 This schematic diagram illustrates the wiring schematic of an integrated multi-beam feed network chip provided in one embodiment of the present invention.

[0028] Figure 3 This schematic diagram illustrates a cross-sectional view of an integrated multi-beam feed network chip provided in one embodiment of the present invention.

[0029] Figure 4 This schematic diagram illustrates a micro-assembly of an integrated multi-beam feed network chip provided in another embodiment of the present invention.

[0030] Figure 5 The schematic diagram illustrates a phased array subarray of an integrated multi-beam feed network chip provided in another embodiment of the present invention.

[0031] Integrated multi-beam fed network chip 1, transceiver chip 2, phased array subarray 3,

[0032] Chip body 11, first signal layer 12, second signal layer 13, first beamforming circuit 14, second beamforming circuit 15

[0033] Antenna element 31. Detailed Implementation

[0034] The description of the embodiments in this specification should be taken in conjunction with the accompanying drawings, which should form part of the complete specification. In the drawings, the shape or thickness of the embodiments may be exaggerated and may be indicated in a simplified or convenient manner. Furthermore, parts of the various structures in the drawings will be described separately; it is worth noting that elements not shown in the figures or not described in words are in a form known to those skilled in the art.

[0035] The descriptions of the embodiments herein, including any references to directions and orientations, are for ease of description only and should not be construed as limiting the scope of the invention. The following description of preferred embodiments involves combinations of features, which may exist independently or in combination; the invention is not particularly limited to the preferred embodiments. The scope of the invention is defined by the claims.

[0036] like Figure 1 As shown, the present invention provides an integrated multi-beam feed network chip 1, which achieves a low-loss, low-cost miniaturized integrated design through a novel internal signal routing method. Figure 1-5 As shown, the integrated multi-beam feed network chip 1 includes a chip body 11, as well as several input port groups, several output ports and several signal layers.

[0037] Several input port groups are used to receive multi-beam input signals; each input port group includes several beam input ports. Several output ports are used to output multi-beam output signals, and the number of beam input ports and output ports in each input port group is the same as the number of beams. Several signal layers are connected sequentially, and each signal layer is provided with several sets of beam combining circuits, the number of beam combining circuits being the same as the number of beams; the beam combining circuits are used to perform pairwise beam combining of the same beam signals among the several input port groups; the beam combining circuits of the first signal layer are connected to the beam input ports respectively, and the beam combining circuits of the last signal layer are connected to the output ports respectively; the input port groups and output ports are arranged along the outer edge of the chip body 11.

[0038] The chip body 11 is rectangular, with output ports distributed along the wide side and beam input ports distributed along the long side. Several input port groups and several output ports are evenly distributed along the outer edge of the chip body 11, and the beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers.

[0039] The beam numbering rules for the beam input ports are as follows:

[0040] For several input port groups, group numbers are assigned sequentially along the long side of the chip body 11 in alphabetical order, with a total of M group numbers.

[0041] The N beam input ports in each input port group are evenly distributed on the two long sides of the chip body 11, and the beam numbers are assigned to the N beam input ports in numerical order.

[0042] For any beam input port, its beam number includes the group number and the beam number;

[0043] The total number of beam input ports is N*M, where the values ​​of M and N are both greater than or equal to 1.

[0044] like Figure 1 As shown, the input port groups are numbered A, B, C, ..., X, and the beam numbers are 1, 2, 3, ..., N. The beam numbers of the input ports in the first group are A1, A2, A3, ..., AN, and the beam numbers of the input ports in the second group are B1, B2, B3, ..., BN. This continues until all group numbers for the X group of input ports are completed. When N equals 8, in the first group of input ports, beam input ports numbered A1-A4 are positioned along one long side of the chip body 11, and beam input ports numbered A5-AN are positioned along the other long side of the chip body 11. In the second group of input ports, beam input ports numbered B1-B4 are positioned along one long side of the chip body 11, and beam input ports numbered A1 and B1 are symmetrically positioned along the boundary line between the first and second groups of input ports.

[0045] Figure 2 This diagram illustrates the basic working principle of multi-layer chip routing. A first beamforming circuit 14 is located on the first signal layer 121, and a second beamforming circuit 15 is located on the second signal layer 13. The principle of multi-layer chip routing is as follows: First, the number of signal layers is determined based on the value of M. If the value of M is greater than 2, the required number of signal layers can be obtained using the formula log2(M) = γ. When the number of signal layers is greater than 1, the multiple signal layers are connected through vias and vertical interconnect structures. For example, when M = 4, 2 signal layers are required; when M = 8, 3 signal layers are required. This routing method is applicable to different chip process designs, including but not limited to CMOS, GaAs, GaN, and InP.

[0046] Figure 3This is a cross-sectional diagram of the signal traces. After different beam signals are loaded onto the beam input port, identical beams are combined. For example, A1 and B1, C1 and D1 are combined in the first signal layer 12. The combined signal of A1 and B1 passes through a via and is transmitted to the second signal layer 2. In the second signal layer 13, the combined beam of A1 and B1 is combined with the combined beam of C1 and D1, resulting in beam BM1. Similarly, the output ports are numbered as beams BM1, BM2, ..., BMN, and these signals are output from the second signal layer 13.

[0047] Figure 4 This is a schematic diagram of chip micro-assembly in another embodiment of the present invention. In this embodiment, the integrated multi-beam feed network chip 1 can be micro-assembled with the transceiver chip 2 to achieve power supply for the transceiver chip. The multi-beam feed network chip 1 has 64 input ports, numbered from A1-A8, B1-B8 to H1-H8; the multi-beam feed network chip 1 has 8 output ports, numbered from BM1 to BM8. The chip micro-assembly is achieved by: arranging the 8 transceiver chips 2 (M=8) in a reasonable layout, then connecting the input terminals of the transceiver chips 2 to the beam input ports of the entire integrated multi-beam feed network chip 1 using bonding wires, and connecting the output terminals of the transceiver chips 2 to the beam input ports of the entire integrated multi-beam feed network chip 1 using bonding wires. Figure 1 The wiring pattern shown is used for design, and the synthesized signal is output through ports BM1-BM8. According to the formula log2(M) = γ, substituting M = 8 into the formula, we can obtain the signal layer number γ as 3. Therefore, when 8 transceiver chips 2 are micro-assembled, the entire chip only requires 3 layers to realize a multi-beam feed network. Similarly, if there are 16 transceiver chips 2 inside the chip, then 4 layers of signal lines are required.

[0048] Figure 5 This is a schematic diagram of a phased array according to another embodiment of the present invention. An integrated multi-beam feed network chip 1 can be applied to a phased array subarray to feed the phased array antenna elements. In this phased array, there are two phased array subarrays 3, each with eight antenna elements 31, which are respectively connected to the integrated multi-beam feed network chip 1. The eight antenna elements 31 can be expanded to 256, 512, 1020, and 2048 array elements; therefore, the number of antenna elements 31 in the phased array subarray 3 includes, but is not limited to, eight. The number of phased array subarrays 3 includes, but is not limited to, two; increasing the size of the phased array subarray 3 requires a correspondingly larger number of multi-beam feed network chips.

[0049] By using the proposed signal layer routing rules, the integrated multi-beam feed network chip proposed in this invention has a smaller size and the loss between layers can be significantly reduced.

[0050] It should be noted that the above description represents a preferred embodiment of the present invention. While preferred embodiments have been described, those skilled in the art, upon understanding the basic inventive concept of the present invention, can make various improvements and modifications without departing from the principles described herein. These improvements and modifications should also be considered within the scope of protection of the present invention. Therefore, the appended claims are intended to include both the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

Claims

1. An integrated multi-beam feed network chip, applied in a phased array subarray, for feeding phased array antenna elements, characterized in that, Including the chip itself, it also includes: Several input port groups are used to access multi-beam input signals; each input port group includes several beam input ports; Several output ports are used to output multi-beam output signals; the number of beam input ports and the number of output ports in each input port group are the same as the number of beams; A plurality of signal layers are connected in sequence, and each signal layer is provided with a plurality of beamforming circuits, the number of beamforming circuits being the same as the number of beams; the beamforming circuits are used to perform pairwise beamforming of the same beam signals between a plurality of input port groups; the beamforming circuits of the first signal layer are respectively connected to the beam input ports, and the beamforming circuits of the last signal layer are respectively connected to the output ports; The input port and the output port are disposed along the outer edge of the chip body; The number of input port groups and the number of signal layers satisfy the following relationship: log2(M)=γ Where M represents the number of input port groups, M≥1, and M is an even number; γ represents the number of signal layers, γ is an integer, and γ≥1; Several signal layers are stacked together, and adjacent signal layers are connected by a vertical connection structure, wherein the vertical connection structure is a through-hole; Several input port groups and several output ports are evenly distributed along the outer edge of the chip body. The beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers. The beam numbering rules for the beam input ports are as follows: For several input port groups, group numbers are assigned sequentially along the long side of the chip body in alphabetical order, with a total of M group numbers. The N beam input ports in each input port group are evenly distributed on the two long sides of the chip body, and beam numbers are assigned to the N beam input ports in numerical order. For any of the aforementioned beam input ports, the beam number includes the group number and the beam number; The total number of beam input ports is N*M, where the values ​​of M and N are both greater than or equal to 1.

2. The integrated multi-beam feed network chip according to claim 1, characterized in that, The chip body is rectangular, with the output ports distributed on the wide side of the chip body and the input ports distributed on the long side of the chip body.

3. The integrated multi-beam feed network chip according to claim 1, characterized in that, The chip has a passive internal architecture.

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