A band reconfigurable ultra-wideband high-efficiency distributed power amplifier

Abstract

This invention discloses a bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier, belonging to the field of wireless communication technology. The device includes multiple power units, a drain traveling wave line, a gate traveling wave line, a drain bias circuit, and a gate bias circuit; wherein a reconfigurable termination load is loaded in the drain and gate traveling wave lines. This invention achieves the reconfiguration of the power amplifier to a higher frequency band by loading reconfigurable termination loads in the gate and drain traveling wave lines, effectively improving the high-frequency efficiency of the distributed power amplifier in the ultra-wideband. Secondly, by using multilayer stacked transistors with peaking inductors as power units, the gain and high-frequency efficiency of the device are improved. Finally, by employing multiple unequal-weighted power units and non-uniform traveling wave lines, a non-uniform distributed architecture is formed, improving the impedance matching of each power unit and enhancing the overall output power and efficiency of the distributed power amplifier in the ultra-wideband.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and specifically relates to a bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier. Background Technology

[0002] With the further development of communication technology, current military and civilian aircraft, ship radar communication systems, and electronic warfare systems are placing higher demands on the performance of their radio frequency front-end systems. As the core component of the final stage of the transmission system and a major consumer of DC power, the power amplifier requires ultra-wideband, high power, high efficiency, and multi-frequency, multi-mode configurability in this context. Therefore, research on reconfigurable ultra-wideband high-efficiency power amplifier architectures has significant strategic value for the development of my country's future military equipment and civilian infrastructure.

[0003] Distributed amplifiers (DAAs) achieve ultra-wideband operation by absorbing transistor parasitic capacitance through artificial transmission lines. Compared to other broadband power amplifier technologies, they offer unparalleled advantages in expanding operating bandwidth. However, their low output power and efficiency have long been major drawbacks, contradicting their potential application requirements as power amplifiers in radar transmission systems. One primary cause of this problem is the lack of comprehensive quantitative analysis of the impact of active load modulation in the distributed architecture. This results in virtually no matching of transistor load impedances in each gain unit, ultimately leading to significantly low overall amplifier efficiency. Furthermore, the fixed traveling-wave line structure cannot address the large variations in transistor parasitic capacitance within the ultra-wideband range, another significant factor contributing to the decrease in in-band average efficiency. Summary of the Invention

[0004] To address the problems existing in the background technology, the present invention provides a bandwidth-reconfigurable ultrawideband high-efficiency distributed power amplifier. This amplifier uses a reconfigurable terminating load on the traveling wave line, effectively solving the problem of reduced high-frequency efficiency in the ultrawideband of the distributed power amplifier. Furthermore, the present invention employs multilayer stacked transistors with peaking inductors as power units and uses power units with different weights to form a non-uniform distributed architecture, effectively improving the overall output power and efficiency of the power amplifier.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A bandwidth-reconfigurable ultrawideband high-efficiency distributed power amplifier includes n power units, a drain traveling line, a gate traveling line, a drain bias circuit, and a gate bias circuit.

[0007] The gate traveling line includes an input terminal, an input DC blocking capacitor, (n+1) gate inductors, and a gate reconfigurable termination load connected in series.

[0008] The drain traveling line includes a drain reconfigurable terminal load, (n+1) drain inductors, an output DC blocking capacitor, and an output terminal connected in series.

[0009] The input terminal of the power unit is connected to the node between adjacent gate inductors, and the output terminal is connected to the node between adjacent drain inductors. n power units are connected in parallel in sequence to form a distributed architecture.

[0010] Radio frequency power is input from the input terminal, distributed to each power unit through the gate traveling wave line for power amplification, and the amplified radio frequency power is collected to the drain traveling wave line and output from the output terminal.

[0011] Furthermore, the input terminal and the output terminal are not on the same side of the power amplifier.

[0012] Furthermore, the drain reconfigurable terminal load and the gate reconfigurable terminal load have the same structure, both consisting of a resistor, an inductor, a DC blocking capacitor to ground, and two switches; wherein, one end of the DC blocking capacitor to ground is grounded, and the other end is connected to the drain inductor or the gate inductor through the resistor; the inductor and the resistor are connected in parallel, and the two switches are located at both ends of the inductor;

[0013] When the power amplifier operates in the low-frequency band, the switch is open, and the reconfigurable terminal load is a pure resistor; when the power amplifier operates in the high-frequency band, the switch is closed, and the reconfigurable terminal load forms an equivalent bandpass characteristic, absorbing the increased transistor parasitic capacitance of the power unit at high frequencies, effectively improving the efficiency of the power amplifier in the high-frequency band, thereby realizing the reconstruction to the high-frequency band.

[0014] Furthermore, the switch is a transistor switch.

[0015] Furthermore, each of the n power units adopts a multilayer stacked transistor structure with peaking inductors to improve gain and high-frequency efficiency, and the weights of the n power units are not exactly the same (i.e., the transistor widths are not exactly the same).

[0016] Furthermore, the inductance values ​​of the (n+1) drain inductors are not entirely the same, and the inductance values ​​of the (n+1) gate inductors are also not entirely the same. The inductance values ​​of the drain inductance and the gate inductance are jointly determined by the parasitic capacitance of adjacent power units and the optimal load impedance, so that the characteristic impedance of the artificial transmission line formed by the parasitic capacitance of each power unit and the adjacent inductors gradually decreases from the input side to the output side. Under the premise of achieving ultra-wideband, better impedance matching is achieved for each power unit, thereby improving the overall output power and efficiency of the power amplifier.

[0017] Furthermore, n is a positive integer greater than or equal to 2.

[0018] Furthermore, the drain bias circuit is composed of one or more inductors connected in parallel; one end of the inductor is connected to the drain bias voltage, and the other end is connected to the drain traveling wave line to provide a bias voltage for the drain of the transistor in the power unit.

[0019] Furthermore, the gate bias circuit consists of a resistor; one end of the resistor is connected to the gate bias voltage, and the other end is connected to the gate traveling wave line to provide a bias voltage for the gate of the transistor in the power unit.

[0020] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0021] This invention first utilizes a reconfigurable terminating load on the traveling wave line, enabling the power amplifier to be reconfigured to higher frequencies, effectively improving the high-frequency efficiency of the distributed power amplifier in the ultra-wideband. Second, by employing multilayer stacked transistors with peaking inductors as power units, the gain and high-frequency efficiency of the power units are improved. Finally, by using multiple unequal-weighted power units and a non-uniform traveling wave line, a non-uniform distributed architecture is formed, improving the impedance matching of each power unit and enhancing the overall output power and efficiency of the distributed power amplifier in the ultra-wideband. Combining these three points, a band-reconfigurable ultra-wideband high-efficiency distributed power amplifier is realized. Attached Figure Description

[0022] Figure 1 This is a system block diagram of the bandwidth-reconfigurable ultrawideband high-efficiency distributed power amplifier of the present invention.

[0023] Figure 2 This is the overall circuit diagram of the reconfigurable ultrawideband high-efficiency distributed power amplifier in the embodiments of the present invention.

[0024] Figure 3 This is a schematic diagram of the power unit in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the structure of the drain traveling wave line in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the gate traveling wave line in an embodiment of the present invention.

[0027] Figure 6 The figure shows the simulation results of the power-added efficiency of the reconfigurable ultrawideband high-efficiency distributed power amplifier in the embodiments of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0029] This embodiment provides a 2-18GHz reconfigurable ultrawideband high-efficiency distributed power amplifier based on 65nm CMOS technology, including four power units, a drain traveling line, a gate traveling line, a drain bias circuit, and a gate bias circuit. Its overall architecture is as follows: Figure 2 As shown.

[0030] In this embodiment, all four power units employ a three-layer stacked transistor structure with peaking inductors, such as... Figure 3 As shown, it includes three transistors Q1-Q3 and two peaking inductors L. P1 and L P2 The three-layer stacked transistors improve the gain of the power unit, while the Peaking inductor reduces the high-frequency parasitic capacitance of the upper transistors, reduces high-frequency energy leakage, and improves the high-frequency gain of the power unit.

[0031] The four power units have two weightings. The power unit closer to the input is a high-weight unit, with the Q1-Q3 transistors each having a width of 192μm. The other three are low-weight units, with the Q1-Q3 transistors each having a width of 128μm.

[0032] The drain traveling wave line, such as Figure 4 As shown, it includes a drain reconfigurable terminal load connected in series and five inductors L. D1 ~L D5 One output DC blocking capacitor C DC2 Output terminal. The characteristic admittance G of the artificial transmission line formed by these 5 drain inductors and the parasitic capacitance of the transistors in adjacent power units. ATL,n (n = 1, 2, 3, 4) must satisfy the following relationship to form a non-uniform distributed architecture with good impedance matching:

[0033]

[0034] Among them, G opt,n (n=1,2,3,4) represents the optimal load admittance of the four power units, G L This represents the load admittance of the entire power amplifier. In this embodiment, L... D1 =911 pH, L D2 =1213 pH, L D3 =715 pH, L D 4 = 332 pH, L D5 =98pH.

[0035] The drain reconfiguration terminal load is provided by a resistor R. D A transistor switch Q SW1 and Q SW2 Controlled parallel inductor L D A DC blocking capacitor C to ground DC1 Composition, transistor switch Q SW1 and Q SW2 It is controlled by an external voltage connected to its gate. Resistor R D The value of satisfies R D =1 / (G opt,1 -G ATL,1 Parallel inductor L D The value satisfies ωL D Less than R D 10% of, where ω is the angular frequency. In this embodiment, R D =597Ω, L D =600pH.

[0036] like Figure 5 As shown, the gate traveling line includes an input terminal and an input DC blocking capacitor C connected in series. D C3 5 gate inductors L G1 ~L G5 Gate reconfigurable terminal load; in this embodiment, L G1 =240 pH, L G2 =L G3 =L G4 =492 pH, L G5 =232pH.

[0037] The gate reconfigurable termination load is composed of a resistor R. G A transistor switch Q SW3 and Q SW4 Controlled parallel inductor L G A DC blocking capacitor C to ground DC4 Composition, transistor switch Q SW3 and Q SW4 It is controlled by an external voltage connected to its gate. The operating mechanism of the gate-reconfigurable termination load is basically the same as that of the drain-reconfigurable termination load. In this embodiment, the resistor R... G Take 50Ω directly, and connect inductor L in parallel. G Take pH 243.

[0038] The drain bias circuit includes two inductors L connected in parallel. BD1 and L BD2 Both inductors have an inductance value of 5.7nH; inductance L BD1 and L BD2One end is connected to the drain bias voltage, and the other end is connected to the inductor L of the drain traveling wave line. D1 and inductor L D2 and inductor L D3 and inductor L D4 Between these two points, a drain bias voltage is provided for the power unit transistors. This dual-connection configuration also effectively reduces DC losses on the drain traveling line, thus improving the overall efficiency of the power amplifier to some extent.

[0039] The gate bias circuit includes a 3.9kΩ resistor R. BG Resistance R BG One end is connected to the gate bias voltage, and the other end is connected to the inductor L of the gate traveling wave line. G4 and inductor L G5 Between these, the gate bias voltage is provided for the power unit transistor.

[0040] Under the above settings, when the transistor switch is open, the power amplifier has high efficiency in the low frequency band (2-9GHz in this embodiment); when the transistor switch is closed, the equivalent bandpass characteristic is realized, the frequency band is switched to the high frequency, and the power amplifier has high efficiency in the high frequency band (9-18GHz in this embodiment).

[0041] The simulation results in the simulation software ADS are as follows: Figure 6 As shown, when the switch is open (low-frequency mode), the power amplifier has a saturated output power of 19.2-20.2 dBm and a saturated power-added efficiency (PAE) of 31%-35% in the 2-9 GHz range; when the switch is closed (high-frequency mode), the power amplifier has a saturated output power of 18.3-19.9 dBm and a power-added efficiency of 23%-31% in the 9-18 GHz range, representing a maximum improvement of 10 percentage points compared to the low-frequency mode.

[0042] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A bandwidth-reconfigurable ultrawideband high-efficiency distributed power amplifier, characterized in that, It includes n power units, a drain traveling line, a gate traveling line, a drain bias circuit, and a gate bias circuit; The gate traveling line includes an input terminal, an input DC blocking capacitor, (n+1) gate inductors, and a gate reconfigurable termination load connected in series. The drain traveling wave line includes a drain reconfigurable terminal load, (n+1) drain inductors, an output DC blocking capacitor, and an output terminal connected in series. The input terminal of the power unit is connected to the node between adjacent gate inductors, and the output terminal is connected to the node between adjacent drain inductors. n power units are connected in parallel in sequence to form a distributed architecture. RF power is input from the input terminal, distributed to each power unit through the gate traveling wave line for power amplification, and the amplified RF power is collected to the drain traveling wave line and output from the output terminal. The drain reconfigurable terminal load and the gate reconfigurable terminal load have the same structure, both consisting of a resistor, an inductor, a DC blocking capacitor to ground, and two switches; wherein, one end of the DC blocking capacitor to ground is grounded, and the other end is connected to the drain inductor or the gate inductor through the resistor; the inductor and the resistor are connected in parallel, and the two switches are located at both ends of the inductor; When the power amplifier operates in the low-frequency band, the switch is open, and the reconfigurable terminal load is a pure resistor; when the power amplifier operates in the high-frequency band, the switch is closed, and the reconfigurable terminal load forms an equivalent bandpass characteristic, absorbing the increased transistor parasitic capacitance of the power unit at high frequencies, thus achieving reconstruction to the high-frequency band.

2. The bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 1, characterized in that, The input terminal and the output terminal are not on the same side of the power amplifier.

3. The bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 2, characterized in that, The switch is a transistor switch.

4. A bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 2 or 3, characterized in that, All n power units employ a multilayer stacked transistor structure with peaking inductors to improve gain and high-frequency efficiency, and the weights of the n power units are not exactly the same.

5. The bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 4, characterized in that, The inductance values ​​of the (n+1) drain inductors are not completely identical, and the inductance values ​​of the (n+1) gate inductors are also not completely identical. The inductance values ​​of the drain inductance and the gate inductance are jointly determined by the parasitic capacitance of adjacent power units and the optimal load impedance, so that the characteristic impedance of the artificial transmission line formed by the parasitic capacitance of each power unit and the adjacent inductors gradually decreases from the input end to the output end. Under the premise of achieving ultra-wideband, better impedance matching is achieved for each power unit, thereby improving the overall output power and efficiency of the power amplifier.

6. The bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 5, characterized in that, n is a positive integer greater than or equal to 2.

7. A bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 6, characterized in that, The drain bias circuit consists of one or more inductors connected in parallel; one end of the inductor is connected to the drain bias voltage, and the other end is connected to the drain traveling wave line to provide a bias voltage for the drain of the transistor in the power unit.

8. The bandwidth-reconfigurable ultra-wideband high-efficiency distributed power amplifier as described in claim 7, characterized in that, The gate bias circuit consists of a resistor; one end of the resistor is connected to the gate bias voltage, and the other end is connected to the gate traveling wave line to provide a bias voltage for the gate of the transistor in the power unit.

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