A random computing digital filter device

Abstract

The application discloses a kind of based on random computing digital filter device, comprising: preprocessing unit, for pre-processing input data;Input cache unit, for pre-processing data is cached and with preset time interval sequentially output cached data;Serial shift register group, for the data input is serially shifted, cache and output the data after serial shift processing;Data conversion unit, for the multiple data of parallel input is converted into multiple random bit sequence and output;Random computing unit, for the multiple random bit sequence and the logic operation processing of multiple filter coefficients configured in advance, obtain and output random filtering result;Data recovery unit, for converting random filtering result into binary data and output;Output cache unit, for caching and output binary data.The digital filter device of the application has low hardware complexity, low hardware resource overhead, and can ensure the calculation accuracy when bit flipping occurs.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more specifically to a digital filter device based on random computation. Background Technology

[0002] Digital filters are fundamental functional units for baseband signal processing in various electronic systems such as communication, navigation, and sensing. They have a wide range of applications and are essentially discrete linear systems with unique frequency response characteristics. When a digital signal is fed into a digital filter, it undergoes a convolution operation with the filter coefficients, thereby suppressing signal components within a certain frequency range. Compared to analog filters, digital filters have the following significant advantages:

[0003] First, digital filters have lower hardware costs and greater flexibility. Digital filters can operate within FPGA programmable logic devices, and their filtering characteristics can be adjusted on demand by changing the digital filter coefficients and order, without needing to consider circuit impedance matching issues. In contrast, analog filters require complex analog circuit design, and their filtering characteristics are basically fixed after the design is completed, with a very small adjustable range, and complex filter impedance matching.

[0004] Secondly, digital filters offer better stability and superior performance. Their performance does not fluctuate due to changes in temperature or humidity, and they possess linear phase characteristics, resulting in superior passband flatness, stopband attenuation, and transition band width compared to analog filters. In contrast, the performance of analog filters deviates with increased workload or changes in the operating environment. Limited by the nonlinear response characteristics of the devices, analog filters struggle to maintain linear phase characteristics.

[0005] In terms of digital filter implementation, existing digital filters mainly consist of digital multipliers, adders, and delay units. Regardless of whether it is a direct-type digital filter structure, a transposed type, or a lattice-type digital filter structure, a multiplier is needed to multiply the input digital signal with the filter coefficients, an adder is needed to accumulate the results of multiplying different coefficients, and a delay unit is needed to buffer a certain length of input data to meet the data memory length requirements of convolution calculations.

[0006] However, in FPGA programmable logic devices, the logic resources occupied by a pipelined multiplier are often tens of times greater than those of an adder of the same bit width. Furthermore, the resource overhead of the multiplier increases dramatically with the increase in the filter data bit width. Therefore, high-order digital filters can only be implemented on high-end FPGAs with abundant logic resources. In some low-cost devices using low-end FPGAs, it is difficult to apply complex digital filters to ensure signal frequency domain selectivity. Moreover, in special scenarios such as satellite applications, due to the single-event effect in the space environment, FPGA programmable logic devices are prone to errors such as bit flips. When bit flips occur, the calculation accuracy of existing digital filters decreases significantly, thus affecting the overall system functionality. Summary of the Invention

[0007] To address some or all of the technical problems existing in the prior art, the present invention provides a digital filter device based on random calculation.

[0008] The technical solution of the present invention is as follows:

[0009] A digital filter device based on random computation is provided, the digital filter device comprising:

[0010] The preprocessing unit is used to preprocess the input data of the digital filter device to obtain and output preprocessed data.

[0011] An input buffer unit is provided, wherein the input terminal of the input buffer unit is connected to the output terminal of the preprocessing unit, and the output terminal of the input buffer unit is connected to the serial shift register group and the data conversion unit respectively. The input buffer unit is used to buffer the input data and output the buffered data sequentially at a preset time interval.

[0012] The serial shift register group includes L-1 first registers connected in sequence. The input terminal of the first first register in the L-1 first registers is connected to the output terminal of the input buffer unit. The output terminals of the L-1 first registers are respectively connected to the data conversion unit. The serial shift register group is used to serially shift the input data and buffer and output the serially shifted data. L represents the number of filter tap coefficients.

[0013] The data conversion unit, whose output is connected to the input of the random computation unit, is used to convert multiple parallel input data into a multi-path random bit sequence and output it.

[0014] The random calculation unit has its output connected to the input of the data recovery unit. The random calculation unit is used to perform logical operations on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results.

[0015] The data recovery unit, the output of which is connected to the input of the output buffer unit, is used to convert the random filtering result into binary data and output it.

[0016] The output buffer unit is used to buffer and output binary data.

[0017] In some optional implementations, the preprocessing expression is:

[0018]

[0019] Where, x i This indicates the obtained preprocessed data. This represents the input data of the digital filter device, where n represents the input data. Data bit width, input data The range of values ​​is [-2]. n-1 ,2 n-1 -1], preprocessed data x i The value range is [0, 2]. n -1].

[0020] In some optional implementations, the data conversion unit includes: a first linear feedback shift register, a first weight generation subunit, and a first numerical comparison subunit;

[0021] The first linear feedback shift register has n stages and is used to generate a cycle period of 2. n A pseudo-random sequence of -1 is used to buffer and output the pseudo-random sequence, where n represents the data bit width of the input data of the digital filter device.

[0022] The first weight generation subunit includes two subunits. The input terminals of the two first weight generation subunits are respectively connected to the output terminal of the first linear feedback shift register. The two first weight generation subunits respectively calculate the weights of the data input to the first linear feedback shift register and output n weights.

[0023] The first numerical comparison subunit comprises L units. The first input terminals of the L first numerical comparison subunits are respectively connected to the output terminals of the input buffer unit and the output terminals of the L-1 first registers. The second input terminals of the odd-numbered bits of the L first numerical comparison subunits are connected to the output terminal of the first first weight generation subunit, and the second input terminals of the even-numbered bits of the L first numerical comparison subunits are connected to the output terminal of the second first weight generation subunit. The first numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the data input from the input buffer unit or the first register, and to perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

[0024] In some optional implementations, the weight calculation expression corresponding to the first first weight generation subunit is:

[0025]

[0026] Where i is a variable, i = 2, 3, ..., n-3, w 1,m (k) represents the k-th weight generated by the first weight generation subunit in the first clock cycle of the m-th clock cycle. This represents the output data of the k-th register in the first linear feedback shift register during the m-th clock cycle. Indicates to Invert the binary representation, k = 1, 2, 3, ..., n, where ∧ represents the logical AND operation.

[0027] In some optional implementations, the weight calculation expression corresponding to the second first weight generation subunit is:

[0028]

[0029] Where i is a variable, i = 2, 3, ..., n-3, w 2,m (k) represents the k-th weight generated by the first weight generation subunit in the second clock cycle of the m-th clock cycle. This represents the output data of the k-th register in the first linear feedback shift register during the m-th clock cycle. Indicates to Invert the binary representation, k = 1, 2, 3, ..., n, where ∧ represents the logical AND operation.

[0030] In some alternative implementations, the first numerical comparison subunit includes: AND gates and OR gates;

[0031] The AND gates include n gates. The first input terminals of the n AND gates are connected to the output terminals of the input buffer unit or one of the first registers. The second input terminals of the n AND gates are connected to the output terminals of the first first weight generation subunit or the second first weight generation subunit. The kth AND gate among the n AND gates is used to perform an AND logic operation on the kth weight input to the first weight generation subunit and the kth data bit of the data input to the input buffer unit or the first register, and output the AND logic operation result.

[0032] The OR gate comprises n-1 gates, which are cascaded in sequence. The output of the AND gate is connected to the input of the OR gate. The n-1 OR gates are used to perform OR logic operations on the n AND logic results output by the n AND gates to obtain and output a random bit sequence.

[0033] In some optional implementations, the random computation unit includes: an XNOR gate, a data selector, and a selector control unit;

[0034] The XOR gates include L gates. The first input terminals of the L XOR gates are respectively connected to the output terminals of the L first numerical comparison subunits. The second input terminals of the L XOR gates are respectively used to input the sign bits of the L pre-configured filter coefficients in two's complement representation. The kth XOR gate among the L XOR gates is used to perform an XOR logic operation on the random bit sequence input to the kth first numerical comparison subunit and the sign bit of the kth filter coefficient in two's complement representation, and to obtain and output the XOR logic operation result.

[0035] The data selector includes L-1 data selectors, which are cascaded in sequence. The output of the XOR gate is connected to the input of the data selector. The L-1 data selectors are used to select one data output from the L data output by the L XOR gates according to the control signal of the selector control unit.

[0036] The selector control unit includes multiple data selectors at the same level connected to the same selector control unit. The selector control unit is used to generate a control signal based on the filter coefficients corresponding to the input data of the XOR gate associated with the connected data selector and send it to the data selector.

[0037] In some optional implementations, the selector control unit includes: a second linear feedback shift register, a second weight generation subunit, and a second numerical comparison subunit;

[0038] The second linear feedback shift register has n stages and is used to generate a cycle period of 2. nThe pseudo-random sequence is -1, and the pseudo-random sequence is buffered and output, where n represents the data bit width of the input data of the digital filter device;

[0039] The input terminal of the second weight generation subunit is connected to the output terminal of the second linear feedback shift register. The second weight generation subunit is used to calculate and generate n weights from the data input to the second linear feedback shift register.

[0040] The second numerical comparison subunit includes s i 1, s i The number of data selectors connected to the selector control unit, s i The first input terminal of each of the second numerical comparison subunits is used to input a pre-configured s i A comparison value, s i The second input terminals of each of the second numerical comparison subunits are respectively connected to the output terminals of the second weight generation subunit. i The output of each of the second numerical comparison subunits is respectively connected to s i The data selector is connected, and the second numerical comparison subunit is used to perform AND logic operations on the n data bits of the n weights and the comparison value respectively, and to perform OR logic operations on the n AND logic operation results to obtain and output a control signal. The comparison value input to the second numerical comparison subunit is determined according to the filter coefficients corresponding to the input data of the XOR gate associated with the data selector connected to the second numerical comparison subunit.

[0041] In some optional implementations, it is configured that: the first input terminal of the data selector connected to the r-th second numerical comparison subunit is associated with P XOR gates, and the filter coefficients corresponding to the input data of the P XOR gates are sequentially... The second input terminal of the data selector connected to the r-th second numerical comparison subunit is associated with Q XOR gates, and the filter coefficients corresponding to the input data of the Q XOR gates are sequentially as follows: The comparison value of the r-th second numerical comparison subunit is then expressed as:

[0042]

[0043] Where, λ i,r This indicates the comparison value of the r-th second numerical comparison subunit, where p and q represent intermediate variables.

[0044] In some optional implementations, the data recovery unit includes: an adder, an n-bit register, and a subtractor;

[0045] The first input terminal of the adder is connected to the output terminal of the random calculation unit, the second input terminal of the adder is connected to the output terminal of the n-bit register, and the output terminal of the adder is connected to the input terminal of the n-bit register. The adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result.

[0046] The output of the n-bit register is also connected to the first input of the subtractor. The n-bit register is used to determine and output 2 based on the accumulation result. n-1 The number of bit "1"s in a clock cycle;

[0047] The second input terminal of the subtractor is used to input 2. n-1 The output of the subtractor is connected to the input of the output buffer unit, and the subtractor is used to perform a subtraction on the data input to the n-bit register and 2. n-1 Subtract the two numbers to obtain and output the binary data.

[0048] The main advantages of the technical solution of this invention are as follows:

[0049] The random computation-based digital filter device of this invention is mainly implemented using logic gate circuits, without multipliers, and only uses one adder and one subtractor, which can significantly reduce hardware complexity and hardware resource consumption, and can be implemented on various FPGAs. By converting binary data into a random bit stream and performing logical operations on the random bit stream, the arithmetic operations such as binary multiplication and addition are equivalently achieved. In the event of single-event flips, only a small number of bits in the random bit stream flip. During the bit accumulation process in the data recovery unit, these bit flips have little impact on the final binary data recovery, which can ensure the calculation accuracy of the digital filter when bit flips occur, and ensure the stable execution of the overall function. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of a digital filter device based on random computation provided in an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of the working timing of a digital filter device based on random computation, provided in an embodiment of the present invention.

[0053] Figure 3 This is a schematic diagram of the structure of a data conversion unit provided in an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of the structure of a first linear feedback shift register provided in an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of the structure of a first weight generation subunit provided in an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram showing the connection relationship between the first linear feedback shift register and the first weight generation subunit in the data conversion unit provided in an embodiment of the present invention;

[0057] Figure 7 This is a schematic diagram of the structure of a first numerical comparison subunit provided in an embodiment of the present invention;

[0058] Figure 8 This is a schematic diagram of the structure of a random calculation unit provided in an embodiment of the present invention;

[0059] Figure 9 This is a schematic diagram of the structure of a selector control unit provided in an embodiment of the present invention;

[0060] Figure 10 This is a schematic diagram of the structure of a data recovery unit provided in an embodiment of the present invention. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0062] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0063] See Figure 1 , Figure 1 This is a schematic diagram of a digital filter device based on random computation provided in an embodiment of the present invention. Figure 1 In this diagram, D represents the first register. This invention provides a digital filter device based on random computation, the digital filter device comprising:

[0064] The preprocessing unit is used to preprocess the input data of the digital filter device, obtain and output the preprocessed data;

[0065] The input buffer unit has its input terminal connected to the output terminal of the preprocessing unit, and its output terminal connected to the serial shift register group and the data conversion unit, respectively. The input buffer unit is used to buffer the input data and output the buffered data sequentially at a preset time interval.

[0066] The serial shift register group includes L-1 first registers connected in sequence. The input of the first first register in the L-1 first registers is connected to the output of the input buffer unit, and the outputs of the L-1 first registers are respectively connected to the data conversion unit. The serial shift register group is used to serially shift the input data, buffer and output the serially shifted data, and L represents the number of filter tap coefficients.

[0067] The data conversion unit has its output connected to the input of the random computation unit. The data conversion unit is used to convert multiple parallel input data into multiple random bit sequences and output them.

[0068] The random computation unit has its output connected to the input of the data recovery unit. The random computation unit is used to perform logical operations on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results.

[0069] The data recovery unit has its output connected to the input of the output buffer unit. The data recovery unit is used to convert the random filtering result into binary data and output it.

[0070] Output buffer unit, used to buffer and output binary data.

[0071] The working principle of the random computation-based digital filter device provided in the embodiments of the present invention will be described below:

[0072] See Figures 1-2 , Figure 2 This is a timing diagram illustrating the operation of a digital filter device based on random computation, provided as an embodiment of the present invention. Assume that the clock frequency corresponding to the input data of the digital filter device is... The operating clock frequency for the digital filter device to perform random calculations is The input data, output data, and filter coefficients of the digital filter device are all signed fixed-point numbers, and the data bit width is n bits.

[0073] Based on the above assumptions, when the random computation-based digital filter device provided in this embodiment of the invention is working, the preprocessing unit first processes the input data of the digital filter device. Perform the transformation and then convert the data x. iThe data is fed into the input buffer unit; the write port (input terminal) of the input buffer unit is configured according to the clock frequency. The read port (output) operates according to the clock frequency. This allows for the isolation of different clock domains; the data x input to the buffer unit is sent by the buffer preprocessing unit. i At the same time, with The buffered data is output sequentially at time intervals, and then sent to a serial shift register group of length L-1 and a data conversion unit. The serial shift register group performs serial shifting and buffering on the received data, and sends the buffered data in L-1 registers together to the data conversion unit. The data conversion unit receives L data (x1, x2, ..., x...). L After that, data conversion begins, transforming the L parallel input data into L channels of length 2. n A random bit sequence of -1 (p1, p2, ..., p...) L The data is then output to the random calculation unit, with a processing delay of 2 clock cycles. Upon receiving the random bit sequence, the random calculation unit performs logical operations on the random bit sequence and pre-configured filter coefficients to obtain a random bit stream y1 corresponding to the output data of the digital filter device, i.e., the random filtering result. This random bit stream is then output to the data recovery unit, with a processing delay of 1 clock cycle. The data recovery unit converts the random bit stream into n bits of data. That is, binary signed data, and outputting the binary signed data to the output buffer unit. The processing delay of the data recovery unit is 1 clock cycle; the write port (input terminal) of the output buffer unit is based on the clock frequency. The read port (output) operates according to the clock frequency. The task is to read and output signed binary data when the output buffer is not empty. As the output of a digital filter device.

[0074] Based on the above working process, it can be seen that in the working clock Within the clock domain, the computational delay of the digital filter device is L(2). n -1)+4 clock cycles.

[0075] Furthermore, in one embodiment of the present invention, when the preprocessing unit preprocesses the input data, the preprocessing expression is:

[0076]

[0077] Where, x i This indicates the obtained preprocessed data. This represents the input data of the digital filter device, where n represents the input data. Data bit width, input data The range of values ​​is [-2]. n-1 ,2 n-1 -1], preprocessed data x i The value range is [0, 2]. n -1].

[0078] refer to Figure 3-7 Furthermore, in one embodiment of the present invention, the data conversion unit includes: a first linear feedback shift register, a first weight generation subunit, and a first numerical comparison subunit;

[0079] The first linear feedback shift register has an order of n and is used to generate a loop with a period of 2. n A pseudo-random sequence of -1 is used for buffering and outputting the pseudo-random sequence, where n represents the data bit width of the input data of the digital filter device.

[0080] The first weight generation subunit includes two subunits. The input terminals of the two first weight generation subunits are respectively connected to the output terminal of the first linear feedback shift register. The two first weight generation subunits respectively calculate the weights of the data input to the first linear feedback shift register and output n weights.

[0081] The first numerical comparison subunit comprises L units. The first input terminals of the L first numerical comparison subunits are respectively connected to the output terminals of the input buffer unit and the output terminals of L-1 first registers. The second input terminals of the odd-numbered first numerical comparison subunits are connected to the output terminal of the first first weight generation subunit, and the second input terminals of the even-numbered first numerical comparison subunits are connected to the output terminal of the second first weight generation subunit. The first numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the data input from the input buffer unit or the first registers, and to perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

[0082] In this embodiment of the invention, the first linear feedback shift register has a series number of n, and by selecting a suitable primitive polynomial, the first linear feedback shift register generates a cycle period of 2. n A pseudo-random sequence of -1 is written back to n shift registers R1, R2, ..., R. n During the operation of the first linear feedback shift register, registers R1, R2, ..., R n The values ​​are fed into two first weight generation sub-units, which calculate the weights required by the first value comparison sub-unit based on the input values.

[0083] Furthermore, in one embodiment of the present invention, the weight calculation expression corresponding to the first weight generation subunit is:

[0084]

[0085] The weight calculation expression for the second first weight generation sub-unit is:

[0086]

[0087] Where i is a variable, i = 2, 3, ..., n-3, w 1,m (k) represents the k-th weight generated by the first weight generation subunit in the m-th clock cycle, w 2,m (k) represents the k-th weight generated by the second first weight generation subunit in the m-th clock cycle. This represents the output data of the k-th register in the first linear feedback shift register during the m-th clock cycle. Indicates to Invert the binary representation, k = 1, 2, 3, ..., n, where ∧ represents the logical AND operation.

[0088] refer to Figure 5 Furthermore, in one embodiment of the present invention, the first weight generation subunit is constructed using OR gates and NOT gates.

[0089] refer to Figure 6 In this embodiment of the invention, the first input port to the nth input port of the first first weight generation subunit are respectively connected to the first register to the nth register of the first linear feedback shift register, and the first input port to the nth input port of the second first weight generation subunit are respectively connected to the nth register to the first register of the first linear feedback shift register, so as to realize the weight calculation method of the first weight generation subunit as defined above.

[0090] In this embodiment of the invention, the first weight generation subunit is implemented using OR gates and NOT gates, which can reduce hardware resource overhead. Simultaneously, the two first weight generation subunits use different orders when utilizing the output bits of the first linear feedback shift register, which can reduce the correlation between the two sets of generated weights, thereby ensuring the accuracy of random calculation.

[0091] refer to Figure 7 Furthermore, in one embodiment of the present invention, the first numerical comparison subunit includes: an AND gate and an OR gate;

[0092] The AND gate comprises n gates. The first input of each of the n AND gates is connected to the output of an input buffer unit or a first register. The second input of each of the n AND gates is connected to the output of a first weight generation subunit or a second first weight generation subunit. The kth AND gate among the n AND gates is used to perform an AND logic operation on the kth weight input to the first weight generation subunit and the kth data bit input to the input buffer unit or the first register, and output the result of the AND logic operation.

[0093] The OR gate consists of n-1 gates, which are cascaded in sequence. The output of the AND gate is connected to the input of the OR gate. The n-1 OR gates are used to perform OR logic operations on the n AND logic results output by the n AND gates to obtain and output a random bit sequence.

[0094] Specifically, the input data received by the first numerical comparison subunit is x. i For example, x i The corresponding n data bits x i (1),x i (2),…,x i (n) in 2 n The value remains unchanged for 1 clock cycle, during which the first weight generation subunit outputs w. 1,m (k), k = 1, 2, ..., n (or w) 2,m (k), k = 1, 2, ..., n) in the m-th clock cycle (m = 1, 2, ..., n) n-1 ) and data x i Each of the n data bits is ANDed with n AND gates, and then the results of the n AND operations are ORed together by cascaded n-1 OR gates to obtain the random sequence p. i The logic value p in the m-th clock cycle i (m).

[0095] In this embodiment of the invention, the first numerical comparison subunit is implemented using AND gates and OR gates, which can reduce hardware resource overhead. The digital logic circuit formed by the AND gates and OR gates can generate a random bit sequence corresponding to the input data.

[0096] refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a random calculation unit provided in an embodiment of the present invention. Figure 8 In this context, MUX stands for data selector. Furthermore, in one embodiment of the present invention, the random calculation unit includes: an XNOR gate, a data selector, and a selector control unit.

[0097] The system includes L XOR gates. The first inputs of the L XOR gates are connected to the outputs of the L first numerical comparison subunits, respectively. The second inputs of the L XOR gates are used to input the sign bits of the L pre-configured filter coefficients in two's complement representation. The kth XOR gate is used to perform an XOR logic operation on the random bit sequence input to the kth first numerical comparison subunit and the sign bits of the kth filter coefficient in two's complement representation, and to obtain and output the XOR logic operation result.

[0098] The data selector includes L-1 data selectors, which are cascaded in sequence. The output of the XOR gate is connected to the input of the data selector. The L-1 data selectors are used to select one data output from the L data output by the L XOR gates according to the control signal of the selector control unit.

[0099] The selector control unit includes multiple data selectors at the same level connected to the same selector control unit. The selector control unit is used to generate control signals based on the filter coefficients corresponding to the input data of the XOR gate associated with the connected data selector and send them to the data selector.

[0100] In this embodiment of the invention, for ease of design, layout, and data processing, L-1 data selectors are configured. class, This indicates rounding up. Furthermore, when the number of output signal channels in the i-th stage is odd, the remaining 1 signal channel will be directly sent to the subsequent stage containing the remaining signal. The two remaining signals will then be combined and fed into a data selector in that subsequent stage for selection. Accordingly, based on the above settings, the number of data selectors deployed in the i-th stage is... or indivual.

[0101] It should be noted that when L-1 data selectors constitute The selector control unit includes at least one level. Data selectors at the same level are connected to the same selector control unit, while data selectors at different levels are connected to different selector control units.

[0102] Specifically, the random bit sequence received by the random computing unit is p. i ,p i-1 ,…,p i-L-1 The L filter coefficients are configured as c1, c2, ..., c L For example, in each clock cycle, under the processing of the random computing unit, the random bit sequence p i ,p i-1 ,…,p i-L-1 The L bit values ​​are respectively associated with sign(c1), sign(c2), ..., sign(c...L Perform an XNOR operation, where sign(c) i ) represents the filter coefficient c i In two's complement representation, the sign bit, the result of the XOR operation, is... After selection by the level data selector, it is used as the random filtering result y. i Output during the current clock cycle.

[0103] Furthermore, in this embodiment of the invention, each level of data selector is controlled by generating an independent control signal through a corresponding selector control unit.

[0104] refer to Figure 9 In one embodiment of the present invention, the selector control unit includes: a second linear feedback shift register, a second weight generation subunit, and a second numerical comparison subunit;

[0105] The second linear feedback shift register has n stages and is used to generate a cycle with a period of 2. n The pseudo-random sequence of -1 is buffered and output, where n represents the data bit width of the input data of the digital filter device;

[0106] The input of the second weight generation subunit is connected to the output of the second linear feedback shift register. The second weight generation subunit is used to calculate and generate n weights from the data input to the second linear feedback shift register.

[0107] The second numerical comparison subunit includes s i 1, s i The number of data selectors connected to the selector control unit, s i The first input terminal of each second numerical comparison subunit is used to input a pre-configured s i A comparison value, s i The second input terminals of each second numerical comparison subunit are respectively connected to the output terminal of the second weight generation subunit, s i The output of each second numerical comparison subunit is respectively connected to s i A data selector is connected, and the second numerical comparison subunit is used to perform AND logic operations on the n data bits of the n weights and the comparison value respectively, and to perform OR logic operations on the n AND logic operation results to obtain and output control signals. The comparison value input to the second numerical comparison subunit is determined according to the filter coefficients corresponding to the input data of the XOR gate associated with the data selector connected to the second numerical comparison subunit.

[0108] It should be noted that the second linear feedback shift register, the second weight generation subunit, and the second numerical comparison subunit described above have the same structure as the first linear feedback shift register, the first weight generation subunit, and the first numerical comparison subunit described above.

[0109] In this embodiment of the invention, different values ​​are selected to initialize the second linear feedback shift register for each selector control unit, thereby ensuring the independence of control signals at each level.

[0110] In this embodiment of the invention, the comparison value input to the second numerical comparison subunit inside the selector control unit is configured according to the data selector connected to the output terminal of the second numerical comparison subunit. Specifically, the first input terminal of the data selector connected to the r-th second numerical comparison subunit of the i-th stage selector control unit is associated with P XOR gates. The XOR gates associated with the first input terminal of the data selector are determined by backtracking the input signal of the first input terminal. The filter coefficients corresponding to the input data of the P XOR gates are sequentially... The second input of the data selector connected to the r-th second numerical comparison subunit is associated with Q XOR gates. The XOR gates associated with the second input of the data selector are determined by backtracking the input signal at the second input. The filter coefficients corresponding to the input data of the Q XOR gates are as follows: The comparison value of the r-th second numerical comparison subunit of the i-th level selector control unit is expressed as:

[0111]

[0112] Where, λ i,r This represents the comparison value of the r-th second numerical comparison subunit input to the i-th level selector control unit, where p and q represent intermediate variables.

[0113] In this embodiment of the invention, based on the structure of the random calculation unit and the selector control unit defined above, once the filter coefficients and order are determined, the comparison value corresponding to the second numerical comparison subunit can also be determined. Therefore, the comparison value corresponding to the second numerical comparison subunit is calculated offline after the filter coefficients and order are determined, and stored inside the random calculation unit of the digital filter device, thereby eliminating the need to deploy additional calculation circuits to determine the comparison value and reducing hardware resource overhead.

[0114] Furthermore, in this embodiment of the invention, the data recovery unit is used to convert the random filtering result into binary data and output it.

[0115] refer to Figure 10 In one embodiment of the present invention, the data recovery unit includes: an adder, an n-bit register, and a subtractor;

[0116] The first input of the adder is connected to the output of the random calculation unit, the second input of the adder is connected to the output of the n-bit register, and the output of the adder is connected to the input of the n-bit register. The adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result.

[0117] The output of the n-bit register is also connected to the first input of the subtractor. The n-bit register is used to determine and output 2 based on the accumulation result. n-1 The number of bit "1"s in a clock cycle;

[0118] The second input of the subtractor is used to input 2. n-1 The output of the subtractor is connected to the input of the output buffer unit. The subtractor is used to subtract the data input to the n-bit register from 2. n-1 Subtract the two numbers to obtain and output the binary data.

[0119] Specifically, refer to Figure 10 y is the random filtering result received by the data recovery unit. i For example, the random filtering result y i By adding bit by bit using an adder, the value of 2 is determined. n The number of bit "1"s within -1 clock cycle is used as y i '. Note y i The range of values ​​for ′ is [0, 2]. n -1], based on the data x input from the input buffer unit i Actual input data of the digital filter device The transformation relationship is obtained by calculating y. i ′-2 n-1 Obtain the actual output of the digital filter device The result is then sent to the output buffer unit. The range of values ​​is [-2]. n-1 ,2 n-1 -1].

[0120] As can be seen, the random computation-based digital filter device provided in this embodiment of the invention is mainly implemented using logic gate circuits, without multipliers, and only uses one adder and one subtractor, which can significantly reduce hardware complexity and hardware resource overhead, and can be implemented on various FPGAs.

[0121] The random computation-based digital filter device provided in this invention converts binary data into a random bit stream and performs logical operations on the random bit stream to achieve equivalent arithmetic operations such as binary multiplication and addition. In the event of a single-event flip, only a small number of bits in the random bit stream flip. During the bit accumulation process in the data recovery unit, these bit flips have little impact on the final binary data recovery, thus ensuring the calculation accuracy of the digital filter in the event of bit flips and ensuring the stable execution of the overall function.

[0122] It should be noted that, in this document, relational terms such as “first” and “second” are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital filter device based on random computation, characterized in that, The digital filter device includes: The preprocessing unit is used to preprocess the input data of the digital filter device to obtain and output preprocessed data. An input buffer unit is provided, wherein the input terminal of the input buffer unit is connected to the output terminal of the preprocessing unit, and the output terminal of the input buffer unit is connected to the serial shift register group and the data conversion unit respectively. The input buffer unit is used to buffer the input data and output the buffered data sequentially at a preset time interval. The serial shift register group includes L-1 first registers connected in sequence. The input terminal of the first first register in the L-1 first registers is connected to the output terminal of the input buffer unit. The output terminals of the L-1 first registers are respectively connected to the data conversion unit. The serial shift register group is used to serially shift the input data and buffer and output the serially shifted data. L represents the number of filter tap coefficients. The data conversion unit, whose output is connected to the input of the random computation unit, is used to convert multiple parallel input data into a multi-path random bit sequence and output it. The random calculation unit has its output connected to the input of the data recovery unit. The random calculation unit is used to perform logical operations on multiple random bit sequences and multiple pre-configured filter coefficients to obtain and output random filtering results. The data recovery unit, whose output is connected to the input of the output buffer unit, is used to convert the random filtering result into binary data and output it. The output buffer unit is used to buffer and output binary data.

2. The digital filter device based on random computation according to claim 1, characterized in that, The preprocessing expression is: ； in, This indicates the obtained preprocessed data. This represents the input data of the digital filter device. Indicates input data Data bit width, input data The range of values ​​is Preprocessed data The range of values ​​is .

3. The digital filter device based on random computation according to claim 1, characterized in that, The data conversion unit includes: a first linear feedback shift register, a first weight generation subunit, and a first numerical comparison subunit; The first linear feedback shift register has n stages and is used to generate a cycle period of... The pseudo-random sequence is buffered and output, where n represents the data bit width of the input data of the digital filter device; The first weight generation subunit includes two subunits. The input terminals of the two first weight generation subunits are respectively connected to the output terminal of the first linear feedback shift register. The two first weight generation subunits respectively calculate the weights of the data input to the first linear feedback shift register and output n weights. The first numerical comparison subunit comprises L units. The first input terminals of the L first numerical comparison subunits are respectively connected to the output terminals of the input buffer unit and the output terminals of the L-1 first registers. The second input terminals of the odd-numbered bits of the L first numerical comparison subunits are connected to the output terminal of the first first weight generation subunit, and the second input terminals of the even-numbered bits of the L first numerical comparison subunits are connected to the output terminal of the second first weight generation subunit. The first numerical comparison subunit is used to perform AND logic operations on the n weights and the n data bits of the data input from the input buffer unit or the first register, and to perform OR logic operations on the n AND logic operation results to obtain and output a random bit sequence.

4. The digital filter device based on random computation according to claim 3, characterized in that, The weight calculation expression corresponding to the first weight generation sub-unit is: ； in, As variables, , Indicates the first The first weight generation subunit generates the first weight value in the first clock cycle. Each weight, Indicates the first In the first linear feedback shift register during the nth clock cycle The output data of each register Indicates to Invert, , Represents the logical AND operation.

5. The digital filter device based on random computation according to claim 4, characterized in that, The weight calculation expression corresponding to the second first weight generation sub-unit is: ； in, As variables, , Indicates the first The second clock cycle generated by the first weight generation subunit. Each weight, Indicates the first In the first linear feedback shift register during the nth clock cycle The output data of each register Indicates to Invert, , Represents the logical AND operation.

6. The digital filter device based on random computation according to claim 5, characterized in that, The first numerical comparison subunit includes: AND gates and OR gates; The AND gates comprise n gates. The first input terminals of the n AND gates are connected to the output terminal of the input buffer unit or one of the first registers. The second input terminals of the n AND gates are connected to the output terminal of the first first weight generation subunit or the second first weight generation subunit. The nth AND gate... The AND gate is used to input the first weight generation subunit. The weight is related to the data input to the input buffer unit or the first register. Perform an AND logical operation on each data bit and output the result of the AND logical operation; The OR gate comprises n-1 gates, which are cascaded in sequence. The output of the AND gate is connected to the input of the OR gate. The n-1 OR gates are used to perform OR logic operations on the n AND logic results output by the n AND gates to obtain and output a random bit sequence.

7. The digital filter device based on random computation according to claim 3 or 6, characterized in that, The random calculation unit includes: an XOR gate, a data selector, and a selector control unit; The XOR gates comprise L gates. The first input terminals of each of the L XOR gates are connected to the output terminals of the L first numerical comparison subunits. The second input terminals of each of the L XOR gates are used to input the sign bits of the L pre-configured filter coefficients in two's complement representation. The first XOR gate in each of the L XOR gates... The XOR gate is used to process the first... The random bit sequence input to the first numerical comparison subunit is compared with the first... The sign bits of each filter coefficient in its two's complement representation are subjected to an XOR logic operation to obtain and output the XOR logic operation result. The data selector includes L-1 data selectors, which are cascaded in sequence. The output of the XOR gate is connected to the input of the data selector. The L-1 data selectors are used to select one data output from the L data output by the L XOR gates according to the control signal of the selector control unit. The selector control unit includes multiple data selectors at the same level connected to the same selector control unit. The selector control unit is used to generate a control signal based on the filter coefficients corresponding to the input data of the XOR gate associated with the connected data selector and send it to the data selector.

8. The digital filter device based on random computation according to claim 7, characterized in that, The selector control unit includes: a second linear feedback shift register, a second weight generation subunit, and a second numerical comparison subunit; The number of stages in the second linear feedback shift register is Used to generate a cycle period of A pseudo-random sequence is generated, and the pseudo-random sequence is buffered and output. This indicates the data bit width of the input data of the digital filter device; The input terminal of the second weight generation subunit is connected to the output terminal of the second linear feedback shift register. The second weight generation subunit is used to calculate and generate n weights from the data input to the second linear feedback shift register. The second numerical comparison subunit includes indivual, This indicates the number of data selectors connected to the selector control unit. The first input terminals of each of the second numerical comparison subunits are respectively used to input pre-configured values. A comparison value, The second input terminals of each of the second numerical comparison subunits are respectively connected to the output terminals of the second weight generation subunit. The outputs of the second numerical comparison subunits are respectively connected to... The data selector is connected, and the second numerical comparison subunit is used to perform AND logic operations on the n data bits of the n weights and the comparison value respectively, and to perform OR logic operations on the n AND logic operation results to obtain and output a control signal. The comparison value input to the second numerical comparison subunit is determined according to the filter coefficients corresponding to the input data of the XOR gate associated with the data selector connected to the second numerical comparison subunit.

9. The digital filter device based on random computation according to claim 8, characterized in that, Setting: Number The first input terminal of the data selector connected to the second numerical comparison subunit is The aforementioned OR gates are associated. The filter coefficients corresponding to the input data of the XOR gates are as follows: , No. The second input terminal of the data selector connected to the second numerical comparison subunit is The aforementioned OR gates are associated. The filter coefficients corresponding to the input data of the XOR gates are as follows: Then enter the first The comparison value of the second numerical comparison subunit is represented as follows: ； in, Indicates the input number The first stage selector control unit The comparison value of the second numerical comparison subunit. and Indicates an intermediate variable.

10. The digital filter device based on random computation according to claim 7, characterized in that, The data recovery unit includes: an adder, an n-bit register, and a subtractor; The first input terminal of the adder is connected to the output terminal of the random calculation unit, the second input terminal of the adder is connected to the output terminal of the n-bit register, and the output terminal of the adder is connected to the input terminal of the n-bit register. The adder is used to accumulate the random filtering result output by the random calculation unit bit by bit and output the accumulated result. The output of the n-bit register is also connected to the first input of the subtractor. The n-bit register is used to determine and output based on the accumulation result. The number of "1" bits in a clock cycle; The second input terminal of the subtractor is used for input. The output of the subtractor is connected to the input of the output buffer unit, and the subtractor is used to perform a bitwise AND operation on the data input to the n-bit register. Subtract the two numbers to obtain and output the binary data.

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