Apparatus and method for pixel merging for charge domain CMOS TDI imaging

Abstract

The invention relates to an apparatus and method for pixel merging for charge domain CMOS TDI imaging. A pixel merging apparatus and method for a charge domain CMOS TDI image sensor, comprising: a row of first transfer gates coupled to a first row of a plurality of pixel registers; a plurality of merge registers coupled to the first transfer gate; a plurality of second transfer gates coupled to the plurality of merge registers; and a row of memory registers coupled to the plurality of second transfer gates.

Description

Technical Field

[0001] The present disclosure relates to the field of pixel binning for charge domain complementary metal oxide semiconductor (CMOS) time delay and integration (TDI) image sensors. Summary of the invention

[0002] In part, in one aspect, the present disclosure relates to a pixel charge merging device of a CMOS TDI image sensor, comprising a row of first transfer gates coupled to a first row of multiple pixel registers arranged in a matrix form, a plurality of merging registers coupled to the first transfer gates, a plurality of second transfer gates coupled to the plurality of merging registers, and a row of storage registers coupled to the plurality of second transfer gates.

[0003] In another aspect, the present disclosure relates to a bidirectional CMOS TDI image sensor including a plurality of pixel registers, a first merging device coupled to one end of the plurality of pixel registers, and a second merging device coupled to another end of the plurality of pixel registers.

[0004] Although the present disclosure relates to different aspects and embodiments, it should be understood that the different aspects and embodiments disclosed herein can be integrated, combined or used together as a combined system, or partially as separate components, devices and systems, as appropriate. Therefore, each embodiment disclosed herein can be incorporated into each aspect to varying degrees depending on the given implementation. These and other features taught by the applicant are set forth herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Unless otherwise indicated, the accompanying drawings illustrate various aspects of the innovations described herein. Referring to the accompanying drawings, wherein like reference numerals represent like parts throughout the several views and the specification, several embodiments of the principles of the present disclosure are illustrated by way of example and not limitation. The accompanying drawings are not drawn to scale. The present disclosure may be more fully understood by reference to the accompanying drawings, wherein:

[0006] Figure 1 is a block diagram of a conventional CMOS TDI image sensor.

[0007] Figure 2 is a block diagram of a pixel-binning CMOS TDI image sensor according to an exemplary embodiment of the present disclosure.

[0008] Figure 3 According to an exemplary embodiment of the present disclosure Figure 2 Detailed view of the image sensor.

[0009] Figure 4A-Figure 4I is a detailed operation sequence of a pixel combining apparatus for four-time combining according to an exemplary embodiment of the present disclosure.

[0010] Figure 5 is a timing diagram of the operation of the pixel merging device according to an exemplary embodiment of the present disclosure.

[0011] Figure 6 is a logic flow chart of an operating method of a pixel merging device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure is directed to pixel merging in the charge domain for CMOS TDI image sensors. Pixel merging is a technique that combines the charges collected by multiple adjacent pixels. For some imaging applications, high speed or high sensitivity is achieved through pixel merging, but the spatial resolution of the image sensor is sacrificed.

[0013] Figure 1 1 is a block diagram of a conventional CMOS TDI image sensor 100. The conventional CMOS TDI image sensor 100 includes a plurality of pixel registers 102 arranged in a matrix form and a plurality of corresponding column parallel circuits 106a and 106b. Each end of the pixel register is provided with a light shielding area 104a and 104b, respectively. The pixel register 102 transmits pixel charges along each column of the matrix in one TDI scanning direction indicated by arrow A or in another TDI scanning direction indicated by arrow A', and reads the charges out to the corresponding column parallel circuit 106a or 106b. A channel stopper 108 separates the charges between adjacent columns 102a and 102b.

[0014] This column-based structure makes it impossible to transfer charge across multiple columns across the channel blocker 108 to perform lateral merging in the charge domain (i.e., charge merging in a direction lateral to the longitudinal direction shown by arrows A or A'). Therefore, this merging operation is performed digitally in conventional CMOS TDI image sensors. However, digital merging is not a noiseless summation and is therefore inferior to charge merging in terms of signal-to-noise ratio.

[0015] Figure 2 The CMOS TDI image sensor 200 adopts pixel merging in the charge domain according to an embodiment of the present disclosure. The image sensor 200 includes a first pixel merging device 202a and a second pixel merging device 202b. The first pixel merging device 202a and the second pixel merging device 202b are respectively embedded in the first light shielding area 104a and the second light shielding area 104b of the image sensor 200.

[0016] In one general aspect of the present disclosure, the first pixel merging device 202a includes a first transmission gate 302a arranged along a row and coupled to one end (i.e., row 110) of the plurality of pixel registers 102, a first plurality of merging registers 304a coupled to the first transmission gate 302a, a plurality of second transmission gates 306 coupled to the first plurality of merging registers 304a, and a first row of a plurality of first storage registers 308a coupled to the plurality of second transmission gates 306. These configurations are Figure 3 is shown in more detail in .

[0017] In one general aspect of the present disclosure, a second pixel merging device includes a third transfer gate arranged along a row and coupled to the other end of the plurality of pixel registers 102, a second plurality of merging registers coupled to the third transfer gate, a plurality of fourth transfer gates coupled to the second plurality of merging registers, and a first row of a plurality of second storage registers coupled to the plurality of fourth transfer gates.

[0018] Figure 3 Detailed view 300 of an image sensor 200 according to an exemplary embodiment of the present disclosure, showing a plurality of pixel registers 102 and a first pixel merging device 202a for four merging operations. The first pixel merging device 202a includes a row of first transfer gates 302a (TG1) coupled between a first row 110 of the plurality of pixel registers 102 and four columns of merging registers 304a. A set of second transfer gates 306 (TG2) includes a first second transfer gate 306a (TG2-1), a second second transfer gate 306b (TG2-2), a third second transfer gate 306c (TG2-3) and a fourth second transfer gate 306d (TG2-4), which are coupled between the merging register 304a and a first row storage register 308a. The merging register 304a, which is oriented orthogonally to the plurality of pixel registers 102, does not have a channel blocker 108. This structure enables the merging register 304a to be as Figure 2 As shown by arrows B and B' in FIG. 1 , the charge is transferred laterally to the pixel register 102. In different aspects, the set of second transfer gates 306 may include more or fewer second transfer gates to perform more or fewer binning times.

[0019] Figure 4A-Figure 4I The detailed operation sequence of the pixel merging device for four-time merging according to an exemplary embodiment of the present disclosure is shown. Figure 4A as well as Figure 2 and Figure 3The first pixel merging device 202a includes a first transmission gate 302a coupled to the plurality of pixel registers 102 of the first row 110, a four-column merging register 304a coupled to the first transmission gate 302a, a group of four second transmission gates 306 coupled to the four-column merging register 304a, and a storage register 308a coupled to the group of four second transmission gates 306.

[0020] exist Figure 4A In the first stage shown, the plurality of pixel registers 102 of the first row 110 store charges (a, b, c, d) in each pixel register. The first transfer gate 302a is clocked low (indicated by the thick solid line) to store the charges in the pixel register.

[0021] exist Figure 4B In the second stage shown, the first transfer gate 302a is clocked high (indicated by the thick dashed line) and transfers the charge (a, b, c, d) from each pixel register 102 to the corresponding binning register 304a below. The first row 110 receives the next charge (e, f, g, h) in each pixel. The first transfer gate 302a is clocked low to hold the charge (e, f, g, h) in the first row 110 until Figure 4C-Figure 4I The merge operation shown is complete.

[0022] exist Figure 4C In the third stage shown, the first second transmission gate 306a is clocked high to transfer the first charge (a) stored in the first merging register above the first second transmission gate 306a to the storage register 308a below the first second transmission gate 306a. The second second transmission gate 306b, the third second transmission gate 306c, and the fourth second transmission gate 306d are clocked low to store the remaining charges (b, c, d) in the remaining merging registers 304a, respectively.

[0023] exist Figure 4D In the fourth stage shown, the merge register 304a transfers the remaining charge (b, c, d) stored in the merge register 304a horizontally one column. The merge register 304a does not have a channel blocker 108 to prevent the charge from being transferred. The second charge (b) is now in the first column merge register 304a.

[0024] exist Figure 4EIn the fifth stage shown, the first second transmission gate 306a transmits the second charge (b) to the storage register 308a. The first charge (a) and the second charge (b) are added (a+b) in the storage register 308a. The second second transmission gate 306b, the third second transmission gate 306c, and the fourth second transmission gate 306d are respectively clocked at a low level to store the remaining charges (c, d) in the remaining merge register 204b.

[0025] exist Figure 4F In the sixth stage shown, the merge register 304a transfers the remaining charge (c, d) stored in the merge register 304a horizontally one column. The third charge (c) is now in the first column merge register 304a.

[0026] exist Figure 4G In the seventh stage shown, the first second transmission gate 306a transmits the third charge (c) to the storage register 308a. The first charge (a), the second charge (b), and the third charge (c) are added (a+b+c) in the storage register 308a. The second second transmission gate 306b, the third second transmission gate 306c, and the fourth second transmission gate 306d are clocked low to store the remaining charge (d) in the merge register 304a.

[0027] exist Figure 4H In the eighth stage shown, the merge register 304a transfers the remaining charge (d) stored in the merge register 304a horizontally one column. The fourth charge (d) is now in the first column merge register 304a.

[0028] exist Fig. 4I In the ninth stage shown, the first second transmission gate 306a transmits the fourth charge (d) to the storage register 308a. The first charge (a), the second charge (b), the third charge (c) and the fourth charge (d) are added in the storage register 308a (a+b+c+d). The second second transmission gate 306b, the third second transmission gate 306c and the fourth second transmission gate 306d are clocked low. The four merge operations are now complete.

[0029] Combination Figure 4A-Figure 4I The described stages are repeated for the next row of charges (e, f, g, h), and so on.

[0030] Figure 4A-Figure 4IThe stages shown are examples of four binning. In general, for n binnings, a row of first transfer gates transfers a row of charges from multiple pixel registers to multiple binning registers. The first of every n second transfer gates transfers the charge stored in the first binning register to the storage register below the first second transfer gate, while keeping the remaining charge in the binning register. The binning register then shifts the remaining row of charges laterally by column. The process of transfer to the storage register and lateral shifting is repeated a total of n-1 times, thereby summing the charges of n columns.

[0031] When merging is disabled, only the first phases (310a, 310b, 310c, 310d and 310e) of the merging registers between adjacent columns of merging registers are clocked at a low level, and a row of signal charges from a plurality of pixel registers is transmitted through a row of first transfer gates through a plurality of merging registers, and then transmitted to a row of storage registers through a plurality of second transfer gates.

[0032] Figure 5 FIG. 5 is a timing diagram 500 of n-times merging operation of a pixel merging device according to an exemplary embodiment of the present disclosure. Referring now to FIG. Figure 5 as well as Figure 2 , Figure 3 and Figure 4A-Figure 4I , a row of first transfer gates (TG1) have a timing waveform 530. When the first transfer gate (TG1) is clocked high, a row of charges stored in a plurality of pixel registers of the first row is transferred to a plurality of binning registers. Then, the first transfer gate (TG1) is clocked low to hold the next row of charges in the plurality of pixel registers of the first row.

[0033] Continue to refer Figure 5 as well as Figure 2 , Figure 3 and Figure 4A-Figure 4I , the first second transfer gate (TG2-1) has a timing waveform 532. The remaining second transfer gates (TG2-2, TG2-3, ..., TG2-n) have a timing waveform 534. After a row of charges is transferred to a plurality of merging registers, the first second transfer gate (TG2-1) is clocked high to transfer the first charges from the first merging register to the following storage register, while the remaining second transfer gates (TG2-2, TG2-3, ..., TG2-n) are clocked low.

[0034] After the charge in the merged column above the first second transfer gate (TG2-1) is transferred to the storage register, the first second transfer gate (TG2-1) is clocked low. The merge register transfers the remaining charge laterally by one column. The transfer of charge to the storage register and the transfer of the remaining charge laterally are repeated n times. Subsequently, the whole process is repeated for the next multiple charges.

[0035] Figure 6 600 is a logic flow diagram of a method of operation of a pixel merging device according to an exemplary embodiment of the present disclosure. Figure 6 as well as Figure 2-Figure 5 According to the method 600 of operating a pixel merging device, a row of first transfer gates transfers 602 a row of charges from a plurality of pixel registers to a plurality of merging registers. Subsequently, according to the method 600 of operating a pixel merging device, one of every N second transfer gates transfers 604 only the first charge from the merging register coupled to the second transfer gate to the storage register coupled to the second transfer gate, while retaining the remaining charges in the remaining merging registers. According to the method 600 of operating a pixel merging device, the first charge is stored 606 in the storage register, and the remaining charges in the merging register are shifted 608 by column. According to the method 600 of operating a pixel merging device, the second transfer gate transfers 610 only the second charge from the merging register coupled to the second transfer gate to the storage register coupled to the second transfer gate, while retaining the remaining charges in the remaining merging registers. The first charge and the second charge are added 612 to generate a sum of the charges. According to the method 600 of operating a pixel merging device, the final transfer 610 and addition 612 are repeated 614 until n mergings are achieved.

[0036] In one aspect, according to the method 600 of operating a pixel merging device, a row of first transfer gates is coupled to first terminals of a plurality of pixel registers, and another row of first transfer gates is coupled to second terminals of a plurality of pixel registers. The method 600 of operating a pixel merging device is performed using one of the two rows of first transfer gates for bidirectional operation in response to the direction of TDI scanning.

[0037] Having described several aspects and embodiments of the technology of the present application, it should be understood that a person of ordinary skill in the art will readily conceive of various changes, modifications and improvements. Such changes, modifications and improvements are intended to fall within the scope of the technology described in the present application. Therefore, it should be understood that the foregoing embodiments are presented only by way of example, and within the scope of the appended claims and their equivalents, the invention embodiments may be practiced in a manner different from that specifically described. In addition, if two or more features, systems, articles, materials and / or methods described herein do not contradict each other, any combination of these features, systems, articles, materials and / or methods is included within the scope of the present disclosure.

[0038] In addition, as described, some aspects may be embodied as one or more methods. The actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed in which the actions are performed in an order different from the order shown, which may include performing some actions simultaneously, even though shown as sequential actions in an illustrative embodiment.

[0039] In the claims and the foregoing specification, all transitional phrases, such as "including," "comprising," "carrying," "having," "containing," "involving," "holding," "consisting of," etc., shall be understood as open-ended, i.e., meaning including but not limited to. The transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively.

Claims

1. A pixel merging device, comprising: a row of first transmission gates coupled to a first row of a plurality of pixel registers; a plurality of merging registers coupled to the first transmission gate; a plurality of second transmission gates coupled to the plurality of merging registers; as well as A row of storage registers is coupled to the plurality of second transmission gates.

2. The pixel merging device according to claim 1, wherein: The binning register is orthogonal to the pixel register.

3. The pixel merging device according to claim 1, wherein: A channel blocker provided between adjacent pixel registers among the plurality of pixel registers does not exist in the merging register.

4. An image sensor, comprising: A plurality of pixel registers arranged in a matrix form; A first merging device coupled to one end of the plurality of pixel registers; as well as The second merging device is coupled to the other end of the plurality of pixel registers.

5. The image sensor according to claim 4, wherein: The first merging device and the second merging device are located in a light shielding area of ​​the image sensor.

6. The image sensor according to claim 4, wherein: The image sensor is a charge domain CMOS TDI image sensor, TDI refers to time delay and integration.

7. A method for pixel merging, comprising: Transferring a row of charges from a plurality of pixel registers to a plurality of binning registers through a row of first transfer gates, wherein binning is for n pixel columns; transferring only the first charge from the merging register coupled to the second transfer gate to the storage register coupled to the second transfer gate through one of every n second transfer gates among the plurality of second transfer gates, while keeping the remaining charge in the remaining merging registers; storing the first charge in the storage register; Shifting the remaining charge in the merge register by column; transferring only the second charge from the merging register coupled to the second transfer gate to the storage register coupled to the second transfer gate through the second transfer gate, while keeping the remaining charge in the remaining merging registers; adding the first charge and the second charge to generate a sum of charges; as well as The transmission and the addition are repeated until n mergings are achieved.

8. The method according to claim 7, further comprising prohibiting merging by: transferring a row of signal charges from the plurality of pixel registers to the plurality of binning registers through a row of first transfer gates; and A row of charges is transferred from the plurality of merging registers to a row of storage registers through the plurality of second transfer gates.

9. The method according to claim 7, wherein: A row of first transmission gates is coupled to the first terminals of the plurality of pixel registers; Another row of first transmission gates is coupled to the second terminals of the plurality of pixel registers; as well as The method is performed for bidirectional operation using one of the first transmission gates in one row or the first transmission gates in another row in response to a direction of TDI scanning.

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