A semiconductor device and a manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor structure, the semiconductor structure comprising a substrate, a plurality of active regions arranged separately in the substrate, a plurality of openings exposing part of the active regions, and a protective layer covering the surface of the substrate between the openings; forming a semiconductor layer in the openings, the surface of the semiconductor layer not being lower than the surface of the protective layer; forming a first dielectric layer covering the semiconductor layer; etching the first dielectric layer and the semiconductor layer in sequence to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structure comprises the semiconductor layer and the first dielectric layer on the semiconductor layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development and advancement of technology, semiconductor devices are continuously moving towards miniaturization and high integration. Dynamic random access memory (DRAM), as an important semiconductor device, is used in various electronic devices due to its fast read and write speeds. DRAM consists of multiple memory cells, each of which typically includes a transistor and a capacitor. Data stored in the capacitor is read or written via the transistor.

[0003] However, there are still many problems that need to be solved in the manufacturing process of semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A semiconductor structure is provided, comprising a substrate, a plurality of active regions disposed discretely within the substrate, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings;

[0008] forming a semiconductor layer in the opening, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer;

[0009] forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer;

[0010] The first dielectric layer and the semiconductor layer are sequentially etched to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structures include the semiconductor layer and a first dielectric layer located on the semiconductor layer.

[0011] In some embodiments, after sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate, the manufacturing method further includes:

[0012] forming an isolation layer, wherein the isolation layer fills the opening;

[0013] A second dielectric layer is formed, where the second dielectric layer covers the sidewalls of the initial bit line structure and covers the isolation layer and the protection layer.

[0014] In some embodiments, forming the isolation layer includes:

[0015] forming an isolation material layer covering the sidewalls and top of the initial bit line structure and filling the opening;

[0016] The isolation material layer covering the top and a portion of the sidewall of the initial bit line structure is removed by etching to form an isolation layer; wherein the surface of the isolation layer is substantially flush with the surface of the protection layer.

[0017] In some embodiments, the etching removes the isolation material layer covering the top and a portion of the sidewall of the initial bit line structure, and the etching liquid includes phosphoric acid.

[0018] In some embodiments, forming the second dielectric layer includes:

[0019] forming a second dielectric material layer covering the sidewalls and top of the initial bit line structure and covering the isolation layer and the protection layer;

[0020] The second dielectric material layer is planarized to form a second dielectric layer; wherein a surface of the second dielectric layer is substantially flush with a surface of the first dielectric layer.

[0021] In some embodiments, after forming the second dielectric layer, the manufacturing method further includes:

[0022] Etching back and removing the first dielectric layer of the initial bit line structure to expose the semiconductor layer of the initial bit line structure;

[0023] Etching back to remove a portion of the semiconductor layer of the initial bit line structure to form a first bit line groove; wherein the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer, and the bit line contact layer contacts the active area; a surface of the bit line contact layer exposed at the bottom of the first bit line groove is substantially flush with a surface of the protective layer;

[0024] A bit line barrier layer and a bit line conductive layer are sequentially formed in the first bit line groove.

[0025] In some embodiments, the etching back to remove the first dielectric layer of the initial bit line structure comprises an etching gas comprising at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3;

[0026] In the etching back process of removing a portion of the semiconductor layer of the initial bit line structure, the etching gas includes at least one of the following: hydrogen bromide HBr and chlorine Cl2.

[0027] In some embodiments, the step of sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove includes:

[0028] forming a bit line blocking layer in the first bit line groove;

[0029] forming a bit line conductive material layer in the first bit line groove;

[0030] The bit line conductive material layer is planarized to form a bit line conductive layer; wherein a surface of the bit line conductive layer is substantially flush with a surface of the second dielectric layer.

[0031] In some embodiments, after sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove, the manufacturing method further includes:

[0032] forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the bit line conductive layer;

[0033] Etching and removing a portion of the third dielectric layer to form a second bit line groove; wherein the bottom of the second bit line groove exposes the bit line conductive layer;

[0034] A bit line insulating layer is formed in the second bit line groove.

[0035] In some embodiments, when etching to remove a portion of the third dielectric layer, the etching gas includes oxygen O2 and hexafluorobutadiene C4F6 and / or octafluorocyclobutane C4F8.

[0036] In some embodiments, forming a bit line insulating layer in the second bit line groove includes:

[0037] forming a bit line insulating material layer in the second bit line groove;

[0038] The bit line insulation layer material layer is planarized to form a bit line insulation layer; wherein the surface of the bit line insulation layer is substantially flush with the surface of the third dielectric layer.

[0039] In some embodiments, after forming the bit line insulating layer in the second bit line groove, the manufacturing method further includes:

[0040] The third dielectric layer and the second dielectric layer are etched away to form a plurality of bit line structures extending in a direction parallel to the substrate; wherein the bit line structures include a bit line contact layer, a bit line barrier layer, a bit line conductive layer and a bit line insulating layer stacked in sequence.

[0041] In some embodiments, in the etching process for removing the third dielectric layer and the second dielectric layer, the etching liquid includes hydrofluoric acid.

[0042] In some embodiments, a height of the first dielectric layer in a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer in a direction perpendicular to the substrate.

[0043] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method as described in the above technical solution.

[0044] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. In the embodiments of the present disclosure, a first dielectric layer and a semiconductor layer are sequentially etched to form an initial bitline structure; in subsequent processes, a bitline barrier layer, a bitline conductive layer, and a bitline insulating layer are sequentially formed. Compared to sequentially etching the bitline insulating layer, the bitline conductive layer, the bitline barrier layer, and the bitline contact layer to form the bitline structure, etching only the first dielectric layer and the semiconductor layer has a smaller etching height, which can effectively reduce stress problems caused by excessive etching height, thereby effectively alleviating the problem of bitline structure swing caused by excessive stress, and further forming storage node contact holes of uniform size between the bitline structures, thereby improving the electrical performance of the semiconductor device and increasing the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figures 1A-1G is a schematic diagram of a cross-sectional structure of an exemplary semiconductor device during the manufacturing process;

[0046] Figure 2 is a schematic diagram of a top view of a semiconductor device according to an example;

[0047] Figures 3A-3G is a schematic cross-sectional structural diagram of another example of a semiconductor device during the manufacturing process;

[0048] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0049] Figures 5A-5K A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0051] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] For a thorough understanding of the present disclosure, reference will be made to the following detailed description, in conjunction with the accompanying drawings, in which:

[0057] Dynamic random access memory includes a plurality of memory cells, each memory cell generally includes a transistor and a capacitor, the gate of the transistor is connected with a word line, the drain of the transistor is connected with a bit line, the source of the transistor is connected with a first electrode plate of the capacitor, and the second electrode plate of the capacitor is connected with a common terminal. The transistor is controlled to be turned on or turned off by applying a voltage on the word line, and then data stored in the capacitor is read through the bit line or data is written into the capacitor through the bit line.

[0058] Here, the directions possibly involved in the embodiments of the present disclosure are defined. The X direction and the Y direction parallel to the substrate are defined, the X direction can be the direction in which the word line structure extends, and the Y direction can be the direction in which the bit line structure extends, the X direction and the Y direction can be perpendicular to each other. The direction perpendicular to the substrate is defined as the Z direction, and the X direction, the Y direction and the Z direction can be perpendicular to each other in pairs.

[0059] Reference Figures 1A-1G , Figures 1A-1G A cross-sectional structure schematic diagram of a semiconductor device in a manufacturing process is shown. Figures 1A-1G An XZ cross-sectional structure schematic diagram of a semiconductor device is shown, and the manufacturing process of the semiconductor device provided by an example will be described in detail below. Figures 1A-1G

[0060] Figure 1A The semiconductor structure 101 shown includes: a substrate 102, a plurality of active regions 103 arranged separately in the substrate 102, an isolation structure 104 between adjacent active regions 103, a plurality of openings 105 exposing part of the active regions 103, and a protective layer 106 covering the surface of the substrate 102 between the openings 105; wherein the protective layer 106 includes a first protective sub-layer 107 and a second protective sub-layer 108.

[0061] ​The semiconductor structure 101 further comprises a semiconductor layer 109, for example polysilicon, filling the opening 105 and covering the surface of the protective layer 106; a bit line barrier material layer 110, for example titanium nitride, covering the semiconductor layer 109; a bit line conductive material layer 111, for example tungsten, covering the bit line barrier material layer 110; and a bit line insulating material layer 112, for example silicon nitride, covering the bit line conductive material layer 111.

[0062] As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1A As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1B As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1B As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113.

[0063] As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113.

[0064] As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1B As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1C As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1C As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113.

[0065] As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113.

[0066] As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1C As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1D As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. Figure 1D As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113. As shown in Figs. 1 1 and 12, the bit line insulating material layer 112 is etched along a direction perpendicular to the substrate 102 to form a bit line insulating layer 113.

[0067] Of course, a portion of the semiconductor layer 109 is also etched during the etching process of the bitline blocking material layer 110. Due to the different etching selectivities between the bitline blocking material layer 110 and the semiconductor layer 109, the sidewalls of the etched portion of the semiconductor layer 109 are not perpendicular to the surface of the substrate 102. More specifically, the sidewalls of the etched portion of the semiconductor layer 109 exhibit an inclined morphology, being narrow at the top and wide at the bottom.

[0068] like Figure 1D and Figure 1E As shown, the semiconductor layer 109 is etched in a direction perpendicular to the substrate 102 to form a bit line contact layer 116 . Figure 1E The bit line structure 123 is shown to include a first bit line structure 117 (eg, Figure 1E The second bit line structure 118 (shown in the dashed box) Figure 1E (as shown in the dotted line box), the first bitline structure 117 sequentially includes a bitline contact layer 116, a bitline barrier layer 115, a bitline conductive layer 114, and a bitline insulating layer 113. The bitline contact layer 116 of the first bitline structure 117 is in direct contact with the active area 103 exposed by the opening 105. The second bitline structure 118 sequentially includes a bitline contact layer 116, a bitline barrier layer 115, a bitline conductive layer 114, and a bitline insulating layer 113. The bitline contact layer 116 of the second bitline structure 118 is in direct contact with the protective layer 106 on the surface of the substrate 102 between the openings 105. Herein, the first bitline structure 117 may also be referred to as a self-bitline (selfBL), and the second bitline structure 118 may also be referred to as a passing bitline (passing BL). Figure 1E In the schematic cross-sectional structure diagram, the height of the bit line contact layer 116 of the first bit line structure 117 in the direction perpendicular to the substrate 102 is greater than the height of the bit line contact layer 116 of the second bit line structure 118 in the direction perpendicular to the substrate 102 .

[0069] because Figure 1E In the schematic cross-sectional structure diagram, both the first bit line structure 117 and the second bit line structure 118 include a bit line contact layer 116. Therefore, the sidewalls of the bit line barrier layer 115 of the first bit line structure 117 and the second bit line structure 118 formed by etching are substantially perpendicular to the surface of the substrate 102. Furthermore, due to a relatively high etch selectivity for the bit line contact layer 116 and the protective layer 106, for example, a relatively high etch selectivity for polysilicon and silicon nitride, the sidewalls of the bit line contact layer 116 of the second bit line structure 118 formed by etching are substantially perpendicular to the surface of the substrate 102. The process of etching the bit line contact layer 116 will substantially not damage the protective layer 106, and will not damage the active area 103 located below the protective layer 106.

[0070] refer to Figure 2 , Figure 2Schematic diagram of a top view of an exemplary semiconductor device. Figure 2 The word line structure 124 and the bit line structure 123 are shown as being perpendicular to each other and parallel to the substrate. For example, the word line structure 124 may extend along the X direction, and the bit line structure 123 may extend along the Y direction. The bit line structure 123 may include a first bit line structure 117 and a second bit line structure 118 . Figure 1E Can be considered as Figure 2 Schematic diagram of the cross-sectional structure in the AA direction.

[0071] It should be noted that the bitline structure 123 has a relatively small dimension along the X-direction, for example, 12 nm, and a large aspect ratio. Specifically, the ratio between the dimension of the bitline structure 123 along the Z-direction and the dimension of the bitline structure 123 along the X-direction is relatively large, for example, approximately 10:1. Furthermore, the bitline insulation layer 113 of the bitline structure 123 has a relatively high height perpendicular to the substrate 102, for example, approximately 85 nm. This results in significant stress during the etching process, which can easily cause wiggling. In other words, the bitline structure 123 cannot extend strictly along the Y-direction.

[0072] like Figure 1F As shown, a first capping layer 119, a second capping layer 120, and a third capping layer 121 are sequentially formed; wherein the first capping layer 119 covers the sidewalls and tops of the first bit line structure 117 and the second bit line structure 118, and covers the sidewalls and bottom of the opening 105. The material of the first capping layer 119 can be, for example, silicon nitride, the material of the second capping layer 120 can be, for example, silicon oxide, and the material of the third capping layer 121 can be, for example, silicon nitride.

[0073] like Figure 1G As shown, the third cover layer 121 , the second cover layer 120 , the first cover layer 119 and the protection layer 106 are sequentially etched between the adjacent first bit line structure 117 and the second bit line structure 118 until the active area 103 is exposed to form a storage node contact hole 122 .

[0074] It should be noted that the first bit line structure 117 and the second bit line structure 118 each include a bit line contact layer 116 , a bit line barrier layer 115 , a bit line conductive layer 114 and a bit line insulating layer 113 in sequence, which is not conducive to reducing the parasitic capacitance of the bit line structure 123 .

[0075] In addition, if the bit line structure 123 has a swing problem, the area of ​​the storage node contact holes 122 formed between the bit line structures 123 is uneven, and the storage node contact holes 122 with smaller areas are filled with conductive material. The contact area between the conductive material in the storage node contact holes 122 and the active area 103 is smaller, resulting in a larger read and write resistance, thereby affecting the electrical performance of the transistor.

[0076] based on Figures 1A-1G The schematic cross-sectional structure diagram of a semiconductor device during the manufacturing process shows an improvement in the process of forming a bit line structure to reduce the parasitic capacitance of the bit line structure.

[0077] refer to Figures 3A-3G , Figures 3A-3G FIG1 is a schematic diagram of the cross-sectional structure of another example semiconductor device during the manufacturing process. Figures 3A-3G The XZ cross-sectional structure diagram of the semiconductor device is shown below. Figures 3A-3G , a manufacturing process of a semiconductor device provided by another example is described in detail.

[0078] Figure 3A The semiconductor structure 201 shown includes: a substrate 202, a plurality of active regions 203 located and separately arranged within the substrate 202, an isolation structure 204 located between adjacent active regions 203, a plurality of openings 205 exposing portions of the active regions 203, and a protective layer 206 covering the surface of the substrate 202 located between the openings 205; wherein the protective layer 206 includes a first protective sublayer 207 and a second protective sublayer 208.

[0079] The semiconductor structure 201 further includes: a semiconductor layer 209, such as polycrystalline silicon, the semiconductor layer 209 filling the opening 205 and the surface of the semiconductor layer 209 being substantially flush with the surface of the protective layer 206; a bit line blocking material layer 210 covering the semiconductor layer 209, such as titanium nitride; a bit line conductive material layer 211 covering the bit line blocking material layer 210, such as metal tungsten; and a bit line insulating material layer 212 covering the bit line conductive material layer 211, such as silicon nitride.

[0080] like Figure 3A and Figure 3B As shown, the bit line insulating material layer 212 is etched along a direction perpendicular to the substrate 202 to form a bit line insulating layer 213 . Figure 3B It is shown that the sidewalls of the bit line insulating layer 213 are substantially perpendicular to the surface of the substrate 202 , that is, the sidewalls of the bit line insulating layer 213 are straight.

[0081] Of course, during the etching process of the bit line insulating material layer 212, a portion of the bit line conductive material layer 211 will also be etched. Due to the different etching selectivities of the bit line insulating material layer 212 and the bit line conductive material layer 211, the sidewalls of the etched portion of the bit line conductive material layer 211 are not perpendicular to the surface of the substrate 202. More specifically, the sidewalls of the etched portion of the bit line conductive material layer 211 exhibit an inclined morphology, being narrow at the top and wide at the bottom.

[0082] like Figure 3B and Figure 3C As shown, the bit line conductive material layer 211 is etched along a direction perpendicular to the substrate 202 to form a bit line conductive layer 214 . Figure 3C It is shown that the sidewalls of the bit line conductive layer 214 are substantially perpendicular to the surface of the substrate 202 , that is, the sidewalls of the bit line conductive layer 214 are straight.

[0083] Of course, a portion of the bit line blocking material layer 210 is also etched during the etching process of the bit line conductive material layer 211. Due to the different etching selectivities between the bit line conductive material layer 211 and the bit line blocking material layer 210, the sidewalls of the etched portion of the bit line blocking material layer 210 are not perpendicular to the surface of the substrate 202. More specifically, the sidewalls of the etched portion of the bit line blocking material layer 210 exhibit an inclined morphology, being narrow at the top and wide at the bottom.

[0084] like Figure 3C and Figure 3D As shown, the bit line barrier material layer 210 is etched in a direction perpendicular to the substrate 202 to form a bit line barrier layer 215 . Figure 3D It is shown that the sidewall of the bit line barrier layer 215 is not perpendicular to the surface of the substrate 202 , that is, the sidewall of the bit line barrier layer 215 is inclined with a narrow upper portion and a wide lower portion.

[0085] Of course, a portion of the semiconductor layer 209 is also etched during the etching of the bitline blocking material layer 210. Due to the different etching selectivities between the bitline blocking material layer 210 and the semiconductor layer 209, the sidewalls of the etched portion of the semiconductor layer 209 are not perpendicular to the surface of the substrate 202. More specifically, the sidewalls of the etched portion of the semiconductor layer 209 exhibit an inclined morphology, being narrow at the top and wide at the bottom.

[0086] like Figure 3D and Figure 3E As shown, the semiconductor layer 209 is etched in a direction perpendicular to the substrate 202 to form a bit line contact layer 216 . Figure 3E The bit line structure 223 is shown to include the first bit line structure 217 (eg Figure 3E The second bit line structure 218 (shown in the dashed box) Figure 3EThe first bit line structure 217 includes a bit line contact layer 216, a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence. The bit line contact layer 216 of the first bit line structure 217 is in direct contact with the active area 203 exposed by the opening 205. The second bit line structure 218 includes a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence. The bit line barrier layer 215 of the second bit line structure 218 is in direct contact with the protective layer 206 on the surface of the substrate 202 between the opening 205.

[0087] and Figures 1A-1G Compared with the semiconductor device shown, Figures 3A-3G The first bit line structure 217 of the exemplary semiconductor device includes a bit line contact layer 216, a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence, and the second bit line structure 218 includes a bit line barrier layer 215, a bit line conductive layer 214 and a bit line insulating layer 213 in sequence. In other words, Figures 3A-3G The second bit line structure of the semiconductor device shown does not include a bit line contact layer, thereby reducing the parasitic capacitance of the bit line structure. In a specific embodiment, the material of the bit line contact layer may include polysilicon. This second bit line structure that does not include a bit line contact layer is referred to as a passing BL polyless.

[0088] However, due to Figure 3E In the schematic cross-sectional structure diagram, the first bit line structure 217 includes a bit line contact layer 216, while the second bit line structure 218 does not include a bit line contact layer. Therefore, the sidewalls of the bit line barrier layer 215 of the first bit line structure 217 formed by etching are basically perpendicular to the surface of the substrate 202, and the sidewalls of the bit line barrier layer 215 of the second bit line structure 218 formed by etching are not perpendicular to the surface of the substrate 202, that is, the sidewalls of the bit line barrier layer 215 of the second bit line structure 218 have an inclined morphology that is narrow at the top and wide at the bottom. Furthermore, because the etching selectivity of the bitline barrier layer 215 (e.g., titanium nitride) and the protective layer 206 (including a first protective sublayer and a second protective sublayer, the first protective sublayer being e.g., silicon oxide and the second protective sublayer being e.g., silicon nitride) is not high enough, for example, between titanium nitride and silicon oxide or silicon nitride, the sidewalls of the bitline barrier layer 215 of the second bitline structure 218 formed by etching are not perpendicular to the surface of the substrate 202. Furthermore, the second protective sublayer 208 and the first protective sublayer 207 located below the bitline barrier layer 215 may be etched, and the active area 203 located below the first protective sublayer 207 may even be exposed. In other words, the etching may damage the active area 203.

[0089] Furthermore, during the process of etching to form the bit line barrier layer 215 , if a process with a high lateral etching rate is used, the neck of the bit line barrier layer 215 may become narrower, or even the bit line structure 223 may collapse.

[0090] like Figure 3F As shown, a first covering layer 219 , a second covering layer 220 and a third covering layer 221 are formed in sequence; wherein the first covering layer 219 covers the sidewalls and tops of the first bit line structure 217 and the second bit line structure 218 , and covers the sidewalls and bottom of the opening 205 .

[0091] like Figure 3G As shown, the third cover layer 221 , the second cover layer 220 , the first cover layer 219 and the protection layer 206 are sequentially etched between the adjacent first bit line structure 217 and the second bit line structure 218 until the active area 203 is exposed to form a storage node contact hole 222 .

[0092] It should be noted that the bitline structure 223 has a large depth-to-width ratio, that is, the ratio between the dimension of the bitline structure 223 along the Z direction and the dimension of the bitline structure 223 along the X direction is large. Furthermore, the bitline insulation layer 213 of the bitline structure 223 has a large height perpendicular to the substrate 202. This results in high stress during the etching process of the bitline insulation layer 213, which can easily cause wobble.

[0093] Furthermore, because the sidewalls of the bitline barrier layer 215 of the second bitline structure 218 exhibit an inclined morphology, narrow at the top and wide at the bottom, and the second protective sublayer 208 and the first protective sublayer 207 below the second bitline structure 218 are also etched into an inclined morphology, narrow at the top and wide at the bottom, the active area 203 may not be fully opened during the etching process to form the storage node contact hole 222 between the adjacent first and second bitline structures 217, 218. This results in a small contact area between the conductive material filled in the storage node contact hole 222 and the active area 203, resulting in a large read / write resistance, and thus causing read / write failures.

[0094] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0095] refer to Figure 4 , Figure 4 Schematic diagram of the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0096] Step S401: providing a semiconductor structure, the semiconductor structure comprising a substrate, a plurality of active regions disposed discretely within the substrate, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings;

[0097] Step S402: forming a semiconductor layer in the opening, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer;

[0098] Step S403: forming a first dielectric layer, where the first dielectric layer covers the semiconductor layer;

[0099] Step S404: sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structure includes a semiconductor layer and a first dielectric layer located on the semiconductor layer.

[0100] refer to Figures 5A-5K , Figures 5A-5K This is a schematic diagram of the cross-sectional structure of the semiconductor device provided in the embodiment of the present disclosure during the manufacturing process. Figures 5A-5K , describing in detail the manufacturing process of the semiconductor device provided by the embodiment of the present disclosure.

[0101] In the embodiment of the present disclosure, in step S401, a semiconductor structure 308 is provided, which includes a substrate 301, a plurality of active regions 302 located in the substrate 301 and separately arranged, a plurality of openings 307 exposing portions of the active regions 302, and a protective layer 306 covering the surface of the substrate 301 located between the openings 307.

[0102] like Figure 5A As shown, the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure includes: providing a substrate 301; etching the substrate 301 to form a plurality of discretely arranged active areas 302; filling the grooves between any adjacent active areas 302; wherein the filling material located between adjacent active areas 302 forms an isolation structure 303, and the filling material covering the surface of the substrate 301 forms a first protective sublayer 304; forming a second protective sublayer 305 covering the first protective sublayer 304; wherein the first protective sublayer 304 and the second protective sublayer 305 together form a protective layer 306.

[0103] In some embodiments, the substrate may include a semiconductor substrate; the material of the semiconductor substrate specifically includes a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate may be a silicon substrate.

[0104] In some embodiments, the process of etching the substrate to form the active region may include, but is not limited to, a wet etching process, a dry etching process, or a combination thereof.

[0105] In some embodiments, the filler material may include, but is not limited to, at least one of oxides, nitrides, and oxynitrides, or a combination thereof. In a specific embodiment, the filler material may be a composite layer of silicon oxide, silicon nitride, and silicon oxide. However, this is not limiting. In actual processes, the filler material may also be other materials, which can be flexibly selected based on actual conditions and are not specifically limited here.

[0106] In some embodiments, the material of the first protective sublayer may include but is not limited to oxide, such as silicon oxide; the material of the second protective sublayer may include but is not limited to nitride, such as silicon nitride.

[0107] In some embodiments, the process for forming the first protective sublayer and the second protective sublayer may include, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. In actual processes, the first protective sublayer and the second protective sublayer may also be formed using other conventional process technologies, which may be flexibly selected based on actual conditions and are not specifically limited herein.

[0108] Continue to refer Figure 5A As shown, the second protective sublayer 305, the first protective sublayer 304, and the substrate 301 can be sequentially etched in a direction perpendicular to the substrate 301 to form an opening 307 that exposes at least a portion of the active area 302. The substrate 301, the multiple active areas 302 discretely disposed within the substrate 301, the multiple openings 307 that expose a portion of the active areas 302, and the protective layer 306 covering the surface of the substrate 301 between the openings 307 together form a semiconductor structure 308.

[0109] Here, the opening may have a cross-sectional shape that is wide at the top and narrow at the bottom, so that the bottom of the opening can be tightened around the active area exposed by the opening, thereby avoiding damage to the surrounding active area during the formation of the opening. In this way, the reliability of the semiconductor device can be improved.

[0110] In some embodiments, the number of openings may be multiple. Figure 5A Only a partial cross-sectional structural diagram of the semiconductor device is shown. The number of openings can be flexibly selected according to the actual process, and the embodiment of the present disclosure does not impose any special limitation on the number of openings.

[0111] Still refer to Figure 5A As shown, in the embodiment of the present disclosure, in step S402, a semiconductor layer 309 is formed within the opening 307. The semiconductor layer 309 at least fills the opening 307, that is, the surface of the semiconductor layer 309 is at least not lower than the surface of the protective layer 306. The surface of the semiconductor layer 309 being at least not lower than the surface of the protective layer 306 includes the following two situations: in the first situation, the surface of the semiconductor layer 309 is substantially flush with the surface of the protective layer 306; in the second situation, the surface of the semiconductor layer 309 is higher than the surface of the protective layer 306.

[0112] In some embodiments, the semiconductor layer can fill the opening, and the surface of the semiconductor layer and the surface of the protective layer are substantially flush. Here, the surface of the semiconductor layer and the surface of the protective layer are substantially flush means that the height difference between the surface of the semiconductor layer and the surface of the protective layer in the direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the surface of the semiconductor layer and the surface of the protective layer in the direction perpendicular to the substrate is zero.

[0113] In other embodiments, the semiconductor layer may fill the opening, and the semiconductor layer covers the surface of the protection layer, that is, the surface of the semiconductor layer is higher than the surface of the protection layer. Figure 5A The diagram shows that the surface of the semiconductor layer is higher than the surface of the protective layer.

[0114] In some embodiments, the material of the semiconductor layer may include, but is not limited to, polysilicon.

[0115] Still refer to Figure 5A As shown, in the embodiment of the present disclosure, in step S403 , a first dielectric layer 310 is formed, and the first dielectric layer 310 covers the semiconductor layer 309 .

[0116] In some embodiments, the material of the first dielectric layer may include but is not limited to oxide, such as silicon oxide.

[0117] like Figure 5B As shown, in the embodiment of the present disclosure, in step S404, the first dielectric layer 310 and the semiconductor layer 309 are sequentially etched along a direction perpendicular to the substrate 301 to form a plurality of initial bit line structures 311 extending in a direction parallel to the substrate 301; wherein the initial bit line structure 311 includes the semiconductor layer 309 and the first dielectric layer 310 located on the semiconductor layer 309.

[0118] It should be noted that the semiconductor layer of the initial bit line structure is in contact with the active region. Figure 5B In the schematic cross-sectional structure diagram, a portion of the semiconductor layer of the initial bit line structure is in direct contact with the active area exposed by the opening, and another portion of the semiconductor layer of the initial bit line structure is in direct contact with the protective layer on the substrate surface between the openings. Figure 5BIt is shown that the height of the initial bit line structure in direct contact with the active region in the direction perpendicular to the substrate is greater than the height of the initial bit line structure in direct contact with the protection layer in the direction perpendicular to the substrate; more specifically, Figure 5B It is shown that the height of the semiconductor layer of the initial bit line structure in direct contact with the active region in the direction perpendicular to the substrate is greater than the height of the semiconductor layer of the initial bit line structure in direct contact with the protective layer in the direction perpendicular to the substrate. Figure 5B Only a schematic diagram of the cross-sectional structure in one cross-sectional direction is illustrated. In the schematic diagrams of the cross-sectional structures in other cross-sectional directions, another part of the semiconductor layer of the initial bit line structure will also be in contact with the active area.

[0119] In other embodiments, when the surface of the semiconductor layer and the surface of the protective layer are substantially flush, the semiconductor layer of a portion of the initial bit line structure in the cross-sectional structural diagram is in direct contact with the active area exposed by the opening, and the first dielectric layer of another portion of the initial bit line structure is in direct contact with the protective layer on the substrate surface between the opening.

[0120] In the embodiment of the present disclosure, the height of the first dielectric layer covering the semiconductor layer in a direction perpendicular to the substrate is relatively small, for example, approximately 10 nm. In the process of sequentially etching the first dielectric layer and the semiconductor layer to form the initial bit line structure, the etching height is relatively small, which can effectively alleviate the stress problem caused by the excessive etching height, thereby effectively alleviating the problem of bit line structure swinging caused by excessive stress, and further, storage node contact holes of uniform size can be formed between the bit line structures, thereby improving the electrical performance of the semiconductor device and enhancing the reliability of the semiconductor device.

[0121] In the embodiment of the present disclosure, after step S404, the manufacturing method further includes:

[0122] forming an isolation layer 313 , wherein the isolation layer 313 fills the opening 307 ;

[0123] A second dielectric layer 314 is formed, and the second dielectric layer 314 covers the sidewalls of the initial bit line structure 311 and covers the isolation layer 313 and the protection layer 306 .

[0124] like Figure 5C As shown, after forming the initial bit line structure 311 , the manufacturing method further includes forming an isolation material layer 312 covering the sidewalls and top of the initial bit line structure 311 and filling the opening 307 ; at this time, the isolation material layer 312 also covers the protective layer 306 on the surface of the substrate 301 between the openings 307 .

[0125] In some embodiments, the material of the isolation material layer may include but is not limited to nitride, such as silicon nitride.

[0126] In some embodiments, the process of forming the isolation material layer may include but is not limited to PVD, CVD, ALD, or any combination thereof. The embodiments of the present disclosure do not impose any particular limitation on the process of forming the isolation material layer.

[0127] like Figure 5C and Figure 5D As shown, the isolation material layer 312 covering the top and part of the sidewall of the initial bit line structure 311 is etched away to form an isolation layer 313; wherein, the isolation layer 313 still fills the opening 307, and the surface of the isolation layer 313 is substantially flush with the surface of the protective layer 306 on the surface of the substrate 301 between the opening 307.

[0128] Here, the isolation layer surface and the protective layer surface being substantially flush means that the height difference between the isolation layer surface and the protective layer surface in a direction perpendicular to the substrate meets the process error range. In a specific embodiment, the height difference between the isolation layer surface and the protective layer surface in a direction perpendicular to the substrate is zero. Figure 5D In the schematic cross-sectional structure diagram, the exposed sidewalls of the initial bit line structures have the same height along a direction perpendicular to the substrate.

[0129] In the embodiment of the present disclosure, a wet etching process may be used to etch away the isolation material layer covering the top and a portion of the sidewalls of the initial bit line structure. The etching liquid in the wet etching process may include phosphoric acid.

[0130] like Figure 5E As shown, after forming the isolation layer 313, the manufacturing method further includes forming a second dielectric material layer, where the second dielectric material layer covers the sidewalls and top of the initial bit line structure 311. That is, the second dielectric material layer covers the sidewalls of the semiconductor layer 309 and the sidewalls of the first dielectric layer 310 of the initial bit line structure 311, and the second dielectric material layer covers the top of the first dielectric layer 310 of the initial bit line structure 311; of course, the second dielectric layer material layer also covers the surface of the protection layer 306 and the surface of the isolation layer 313 between adjacent initial bit line structures 311.

[0131] In some embodiments, the material of the second dielectric material layer may include but is not limited to oxide, such as silicon oxide.

[0132] Still refer to Figure 5E As shown, the second dielectric material layer is planarized to expose the first dielectric layer 310. The remaining second dielectric material layer forms a second dielectric layer 314. The surface of the second dielectric layer 314 is substantially flush with the surface of the first dielectric layer 310. In other words, the second dielectric layer 314 covers the sidewalls of the initial bit line structures 311 and exposes the tops of the initial bit line structures 311. The second dielectric layer 314 also covers the surface of the protection layer 306 and the surface of the isolation layer 313 between adjacent initial bit line structures 311.

[0133] In some embodiments, the planarization process may include but is not limited to chemical mechanical polishing (CMP).

[0134] Here, "the second dielectric layer surface is substantially flush with the first dielectric layer surface of the initial bitline structure" means that the height difference between the second dielectric layer surface and the first dielectric layer surface in a direction perpendicular to the substrate satisfies a process tolerance. In one specific embodiment, the height difference between the second dielectric layer surface and the first dielectric layer surface in a direction perpendicular to the substrate is zero.

[0135] like Figure 5E and Figure 5F As shown, after forming the second dielectric layer 314, the manufacturing method further includes: etching back and removing the first dielectric layer 310 of the initial bit line structure 311 in a direction perpendicular to the substrate 301 to expose the semiconductor layer 309 of the initial bit line structure 311; continuing to etch back and remove a portion of the semiconductor layer 309 of the initial bit line structure 311 in a direction perpendicular to the substrate 301 to form a first bit line groove 315; wherein the remaining semiconductor layer of the initial bit line structure 311 forms a bit line contact layer 316, and the bit line contact layer 316 is in direct contact with the active area 302 exposed by the opening 307; and the surface of the bit line contact layer 316 exposed at the bottom of the first bit line groove 315 is substantially flush with the surface of the protective layer 306.

[0136] Here, an etch-back process (Etch Back) can be used to remove the first dielectric layer and part of the semiconductor layer of the initial bit line structure. Figure 5E and Figure 5F It schematically shows that for an initial bit line structure directly contacting an active area, a portion of a semiconductor layer of the initial bit line structure is removed, and the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer; Figure 5E and Figure 5F It is also shown that for the initial bit line structure in direct contact with the protection layer, all semiconductor layers of the initial bit line structure are removed, and the bottom of the first bit line groove is formed to expose the surface of the protection layer.

[0137] It should be noted that the initial bit line structure extends along the Y direction. Figure 5E and Figure 5F The diagram illustrates that the initial bit line structure in direct contact with the active area does not always remain in direct contact with the active area as it extends along the Y direction. For the same initial bit line structure extending along the Y direction, a portion of the initial bit line structure is in direct contact with the active area, while another portion of the initial bit line structure is in direct contact with the protective layer.

[0138] Here, a portion of the bottom of the first bit line groove 315 exposes the semiconductor layer, and another portion of the bottom of the first bit line groove 315 exposes the protection layer; and a sidewall of the first bit line groove 315 exposes the second dielectric layer.

[0139] In the embodiment of the present disclosure, the etching gas used to etch back and remove the first dielectric layer 310 of the initial bit line structure 311 includes at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3;

[0140] The etching gas used to etch back and remove the portion of the semiconductor layer 309 from the initial bit line structure 311 includes at least one of the following: hydrogen bromide (HBr) and chlorine (Cl 2 ).

[0141] In the embodiment of the present disclosure, etching is divided into two stages. In the first etching stage, the first dielectric layer can be etched away to expose the semiconductor layer; in the second etching stage, part of the semiconductor layer (for example, polysilicon) can be etched away, and etching is performed using hydrogen bromide and / or chlorine gas, which has a relatively high etching selectivity for polysilicon and silicon oxide.

[0142] like Figure 5G As shown, after forming the first bit line groove 315, the manufacturing method further includes: forming a bit line barrier layer 317 in the first bit line groove 315, wherein the surface of the bit line barrier layer 317 is lower than the surface of the second dielectric layer 314; forming a conductive material layer in the first bit line groove 315, at this time the conductive material layer can fill the first bit line groove 315 and cover the surface of the second dielectric layer 314 between the first bit line grooves 315; planarizing the bit line conductive material layer to expose the surface of the second dielectric layer 314, and forming the remaining bit line conductive material layer (i.e., the bit line conductive material layer located in the first bit line groove) into a bit line conductive layer 318; wherein the surface of the bit line conductive layer 318 is substantially flush with the surface of the second dielectric layer 314.

[0143] Here, "the surface of the bit line conductive layer and the surface of the second dielectric layer are substantially flush" means that the height difference between the surface of the bit line conductive layer and the surface of the second dielectric layer in a direction perpendicular to the substrate meets a process error range. In one specific embodiment, the height difference between the surface of the bit line conductive layer and the surface of the second dielectric layer in a direction perpendicular to the substrate is zero.

[0144] Here, the height of the first bit line groove along the direction perpendicular to the substrate is the sum of the heights of the bit line barrier layer and the bit line conductive layer along the direction perpendicular to the substrate; the size of the first bit line groove along the direction parallel to the substrate, the size of the bit line barrier layer along the direction parallel to the substrate, and the size of the bit line conductive layer along the direction parallel to the substrate are the same.

[0145] In some embodiments, the process of forming the bit line barrier layer and the bit line conductive material layer may include but is not limited to PVD, CVD, ALD or any combination thereof. The embodiments of the present disclosure do not specifically limit the process of forming the bit line barrier layer and the bit line conductive material layer.

[0146] In some embodiments, the planarization process may include, but is not limited to, CMP.

[0147] In some embodiments, the material of the bit line barrier layer may include but is not limited to titanium nitride; the material of the bit line conductive layer may include but is not limited to metal tungsten.

[0148] like Figure 5H As shown, after the bit line barrier layer 317 and the bit line conductive layer 318 are formed in sequence, the manufacturing method further includes: forming a third dielectric layer 319 , wherein the third dielectric layer 319 covers the second dielectric layer 314 and the bit line conductive layer 318 .

[0149] In some embodiments, the material of the third dielectric layer may include but is not limited to oxide, such as silicon oxide. In a specific embodiment, the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer may be the same.

[0150] In some embodiments, the process of forming the first dielectric layer, the second dielectric layer, and the third dielectric layer may include but is not limited to PVD, CVD, ALD, or any combination thereof. The embodiments of the present disclosure do not specifically limit the process of forming the first dielectric layer, the second dielectric layer, and the third dielectric layer.

[0151] like Figure 5I As shown, a portion of the third dielectric layer 319 is etched away in a direction perpendicular to the substrate 301 to expose the bit line conductive layer 318, thereby forming a second bit line groove 320. The sidewalls of the second bit line groove 320 expose the third dielectric layer 319, and the bottom of the second bit line groove 320 exposes the bit line conductive layer 318.

[0152] Here, the first bit line groove and the second bit line groove have the same size in a direction parallel to the substrate, and their orthographic projections on the substrate coincide with each other.

[0153] In the embodiment of the present disclosure, a dry etching process may be used to etch away a portion of the third dielectric layer 319 , wherein the etching gas in the dry etching process includes oxygen O 2 and hexafluorobutadiene C 4 F 6 and / or octafluorocyclobutane C 4 F 8 .

[0154] Here, in the dry etching process, O2 and C4F6; or, O2 and C4F8; or, O2, C4F6 and C4F8 can be used as etching gases.

[0155] like Figure 5JAs shown, a bit line insulation material layer is formed in the second bit line groove 320; the bit line insulation material layer is planarized to expose the surface of the third dielectric layer 319, and the remaining bit line insulation material layer (i.e., the bit line insulation material layer located in the second bit line groove) forms a bit line insulation layer 321; wherein, the surface of the bit line insulation layer 321 is substantially flush with the surface of the third dielectric layer 319.

[0156] In some embodiments, the process of forming the bit line insulating material layer may include but is not limited to PVD, CVD, ALD, or any combination thereof. The embodiments of the present disclosure do not impose any particular limitation on the process of forming the bit line insulating material layer.

[0157] In some embodiments, the planarization process includes, but is not limited to, CMP.

[0158] Here, "the surface of the bit line insulation layer and the surface of the third dielectric layer are substantially flush" means that the height difference between the surface of the bit line insulation layer and the surface of the third dielectric layer in a direction perpendicular to the substrate meets a process error range. In one specific embodiment, the height difference between the surface of the bit line insulation layer and the surface of the third dielectric layer in a direction perpendicular to the substrate is zero.

[0159] In some embodiments, the material of the bit line insulating layer may include, but is not limited to, nitride, eg, silicon nitride.

[0160] like Figure 5J and Figure 5K As shown, after forming the bit line insulating layer 321, the manufacturing method further includes: etching and removing the third dielectric layer 319 and the second dielectric layer 314 to form a plurality of bit line structures 324 extending in a direction parallel to the substrate 301; wherein the bit line structures 324 include a bit line contact layer 316, a bit line barrier layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 stacked in sequence. Figure 5K The bit line structure is shown extending along the Y direction.

[0161] Here, the third dielectric layer and the second dielectric layer are removed by etching to expose the sidewalls of the bit line insulating layer, the bit line conductive layer and the bit line barrier layer, and expose the isolation layer and the protection layer surface between adjacent bit line structures.

[0162] Figure 5K The cross-sectional structure diagram shows that the bit line structure 324 includes a first bit line structure 322 (eg Figure 5K The second bit line structure 323 (shown in the dashed box) Figure 5KAs shown in the dotted box, the first bit line structure 322 includes a bit line contact layer 316, a bit line barrier layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 in sequence, wherein the bit line contact layer 316 is in contact with the active area 302; the second bit line structure 323 includes a bit line barrier layer 317, a bit line conductive layer 318 and a bit line insulating layer 321 in sequence, wherein the bit line barrier layer 317 is in contact with the protective layer 306.

[0163] It should be noted that the bit line structure 324 includes the first bit line structure 322 and the second bit line structure 323 , which does not mean that the semiconductor device includes two types of bit line structures. Figure 5K The diagram shows that the first bit line structure 322 is in direct contact with the active area 302 exposed by the opening 307 , but does not mean that the first bit line structure 322 is in direct contact with the active area 302 all the time during the process of extending along the Y direction; Figure 5K The diagram illustrates direct contact between the second bit line structure 323 and the protective layer 306 on the surface of the substrate 301 between the opening 307. This does not mean that the second bit line structure 323 is always in direct contact with the protective layer 306 during its extension along the Y direction. In the disclosed embodiment, for the same bit line structure extending along the Y direction, a portion of the bit line structure (i.e., the first bit line structure) includes a bit line contact layer, while another portion of the bit line structure (i.e., the second bit line structure) does not include a bit line contact layer. For the same bit line structure extending along the Y direction, a portion of the bit line structure (i.e., the first bit line structure) is in direct contact with the active area, while another portion of the bit line structure (i.e., the second bit line structure) is in direct contact with the protective layer. In other words, for the same bit line structure extending along the Y direction, a portion of the bit line structure is the first bit line structure, and another portion of the bit line structure is the second bit line structure. Here, the second bit line structure does not include a bit line contact layer, which can reduce the parasitic capacitance of the bit line structure.

[0164] In the embodiment of the present disclosure, the process of forming the second bit line structure can avoid damaging the active area, so that storage node contact holes of uniform size can be formed between the bit line structures, thereby improving the electrical performance of the semiconductor device and enhancing the reliability of the semiconductor device.

[0165] In the embodiment of the present disclosure, a wet etching process may be used to etch away the third dielectric layer and the second dielectric layer. The etching liquid in the wet etching process may include hydrofluoric acid, such as dilute hydrofluoric acid (DHF).

[0166] In the embodiment of the present disclosure, a height of the first dielectric layer in a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer in a direction perpendicular to the substrate.

[0167] In the disclosed embodiment, the first dielectric layer and the semiconductor layer are sequentially etched to form an initial bitline structure; subsequently, a bitline barrier layer, a bitline conductive layer, and a bitline insulating layer are sequentially formed. Compared to sequentially etching the bitline insulating layer, the bitline conductive layer, the bitline barrier layer, and the bitline contact layer to form the bitline structure, etching only the first dielectric layer and the semiconductor layer results in a smaller etch depth, effectively reducing stress issues caused by excessive etch depths and, consequently, mitigating bitline structure swing issues caused by excessive stress.

[0168] An embodiment of the present disclosure provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method in the above technical solution.

[0169] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. In the embodiments of the present disclosure, a first dielectric layer and a semiconductor layer are sequentially etched to form an initial bitline structure; in subsequent processes, a bitline barrier layer, a bitline conductive layer, and a bitline insulating layer are sequentially formed. Compared to sequentially etching the bitline insulating layer, the bitline conductive layer, the bitline barrier layer, and the bitline contact layer to form the bitline structure, etching only the first dielectric layer and the semiconductor layer has a smaller etching height, which can effectively reduce stress problems caused by excessive etching height, thereby effectively alleviating the problem of bitline structure swing caused by excessive stress, and further forming storage node contact holes of uniform size between the bitline structures, thereby improving the electrical performance of the semiconductor device and increasing the reliability of the semiconductor device.

[0170] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0171] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A semiconductor structure is provided, comprising a substrate, a plurality of active regions disposed discretely within the substrate, a plurality of openings exposing portions of the active regions, and a protective layer covering a surface of the substrate between the openings; forming a semiconductor layer in the opening, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer; forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer; Sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate; wherein the initial bit line structures include the semiconductor layer and a first dielectric layer located on the semiconductor layer; forming an isolation layer, wherein the isolation layer fills the opening; forming a second dielectric layer, wherein the second dielectric layer covers the sidewalls of the initial bit line structure and covers the isolation layer and the protection layer; Etching back and removing the first dielectric layer of the initial bit line structure to expose the semiconductor layer of the initial bit line structure; Etching back to remove a portion of the semiconductor layer of the initial bit line structure to form a first bit line groove; wherein the remaining semiconductor layer of the initial bit line structure forms a bit line contact layer, and the bit line contact layer contacts the active area; a surface of the bit line contact layer exposed at the bottom of the first bit line groove is substantially flush with a surface of the protective layer; A bit line barrier layer and a bit line conductive layer are sequentially formed in the first bit line groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of the isolation layer comprises: forming an isolation material layer covering the sidewalls and top of the initial bit line structure and filling the opening; The isolation material layer covering the top and a portion of the sidewall of the initial bit line structure is removed by etching to form an isolation layer; wherein the surface of the isolation layer is substantially flush with the surface of the protection layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The etching removes the isolation material layer covering the top and a portion of the sidewall of the initial bit line structure, and the etching liquid includes phosphoric acid.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of the second dielectric layer includes: forming a second dielectric material layer covering the sidewalls and top of the initial bit line structure and covering the isolation layer and the protection layer; The second dielectric material layer is planarized to form a second dielectric layer; wherein a surface of the second dielectric layer is substantially flush with a surface of the first dielectric layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: In the etching back process for removing the first dielectric layer of the initial bit line structure, the etching gas comprises at least one of the following: carbon tetrafluoride CF4 and trifluoromethane CHF3; In the etching back process for removing a portion of the semiconductor layer of the initial bit line structure, the etching gas includes at least one of the following: hydrogen bromide HBr and chlorine Cl2.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove comprises: forming a bit line blocking layer in the first bit line groove; forming a bit line conductive material layer in the first bit line groove; The bit line conductive material layer is planarized to form a bit line conductive layer; wherein a surface of the bit line conductive layer is substantially flush with a surface of the second dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: After sequentially forming a bit line barrier layer and a bit line conductive layer in the first bit line groove, the manufacturing method further includes: forming a third dielectric layer, wherein the third dielectric layer covers the second dielectric layer and the bit line conductive layer; Etching and removing a portion of the third dielectric layer to form a second bit line groove; wherein the bottom of the second bit line groove exposes the bit line conductive layer; A bit line insulating layer is formed in the second bit line groove.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: In the etching process for removing a portion of the third dielectric layer, the etching gas includes oxygen O2 and hexafluorobutadiene C4F6 and / or octafluorocyclobutane C4F8.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The forming of the bit line insulating layer in the second bit line groove includes: forming a bit line insulating material layer in the second bit line groove; The bit line insulation layer material layer is planarized to form a bit line insulation layer; wherein the surface of the bit line insulation layer is substantially flush with the surface of the third dielectric layer.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the bit line insulating layer in the second bit line groove, the manufacturing method further includes: The third dielectric layer and the second dielectric layer are etched away to form a plurality of bit line structures extending in a direction parallel to the substrate; wherein the bit line structures include a bit line contact layer, a bit line barrier layer, a bit line conductive layer and a bit line insulating layer stacked in sequence.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In the etching process for removing the third dielectric layer and the second dielectric layer, the etching liquid includes hydrofluoric acid.

12. The method for manufacturing a semiconductor device according to claim 7, wherein: A height of the first dielectric layer in a direction perpendicular to the substrate is smaller than a height of the bit line insulating layer in a direction perpendicular to the substrate.

13. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 12.

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