Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: providing a substrate; depositing a first insulating layer on the substrate; depositing a gate layer on the first insulating layer; forming a first photoresist layer having a gate layer pattern on the gate layer; using the first photoresist layer as a mask, depositing a second insulating layer on the first insulating layer and on the sidewall surfaces of the gate layer, wherein the top surface of the second insulating layer is flush with the top surface of the gate layer; forming source / drain regions on a portion of the top surface of the second insulating layer; and forming a channel layer on the source / drain regions, on a portion of the second insulating layer, and on the gate layer through an annealing process, wherein the top surface of the channel layer is flush with the top surface of the source / drain regions. By forming the gate layer within the first and second insulating layers, the gate layer is buried, thereby reducing the overlap area between the gate layer and the source / drain regions, lowering the possibility of parasitic capacitance, and avoiding gate breakdown.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] MOSFET, short for Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), is a common semiconductor device consisting of a source, gate, and drain. The gate is isolated from the semiconductor layer by an oxide layer. Its working principle is to apply a voltage to the gate to change the charge carrier density in the channel, thereby controlling the flow of electrons in the channel.

[0003] However, the gate and source / drain electrodes in current transistors are prone to parasitic capacitance, which affects the high-frequency characteristics of the transistor, reduces its switching speed and response time, and affects the performance of the semiconductor device. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the performance of semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: providing a substrate; depositing a first insulating layer on the substrate; depositing a gate layer on the first insulating layer; forming a first photoresist layer having a gate layer pattern on the gate layer; using the first photoresist layer as a mask, depositing a second insulating layer on the first insulating layer and the side wall surface of the gate layer, wherein the top surface of the second insulating layer is flush with the top surface of the gate layer; forming a source / drain region on a portion of the top surface of the second insulating layer; and using an annealing process to form a channel layer on the source / drain region, on a portion of the second insulating layer, and on the gate layer, wherein the top surface of the channel layer is flush with the top surface of the source / drain region.

[0006] Optionally, the process of forming the first insulating layer and the second insulating layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 1000 angstroms per minute to 3000 angstroms per minute.

[0007] Optionally, the thickness of the first insulating layer ranges from 100 nanometers to 150 nanometers, the thickness of the second insulating layer ranges from 60 nanometers to 100 nanometers, the thickness of the gate layer ranges from 60 nanometers to 100 nanometers, and the material of the first insulating layer and the second insulating layer is silicon nitride.

[0008] Optionally, the process of forming the source / drain region is a CVD process or a PVD process.

[0009] Optionally, the thickness of the source / drain region ranges from 100 nanometers to 200 nanometers, and the material of the source / drain region is one of copper, aluminum, gold, nickel, and polysilicon.

[0010] Optionally, after the step of forming the source / drain region, the method further includes: etching a portion of the source / drain region to form an “L”-shaped source / drain region.

[0011] Optionally, the process of etching the source / drain region is a dry etching process or a wet etching process, and the parameters of the dry etching process are that the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2 and Ar, the gas flow rate of the etching gas is 100sccm to 500sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, the etching time is 30 seconds to 45 seconds, and the etching depth is 100 nanometers to 150 nanometers.

[0012] Optionally, after the step of forming the gate layer, it also includes: forming a first gate dielectric layer on the side wall surface of the gate layer; forming a first buffer layer on the side wall surface of the first gate dielectric layer, and the top surfaces of the first gate dielectric layer and the first buffer layer are flush with the top surface of the gate layer.

[0013] Optionally, after the step of forming the second insulating layer, the step further includes: forming a second gate dielectric layer on the substrate; forming a second photoresist layer on the second gate dielectric layer; using the second photoresist layer as a mask, etching the second gate dielectric layer until the surface of the second insulating layer and the surface of the first buffer layer are exposed; forming a second buffer layer on the substrate; forming a third photoresist layer on the second buffer layer; using the third photoresist layer as a mask, etching the second buffer layer until the surface of the second insulating layer is exposed.

[0014] Optionally, the material of the first gate dielectric layer and the material of the second gate dielectric layer are one or a combination of silicon oxide and silicon nitride, and the material of the first buffer layer and the second buffer layer are Al2O3.

[0015] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; a first insulating layer located on the substrate; a gate layer located on a portion of the first insulating layer; a second insulating layer located on a portion of the first insulating layer and on both sides of the gate layer, the top surface of the second insulating layer being flush with the top surface of the gate layer; a source / drain region located on the top surface of the second insulating layer; and a channel layer, the channel layer covering a portion of the source / drain region, a portion of the second insulating layer, and the gate layer.

[0016] Optionally, the thickness of the first insulating layer ranges from 100 nanometers to 150 nanometers, the thickness of the second insulating layer ranges from 60 nanometers to 100 nanometers, the thickness of the gate layer ranges from 60 nanometers to 100 nanometers, and the material of the first insulating layer and the second insulating layer is silicon nitride.

[0017] Optionally, the semiconductor structure also includes: a first gate dielectric layer, located on the sidewall surface of the gate layer; a first buffer layer, located on the sidewall surface of the first gate dielectric layer; a second gate dielectric layer, located on the top surface of the first gate dielectric layer and the top surface of the gate layer; and a second buffer layer, located on the surface of the second gate dielectric layer and the surface of the first buffer layer.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The present invention forms the gate layer on the first insulating layer and forms the second insulating layer on both sides of the gate layer, so that the first insulating layer and the second insulating layer form a "U"-shaped structure, the gate layer is located in the U-shaped opening, and the buried structure of the gate layer is realized. The source / drain region is formed on part of the second insulating layer, so that the source / drain region and the gate layer have no overlapping parts in the direction parallel to the substrate and the direction perpendicular to the substrate, thereby increasing the distance between the source / drain region and the gate layer, reducing the possibility of generating parasitic capacitance, avoiding gate breakdown, and increasing the contact area between the source / drain region and the channel layer, reducing the difficulty of the alignment process of photolithography and etching, and reducing the impact of the edge effect that may occur after annealing the channel layer.

[0020] Furthermore, by etching the source / drain region to form an "L"-shaped structure, the area of ​​the source / drain region is reduced, thereby reducing the possibility of generating parasitic capacitance and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Is a semiconductor structure is a structural diagram;

[0022] Figures 2 to 7 is a schematic diagram of a process for forming a semiconductor structure according to an embodiment of the present invention;

[0023] Figures 8 and 9 FIG. 4 is a schematic diagram of a process for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0024] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0025] Existing transistors, such as Figure 1 The transistor includes: a substrate 100; a gate 101 located on the substrate 100; a source / drain 102, the source / drain 102 being located on both sides of the gate 101, and part of the source / drain 102 and the gate 101 having an overlapping portion in a direction perpendicular to the substrate 100.

[0026] In the above scheme, the source / drain is adjacent to the gate, and part of the source / drain overlaps with the gate in a direction perpendicular to the substrate, which makes it easy for the gate and the source / drain to generate parasitic capacitance, affecting the high-frequency characteristics of the transistor, reducing its switching speed and response time, and affecting the performance of the semiconductor device.

[0027] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a gate layer is formed within a first insulating layer and a second insulating layer, so that the gate layer is a buried structure, reducing the overlapping area between the gate layer and the source / drain region, reducing the possibility of generating parasitic capacitance, and avoiding gate breakdown. The source / drain region is formed on the second insulating layer, which increases the contact area between the source / drain region and the channel layer, reduces the difficulty of the alignment process of photolithography and etching, and reduces the impact of edge effects that may occur after annealing of the channel layer.

[0028] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figures 2 to 7 It is a structural schematic diagram of another method for forming a semiconductor structure in an embodiment of the present invention.

[0030] Please refer to Figure 2 , providing a substrate 200; depositing a first insulating layer 2011 on the substrate 200; and depositing a gate material layer 2021 on the first insulating layer 2011.

[0031] In this embodiment, the substrate 200 is made of silicon.

[0032] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0033] In this embodiment, the process for forming the first insulating layer 2011 is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute.

[0034] In some embodiments of the present invention, the thickness of the first insulating layer 2011 ranges from 100 nanometers to 150 nanometers.

[0035] In some embodiments of the present invention, the material of the first insulating layer 2011 is silicon nitride.

[0036] Please refer to Figure 3 A first photoresist layer (not shown in the figure) having a gate layer 202 pattern is formed on the gate material layer 2021. The gate material layer 2021 is etched away using the first photoresist layer as a mask until the surface of the first insulating layer 2011 is exposed to form the gate layer 202.

[0037] In some embodiments of the present invention, the gate layer 202 has a thickness ranging from 60 nanometers to 100 nanometers.

[0038] In some embodiments of the present invention, the material of the gate layer 202 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, ruthenium oxide or one or more combinations thereof.

[0039] Please refer to Figure 4 , forming a first gate dielectric layer 2031 on the sidewall surface of the gate layer 202 ; and forming a first buffer layer 2032 on the sidewall surface of the first gate dielectric layer 2031 .

[0040] In this embodiment, the top surfaces of the first gate dielectric layer 2031 and the first buffer layer 2032 are flush with the top surface of the gate layer 202 .

[0041] In some embodiments of the present invention, after the step of forming the first gate dielectric layer 2031 and the first buffer layer 2032, it also includes: using the first photoresist layer as a mask, depositing a second insulating layer 2012 on the first insulating layer 2011 and the side wall surface of the gate layer 202, and the top surface of the second insulating layer 2012 is flush with the top surface of the gate layer 202.

[0042] In this embodiment, the process for forming the second insulating layer 2012 is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 1000 angstroms per minute to 2000 angstroms per minute.

[0043] In some embodiments of the present invention, the thickness of the second insulating layer 2012 ranges from 60 nanometers to 100 nanometers.

[0044] In some embodiments of the present invention, the material of the second insulating layer 2012 is silicon nitride.

[0045] The first insulating layer 2011 and the second insulating layer 2012 constitute an insulating layer 201 , and the insulating layer 201 is used to accommodate the gate layer 202 .

[0046] Please refer to Figure 5 After the step of forming the second insulating layer 2012, the method further includes: forming a second gate dielectric layer 2033 on the substrate 200; forming a second photoresist layer (not shown in the figure) on the second gate dielectric layer 2033; using the second photoresist layer as a mask, etching the second gate dielectric layer 2033 until the surface of the second insulating layer 2012 and the surface of the first buffer layer 2032 are exposed; forming a second buffer layer 2034 on the substrate 200; forming a third photoresist layer (not shown in the figure) on the second buffer layer 2034; using the third photoresist layer as a mask, etching the second buffer layer 2034 until the surface of the second insulating layer 2012 is exposed.

[0047] The first buffer layer 2032 and the second buffer layer 2034 are used to prevent gate layer leakage.

[0048] In some embodiments of the present invention, the material of the first gate dielectric layer 2031 and the material of the second gate dielectric layer 2033 are one or a combination of silicon oxide and silicon nitride, and the material of the first buffer layer 2032 and the second buffer layer 2034 are Al2O3.

[0049] Please refer to Figure 6 , forming a first source / drain region 204 on a portion of the top surface of the second insulating layer 2012 .

[0050] The first source / drain region 204 is formed by a CVD process or a PVD process.

[0051] In a specific embodiment, the deposition process of the first source / drain region 204 is to first cover the second insulating layer 2012 with a metal seed layer before using the CVD process for deposition to ensure the density between the first source / drain region 204 and the second insulating layer 2012, and then etch it into the target shape through a photolithography and etching process.

[0052] In other embodiments, the deposition process of the first source / drain region is to use a PVD process, using techniques such as thermal evaporation or electron beam evaporation to heat the silver source to its evaporation temperature, so that it evaporates and deposits on the surface of the second insulating layer 2012.

[0053] The thickness of the first source / drain region 204 ranges from 100 nanometers to 200 nanometers, and the material of the first source / drain region 204 is one of copper, aluminum, gold, nickel, and polysilicon.

[0054] Please refer to Figure 7 , an annealing process is used to form a first channel layer 205 on the first source / drain region 204, on a portion of the second insulating layer 2012 and on the gate layer 202, and the top surface of the first channel layer 205 is flush with the top surface of the first source / drain region 204.

[0055] In this embodiment, the process parameters of the annealing process are: annealing temperature is 300° C. to 600° C., time is 15 seconds to 45 seconds, and annealing atmosphere is one or more combinations of pure oxygen and ozone.

[0056] Of course, the present invention is not limited to this, and other oxidizing atmospheres in the annealing process are within the protection scope of the present invention.

[0057] In this embodiment, the thickness of the first channel layer 205 ranges from 50 nanometers to 100 nanometers, and the first channel layer 205 is made of an organic semiconductor material of pentacene having a certain ductility.

[0058] Other materials of the first channel layer 205 are within the protection scope of the present invention.

[0059] In some embodiments of the present invention, after the step of forming the first channel layer 205, it also includes: forming a passivation layer on the first source / drain region 204 and the first channel layer 205; etching the passivation layer (not shown in the figure) on the first source / drain region 204 until the surface of the first source / drain region 204 is exposed to form a first opening (not shown in the figure); and forming a first source / drain electrode in the first opening.

[0060] In the above scheme, the present invention forms the gate layer 202 on the first insulating layer 2011 and forms the second insulating layer 2012 on both sides of the gate layer 202, so that the first insulating layer 2011 and the second insulating layer 2012 form a "U"-shaped structure, and the gate layer 202 is located in the U-shaped opening to realize the buried structure of the gate layer 202, and the source / drain region is formed on part of the second insulating layer 2012, so that the source / drain region and the gate layer 202 have no overlapping parts in the direction parallel to the substrate 200 and the direction perpendicular to the substrate 200, thereby increasing the distance between the source / drain region and the gate layer 202, reducing the possibility of generating parasitic capacitance, avoiding gate breakdown, and increasing the contact area between the source / drain region and the channel layer, reducing the difficulty of the alignment process of photolithography and etching, and reducing the impact of the edge effect that may occur after annealing of the channel layer.

[0061] Figures 8 and 9 It is a structural schematic diagram of another method for forming a semiconductor structure in an embodiment of the present invention.

[0062] Please Figure 6 Based on reference Figure 8 After the step of forming the first source / drain region 204 , the method further includes: etching a portion of the first source / drain region 204 to form an “L”-shaped second source / drain region 304 .

[0063] Of course, the present invention is not limited thereto, and other shapes of the second source / drain region 304 are within the protection scope of the present invention.

[0064] In this embodiment, the process of etching the first source / drain region 204 is a dry etching process or a wet etching process. The parameters of the dry etching process are that the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2 and Ar, the gas flow rate of the etching gas is 100sccm to 500sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, the etching time is 30 seconds to 45 seconds, and the etching depth is 100 nanometers to 150 nanometers.

[0065] Please refer to Figure 9 , an annealing process is used to form a second channel layer 305 on the second source / drain region 304, on a portion of the second insulating layer 2012 and on the gate layer 202, and the top surface of the second channel layer 305 is flush with the top surface of the second source / drain region 304.

[0066] In some embodiments of the present invention, after the step of forming the second channel layer 305, it also includes: forming a passivation layer (not shown in the figure) on the second source / drain region 304 and the second channel layer 305; etching the passivation layer (not shown in the figure) on the second source / drain region 304 until the surface of the second source / drain region 304 is exposed to form a second opening (not shown in the figure); and forming a second source / drain electrode in the second opening.

[0067] In this embodiment, the thickness of the second channel layer 305 is in a range of 50 nanometers to 100 nanometers. The second channel layer 305 is made of an organic semiconductor material of pentacene having a certain ductility.

[0068] Other materials of the second channel layer 305 are within the protection scope of the present invention.

[0069] The thickness of the second channel layer 305 ranges from 100 nanometers to 150 nanometers.

[0070] In the above solution, by etching the source / drain regions to form an "L"-shaped structure, the area of ​​the source / drain regions is reduced, thereby reducing the possibility of generating parasitic capacitance and improving the performance of the semiconductor device.

[0071] Furthermore, when the second source / drain region 304 is an “L”-shaped structure, compared to when the source / drain region is rectangular, the contact area between the second source / drain region 304 and the second channel layer 305 is increased, thereby increasing the current.

[0072] Accordingly, please continue to refer to Figure 7 as well as Figure 9 The present invention provides a semiconductor structure, comprising: a substrate 200; a first insulating layer 2011, located on the substrate 200; a gate layer 202, located on a portion of the first insulating layer 2011; a second insulating layer 2012, located on a portion of the first insulating layer 2011 and on both sides of the gate layer 202, wherein the top surface of the second insulating layer 2012 is flush with the top surface of the gate layer 202; a source / drain region, located on the top surface of the second insulating layer 2012; and a channel layer, wherein the channel layer covers a portion of the source / drain region, a portion of the second insulating layer 2012, and the gate layer 202.

[0073] In this embodiment, the thickness of the first insulating layer 2011 ranges from 100 nanometers to 150 nanometers, the thickness of the second insulating layer 2012 ranges from 60 nanometers to 100 nanometers, the thickness of the gate layer 202 ranges from 60 nanometers to 100 nanometers, and the material of the first insulating layer 2011 and the second insulating layer 2012 is silicon nitride.

[0074] In this embodiment, the thickness of the source / drain region ranges from 100 nanometers to 200 nanometers, and the material of the source / drain region is copper or aluminum.

[0075] In this embodiment, the semiconductor structure also includes: a first gate dielectric layer 2031, located on the sidewall surface of the gate layer 202; a first buffer layer 2032, located on the sidewall surface of the first gate dielectric layer 20312031; a second gate dielectric layer 2033, located on the top surface of the first gate dielectric layer 20312031 and the top surface of the gate layer 202; and a second buffer layer 2034, located on the surface of the second gate dielectric layer 2033 and the surface of the first buffer layer 2032.

[0076] In some embodiments of the present invention, the material of the first gate dielectric layer 2031 and the material of the second gate dielectric layer 2033 are one or a combination of silicon oxide and silicon nitride, and the material of the first buffer layer 2032 and the second buffer layer 2034 are Al2O3.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Depositing a first insulating layer on the substrate; depositing a gate layer on the first insulating layer; forming a first photoresist layer having a gate layer pattern on the gate layer; Using the first photoresist layer as a mask, depositing a second insulating layer on the first insulating layer and the sidewall surface of the gate layer, wherein the top surface of the second insulating layer is flush with the top surface of the gate layer; forming a source / drain region on a portion of the top surface of the second insulating layer; After the step of forming the source / drain region, the method further includes: etching a portion of the source / drain region to form an "L"-shaped source / drain region; An annealing process is adopted to form a channel layer on the source / drain region, a portion of the second insulating layer, and the gate layer, wherein a top surface of the channel layer is flush with a top surface of the source / drain region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first insulating layer and the second insulating layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 1000 angstroms per minute to 3000 angstroms per minute.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first insulating layer ranges from 100 nanometers to 150 nanometers, the thickness of the second insulating layer ranges from 60 nanometers to 100 nanometers, the thickness of the gate layer ranges from 60 nanometers to 100 nanometers, and the material of the first insulating layer and the second insulating layer is silicon nitride.

4. The method for forming a semiconductor structure according to claim 1, wherein: The source / drain regions are formed by a CVD process or a PVD process.

5. The method for forming a semiconductor structure according to claim 4, wherein: The thickness of the source / drain region ranges from 100 nanometers to 200 nanometers, and the material of the source / drain region is one of copper, aluminum, gold, nickel, and polysilicon.

6. The method for forming a semiconductor structure according to claim 4, wherein: The process of etching the source / drain region is a dry etching process or a wet etching process. The parameters of the dry etching process are that the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2 and Ar, the gas flow rate of the etching gas is 100sccm to 500sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, and the etching time is 30 seconds to 45 seconds.

7. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming the gate layer, the method further includes: forming a first gate dielectric layer on the sidewall surface of the gate layer; A first buffer layer is formed on the sidewall surface of the first gate dielectric layer, and the top surfaces of the first gate dielectric layer and the first buffer layer are flush with the top surface of the gate layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: After the step of forming the second insulating layer, the method further includes: forming a second gate dielectric layer on the substrate; forming a second photoresist layer on the second gate dielectric layer; Using the second photoresist layer as a mask, etching the second gate dielectric layer until a surface of the second insulating layer and a surface of the first buffer layer are exposed; forming a second buffer layer on the substrate; forming a third photoresist layer on the second buffer layer; Using the third photoresist layer as a mask, the second buffer layer is etched until a surface of the second insulating layer is exposed.

9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first gate dielectric layer and the material of the second gate dielectric layer are one or a combination of silicon oxide and silicon nitride, and the material of the first buffer layer and the second buffer layer are Al2O3.

10. A semiconductor structure, characterized in that include: substrate; a first insulating layer, located on the substrate; a gate layer, located on a portion of the first insulating layer; a second insulating layer, located on a portion of the first insulating layer and on both sides of the gate layer, wherein a top surface of the second insulating layer is flush with a top surface of the gate layer; a source / drain region located on the top surface of the second insulating layer, wherein the source / drain region is an "L"-shaped structure; A channel layer covers a portion of the source / drain region, a portion of the second insulating layer, and the gate layer.

11. The semiconductor structure according to claim 10, wherein: The thickness of the first insulating layer ranges from 100 nanometers to 150 nanometers, the thickness of the second insulating layer ranges from 60 nanometers to 100 nanometers, the thickness of the gate layer ranges from 60 nanometers to 100 nanometers, and the material of the first insulating layer and the second insulating layer is silicon nitride.

12. The semiconductor structure according to claim 10, wherein: Also includes: A first gate dielectric layer is located on the sidewall surface of the gate layer; a first buffer layer is located on the sidewall surface of the first gate dielectric layer; a second gate dielectric layer is located on the top surface of the first gate dielectric layer and the top surface of the gate layer; and a second buffer layer is located on the surface of the second gate dielectric layer and the surface of the first buffer layer.

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