Shielded gate trench mosfet device and method of manufacturing the same

Abstract

The application provides a shield gate trench MOSFET device and a preparation method thereof, and at least comprises the following steps: forming a first trench unit and a second trench unit on a substrate with an epitaxial layer, forming a first dielectric layer and a first polysilicon in the first trench unit, forming a combined gate dielectric layer on the inner wall of the second trench unit and filling the second polysilicon, the combined gate dielectric layer is composed of an inner silicon oxide layer, a silicon nitride layer and an outer silicon oxide layer, and then forming a body region, a source region and an upper metal layer. The thickness of the inner silicon oxide layer is reduced, and the stress concentration between the silicon oxide and the polysilicon on both sides of the inner wall of the second trench unit is reduced. At the same time, the combined gate dielectric layer effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the interface of the inner wall of the trench, and reduces the risk of wafer warping. Finally, the combined gate dielectric layer has a higher dielectric constant, so that the device has a higher gate withstand voltage capacity at a low threshold voltage, improves the gate leakage and improves the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit manufacturing, and relates to a shielded gate trench MOSFET device and a preparation method thereof. BACKGROUND

[0002] Shielded gate trench MOSFET (SGT MOSFET) uses two-dimensional charge balance principle to break through the performance limit of traditional power MOSFET. Compared with traditional trench MOSFET, SGT MOSFET realizes the function of body field plate by setting a shield gate in the drift region, effectively reduces the on-resistance and improves the energy utilization efficiency of the system. In addition, the design of SGT MOSFET also considers reducing the gate-drain capacitance, thereby improving the switching performance of the device.

[0003] The left-right structure shielded gate trench MOSFET technology is an advanced power semiconductor device, which optimizes the electric field distribution by introducing a shield gate in the trench, thereby improving the on-resistance, switching speed and reliability of the device. This technology is mainly applied in the fields of medium and low voltage, such as power management, motor drive, DC / DC and AC / DC sub-system current switching, etc. However, in the manufacturing process of left-right structure shielded gate trench, especially in the manufacturing of gate trench structure, wafer warpage is a common problem. This is mainly caused by the non-uniformity of internal mechanical stress and a large amount of thermal stress during etching the trench. For example, in the preparation of shallow trench isolation structure, a trench is first etched in the shield gate dielectric layer, and then a dense gate oxide layer is formed on the surface by thermal oxidation. The gate oxide layer is mostly formed by thermal oxidation process. When the thickness of the silicon oxide is too large, the oxygen in the thermal oxidation process will continue to accumulate at the interface between the polysilicon and the silicon oxide, and the density of the silicon oxide generated in the thermal oxidation process will continue to increase, thereby causing extrusion stress on the polysilicon and the substrate on both sides of the trench in the microcosmic view, and the wafer warpage in the macroscopic view. In addition, after the polysilicon is filled in the subsequent gate trench, the oxygen will still penetrate the oxide layer and react with the polysilicon and the oxide layer in the subsequent high-temperature process in the semiconductor process, causing continuous thermal stress on the substrate and the polysilicon on both sides of the trench.

[0004] Therefore, how to provide a shielded gate trench MOSFET device and a preparation method thereof to reduce the probability of wafer warpage generated in the manufacturing process of left-right structure shielded gate trench, and improve the yield, has become an important technical problem to be solved by the person skilled in the art.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the skilled in the art. The above technical scheme cannot be considered as known to the skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the present application aims to provide a shielded gate trench MOSFET device and a preparation method thereof, which is used to solve the wafer warping problem in the manufacturing process of the left-right structure SGT-MOSFET device, thereby further improving the gate withstand voltage capability.

[0007] To achieve the above-mentioned objects and other related objects, the present application provides a preparation method of a shielded gate trench MOSFET device, which at least comprises:

[0008] providing a semiconductor substrate with an epitaxial layer, and forming a hard mask layer on the surface of the epitaxial layer;

[0009] patterning the hard mask layer and etching the epitaxial layer to form a plurality of first trench units in the epitaxial layer and remove the hard mask layer;

[0010] forming a first dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer;

[0011] forming a first polysilicon filling the first trench unit on the first dielectric layer, and removing the first dielectric layer and the first polysilicon on the surface of the epitaxial layer;

[0012] forming a second trench unit in the first dielectric layer, the second trench unit being distributed on both sides of the first polysilicon, and the second trench unit exposing the sidewall of the first polysilicon and the sidewall of the epitaxial layer;

[0013] forming a combined gate dielectric layer, the combined gate dielectric layer being composed of an inner silicon oxide layer, a silicon nitride layer and an outer silicon oxide layer; the combined gate dielectric layer covering the surface of the second trench unit, the surface of the first polysilicon, the surface of the first dielectric layer and the surface of the epitaxial layer; the inner silicon oxide layer being prepared by a thermal oxidation process; forming a second polysilicon covering the combined gate dielectric layer and filling the second trench unit;

[0014] forming a body region in the epitaxial layer at the side of the first trench unit, and forming a source region in the body region;

[0015] forming an interlayer dielectric layer on the combined gate dielectric layer, and the interlayer dielectric layer having a first connecting hole exposing the body region and a second connecting hole exposing the first polysilicon;

[0016] forming an upper metal structure filling the first connection hole and the second connection hole.

[0017] Optionally, the combined gate dielectric layer comprises a first combined gate dielectric layer and a second combined gate dielectric layer; the first combined gate dielectric layer is located near the first polysilicon sidewall, the second combined gate dielectric layer is located near the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer.

[0018] Optionally, the thickness of the inner oxidized silicon of the first combined gate dielectric layer is 1-5 nm. The thickness of the silicon nitride in the first combined gate dielectric layer is 1-5 nm. The thickness of the inner oxidized silicon of the second combined gate dielectric layer is 1-5 nm. The thickness of the silicon nitride in the second combined gate dielectric layer is 1-5 nm.

[0019] Optionally, the surface of the second polysilicon is lower than the surface of the combined gate dielectric layer.

[0020] Optionally, forming the upper metal structure comprises the following steps:

[0021] forming an interlayer dielectric layer covering the epitaxial layer;

[0022] etching a contact hole in the interlayer dielectric layer and forming an injection region, forming a first connection hole penetrating through the interlayer dielectric layer and the body region and a second connection hole penetrating through the interlayer dielectric layer and the first polysilicon;

[0023] forming a metal connection layer in the first connection hole and the second connection hole and forming a front metal layer on the surface of the interlayer dielectric layer.

[0024] Optionally, the interlayer dielectric layer comprises one or a laminated combination of a silicon oxide layer, a silicon nitride layer, and a phosphosilicate glass layer.

[0025] In addition, the present application also provides a shielded gate trench MOSFET device, which at least comprises:

[0026] a semiconductor substrate with an epitaxial layer;

[0027] a first trench unit in the epitaxial layer;

[0028] a first dielectric layer on the inner wall of the first trench unit;

[0029] a first polysilicon on the first dielectric layer and filling the first trench unit;

[0030] a second trench unit in the first dielectric layer, the second trench unit being distributed on both sides of the first polysilicon, and the second trench unit exposing the sidewall of the first polysilicon and the sidewall of the epitaxial layer;

[0031] a combined gate dielectric layer, the combined gate dielectric layer being composed of an inner oxidized silicon, a silicon nitride, and an outer oxidized silicon layer; the combined gate dielectric layer covering the inner wall of the second trench unit, the surface of the first polysilicon, and the surface of the semiconductor substrate;

[0032] a second polysilicon, covering the combined gate dielectric layer and filling the second trench unit;

[0033] a body region in the epitaxial layer on the side of the first trench unit;

[0034] a source region, the source region being in the body region;

[0035] an interlayer dielectric layer on the combined gate dielectric layer, and the interlayer dielectric layer having a first connecting hole exposing the body region and a second connecting hole exposing the first polysilicon;

[0036] an upper metal structure filling the first connecting hole and the second connecting hole. Optionally, the combined gate dielectric layer includes a first combined gate dielectric layer and a second combined gate dielectric layer; wherein the first combined gate dielectric layer is located on the side close to the sidewall of the first polysilicon, the second combined gate dielectric layer is located on the side close to the sidewall of the epitaxial layer, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer; the thickness of the inner oxidized silicon in the first combined gate dielectric layer is the thickness of the silicon nitride in the first combined gate dielectric layer is the thickness of the outer oxidized silicon in the second combined gate dielectric layer is the thickness of the silicon nitride in the second combined gate dielectric layer is Optionally, the surface of the second polysilicon is lower than the surface of the combined gate dielectric layer.

[0037] Optionally, the shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

[0038] As described above, the shielding gate trench MOSFET device and the manufacturing method thereof of the present application at least include: forming a first trench unit and a second trench unit on a substrate with an epitaxial layer, forming a first dielectric layer and a first polysilicon in the first trench unit, forming a combined gate dielectric layer on the inner wall of the second trench unit and filling a second polysilicon, the combined gate dielectric layer is composed of an inner silicon oxide, a silicon nitride and an outer silicon oxide, forming a body region and a source region and an upper metal layer on the surface of the combined gate dielectric layer and the second polysilicon. The thickness of the inner silicon oxide is reduced, which reduces the stress concentration between the inner silicon oxide and the polysilicon on both sides of the inner wall of the second trench unit; at the same time, the combined gate dielectric layer effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the interface of the inner wall of the trench; in addition, due to the integrity of the combined gate dielectric layer, the stress concentration of each position of the wafer in the subsequent semiconductor high-temperature process is effectively reduced, and the risk of wafer warping is reduced. Finally, the combined gate dielectric layer has a higher dielectric constant, so that the device has higher gate withstand voltage capability at a low threshold voltage, improves the gate leakage and improves the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 The flowchart shows the manufacturing method of the shielding gate trench MOSFET device of the present application.

[0040] Figure 2 The structure diagram shows the structure after forming a hard mask layer on the surface of the epitaxial layer of the semiconductor substrate in the present application.

[0041] Figure 3 The structure diagram shows the structure after forming a first trench unit in the epitaxial layer in the present application.

[0042] Figure 4 The structure diagram shows the structure after forming a first dielectric layer on the sidewall of the first trench unit and the surface of the epitaxial layer in the present application.

[0043] Figure 5a The structure diagram shows the structure after filling a first polysilicon in the first trench unit in the present application.

[0044] Figure 5b The structure diagram shows the structure after removing the first polysilicon and the first dielectric layer on the surface of the epitaxial layer in the present application.

[0045] Figure 6 The structure diagram shows the structure after forming a second trench unit in the first dielectric layer in the present application.

[0046] Figure 7 The structure diagram shows the structure after forming a combined gate dielectric layer in the present application.

[0047] Figure 8A partial enlarged structure diagram of the combined gate dielectric layer in the application is shown.

[0048] Figure 9 A structure diagram after forming the second polysilicon in the application is shown.

[0049] Figure 10 A structure diagram after forming the body region and the source region in the application is shown.

[0050] Figure 11a A structure diagram after forming the interlayer dielectric layer in the application is shown.

[0051] Figure 11b A structure diagram after forming the first connecting hole, the second connecting hole, the first implantation region and the second implantation region in the application is shown.

[0052] Figure 12a A structure diagram after forming the barrier layer on the sidewall of the first connecting hole and the sidewall of the second connecting hole in the application is shown.

[0053] Figure 12b A structure diagram after forming the metal connecting column in the first connecting hole and the second connecting hole in the application is shown.

[0054] Figure 12c A structure diagram after forming the front metal layer in the application is shown.

[0055] BRIEF DESCRIPTION OF DRAWINGS

[0056] 100 semiconductor substrate

[0057] 110 epitaxial layer

[0058] 120 hard mask layer

[0059] 200 first trench unit

[0060] 210 first dielectric layer

[0061] 220 first polysilicon

[0062] 300 second trench unit

[0063] 310 combined gate dielectric layer

[0064] 320 first combined gate dielectric layer

[0065] 321 first silicon oxide

[0066] 322 first silicon nitride

[0067] 323 second silicon oxide

[0068] 330 second combined gate dielectric layer

[0069] 331 third silicon oxide

[0070] 332 second silicon nitride

[0071] 333 fourth silicon oxide

[0072] 340 second polysilicon

[0073] 610 body region

[0074] 620 source region

[0075] 400 interlayer dielectric layer

[0076] 410 dielectric silicon oxide layer

[0077] 420 phosphosilicate glass layer

[0078] 510 barrier layer

[0079] 520 metal via

[0080] 530 front metal layer

[0081] 540 first connection hole

[0082] 550 second connection hole

[0083] 630 implant region

[0084] 631 second implant region

[0085] 632 first implant region DETAILED DESCRIPTION

[0086] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is to be understood that variations and modifications of the embodiments can be made based on the description set forth herein, without departing from the scope and spirit of the application. Further, it is to be understood that the application can be practiced by employing both procedures and devices employing such procedures. Such equivalent constructions and procedures are intended to be within the scope of the present application.

[0087] It is also to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments of the application will be apparent to those of skill in the art upon reviewing the above description. The scope of the application should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with their full scope of equivalents.

[0088] Embodiment One

[0089] The embodiment provides a manufacturing method of a shield gate trench MOSFET device. Figure 1 The manufacturing method of the shield gate trench MOSFET device comprises the following steps.

[0090] Firstly, step S1 is performed, referring to Figure 1 and Figure 2 , a semiconductor substrate 100 with an epitaxial layer 110 is provided, and a hard mask layer 120 is formed on the surface of the epitaxial layer 110.

[0091] Specifically, the epitaxial layer 110 can be an N++-doped silicon substrate, a germanium-silicon substrate, a silicon carbide substrate or the like. In the embodiment, the substrate 100 is an N++-doped silicon substrate, and the epitaxial layer 110 is an N-type monocrystalline silicon epitaxial layer.

[0092] Further, the structure of the hard mask layer 120 can be a single silicon oxide layer with a certain thickness, or can comprise a combination layer of silicon oxide-silicon nitride-silicon oxide stacked from bottom to top. Preferably, in the embodiment, the hard mask layer 120 adopts the combination layer of silicon oxide-silicon nitride-silicon oxide.

[0093] Then, step S2 is performed, referring to Figure 1 and Figure 3 , the hard mask layer 120 is patterned, and the epitaxial layer 110 is etched to form a plurality of first trench units 200 in the epitaxial layer 110 and remove the hard mask layer 120.

[0094] Specifically, the hard mask layer 120 is used to define the region position of the first trench unit 200 to be prepared by a photolithography process, so as to etch the required first trench unit 200. The specific implementation of the photolithography and etching process can be realized by using conventional means known by those skilled in the art, and is not specifically limited here.

[0095] Then, step S3 is performed, referring to Figure 1 and Figure 4 , a first dielectric layer 210 is formed on the inner wall of the first trench unit 200 and the surface of the epitaxial layer 110.

[0096] Specifically, the first dielectric layer 210 is usually grown on the surface of the epitaxial layer 110 and the sidewall of the first trench unit 200 by using a furnace tube and combining a CVD process to form a first dielectric layer 210 with a certain thickness. Preferably, the material of the first dielectric layer 210 in the embodiment comprises silicon oxide.

[0097] Further, the epitaxial layer 110 constitutes a drift region, and the subsequent first polysilicon 220 performs lateral depletion on the drift region through the first dielectric layer 210 to improve the withstand voltage of the shield gate MOSFET device in a reverse bias state.

[0098] Then, step S4 is performed, referring to Figure 1 and Figures 5a-5b , the first polysilicon 220 filling the first trench unit 200 is formed on the first dielectric layer 210, and the first dielectric layer 210 and the first polysilicon 220 on the surface of the epitaxial layer 110 are removed.

[0099] Specifically, the first polysilicon 220 can be first subjected to a planarization treatment to expose the surface of the first dielectric layer 210, and then the first polysilicon 220 and the first dielectric layer 210 are subjected to planarization until the surface of the epitaxial layer 110 is exposed. The planarization treatment can include mechanical grinding or CMP, which is not limited here.

[0100] Then, step S5 is performed, referring to Figure 1 and Figure 6 , the second trench unit 300 is formed in the first dielectric layer 210, the second trench unit 300 is distributed on both sides of the first polysilicon 220, and the second trench unit 300 exposes the sidewall of the first polysilicon 220 and the sidewall of the epitaxial layer 110.

[0101] Then, step S6 is performed, referring to Figure 1 and Figure 7 , a combined gate dielectric layer 310 is formed on the surface of the epitaxial layer 110, the combined gate dielectric layer 310 is composed of an inner oxide silicon, a silicon nitride and an outer oxide silicon layer; the combined gate dielectric layer 310 covers the inner wall of the second trench unit 300, the surface of the first polysilicon 220 and the surface of the epitaxial layer 110; the inner oxide silicon is prepared by a thermal oxidation process.

[0102] Specifically, in order to ensure that the sidewall and bottom of the second trench unit 300 are clean and free of pollution, the second trench unit 300 is usually formed by etching the upper layer of the first dielectric layer 210, then the metal impurities in the second trench unit 300 are removed by cleaning, and then a thermal oxidation process is performed in a high-temperature thermal oxidation environment, thereby forming high-quality inner oxide silicon to ensure the uniformity and density of the inner oxide silicon.

[0103] Further, a layer of silicon nitride is deposited on the surface of the inner oxide silicon by chemical vapor deposition. Then, a layer of outer oxide silicon is grown on the surface of the silicon nitride.

[0104] Further, referring toFigure 8 The combined gate dielectric layer 310 includes a first combined gate dielectric layer 320 and a second combined gate dielectric layer 330 located in the first trench unit 200; the first combined gate dielectric layer 320 is located close to the sidewall of the first polysilicon 220; the second combined gate dielectric layer 330 is located close to the sidewall of the epitaxial layer 110.

[0105] As an example, the inner silicon oxide in the first combined gate dielectric layer 320 is the first silicon oxide 321, and the thickness of the first silicon oxide 321 is like The silicon nitride in the first combined gate dielectric layer 320 is a first silicon nitride 322, and the thickness of the first silicon nitride 322 is like The outer silicon oxide in the first combined gate dielectric layer 320 is the second silicon oxide 323 , which is not limited here and is defined according to actual needs.

[0106] As an example, the inner silicon oxide of the second combined gate dielectric layer 330 is a third silicon oxide 331, and the thickness of the third silicon oxide 331 is like The silicon nitride of the second combined gate dielectric layer 330 is a second silicon nitride 332, and the thickness of the second silicon nitride 332 is like The outer silicon oxide in the second combined gate dielectric layer 330 is the fourth silicon oxide 333 , which is not limited here and is defined according to actual needs.

[0107] Furthermore, the first silicon oxide 321 and the third silicon oxide 331 are formed simultaneously. During the thermal oxidation process, due to the difference in polysilicon composition on the left and right sidewalls of the second trench unit 300, the thickness of the inner silicon oxide formed on both sides of the second trench unit 300 is different. The first silicon nitride 322 and the second silicon nitride 332 are formed simultaneously by chemical vapor deposition, and therefore have the same thickness. Similarly, the second silicon oxide 323 in the first combined gate dielectric layer 320 and the fourth silicon oxide 333 in the second combined gate dielectric layer 330 have the same thickness. This is not limited here and is defined based on actual needs.

[0108] In this embodiment, compared with the prior art, the inner oxidation silicon thermal oxidation process time is reduced, and the thickness of the inner oxidation silicon is reduced, thereby avoiding stress concentration between the inner oxidation silicon and the first polysilicon 220. Meanwhile, on this basis, a silicon nitride layer and an outer oxidation silicon layer are added to form a combined gate dielectric layer 310, which effectively reduces the risk of stress concentration at the interface between the inner oxidation silicon and the first polysilicon 220 of the second trench unit 300 in subsequent high-temperature processes; in addition, since the first polysilicon 220 and the surface of the semiconductor substrate 100 are both covered with a silicon oxide / silicon nitride / silicon oxide three-layer structure, the stress concentration at each position of the wafer is effectively reduced in subsequent semiconductor high-temperature processes, and the risk of wafer warping is reduced.

[0109] Then, step S7 is performed, referring to Figure 1 and Figure 9 , the second polysilicon 340 is filled in the inner wall of the combined gate dielectric layer 310 in the second trench unit 300.

[0110] Specifically, the bottom and side of the second polysilicon 340 are isolated from the first polysilicon 220 by the first combined gate dielectric layer 320; the second polysilicon 340 and the sidewall of the first trench unit 200 are isolated by the second combined gate dielectric layer 330.

[0111] Specifically, the second polysilicon 340 is subjected to a planarization process to expose the surface of the combined dielectric layer 310, and further, the second polysilicon 340 is etched so that the surface of the second polysilicon 340 is lower than the surface of the combined gate dielectric layer 310.

[0112] Further, the etching process of the second polysilicon 340 can adopt dry etching or wet etching, which will not be described here.

[0113] Then, step S8 is performed, referring to Figure 1 and Figure 10 , a body region 610 is formed in the epitaxial layer 110 on both sides of the first trench unit 200, and a source region 620 is formed in the body region 610.

[0114] Specifically, the source region 620 is located on the upper surface layer of the body region 610. The body region 610 is adjacent to the sidewall of the first trench unit 200, and the bottom surface of the body region 610 is higher than the bottom surface of the second polysilicon 340.

[0115] As an example, the body region 610 includes a P-type body region, and the method of forming the body region 610 includes ion implantation, for example, ion implantation can be used to implant P-type impurities in the epitaxial layer 110. In other examples, photolithography is used to define the implantation area as needed.

[0116] As an example, the source region 620 comprises an N+ type source region, and the method of forming the source region 620 comprises: forming a mask layer on the surface of the epitaxial layer 110, the mask layer can be selected from photoresist, forming a plurality of openings in the mask layer by exposure, development and other photolithography steps to define a plurality of ion implantation regions, and performing N-type ion implantation on the epitaxial layer 110 based on the plurality of ion implantation regions defined in the mask layer to form the source region 620 on the upper surface layer of the body region 610. Then, step S9 is performed, referring to Figures 11a-11b An interlayer dielectric layer 400 is formed on the combined gate dielectric layer 310, and the interlayer dielectric layer 400 has a first connection hole 540 exposing the body region 610 and a second connection hole 550 exposing the first polysilicon 220.

[0117] Then, step S10 is performed, referring to Figures 12a-12c An upper metal structure is formed to fill the first connection hole 540 and the second connection hole 550.

[0118] Specifically, the step of forming the upper metal structure further comprises:

[0119] S10-1, referring to Figure 12a The interlayer dielectric layer 400 is formed to cover the epitaxial layer 110.

[0120] Specifically, the interlayer dielectric layer 400 comprises one or a laminated combination of a silicon oxide layer, a silicon nitride layer, and a phosphosilicate glass layer. In this embodiment, the interlayer dielectric layer 400 comprises a laminated structure of a dielectric silicon oxide layer 410 and a phosphosilicate glass layer 420.

[0121] S10-2, referring to Figure 12b Contact hole etching is performed in the interlayer dielectric layer 400 to form an implantation region 630, and a first connection hole 540 penetrating the interlayer dielectric layer 400 and the body region 610 and a second connection hole 550 penetrating the interlayer dielectric layer 400 and the first polysilicon 220 are formed.

[0122] Further, different mask plates are used to expose photoresist, and the contact hole area is defined in the developed photoresist; different key size contact holes, including the first connection hole 540 and the second connection hole 550, are formed by dry etching through the interlayer dielectric layer 400.

[0123] Still further, ion implantation is performed in the first connection hole 540 to form a first implantation region 632, and ion implantation is performed at the bottom of the second connection hole 550 to form a second implantation region 631, and the implanted ions enter the bottom of the contact hole to a predetermined depth. As an example, the ion implantation adopts P-type ion implantation.

[0124] S10-3, referring to Figure 12c A metal connection layer is formed in the first connection hole 540 and the second connection hole 550, and a front metal layer 530 is formed on the surface of the interlayer dielectric layer 400.

[0125] Specifically, in order to ensure better metal connection of the first connection hole 540 and the second connection hole 550, the embodiment fills the contact hole with metal W and thins the metal connection column 520. In order to avoid polysilicon metallization, a barrier layer 510 is formed on the inner wall of the first connection hole 540 and the second connection hole 550 by chemical vapor deposition in the example. Preferably, the material of the barrier layer 510 includes Ti / TiN.

[0126] Further, the front metal layer 530 is formed on the surface of the interlayer dielectric layer 400 and connected with the metal connection column 520.

[0127] Further, the front metal layer 530 is connected with the source electrode through the first connection hole 540 and the source region 620, and the body region 610 is short-circuited with the source electrode. A drain region can be formed on the back of the semiconductor substrate 100, a back metal layer is formed and the drain electrode is led out through the back metal layer. In order to distinguish the gate electrode, the first polysilicon 220 is connected with the source electrode through the second connection hole 550 to form a shielding gate electrode, and the second polysilicon 340 is connected with the gate metal in other places to form a control gate electrode. Since there is a large potential difference between the shielding gate electrode and the drift region formed by the epitaxial layer 110, the first dielectric layer 210 has a relatively thick thickness. The first gate electrode, which is always connected to a low potential, acts as a constant companion, and the RESURF (Reduced Surface Field) effect of the dielectric layer is introduced. In the off state, it helps to deplete the N-type impurities of the drift region and optimizes the electric field distribution, thereby allowing the drift region to adopt a higher doping concentration while maintaining the breakdown voltage or even optimizing it, reducing the on-resistance of the device and achieving low static loss.

[0128] As an example, the present embodiment takes an N-type device as an example to provide a preparation method of a shield gate trench MOSFET device. The semiconductor epitaxial layer 110 and the source region 620 have N-type conductive type ion doping, and the body region 610 and the implanted region 630 have P-type conductive type ion doping. In some other embodiments, a preparation method of a shield gate trench MOSFET device taking a P-type device as an example can also be provided. The epitaxial layer 110 and the source region 620 have P-type conductive type ion doping, and the body region 610 and the implanted region 630 have N-type conductive type ion doping. Here, no further description is given.

[0129] The preparation method of the shielding gate trench MOSFET device provided in the embodiment reduces the thickness of the inner oxide silicon, reduces the stress concentration between the oxide silicon and the polysilicon on the two sides of the inner wall of the second trench unit 300; at the same time, the combined gate dielectric layer 310 covering the first polysilicon 220, the epitaxial layer 110 and the second trench unit 300 effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the interface of the inner wall of the trench, also reduces the stress concentration problem of each position of the wafer in the subsequent high-temperature process, and reduces the risk of wafer warping. Finally, the combined gate dielectric layer 310 has a higher dielectric constant, so that the device has a higher gate withstand voltage capability at a low threshold voltage, improves the gate leakage and improves the performance of the device.

[0130] Embodiment two

[0131] The embodiment also provides a shielding gate trench MOSFET device, which is made by the manufacturing method as described in the embodiment one or other suitable similar method. The preparation method, material and structure of the shielding gate trench MOSFET device can be referred to the embodiment one. Refer to Figure 12c , which is a structural schematic diagram of the shielding gate trench MOSFET device, wherein the shielding gate trench MOSFET device comprises:

[0132] a semiconductor substrate 100 with an epitaxial layer 110;

[0133] a first trench unit 200 in the epitaxial layer 110;

[0134] a first polysilicon 220 on the first dielectric layer 210 and filling the first trench unit 200;

[0135] a second trench unit 300 in the first dielectric layer 210, the second trench unit 300 being distributed on the two sides of the first polysilicon 220, and the second trench unit 300 exposing the sidewall of the first polysilicon 220 and the sidewall of the epitaxial layer 110;

[0136] a combined gate dielectric layer 310, which is composed of stacked inner oxide silicon, silicon nitride and outer oxide silicon; the combined gate dielectric layer 310 covers the inner wall of the second trench unit 300, the surface of the first polysilicon 220 and the surface of the epitaxial layer 110; the inner oxide silicon is prepared by a thermal oxidation process;

[0137] a second polysilicon 340 covering the combined gate dielectric layer 310 and filling the second trench unit 300;

[0138] body region 610 in the epitaxial layer 110 at the side of the first trench unit 200;

[0139] source region 620 in the body region 610;

[0140] interlayer dielectric layer 400 on the combined gate dielectric layer 310, and the interlayer dielectric layer 400 has a first connecting hole 540 exposing the body region and a second connecting hole 550 exposing the first polysilicon 220;

[0141] upper metal structure filling the first connecting hole 540 and the second connecting hole 550.

[0142] As an example, the combined gate dielectric layer 310 includes a first combined gate dielectric layer 320 and a second combined gate dielectric layer 330; the first combined gate dielectric layer 320 is between the sidewall of the first polysilicon 220 and the sidewall of the second polysilicon 340; the second combined gate dielectric layer 330 is between the sidewall of the second polysilicon 340 and the sidewall of the epitaxial layer 110.

[0143] As an example, the inner silicon oxide in the first combined gate dielectric layer 320 is a first silicon oxide 321, and the thickness of the first silicon oxide 321 is As an example, the thickness of the first silicon oxide 321 is any value within the range of As an example, the silicon nitride in the first combined gate dielectric layer 320 is a first silicon nitride 322, and the thickness of the first silicon nitride 322 is As an example, the thickness of the first silicon nitride 322 is any value within the range of As an example, the outer silicon oxide in the first combined gate dielectric layer 320 is a second silicon oxide 323, which is not limited here and is defined according to actual needs.

[0144] As an example, the inner silicon oxide in the second combined gate dielectric layer 330 is a third silicon oxide 331, and the thickness of the third silicon oxide 331 is As an example, the thickness of the third silicon oxide 331 is any value within the range of As an example, the silicon nitride in the second combined gate dielectric layer 330 is a second silicon nitride 332, and the thickness of the second silicon nitride 332 is As an example, the thickness of the second silicon nitride 332 is any value within the range of As an example, the outer silicon oxide in the second combined gate dielectric layer 330 is a fourth silicon oxide 333, which is not limited here and is defined according to actual needs.

[0145] In the structure of the shielded gate trench MOSFET device in this embodiment, the extrusion stress between the inner oxide silicon and the first polysilicon 220 in the second trench unit 300 is reduced by reducing the thickness of the inner oxide silicon. Meanwhile, on the basis of the inner oxide silicon, a silicon nitride layer and an outer oxide silicon layer are added to form the combined gate dielectric layer 310, which effectively avoids the risk of stress concentration on the interface in the trench in subsequent high-temperature processes. In addition, since the first polysilicon 220 and the surface of the semiconductor substrate 100 are both covered with a three-layer structure of oxide silicon / silicon nitride / oxide silicon, the stress concentration at each position of the wafer is effectively reduced, and the risk of wafer warping is reduced.

[0146] As an example, the surface of the formed second polysilicon 340 is lower than the surface of the combined gate dielectric layer 310. Further, the upper metal structure further includes:

[0147] A first connection hole 540 and a first implantation region 632, the first connection hole 540 penetrating through the interlayer dielectric layer 400 and the body region 610;

[0148] A second connection hole 550 and a second implantation region 631, the second connection hole 550 penetrating through the interlayer dielectric layer 400 and the first polysilicon 220;

[0149] A metal connection layer and a front metal layer 530, the metal connection layer penetrating through the first connection hole 540 and the second connection hole 550, and the front metal layer 530 covering the surface of the interlayer dielectric layer 400 and being electrically connected with the metal connection layer.

[0150] Specifically, the interlayer dielectric layer 400 includes one or a laminated combination of a silicon oxide layer, a silicon nitride layer, and a phosphosilicate glass layer. In this embodiment, the interlayer dielectric layer 400 includes a laminated structure of a dielectric silicon oxide layer 410 and a phosphosilicate glass layer 420.

[0151] Specifically, the metal connection layer includes a barrier layer 510 and a metal connection column 520, and the material of the barrier layer 510 includes Ti / TiN.

[0152] Further, the front metal layer 530 is in contact with the source electrode through the first connection hole 540 and the source region 620, and the body region 610 is short-circuited with the source electrode. A drain region can be formed on the back surface of the semiconductor substrate 100, a back metal layer is formed, and the drain electrode is led out through the back metal layer. To distinguish the gate electrode, the first polysilicon 220 is connected with the source electrode through the second connection hole 550 to form a shielded gate electrode, and the second polysilicon 340 is connected with the gate metal in other places to form a control gate electrode.

[0153] Further, the epitaxial layer 110 and the source region 620 have ion doping of a first conductive type, the body region 620 and the implanted region 630 have ion doping of a second conductive type, and the first conductive type and the second conductive type are opposite conductive types.

[0154] To sum up, the preparation method of the shield gate trench MOSFET device of the present application at least includes: forming a first trench unit and a second trench unit on a substrate with an epitaxial layer, forming a first dielectric layer and a first polysilicon in the first trench unit, forming a combined gate dielectric layer on the inner wall of the second trench unit and filling a second polysilicon, the combined gate dielectric layer is composed of an inner silicon oxide, a silicon nitride and an outer silicon oxide layer, and then forming a body region and a source region and an upper metal layer. The thickness of the inner silicon oxide is reduced, which reduces the stress concentration between the inner silicon oxide and the polysilicon on both sides of the inner wall of the second trench unit; at the same time, the combined gate dielectric layer effectively reduces the influence of the subsequent high-temperature process on the stress concentration of the inner wall interface; in addition, due to the uniform distribution of the combined gate dielectric layer, the stress concentration of each position of the wafer is improved as a whole, thereby reducing the risk of wafer warping. Finally, the combined gate dielectric layer has a higher dielectric constant, and the MOSFET device can have higher gate withstand voltage capability at a low threshold voltage, improve gate leakage and improve device performance. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0155] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a shielded gate trench MOSFET device, characterized by, The following steps are involved: Providing a semiconductor substrate having an epitaxial layer, and forming a hard mask layer on a surface of the epitaxial layer; Patterning the hard mask layer, etching the epitaxial layer, forming a plurality of first trench units in the epitaxial layer, and removing the hard mask layer; forming a first dielectric layer on the inner wall of the first trench unit and the surface of the epitaxial layer; forming a first polysilicon layer filling the first trench unit on the first dielectric layer, and removing the first dielectric layer and the first polysilicon layer located on the surface of the epitaxial layer; forming second trench units in the first dielectric layer, wherein the second trench units are distributed on both sides of the first polysilicon layer, and the second trench units expose sidewalls of the first polysilicon layer and sidewalls of the epitaxial layer; forming a composite gate dielectric layer, the composite gate dielectric layer being composed of inner silicon oxide, silicon nitride, and outer silicon oxide stacked together; the composite gate dielectric layer covering the inner wall of the second trench unit, the surface of the first polysilicon, and the surface of the epitaxial layer; the inner silicon oxide being prepared by a thermal oxidation process; forming a second polysilicon layer covering the combined gate dielectric layer and filling the second trench unit; forming a body region in the epitaxial layer on a side of the first trench unit, and forming a source region in the body region; An interlayer dielectric layer is formed on the combined gate dielectric layer, wherein the interlayer dielectric layer has a first connection hole exposing the body region and a second connection hole exposing the first polysilicon; and an upper metal structure is formed to fill the first connection hole and the second connection hole.

2. The manufacturing method of a shielded gate trench-MOSFET device according to claim 1, characterized in that: The combined gate dielectric layer includes a first combined gate dielectric layer and a second combined gate dielectric layer, wherein the first combined gate dielectric layer is located close to the first polysilicon sidewall, the second combined gate dielectric layer is located close to the epitaxial layer sidewall, and the thickness of the first combined gate dielectric layer is greater than the thickness of the second combined gate dielectric layer.

3. The manufacturing method of a shielded gate trench-MOSFET device according to claim 2, wherein: a thickness of the inner oxidized silicon in the first combined gate dielectric layer is a thickness of the silicon nitride in the first combined gate dielectric layer is a thickness of the outer oxidized silicon in the second combined gate dielectric layer is a thickness of the silicon nitride in the second combined gate dielectric layer is 4. The method of fabricating a shielded gate trench MOSFET device according to claim 1, wherein: The surface of the formed second polysilicon is lower than the surface of the combined gate dielectric layer.

5. The method of fabricating a shielded gate trench MOSFET device according to claim 1, wherein: Forming the upper metal structure includes the following steps: forming an interlayer dielectric layer covering the epitaxial layer; Etching a contact hole in the interlayer dielectric layer and forming an implantation region, forming a first connection hole penetrating the interlayer dielectric layer and the body region, and a second connection hole penetrating the interlayer dielectric layer and the first polysilicon; A metal connection layer is formed in the first connection hole and the second connection hole, and a front metal layer is formed on the surface of the interlayer dielectric layer.

6. The method of fabricating a shielded gate trench MOSFET device according to claim 5, wherein: The interlayer dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a silicon phosphate glass layer, or a stacked combination thereof.

7. A shielded gate trench MOSFET device, characterized by, include: a semiconductor substrate having an epitaxial layer; A first trench unit is located in the epitaxial layer; a first dielectric layer, located on the inner wall of the first trench unit; a first polysilicon layer located on the first dielectric layer and filling the first trench unit; a second trench unit located in the first dielectric layer, the second trench unit being distributed on both sides of the first polysilicon layer, and the second trench unit exposing a sidewall of the first polysilicon layer and a sidewall of the epitaxial layer; a combined gate dielectric layer, the combined gate dielectric layer is composed of a layer of inner oxidized silicon, a layer of silicon nitride and a layer of outer oxidized silicon, the combined gate dielectric layer covers the inner wall of the second trench unit, the surface of the first polysilicon and the surface of the epitaxial layer, the inner oxidized silicon is prepared by a thermal oxidation process; a second polysilicon, covering the combined gate dielectric layer and filling the second trench unit; a body region, located in the epitaxial layer at the side of the first trench unit; a source region, located in the body region; an interlayer dielectric layer, located on the combined gate dielectric layer, and the interlayer dielectric layer has a first connecting hole exposing the body region and a second connecting hole exposing the first polysilicon; an upper metal structure, filling the first connecting hole and the second connecting hole.

8. The shielded gate trench MOSFET device of claim 7, wherein: The combination gate dielectric layer comprises a first combination gate dielectric layer and a second combination gate dielectric layer; wherein the first combination gate dielectric layer is located near the first polysilicon sidewall, the second combination gate dielectric layer is located near the epitaxial layer sidewall, and the thickness of the first combination gate dielectric layer is greater than the thickness of the second combination gate dielectric layer; the thickness of the inner oxidized silicon in the first combination gate dielectric layer is The thickness of the inner oxidized silicon in the first combination gate dielectric layer is The thickness of the outer oxidized silicon of the second combination gate dielectric layer is The thickness of the outer oxidized silicon in the second combination gate dielectric layer is 9. The shielded gate trench MOSFET device of claim 7, wherein: The surface of the second polysilicon formed is lower than the surface of the combined gate dielectric layer.

10. The shielded gate trench MOSFET device of claim 7, wherein: The shielded gate trench MOSFET device includes a P-type MOSFET device or an N-type MOSFET device.

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