Silicon-controlled electrostatic protection device with embedded PNP and GGNMOS and manufacturing method of silicon-controlled electrostatic protection device

Abstract

The invention discloses a PNP and GGNMOS embedded silicon controlled electrostatic protection device and a manufacturing method thereof, a unidirectional silicon controlled structure is selected, a floating N + injection region is added in an N trap, a floating P + injection region is added between an NW and a PW, and the P + injection region connected with an anode is adjacent to the floating N + injection region and the floating P + injection region to jointly form an embedded PNP triode; an NMOS (N-channel metal oxide semiconductor) structure (namely GGNMOS) with a grounded grid electrode is embedded in the PW, a P + injection region in the PW is connected with a drain electrode of the GGNMOS, equivalently, a parasitic NPN triode exists in the PW, and meanwhile, a collector electrode of the parasitic NPN triode is connected with a base electrode of an NPN triode in the main SCR. A parasitic PNP triode and an NPN triode which are added on the basis of a traditional SCR are connected in series through a wire, a surface shunt path can be formed, and therefore the positive feedback effect of a main SCR path is effectively weakened, and the maintaining voltage is improved; the electrostatic protection device of the silicon controlled rectifier has the characteristics of high maintaining voltage and high failure current, can keep away from the latch risk, and effectively protects an internal circuit.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a thyristor electrostatic protection device with embedded PNP and GGNMOS and a manufacturing method thereof. Background Art

[0002] As integrated circuit manufacturing processes gradually improve and feature sizes gradually decrease, the failure problem caused by electrostatic discharge (ESD) has attracted more and more attention. Thinner gate oxides and shallower junction depths in advanced processes are easily affected by electrostatic discharge, and ESD poses a serious threat to integrated circuits. Therefore, engineers will try every means to design ESD protection for integrated circuit chips and electronic products to improve the reliability of chip products.

[0003] Commonly used ESD protection devices include diodes, bipolar transistors, MOSFETs, and silicon controlled rectifiers (SCRs). Compared with other ESD protection devices, traditional SCR devices have the advantages of strong discharge capacity per unit area, small parasitic capacitance, and strong robustness. Figure 1 , its equivalent circuit diagram is shown in Figure 2 . When an ESD pulse is applied to the anode of the unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current will be generated inside the device. The current flows through the first P-well and flows to the cathode through the parasitic resistance. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of the transistor NPN. When this voltage is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After the transistor is turned on, it provides base current for the horizontal PNP transistor, and the horizontal PNP transistor is turned on, further providing base current for the vertical NPN transistor, forming a positive feedback mechanism to fully open the SCR path. Therefore, even if there is no avalanche current afterwards, the large current can be discharged due to the conduction of the transistor.

[0004] However, the trigger voltage of traditional SCR devices is too high, and under advanced process conditions, it has far exceeded the gate oxide breakdown voltage of the protected device. When an ESD event occurs, the internal device has been destroyed by the transient large current before the SCR starts working. Traditional SCR devices also have the disadvantage of too low holding voltage, which is about 2V, and are prone to latch-up risks. Therefore, a lot of in-depth research is needed to apply the SCR structure to actual circuits. How to design an ESD protection device based on the traditional SCR structure so that it retains the advantages of the traditional SCR structure of low clamping voltage and strong robustness, while reducing and increasing the holding voltage to ensure that the device performance parameters meet the design window is a severe and important challenge. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a thyristor electrostatic protection device with embedded PNP and GGNMOS and a manufacturing method thereof, and is applied to the design of an ESD protection network with an operating voltage of 0 to 5.5V.

[0006] The technical solution of the present invention to solve the above problems is:

[0007] In a first aspect, an embodiment of the present invention provides a thyristor electrostatic protection device with embedded PNP and GGNMOS, including a P-type substrate; an N-type buried layer is provided in the P-type substrate; an N-type deep well is provided above the N-type buried layer; a first N-well and a first P-well are provided on the N-type deep well; a first N-well and a first P-well are provided on the N-type deep well in sequence from left to right; a first N-well and a first P-well are provided on the N-type deep well in sequence from left to right; a first N+ injection region, a first P+ injection region, and a second N+ injection region are provided on the first N-well in sequence from left to right; a second P+ injection region is provided between the first N-well and the first P-well; a third P+ injection region, a third N+ injection region, a first gate, a fourth N+ injection region, and a fourth P+ injection region are provided in sequence from left to right in the first P-well; the first gate is between the third N+ injection region and the fourth N+ injection region;

[0008] The two electrodes of the first N+ injection region and the first P+ injection region in the first N well are connected together and serve as the anode of the device; the three electrodes of the first gate, the fourth N+ injection region and the fourth P+ injection region in the first P well are connected together and serve as the cathode of the device; the third P+ injection region and the third N+ injection region in the first P well are connected together through a metal wire and are not connected to a potential.

[0009] Preferably, there are six field oxygen isolation regions; the first field oxygen isolation region is between the left side of the first N+ injection region and the left edge of the P-type substrate, the second field oxygen isolation region is between the first N+ injection region and the first P+ injection region, the third field oxygen isolation region is between the second P+ injection region and the third P+ injection region, the fourth field oxygen isolation region is between the third P+ injection region and the third N+ injection region, the fifth field oxygen isolation region is between the fourth N+ injection region and the fourth P+ injection region, and the sixth field oxygen isolation region is between the right side of the fourth P+ injection region and the right edge of the P-type substrate.

[0010] Preferably, the first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region, the fourth field oxygen isolation region, the fifth field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the first P-well.

[0011] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the second N injection region and the second P+ injection region; at this time, the first P+ injection region, the second N+ injection region and the second P+ injection region constitute a lateral PNP transistor Qp2, the third N+ injection region, the first gate and the fourth N+ injection region constitute an NMOS, and the first gate is connected to the cathode, the purpose is to close the conductive channel of the NMOS, and form a parasitic lateral NPN transistor Qn2 in the first P well; the third P+ injection region and the third N+ injection region are connected by a wire, so that the collector of the parasitic NPN transistor Qn2 is connected to the base region of the NPN transistor Qn1 in the main SCR structure, so that the parasitic NPN transistor Qn2 extracts the base current of the NPN transistor Qn1 in the main SCR, which can increase the holding voltage of the device.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N injection region / first N well / first deep N well / N-type buried layer constitutes a parasitic resistor Rn, and the fourth P+ injection region / first P well constitutes a parasitic resistor Rp, the first P+ injection region, the first N well / first deep N well / N-type buried layer and the first P well constitute a parasitic PNP transistor Qp1, and the first N well / first deep N well / N-type buried layer, the first P well and the fourth N+ injection region constitute a parasitic NPN transistor Qn1. When the voltage drop across the parasitic resistor Rp reaches 0.7V, the parasitic transistor NPN Qn1 is turned on and provides a base current to the parasitic PNP transistor Qp1 to promote its conduction. When the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn1 are turned on, a forward SCR path is formed to form a positive feedback effect, and the device is successfully triggered.

[0013] Preferably, the width S1 of the second N+ implantation region is adjustable, and when S1 is reduced, the trigger path of the device is shortened, and the trigger voltage is reduced accordingly. At the same time, reducing S1 is equivalent to reducing the base width of the parasitic PNP transistor Qp2, thereby improving the emission efficiency of the parasitic PNP transistor Qp2, enhancing the shunting ability of the surface path, and increasing the holding voltage of the device.

[0014] Preferably, the width S2 of the second P+ injection region is adjustable. When S2 increases, it is equivalent to widening the base width of the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn1, thereby reducing the emission efficiency of the parasitic transistors, weakening the positive feedback effect of the SCR path, and increasing the maintenance voltage.

[0015] In a second aspect, an embodiment of the present invention provides a method for manufacturing a thyristor electrostatic protection device embedded with PNP and GGNMOS, comprising the following steps:

[0016] Step 1: forming an N-type buried layer in a P-type substrate;

[0017] Step 2: Generate an N-type deep well above the N-type buried layer;

[0018] Step 3: generating a first N-well and a first P-well in the first N-type deep well;

[0019] Step 4: A first N+ injection region, a first P+ injection region, and a second N+ injection region are sequentially provided on the first N well from left to right; a second P+ injection region is provided between the first N well and the first P well; a third P+ injection region, a third N+ injection region, a first gate, a fourth N+ injection region, and a fourth P+ injection region are sequentially provided in the first P well from left to right;

[0020] Step 5: Generate a first field oxygen isolation zone between the left side of the first N+ injection zone and the left edge of the P-type substrate, generate a second field oxygen isolation zone between the first N+ injection zone and the first P+ injection zone, generate a third field oxygen isolation zone between the second P+ injection zone and the third P+ injection zone, generate a fourth field oxygen isolation zone between the third P+ injection zone and the third N+ injection zone, generate a fifth field oxygen isolation zone between the fourth N+ injection zone and the fourth P+ injection zone, and generate a sixth field oxygen isolation zone between the right side of the fourth P+ injection zone and the right edge of the P-type substrate.

[0021] Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0022] Step seven: Connect the two electrodes of the first N+ injection region and the first P+ injection region in the first N well together and use them as the anode of the device; connect the three electrodes of the first gate, the fourth N+ injection region and the fourth P+ injection region in the first P well together and use them as the cathode of the device; connect the third P+ injection region and the third N+ injection region in the first P well together through a metal wire without connecting any potential.

[0023] Preferably, before forming the N-type buried layer in the P-type substrate, the method further comprises:

[0024] A silicon dioxide film is grown on a P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is reached to remove the silicon nitride layer.

[0025] The beneficial effects of the present invention are:

[0026] 1. The present invention adjusts the breakdown surface and, based on the traditional unidirectional thyristor electrostatic protection device, introduces a second P+ injection region spanning between the first N well and the first P well, and adds a second N+ injection region between the first P+ injection region and the second P+ injection region, thereby changing the breakdown surface from the well breakdown of the first N well and the first P well to the junction breakdown of the second N+ injection region and the second P+ injection region, thereby effectively reducing the trigger voltage of the device and making the device easier to turn on.

[0027] 2. In order to better exert the performance of the unidirectional thyristor, the present invention embeds a PNP transistor and a gate-grounded NMOS structure on the basis of the traditional SCR. The first P+ injection region, the second N+ injection region and the second P+ injection region located in the first N well form a lateral PNP type transistor Qp2. When avalanche breakdown occurs between the second N+ injection region and the second P+ injection region, a large number of carriers generated flow into the first N well and the first P well, resulting in a voltage drop of more than 0.7V across the parasitic resistance Rn formed by the first N injection region / first N well / first deep N well / N-type buried layer and the parasitic resistance Rp formed by the fourth P+ injection region / first P well, thereby turning on the main SCR path.

[0028] The third N+ injection region, the first gate and the fourth N+ injection region in the first P well form an NMOS, and the first gate is connected to the cathode, the purpose is to close the conductive channel of the NMOS, and form a parasitic lateral NPN transistor Qn2 in the first P well. The third P+ injection region and the third N+ injection region are connected through a wire, so that the collector of the parasitic NPN transistor Qn2 is connected to the base region of the NPN transistor Qn1 in the main SCR structure, so that the parasitic NPN transistor Qn2 extracts the base current of the NPN transistor Qn1 in the main SCR. At the same time, the collector of the PNP transistor Qp2 is connected to the collector of the parasitic NPN transistor Qn2 through a wire, and the surface path formed by the transistor Qp2 and the transistor Qn2 will shunt the current of the main SCR and weaken the positive feedback effect, thereby increasing the holding voltage of the device. At the same time, the device maintains good ESD robustness.

[0029] 3. The width S1 of the second N+ implantation region of the present invention is adjustable. When S1 is reduced, the trigger path of the device is shortened, and the trigger voltage is reduced accordingly. At the same time, reducing S1 is equivalent to reducing the base width of the parasitic PNP transistor Qp2, thereby improving the emission efficiency of the parasitic PNP transistor Qp2, enhancing the shunting ability of the surface path, and increasing the holding voltage of the device.

[0030] 4. The width S2 of the second P+ injection region of the present invention is adjustable. When S2 increases, it is equivalent to widening the base width of the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn2, thereby weakening the emission efficiency of the parasitic transistor, weakening the positive feedback effect of the SCR path, and increasing the maintenance voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic protection device.

[0032] Figure 2 This is the equivalent circuit diagram of the traditional unidirectional SCR electrostatic protection device.

[0033] Figure 3 It is a cross-sectional view of an embodiment of the present invention.

[0034] Figure 4 2 is an equivalent circuit diagram of an embodiment of the present invention.

[0035] Figure 5 A total current density distribution simulation diagram of a thyristor electrostatic protection device with embedded PNP and GGNMOS provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0038] like Figure 3 As shown, a thyristor electrostatic protection device with embedded PNP and GGNMOS includes a P-type substrate 101; an N-type buried layer 201 is provided in the substrate; an N-type deep well 301 is provided above the N-type buried layer 201; a first N-well 401 and a first P-well 402 are provided on the N-type deep well; a first N+ injection region 501, a first P+ injection region 502, and a second N+ injection region 503 are provided on the first N-well 401 from left to right; a second P+ injection region 504 is provided between the first N-well 401 and the first P-well 402 and bridged between the two wells; a third P+ injection region 505, a third N+ injection region 506, a first gate 701, a fourth N+ injection region 507, and a fourth P+ injection region 508 are provided on the first P-well 402 from left to right; the first gate 701 is provided at the third N+ injection region 506, a first gate 701, a fourth N+ injection region 507, and a fourth P+ injection region 508; The first N+ injection region 501 and the first P+ injection region 502 in the first N well 401 are connected together and serve as the anode of the device; the first gate 701, the fourth N+ injection region 507 and the fourth P+ injection region 508 in the first P well 402 are connected together and serve as the cathode of the device; the third P+ injection region 505 and the third N+ injection region 506 in the first P well 402 are connected together through a metal wire without connecting a potential; in this way, after the SCR path is turned on, a PNP-NPN path will appear on the surface of the device, and part of the current of the SCR path will be discharged through this path, which will suppress the positive feedback effect in the original SCR path. This structural design can effectively improve the holding voltage of the device.

[0039] In one embodiment, the thyristor electrostatic protection device with embedded PNP and GGNMOS has six field oxygen isolation regions; the first field oxygen isolation region 601 is between the left side of the first N+ injection region 501 and the left edge of the P-type substrate 101, the second field oxygen isolation region 602 is between the first N+ injection region 501 and the first P+ injection region 502, the third field oxygen isolation region 603 is between the second P+ injection region 504 and the third P+ injection region 505, the fourth field oxygen isolation region 604 is between the third P+ injection region 505 and the third N+ injection region 506, the fifth field oxygen isolation region 605 is between the fourth N+ injection region 507 and the fourth P+ injection region 508, and the sixth field oxygen isolation region 606 is between the right side of the fourth P+ injection region 508 and the right edge of the P-type substrate 101.

[0040] In one embodiment, the first field oxygen isolation region 601 and the second field oxygen isolation region 602 are located on the surface of the first N-well 401 ; the third field oxygen isolation region 603 , the fourth field oxygen isolation region 604 , the fifth field oxygen isolation region 605 and the sixth field oxygen isolation region 606 are located on the surface of the first P-well 402 .

[0041] In one embodiment, if Figures 4 to 5 As shown, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the second N+ injection region 503 and the second P+ injection region 504; at this time, the first P+ injection region 502, the second N+ injection region 503 and the second P+ injection region 504 constitute a lateral PNP transistor Qp2, the third N+ injection region 506, the first gate 701 and the fourth N+ injection region 507 constitute an NMOS, and the first gate 701 is connected to the cathode, the purpose is to close the conductive channel of the NMOS, and form a parasitic lateral NPN transistor Qn2 in the first P well 402; the third P+ injection region 505 and the third N+ injection region 506 are connected by a wire, so that the collector of the parasitic NPN transistor Qn2 is connected to the base region of the NPN transistor Qn1 in the main SCR structure, so that the parasitic NPN transistor Qn2 extracts the base current of the NPN transistor Qn1 in the main SCR. At the same time, the collector of the PNP transistor Qp2 is connected to the collector of the parasitic NPN transistor Qn2 through a wire, and the surface path formed by the transistors Qp2 and Qn2 will shunt the current of the main SCR and weaken the positive feedback effect, thereby increasing the holding voltage of the device. At the same time, the device maintains good ESD robustness.

[0042] When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N injection region 501 / the first N well 401 / the first deep N well 301 / the N-type buried layer 201 constitutes a parasitic resistor Rn, and the fourth P+ injection region 508 / the first P well 402 constitutes a parasitic resistor Rp. The first P+ injection region 502, the first N well 401 / the first deep N well 301 / the N-type buried layer 201 and the first P well 402 constitute a parasitic PNP transistor Qp1, and the first N well 401 / the first deep N well 301 / the N-type buried layer 201, the first P well 402 and the fourth N+ injection region 507 constitute a parasitic NPN transistor Qn1. When the voltage drop across the parasitic resistor Rp reaches 0.7V, the parasitic transistor NPN Qn1 is turned on and provides base current to the parasitic PNP transistor Qp1, thereby promoting its conduction. When the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn1 are turned on, a forward SCR path is formed, forming a positive feedback effect, and the device is successfully triggered.

[0043] According to the requirements of the ESD design window in different application scenarios, the device can reduce the width S1 of the second N+ injection region 503, shorten the trigger path of the device, and reduce the trigger voltage accordingly. At the same time, reducing S1 is equivalent to reducing the base width of the parasitic PNP transistor Qp2, thereby improving the emission efficiency of the parasitic PNP transistor Qp2, enhancing the shunting ability of the surface path, and increasing the holding voltage of the device; the width S2 of the second P+ injection region 504 is adjustable, and when S2 increases, the holding voltage increases.

[0044] The embodiment of the present invention further provides a method for manufacturing a thyristor electrostatic protection device with embedded PNP and GGNMOS, comprising the following steps:

[0045] Step 1: forming an N-type buried layer 201 in a P-type substrate 101;

[0046] Step 2: generating an N-type deep well 301 above the N-type buried layer 201;

[0047] Step 3: generating a first N-well 401 and a first P-well 402 in the first N-type deep well 301;

[0048] Step 4: Generate a first N-well 401 and a first P-well 402 from left to right on the N-type deep well; generate a first N+ injection region 501, a first P+ injection region 502, and a second N+ injection region 503 from left to right on the first N-well; generate a second P+ injection region 504 between the first N-well and the first P-well; generate a third P+ injection region 505, a third N+ injection region 506, a first gate 701, a fourth N+ injection region 507, and a fourth P+ injection region 508 from left to right in the first P-well;

[0049] Step 5: Generate a first field oxygen isolation region 601 between the left side of the first N+ injection region 501 and the left edge of the P-type substrate 101, generate a second field oxygen isolation region 602 between the first N+ injection region 501 and the first P+ injection region 502, generate a third field oxygen isolation region 603 between the second P+ injection region 504 and the third P+ injection region 505, generate a fourth field oxygen isolation region 604 between the third P+ injection region 505 and the third N+ injection region 506, generate a fifth field oxygen isolation region 605 between the fourth N+ injection region 507 and the fourth P+ injection region 508, and generate a sixth field oxygen isolation region 606 between the right side of the fourth P+ injection region 508 and the right edge of the P-type substrate 402.

[0050] Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas;

[0051] Step seven: Connect the two electrodes of the first N+ injection region 501 and the first P+ injection region 502 in the first N well 401 together and use them as the anode of the device; connect the three electrodes of the first gate 701, the fourth N+ injection region 507 and the fourth P+ injection region 508 in the first P well 402 together and use them as the cathode of the device; connect the third P+ injection region 505 and the third N+ injection region 506 in the first P well 402 together through a metal wire without connecting any potential.

[0052] The present invention discloses a method for manufacturing a thyristor electrostatic protection device with embedded PNP and GGNMOS, which is simple in process and easy to operate. In order to better exert the performance of the unidirectional thyristor, the present invention embeds a PNP triode and a gate-grounded NMOS structure, generating a new surface path that weakens the positive feedback effect of the SCR path, thereby suppressing the latch effect, and effectively improving the protection performance and failure level of the device. The device can be used in the ESD protection design of the I / O port of 0 to 5.5V. The example device of the present invention adopts a 0.25μm BCDMOS process.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A thyristor electrostatic protection device with embedded PNP and GGNMOS, characterized in that: including a P-type substrate; An N-type buried layer is provided in the substrate; An N-type deep well is located above the N-type buried layer; The N-type deep well is provided with a first N-well and a first P-well; The N-type deep well is provided with a first N-well and a first P-well from left to right in sequence; the first N-well is provided with a first N+ injection region, a first P+ injection region, and a second N+ injection region from left to right in sequence; a second P+ injection region is provided between the first N-well and the first P-well; the first P-well is provided with a third P+ injection region, a third N+ injection region, a first gate, a fourth N+ injection region, and a fourth P+ injection region from left to right in sequence; The first gate is between the third N+ implantation region and the fourth N+ implantation region; The two electrodes of the first N+ injection region and the first P+ injection region in the first N well are connected together and serve as the anode of the device; the three electrodes of the first gate, the fourth N+ injection region and the fourth P+ injection region in the first P well are connected together and serve as the cathode of the device; the third P+ injection region and the third N+ injection region in the first P well are connected together through a metal wire and are not connected to a potential.

2. The thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 1, characterized in that: There are six field oxygen isolation regions; a first field oxygen isolation region is provided between the left side of the first N+ injection region and the left edge of the P-type substrate, a second field oxygen isolation region is provided between the first N+ injection region and the first P+ injection region, a third field oxygen isolation region is provided between the second P+ injection region and the third P+ injection region, a fourth field oxygen isolation region is provided between the third P+ injection region and the third N+ injection region, a fifth field oxygen isolation region is provided between the fourth N+ injection region and the fourth P+ injection region, and a sixth field oxygen isolation region is provided between the right side of the fourth P+ injection region and the right edge of the P-type substrate.

3. The field oxygen isolation region according to claim 2, characterized in that: The first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region, the fourth field oxygen isolation region, the fifth field oxygen isolation region, and the sixth field oxygen isolation region are located on the surface of the first P-well.

4. The thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the second N injection region and the second P+ injection region; at this time, the first P+ injection region, the second N+ injection region and the second P+ injection region constitute a lateral PNP transistor Qp2, the third N+ injection region, the first gate and the fourth N+ injection region constitute an NMOS, and the first gate is connected to the cathode, the purpose is to close the conductive channel of the NMOS, and form a parasitic lateral NPN transistor Qn2 in the first P well; the third P+ injection region and the third N+ injection region are connected by a wire, so that the collector of the parasitic NPN transistor Qn2 is connected to the base region of the NPN transistor Qn1 in the main SCR structure, so that the parasitic NPN transistor Qn2 extracts the base region current of the NPN transistor Qn1 in the main SCR, which can increase the holding voltage of the device.

5. The thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N injection region / first N well / first deep N well / N-type buried layer constitutes a parasitic resistor Rn, and the fourth P+ injection region / first P well constitutes a parasitic resistor Rp. The first P+ injection region, the first N well / first deep N well / N-type buried layer and the first P well constitute a parasitic PNP transistor Qp1. The first N well / first deep N well / N-type buried layer, the first P well and the fourth N+ injection region constitute a parasitic NPN transistor Qn1. When the voltage drop across the parasitic resistor Rp reaches 0.7V, the parasitic transistor NPN Qn1 is turned on and provides a base current to the parasitic PNP transistor Qp1 to promote its conduction. When the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn1 are turned on, a forward SCR path is formed to form a positive feedback effect, and the device is successfully triggered.

6. The thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 1, characterized in that: The width S1 of the second N+ injection region is adjustable. When S1 decreases, the trigger path of the device is shortened and the trigger voltage decreases accordingly. At the same time, reducing S1 is equivalent to reducing the base width of the parasitic PNP transistor Qp2, thereby improving the emission efficiency of the parasitic PNP transistor Qp2, enhancing the shunting capacity of the surface path, and increasing the holding voltage of the device.

7. The thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 1, characterized in that: The width S2 of the second P+ injection region is adjustable. When S2 increases, it is equivalent to widening the base width of the parasitic PNP transistor Qp1 and the parasitic NPN transistor Qn1, thereby reducing the emission efficiency of the parasitic transistors, weakening the positive feedback effect of the SCR path, and increasing the maintenance voltage.

8. A method for manufacturing a thyristor electrostatic protection device with embedded PNP and GGNMOS according to any one of claims 1 to 7, comprising the following steps: Step 1: forming an N-type buried layer in a P-type substrate; Step 2: Generate an N-type deep well above the N-type buried layer; Step 3: generating a first N-well and a first P-well in the first N-type deep well; Step 4: Generate a first N+ injection region, a first P+ injection region, and a second N+ injection region from left to right on the first N well; A second P+ implantation region is generated between the first N well and the first P well, bridging the two wells; On the first P well, a third P+ injection region, a third N+ injection region, a first gate, a fourth N+ injection region and a fourth P+ injection region are sequentially generated from left to right; Step 5: generating a first field oxygen isolation region between the left side of the first N+ implantation region and the left edge of the P-type substrate, generating a second field oxygen isolation region between the first N+ implantation region and the first P+ implantation region, generating a third field oxygen isolation region between the second P+ implantation region and the third P+ implantation region, generating a fourth field oxygen isolation region between the third P+ implantation region and the third N+ implantation region, generating a fifth field oxygen isolation region between the fourth N+ implantation region and the fourth P+ implantation region, and generating a sixth field oxygen isolation region between the right side of the fourth P+ implantation region and the right edge of the P-type substrate; Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step 7: Connect the first N+ injection region and the first P+ injection region together and use them as the anode of the device, connect the third P+ injection region and the third N+ injection region together without connecting any potential, and connect the first gate, the fourth N+ injection region and the fourth P+ injection region together and use them as the cathode of the device.

9. The method for manufacturing a thyristor electrostatic protection device with embedded PNP and GGNMOS according to claim 8, characterized in that: The step 1 also includes the following steps: A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

Images