Silicon-controlled electrostatic protection device with low triggering and high maintaining voltage and manufacturing method of silicon-controlled electrostatic protection device

Abstract

The invention discloses a low-trigger high-maintaining-voltage silicon-controlled electrostatic protection device and a manufacturing method thereof, an N trap is added to the right side of a cathode of a traditional double-trap silicon-controlled device to form three traps, the three traps are connected to an anode through N + injection, and compared with a traditional one-way low-trigger silicon-controlled electrostatic protection device, the low-trigger high-maintaining-voltage silicon-controlled electrostatic protection device has a shorter distance between the cathode and the anode. Besides, an NMOS (N-channel Metal Oxide Semiconductor) and P + injection are embedded in a P trap of the device, a grid drain of the NMOS is connected with the P + injection, a source of the NMOS is connected with a cathode, a surface ESD (Electro-Static Discharge) current discharge path is added on the basis of a traditional unidirectional silicon controlled electrostatic protection device, and the positive feedback effect of the SCR discharge path can be effectively inhibited. Therefore, the device has the characteristics of low trigger voltage and high maintaining voltage, and a core circuit of a chip is effectively protected from the risk of latching. The device can be applied to ESD protection of the I / O port with the working voltage of 0-5.5 V.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and in particular to a thyristor ESD protection device with low triggering voltage and high sustaining voltage, and its manufacturing method. Background Technology

[0002] With advancements in semiconductor manufacturing processes, ESD-induced failures of integrated circuit chips and electronic products have become increasingly severe. ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by product engineers. The ESD design window is a key issue that product engineers need to consider when designing ESD protection systems, including the trigger voltage V. t1 Trigger current I t1 Sustaining voltage V h , holding current I h Failure voltage V t2 Failure current I t2 On-resistance R on The trigger voltage of an ESD protection device must be lower than the highest withstand voltage (drain-source breakdown voltage) of the protected port of the core circuit; typically, the trigger voltage should be 10% to 20% lower than the highest withstand voltage. The sustaining voltage of the ESD protection device must be 1.1 to 1.2 times higher than the normal operating voltage of the core circuit to prevent latch-up caused by the ESD protection device remaining constantly on. The failure current I of the ESD protection device... t2 It is one of the important parameters for measuring the robustness of ESD protection devices. It represents the maximum current that the ESD protection device can withstand, and in order to effectively protect the core circuit, it must withstand the failure current I. t2 At this time, the clamping voltage of the ESD protection device must be less than the maximum withstand voltage of the protected port; the on-resistance R of the ESD protection device on It refers to the resistance characteristics of the device after it reaches the sustain point, and its relationship with the sustaining voltage V. h , holding current I h Failure voltage V t2 Failure current I t2 According to Ohm's law, the on-resistance R is... on Represented as failure voltage V t2 Sustaining voltage V h Difference and failure current I t2 , holding current I h The ratio of the difference; Human Body Mode (HBM) considers the equivalent resistance of the human body to be 1.5kΩ, and the HBM protection level is 1500 times I. t2 .

[0003] ESD-induced failure modes include hard failure, soft failure, and latent failure. The causes of these failures can be categorized into electrical failure and thermal failure. Thermal failure refers to the generation of a current of several to tens of amperes in a localized area of ​​the chip when an ESD pulse occurs. This current is short-lived but generates a large amount of heat, causing localized metal interconnects to melt or hot spots to form on the chip, leading to secondary breakdown. Electrical failure occurs when the electric field strength created by the voltage applied to the gate oxide layer exceeds the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes increasingly serious, the study of its physical mechanisms is receiving increasing attention.

[0004] Compared with other ESD devices, traditional unidirectional thyristor devices have a dual conductivity modulation mechanism, high discharge efficiency per unit area, small parasitic capacitance per unit area, and the best robustness.

[0005] A cross-sectional view of a traditional unidirectional low-trigger-voltage SCR electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the anode of a unidirectional low-trigger-voltage SCR, N+ injection forms a reverse-biased PN junction with the P-type shallow well. When this pulse voltage exceeds the avalanche breakdown voltage of this PN junction, a large avalanche current is generated inside the device. This current flows through the P-type shallow well / P-type substrate and through the parasitic resistance to the cathode. The voltage drop across the parasitic resistance of the P-type shallow well is equivalent to the base voltage drop of an NPN1 transistor. When this voltage exceeds the forward turn-on voltage of the lateral NPN1 transistor, the transistor turns on. After this transistor turns on, it provides base current to the PNP transistor, which also turns on, forming a positive feedback mechanism that fully opens the SCR path. Therefore, even if there is no subsequent avalanche current, the open SCR path can still discharge a large current. Unidirectional low-trigger-voltage SCRs can provide electrostatic protection for circuits with positive operating signal voltages. However, due to their high trigger voltage and low holding voltage, latch-up can easily occur, which needs to be carefully considered during the design process. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a low-trigger, high-sustaining thyristor electrostatic discharge (ESD) device and its fabrication method, which is applied to ESD protection network design with operating voltages of 0–5.5V.

[0007] The technical solution of the present invention to solve the above problems is:

[0008] In a first aspect, embodiments of the present invention provide a low-trigger, high-sustainment silicon-controlled electrostatic discharge (SSD) device, comprising a P-type substrate; an N-type buried layer in the P-type substrate; an N-type deep well above the N-type buried layer; a first N-well, a first P-well, and a second N-well sequentially arranged from left to right on the N-type deep well. The first N-well, the first P-well, and the second N-well sequentially arranged from left to right on the N-type deep well; a first N+ implant and a first P+ implant sequentially arranged from left to right on the first N-well; a second P+ implant, a second N+ implant, a first gate, a third N+ implant, and a second gate sequentially arranged from left to right on the first P-well; a fourth N+ implant between the first N-well and the first shallow P-well; and an N+ implant on the second N-well. The first gate is located between the second N+ implant and the third N+ implant, and the second gate is located between the second N+ implant and the fourth N+ implant.

[0009] The first N+ injection, the first P+ injection, and the N+ injection in the first N-well are all connected together and serve as the anode of the device; the third N+ injection in the first P-well and the second gate are connected together and serve as the cathode of the device; the first P+ injection, the second N+ injection, and the third gate in the first P-well are connected together by a metal wire and are not connected to any potential.

[0010] Preferably, there are four field oxygen isolation zones; the first field oxygen isolation zone is between the first N+ injection and the first P+ injection zone, the second field oxygen isolation zone is between the first P+ injection and the second P+ injection zone, the third field oxygen is between the second P+ injection and the second N+ injection zone, and the fourth field oxygen is between the fourth N+ injection and the fifth N+ injection zone.

[0011] Preferably, the first field oxygen isolation region is located on the surface of the first N-well; the second field oxygen isolation region is connected across the surfaces of the first N-well and the first P-well; the third field oxygen isolation region is located on the surface of the first P-well; and the fourth field oxygen isolation region is located on the surface of the second N-well.

[0012] Preferably, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N-well, and the first P-well constitute a vertical PNP transistor, the first N-well, the first P-well, and the third N+ injection constitute a horizontal NPN transistor structure, and the third N+ injection, the first P-well, and the fifth N+ injection constitute a horizontal NPN transistor.

[0013] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, there are two breakdown surfaces: one is a reverse-biased PN junction composed of the first N-well and the second P-well, and the other is a reverse-biased PN junction composed of the first P-well and the fourth N+ injection. Because the BV of the second breakdown surface is lower and its cathode-cathode distance is shorter, avalanche breakdown occurs first at the second breakdown surface. After avalanche breakdown, the ESD current flows into the cathode through the fifth N+ injection, the second N-well, the fourth N+ injection, the first P-well, and the third N+ injection. A voltage drop is formed across the equivalent resistance of the first P-well. When the voltage drop reaches 0.7V, the right-side transverse NPN transistor turns on and provides base current to the left-side longitudinal PNP transistor, thus promoting its conduction and forming a positive feedback effect. At this point, the device is successfully triggered.

[0014] Preferably, an NMOS is provided in the first P-well. The ESD current forms a voltage drop across the equivalent resistance of the first P-well. When the voltage drop reaches the threshold voltage of the MOS transistor, the NMOS channel opens, forming a surface path consisting of the first P+ injection region, the first N-well, and the first P-well, which is a vertical PNP transistor connected in series with the NMOS. This can effectively suppress the positive feedback effect of the SCR discharge path and improve the holding voltage of the device.

[0015] Preferably, the size S1 of the second injected P+ is adjustable, and the sustaining voltage of the device increases as the distance of S1 increases.

[0016] Secondly, embodiments of the present invention provide a method for fabricating a low-trigger, high-sustaining silicon-controlled electrostatic discharge (SCD) device, comprising the following steps:

[0017] Step 1: Form an N-type buried layer in a P-type substrate;

[0018] Step 2: Generate an N-type deep well above the N-type buried layer;

[0019] Step 3: Generate the first N-well and the first P-well within the first type N deep well;

[0020] Step 4: Generate the first N+ implant and the first P+ implant sequentially from left to right on the first N-well; generate the second P+ implant, the second N+ implant, the first gate, the third N+ implant, and the second gate sequentially from left to right on the first P-well; generate a fourth N+ implant region between the first P-well and the second N-well, bridging the two wells.

[0021] Step 5: A first field oxygen isolation region is formed between the first N+ injection and the first P+ injection on the first N-well; a second field oxygen is generated between the first P+ injection bridging the first N-well and the second P+ injection on the first P-well; and a third field oxygen is produced between the fourth N+ injection and the fifth N+ injection on the second N-well.

[0022] Step 6: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0023] Step 7: Connect the first N+ implant, the first P+ implant, and the fifth N+ implant together as the anode of the device; connect the second P+ implant, the second N+ implant, and the first gate together without applying a potential; and connect the third N+ implant and the second gate implant together as the cathode of the device.

[0024] Preferably, before forming the N-type buried layer in the P-type substrate, the method further includes:

[0025] A silicon dioxide thin film is grown on a P-type substrate, followed by the deposition of a silicon nitride layer. A photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop the wafer to form a shallow isolation trench. The silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Then, chemical mechanical polishing is performed until the silicon nitride layer is removed.

[0026] The beneficial effects of this invention are as follows:

[0027] 1. This invention changes the trigger current conduction path. Based on the traditional unidirectional low-trigger SCR electrostatic discharge protection device, by introducing a second N-well to the right of the first P-well and a fifth N+ injection connected to the anode, the trigger current conduction path is changed from first N+ injection, first N-well, second N+ injection, second P-well, second P+ injection to fifth N+ injection, second N-well, fourth N+ injection, first P-well, third N+ injection. This shortens the anode-cathode distance, effectively reduces the device's trigger voltage, and makes the device easier to turn on.

[0028] 2. In this invention, an NMOS is introduced into the first P-well and injected into the third P+ region. The gate and drain of the NMOS are connected to the third P+ injection region via a metal connection without being connected to a potential, and the source is connected to the cathode. When the ESD current forms a voltage drop across the equivalent resistance of the first P-well, and the voltage drop reaches the threshold voltage of the MOS transistor, the NMOS channel opens, forming a surface path consisting of the first P+ injection region, the first N-well, and the first P-well, which constitutes a vertical PNP transistor connected in series with the NMOS. This effectively suppresses the positive feedback effect of the SCR discharge path and improves the holding voltage of the device.

[0029] 3. The width S1 of the second P+ injection in this invention is adjustable. When S1 increases, it is equivalent to widening the base region width of the parasitic NPN and PNP transistors. On the other hand, it can enhance the surface current path, thereby weakening the positive feedback effect of the SCR path and maintaining the voltage increase. Attached Figure Description

[0030] Figure 1This is a cross-sectional view of a traditional unidirectional LVTSCR electrostatic discharge protection device.

[0031] Figure 2 This is the equivalent circuit diagram of a traditional unidirectional LVTSCR electrostatic discharge protection device.

[0032] Figure 3 This is a cross-sectional view of an embodiment of the present invention.

[0033] Figure 4 This is an equivalent circuit diagram of an embodiment of the present invention.

[0034] Figure 5 The simulation diagram shows the total current density distribution of a thyristor electrostatic discharge (ESD) device with reduced triggering and improved maintenance, as provided in an embodiment of the present invention. Detailed Implementation

[0035] The following description, in conjunction with the accompanying drawings and embodiments, further illustrates the ESD protection design of the present invention applied to analog switch chips.

[0036] like Figure 3 As shown, a low-trigger, high-sustainment silicon controlled rectifier (SCR) electrostatic discharge (ESD) device includes a P-type substrate 101; an N-type buried layer 201 is disposed in the substrate; an N-type deep well 301 is located above the N-type buried layer 201; a first N-well 401, a first P-well 402, and a second N-well 403 are disposed on the N-type deep well; a first N+ implant 501 and a first P+ implant 502 are disposed sequentially from left to right on the first N-well 401; a second P+ implant 503, a second N+ implant 504, a first gate 701, a third N+ implant 505, and a second gate 702 are disposed sequentially from left to right on the first P-well 402; a fourth N+ implant 506 is disposed between the first P-well 402 and the second N-well 403, bridging the two wells; a fifth N+ implant 507 is disposed on the second N-well 403; the first gate 701 is disposed between the second N+ implant 504 and the third N+ implant 505; Between 05, the second gate 702 is between the third N+ injection 505 and the fourth N+ injection 506; the three electrodes of the first N-well 401, the second P+ injection 502, and the fifth N+ injection 507 in the second N-well 403 are connected together and serve as the anode of the device; the third N+ injection 505 in the first P-well 402 is connected together with the two electrodes of the second gate and serves as the cathode of the device; the second P+ injection 503 and the second N+ injection 504 in the first P-well 402 are connected together with the first gate 701 through a metal wire and are not connected to a potential; in this way, after the SCR path is turned on, a PNP series NMOS path will appear on the surface of the device, which will discharge part of the current of the SCR path through this path, thus suppressing the positive feedback effect in the original SCR path and improving the holding voltage.

[0037] In one embodiment, the first oxygen isolation region 601 is between the first N+ injection 501 and the first P+ injection 502, the second oxygen isolation region 602 is between the first P+ injection 502 and the second P+ injection 503, the third oxygen isolation region is between the second P+ injection 503 and the second N+ injection 504, and the fourth oxygen isolation region 604 is between the fourth N+ injection 506 and the fifth N+ injection 507.

[0038] In one implementation, such as Figures 4 to 5 As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region 502, the first N-well 401, and the first P-well 402 form a vertical PNP transistor, the first N-well 401, the first P-well 402, and the third N+ injection 505 form a horizontal NPN transistor structure, and the third N+ injection 505, the first P-well 402, and the fifth N+ injection 507 form a horizontal NPN transistor.

[0039] When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, there are two breakdown surfaces: one is the reverse-biased PN junction formed by the first N-well 401 and the second P-well 402, and the other is the reverse-biased PN junction formed by the first P-well 402 and the fourth N+ injection 506. Because the BV of the second breakdown surface is lower and its cathode-cathode distance is shorter, avalanche breakdown occurs first at the second breakdown surface. After avalanche breakdown, the ESD current flows into the cathode through the fifth N+ injection 507, the second N-well 403, the fourth N+ injection 506, the first P-well 402, and the third N+ injection 505. A voltage drop is formed across the equivalent resistance of the first P-well 402. When the voltage drop reaches 0.7V, the right-side transverse NPN transistor turns on and provides base current to the left-side longitudinal PNP transistor, thus promoting its conduction and forming a positive feedback effect. At this point, the device is successfully triggered.

[0040] An NMOS is provided in the first P-well 402. The ESD current forms a voltage drop across the equivalent resistance of the first P-well 402. When the voltage drop reaches the threshold voltage of the MOS transistor, the NMOS channel opens, forming a surface path of a vertical PNP transistor connected in series with the NMOS, which consists of the first P+ injection region 502, the first N-well 401, and the first P-well 402. This can effectively suppress the positive feedback effect of the SCR discharge path and improve the holding voltage of the device.

[0041] This device can adjust the width S1 of the third P+ injection 503 according to the ESD design window requirements of different application scenarios. When S1 increases, the voltage increases. When S1 increases, it is equivalent to widening the base region width of the parasitic NPN and PNP transistors. On the other hand, it can enhance the surface current path, thereby weakening the positive feedback effect of the SCR path and maintaining the voltage increase.

[0042] This invention also provides a method for fabricating a unidirectional thyristor electrostatic discharge (ESD) device with an NMOS gate-controlled diode, comprising the following steps:

[0043] Step 1: Form an N-type buried layer 201 in a P-type substrate 101;

[0044] Step 2: Generate an N-type deep well 301 above the N-type buried layer 201;

[0045] Step 3: Generate the first N-well 401, the first P-well 402, and the second N-well 403 within the first N-type deep well 301;

[0046] Step 4: Generate a first N+ implant 501 and a first P+ implant 502 sequentially from left to right on the first N-well 401; generate a second P+ implant 503, a second N+ implant 504, a first gate 701, a third N+ implant 505, and a second gate 702 sequentially from left to right on the first P-well 402; generate a fourth N+ implant 506 between the first P-well 402 and the second N-well 403, bridging the two wells; generate a fifth N+ implant 507 on the second N-well 403.

[0047] Step 5: A first field oxygen isolation region 601 is formed between the first N+ injection 501 and the first P+ injection 502; a second field oxygen isolation region 602 is formed between the first P+ injection 502 and the second P+ injection 503; a third field oxygen isolation region 603 is formed between the second P+ injection 503 and the second N+ injection 504; and a fourth field oxygen isolation region 604 is formed between the fourth N+ injection 506 and the fifth N+ injection 507.

[0048] Step 6: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0049] Step 7: Connect the first N+ injection 501, the second P+ injection 502, and the fifth N+ injection 507 together to form the anode of the device. Connect the third N+ injection 505 and the second gate electrode together to form the cathode of the device. Connect the second P+ injection 503, the second N+ injection 504, and the first gate 701 together with a metal wire, without applying any potential.

[0050] The fabrication method of this invention for a low-trigger, high-sustain SCR electrostatic discharge (ESD) device is simple and easy to operate. To better utilize the performance of the unidirectional SCR, this invention improves the anode-cathode spacing of the device's trigger current path, accelerating the device's turn-on speed. The NMOS structure introduced in this invention generates a new surface path that weakens the positive feedback effect of the SCR path, thereby suppressing latch-up and effectively improving the device's protection performance and failure level. This device can be used in ESD protection designs for 0–5.5V I / O ports. The example device of this invention uses a 0.25μm BCDMOS process.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A thyristor electrostatic protection device with low triggering and high holding voltage, characterized in that: including a P-type substrate; An N-type buried layer is provided in the substrate; An N-type deep well is located above the N-type buried layer; The N-type deep well is provided with a first N-well, a first P-well and a second N-well from left to right in sequence; The N-type deep well is provided with a first N-well, a first P-well and a second N-well from left to right in sequence; the first N-well is provided with a first N+ injection and a first P+ injection from left to right in sequence; the first P-well is provided with a second P+ injection, a second N+ injection and a first gate, a third N+ injection and a second gate from left to right in sequence; there is a fourth N+ injection between the first N-well and the first shallow P-well; the second N-well is provided with an N+ injection; The first gate is between the second N+ injection and the third N+ injection, and the second gate is between the second N+ injection and the fourth N+ injection; The first N+ injection, the first P+ injection and the N+ injection in the first N well are connected together and serve as the anode of the device; the third N+ injection in the first P well and the second gate are connected together and serve as the cathode of the device; The first P+ injection, the second N+ injection and the third gate in the first P well are connected together through metal wires and are not connected to a potential.

2. The low trigger and high holding voltage thyristor electrostatic protection device according to claim 1, characterized in that: There are four field oxygen isolation zones; The first field oxygen isolation region is between the first N+ implant and the first P+ implant region, the second field oxygen isolation region is between the first P+ implant and the second P+ implant, the third field oxygen is between the second P+ implant and the second N+ implant, and the fourth field oxygen is between the fourth N+ implant and the fifth N+ implant.

3. The field oxygen isolation region according to claim 2, characterized in that: The first field oxygen isolation region is located on the surface of the first N-well; the second field oxygen isolation region is connected across the first N-well and the first P-well surfaces; the third field oxygen isolation region is located on the surface of the first P-well; and the fourth field oxygen isolation region is located on the surface of the second N-well.

4. The low trigger and high holding voltage thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection region, the first N well, and the first P well form a vertical PNP transistor, the first N well, the first P well, and the third N+ injection form a horizontal NPN transistor structure, and the third N+ injection, the first P well, and the fifth N+ injection form a horizontal NPN transistor.

5. The low trigger and high holding voltage thyristor electrostatic protection device according to claim 1, characterized in that: When the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, there are two breakdown planes, one is the reverse-biased PN junction composed of the first N-well and the second P-well, and the other is the reverse-biased PN junction composed of the first P-well and the fourth N+ injection. Since the BV of the second breakdown plane is lower and the distance between the anode and cathode is shorter, the avalanche breakdown occurs first on the second breakdown plane; after the avalanche breakdown occurs, the ESD current flows into the cathode through the fifth N+ injection, the second N-well, the fourth N+ injection, the first P-well, and the third N+ injection; and a voltage drop is formed on the equivalent resistance of the first P-well. When the voltage drop reaches 0.7V, the right-side horizontal NPN transistor is turned on and provides base current to the left-side vertical PNP transistor, thereby promoting its conduction, forming a positive feedback effect, and the device is successfully triggered.

6. The low trigger and high holding voltage thyristor electrostatic protection device according to claim 1, characterized in that: An NMOS is arranged in the first P well, and an ESD current forms a voltage drop on the equivalent resistance of the first P well. When the voltage drop reaches the threshold voltage of the MOS tube, the NMOS channel is opened, forming a surface path of a vertical PNP type triode connected in series with the NMOS, which is composed of the first P+ injection region, the first N well, and the first P well. This can effectively suppress the positive feedback effect of the SCR discharge path and improve the holding voltage of the device.

7. The thyristor electrostatic protection device with low triggering and high holding voltage according to claim 1, characterized in that: The size S1 of the second implanted P+ is adjustable, and when the distance S1 increases, the holding voltage of the device increases.

8. A method for manufacturing a thyristor electrostatic protection device with low triggering and high holding voltage, comprising the following steps: Step 1: forming an N-type buried layer in a P-type substrate; Step 2: Generate an N-type deep well above the N-type buried layer; Step 3: generating a first N-well and a first P-well in the first N-type deep well; Step 4: Generate a first N+ injection and a first P+ injection on the first N well from left to right; A second P+ injection, a second N+ injection, a first gate, a third N+ injection and a second gate are sequentially generated on the first P well from left to right; a fourth N+ injection region is generated between the first P well and the second N well to bridge the two wells; Step 5: Form a first field oxygen isolation region between the first N+ implant and the first P+ implant on the first N well, generate a second field oxygen between the first P+ implant across the first N well and the second P+ implant on the first P well, and generate a third field oxygen between the fourth N+ implant and the fifth N+ implant on the second N well. Step 6: Anneal all implanted areas to eliminate the migration of impurities in the implanted areas; Step 7: Connect the first N+ injection, the first P+ injection, and the fifth N+ injection together and use them as the anode of the device, connect the second P+ injection, the second N+ injection, and the first gate together without connecting any potential, and connect the third N+ injection and the second gate injection together and use them as the cathode of the device.

9. The method for manufacturing a low-trigger and high-maintenance thyristor electrostatic protection device according to claim 8, characterized in that: The following steps are also included before step one: growing a layer of silicon dioxide film on a P-type substrate, and then depositing a layer of silicon nitride; spin coating a photoresist layer on the wafer, exposing and developing it with a mask to form an isolation shallow groove; etching the silicon dioxide, silicon nitride and the isolation shallow groove to remove the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical polishing until the silicon nitride layer is formed to remove the silicon nitride layer.

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