Solar cell and preparation method thereof

Abstract

An embodiment of the present application relates to the field of solar cells and provides a solar cell and a preparation method thereof, the preparation method comprising: providing a substrate, the substrate comprising alternating metal areas and non-metal areas; forming a doped semiconductor layer on a first surface of the substrate; the doped semiconductor layer is doped with a first doping element; forming a metal paste on the surface of the doped semiconductor layer corresponding to the metal area; performing a first sintering treatment, the first sintering treatment being used to convert the metal paste into a metal conductive layer, and in the first sintering treatment, the metal elements in the metal paste diffuse into a partial thickness of the doped semiconductor layer; forming an electrode paste, the electrode paste being located on the surface of the first passivation layer corresponding to the metal area; performing a second sintering treatment, the second sintering treatment being used to convert the electrode paste into a first electrode, the first electrode being electrically connected to the metal conductive layer, wherein the ratio of the thickness of the metal conductive layer to the thickness of the first electrode is 1:4 to 1:5.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and more particularly to a solar cell and a method for preparing the same. Background Art

[0002] With the gradual depletion of fossil fuels, solar cells are becoming increasingly popular as a new energy alternative. Solar cells convert sunlight into electricity. They utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating the efficient use of electrical energy.

[0003] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated Emitter and Real Cell), and heterojunction cells. Different film layer configurations and functional limitations are used to reduce optical losses and lower the recombination of photogenerated carriers on the surface and in the silicon substrate, thereby improving the photoelectric conversion efficiency of solar cells.

[0004] However, the photoelectric conversion efficiency of current solar cells is still poor. Summary of the Invention

[0005] The embodiments of the present application provide a solar cell and a method for manufacturing the same, which are at least beneficial to improving the photoelectric conversion efficiency of the solar cell and reducing the manufacturing cost.

[0006] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a method for preparing a solar cell, comprising: providing a substrate, the substrate comprising a first surface and a second surface relative to each other, the substrate comprising alternating metal areas and non-metal areas; forming a doped semiconductor layer on the first surface of the substrate; the doped semiconductor layer is doped with a first doping element; forming a metal paste on the surface of the doped semiconductor layer corresponding to the metal area; performing a first sintering treatment, the first sintering treatment being used to convert the metal paste into a metal conductive layer, and in the first sintering treatment, the metal element in the metal paste diffuses into a partial thickness of the doped semiconductor layer; forming a first passivation layer, the first passivation layer being located on the surface of the metal conductive layer and on the doped semiconductor layer corresponding to the non-metal area; forming an electrode paste, the electrode paste being located on the surface of the first passivation layer corresponding to the metal area; performing a second sintering treatment, the second sintering treatment being used to convert the electrode paste into a first electrode, the first electrode being electrically connected to the metal conductive layer; wherein the ratio of the thickness of the metal conductive layer to the thickness of the first electrode is 1:4 to 1:5.

[0007] In some embodiments, before forming the doped semiconductor layer, the method further includes: forming a first tunneling dielectric layer on the first surface of the substrate, the doped semiconductor layer being located on the first tunneling dielectric layer; before forming the metal paste, the method further includes: forming a second tunneling dielectric layer on the second surface of the substrate; forming a doped conductive layer, the doped conductive layer being located on the surface of the second tunneling dielectric layer, the first doping element being one of an N-type doping element or a P-type doping element, and the doped conductive layer being doped with the other of the N-type doping element or the P-type doping element; forming a second passivation layer and a second electrode, the second passivation layer being located on the doped conductive layer, the second electrode being located on the second passivation layer, and the second electrode being electrically connected to the doped conductive layer.

[0008] In some embodiments, in the same preparation process, a metal paste is formed on the surface of the doped semiconductor layer corresponding to the metal area, and the metal paste is formed on the surface of the doped conductive layer corresponding to the metal area. The first sintering treatment is also used to diffuse the metal elements in the metal paste into a partial thickness of the doped conductive layer; the second passivation layer is also located on the metal conductive layer, and the second electrode is electrically connected to the metal conductive layer.

[0009] In some embodiments, the doping concentration of the first doping element is 2×e 20 cm -3 ~3×e 20 cm -3 , the thickness of the doped semiconductor layer is 100nm to 130nm.

[0010] In some embodiments, the metal paste includes: 0.3 wt% to 1 wt% of glass component, 90 wt% to 98 wt% of metal particles, 0.5 wt% to 3 wt% of binder, 0.5 wt% to 3 wt% of auxiliary agent and 0.5 wt% to 3 wt% of solvent.

[0011] In some embodiments, the metal particles are aluminum, copper, or silver.

[0012] In some embodiments, the process parameters of the first sintering treatment include: a sintering temperature of 750°C to 900°C, and a sintering time of 20s to 40s; the process parameters of the second sintering treatment include: a sintering temperature of 750°C to 900°C, and a sintering time of 20s to 60s.

[0013] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a solar cell, comprising: a substrate, the substrate comprising a first surface and a second surface relative to each other, the substrate comprising alternating metal areas and non-metal areas; a doped semiconductor layer, the doped semiconductor layer being located on the first surface of the substrate, the doped semiconductor layer being doped with a first doping element; a metal conductive layer, the metal conductive layer being located on the surface of the doped semiconductor layer corresponding to the metal area; a partial thickness of the doped semiconductor layer containing the metal elements of the metal conductive layer; a first passivation layer, the first passivation layer being located on the doped semiconductor layer in the non-metal area and on the surface of the metal conductive layer; a first electrode, the first electrode being located on the surface of the first passivation layer corresponding to the metal area, the first electrode being electrically connected to the metal conductive layer; wherein the ratio of the thickness of the metal conductive layer to the thickness of the first electrode is 1:4 to 1:5.

[0014] In some embodiments, it also includes: a first tunneling dielectric layer, the first tunneling dielectric layer is located between the first surface and the doped semiconductor layer; a second tunneling dielectric layer, the second tunneling dielectric layer is located on the second surface; a doped conductive layer, the doped conductive layer is located on the surface of the second tunneling dielectric layer; a second passivation layer, the second passivation layer is located on the doped conductive layer; a second electrode, the second electrode is located on the second passivation layer, and the second electrode is electrically connected to the doped conductive layer.

[0015] In some embodiments, the thickness of the metal conductive layer is 1 μm to 5 μm; the thickness of the first electrode is 4 μm to 8 μm.

[0016] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0017] In the technical solution provided in the embodiment of the present application, in the process of preparing a solar cell, a doped semiconductor layer is first formed on the surface of the substrate, and then a metal paste is formed on the surface of the doped semiconductor layer. In this way, the metal paste can serve as a contact layer, which can reduce the thickness and concentration of the doped semiconductor layer, thereby avoiding optical absorption and composite defects caused by the high doping concentration caused by the doped semiconductor layer. Secondly, the first electrode is designed to contact the metal conductive layer, and the ratio of the thickness of the finally formed metal conductive layer to the thickness of the first electrode is 1:4 to 1:5, which reduces the amount of electrode paste used, improves the degree of damage to the first passivation layer caused by the electrode paste, and the first passivation layer can play a better passivation effect. The amount of electrode paste used is reduced, which can reduce the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplified by the figures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A flow chart of a method for preparing a solar cell provided in one embodiment of the present application;

[0020] Figures 2 to 14 A cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in an embodiment of the present application;

[0021] Figure 15 A cross-sectional view of a laminated battery provided in yet another embodiment of the present application;

[0022] Figure 16 A schematic structural diagram of a photovoltaic module provided in yet another embodiment of the present application;

[0023] Figure 17 for Figure 16 A cross-section along the M1-M2 section. DETAILED DESCRIPTION

[0024] As known from the background art, the photoelectric conversion efficiency of current solar cells is poor.

[0025] An embodiment of the present application provides a method for preparing a solar cell, by adding a step of forming a metal paste on the surface of the doped semiconductor layer, and then forming a metal conductive layer through a first sintering treatment. In this way, the metal conductive layer can serve as an interface in contact with the first electrode to reduce the power loss caused to the solar cell by the doped semiconductor layer in contact with the metal conductive layer and the first electrode, thereby improving the photoelectric conversion efficiency of the solar cell and reducing the preparation cost.

[0026] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the description of the embodiments of this application, the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0029] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0030] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0031] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0032] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as "approximately" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0033] In the description of the embodiments of the present application, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therebetween. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located therebetween.

[0034] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "part" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0035] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0036] Figure 1 A flow chart of a method for preparing a solar cell provided in one embodiment of the present application.

[0037] refer to Figure 1 According to some embodiments of the present application, one aspect of the present application provides a method for fabricating a solar cell. The method includes providing a substrate, the substrate including a first surface and a second surface opposite each other, the substrate including alternating metal regions and non-metal regions. The method includes forming a doped semiconductor layer on the first surface of the substrate; the doped semiconductor layer is doped with a first doping element. The method includes forming a metal paste on the surface of the doped semiconductor layer corresponding to the metal region. The method includes performing a first sintering process, the first sintering process being used to convert the metal paste into a metal conductive layer, and during the first sintering process, the metal element in the metal paste diffuses into a portion of the thickness of the doped semiconductor layer. The method includes forming a first passivation layer, the first passivation layer being located on the surface of the metal conductive layer and on the doped semiconductor layer corresponding to the non-metal region. The method includes forming an electrode paste, the electrode paste being located on the surface of the first passivation layer corresponding to the metal region. The method includes performing a second sintering process, the second sintering process being used to convert the electrode paste into a first electrode, the first electrode being electrically connected to the metal conductive layer; wherein the ratio of the thickness of the metal conductive layer to the thickness of the first electrode is 1:4 to 1:5.

[0038] In the technical solution provided in the embodiment of the present application, in the process of preparing a solar cell, a doped semiconductor layer is first formed on the surface of the substrate, and then a metal paste is formed on the surface of the doped semiconductor layer. In this way, the metal paste can serve as a contact layer, which can reduce the thickness and concentration of the doped semiconductor layer, thereby avoiding optical absorption and composite defects caused by the high doping concentration caused by the doped semiconductor layer. Secondly, the first electrode is designed to contact the metal conductive layer, and the ratio of the thickness of the finally formed metal conductive layer to the thickness of the first electrode is 1:4 to 1:5, which reduces the amount of electrode paste used, improves the degree of damage to the first passivation layer caused by the electrode paste, and the first passivation layer can play a better passivation effect. The amount of electrode paste used is reduced, which can reduce the preparation cost.

[0039] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0040] Figures 2 to 14The following is a cross-sectional view of a solar cell corresponding to each step in a method for preparing a solar cell provided in one embodiment of the present application. Figures 2 to 7 The doped semiconductor layer is located on the front side of the substrate as an example, and the film layer structure on the back side of the substrate is not shown; Figure 8 The doped semiconductor layer is located on the back side of the substrate as an example, and the film layer structure on the front side of the substrate is not shown; Figures 9 to 14 The doped semiconductor layer is located on the front side of the substrate, and the back side of the substrate has a second tunnel dielectric layer and a doped conductive layer as an example. The above are all examples to assist in explaining the technical solution, which does not constitute a limitation on the scope of protection of the embodiments of this application and all technical solutions.

[0041] refer to Figure 2 The preparation method includes: providing a substrate 100, the substrate 100 includes a first surface 13 and a second surface 14 opposite to each other, and the substrate 100 includes metal areas 11 and non-metal areas 12 arranged alternately.

[0042] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be in a single crystalline state, a polycrystalline state, an amorphous state, or a microcrystalline state (a state having both single crystalline and amorphous states is referred to as a microcrystalline state). For example, silicon may be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0043] In some embodiments, the material of substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide, and the like. Substrate 100 may also be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0044] In some embodiments, the substrate 100 may be an N-type semiconductor substrate doped with an N-type dopant element, which may be any Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0045] In some embodiments, the solar cell is a single-sided cell, where the first surface 13 can serve as the light-receiving surface (front surface) for receiving incident light, and the second surface 14 serves as the backlight surface (back surface). The backlight surface can also receive incident light, but the efficiency of receiving the incident light is lower than that of the light-receiving surface.

[0046] In some embodiments, the metal region 11 refers to the first electrode 106 (refer to Figure 7 ) is located in the area where the orthographic projection on the substrate 100 is located, the non-metallic area 12 refers to the first electrode 106 (reference Figure 7 ) on the substrate 100. In order to ensure that the film layer contacted by the first electrode 106 has a high doping concentration or that the areas contacted by the first electrode 106 are all high-concentration areas, thereby reducing contact resistance, the area of ​​the metal region 11 is generally set to be greater than or equal to the area of ​​the orthographic projection of the first electrode 106 on the substrate 100. In other words, the orthographic projection area of ​​the first electrode 106 on the substrate 100 is smaller than the area of ​​the metal region, and the orthographic projection position must be within the metal region.

[0047] In some embodiments, the front surface of the substrate 100 has a velvet structure 111, which can increase the internal reflectivity of incident light, thereby improving the photoelectric conversion efficiency. The velvet structure 111 can include multiple protrusions 101. The protrusions 101 can be arranged adjacently or spaced apart, or stacked or partially overlapped. The embodiments of the present application do not limit the number, arrangement, or shape of the protrusions 101.

[0048] The velvet structure 111 can be obtained by performing a texturing treatment on one surface of the original substrate. The texturing treatment can include conventional methods such as solution texturing, laser texturing, and ion texturing.

[0049] refer to Figure 3 The preparation method includes: forming a doped semiconductor layer 102 on the first surface 13 of the substrate 100; and doping the doped semiconductor layer 102 with a first doping element.

[0050] In some embodiments, the doped semiconductor layer serves as an emitter, the first doping element is a P-type doping element, and the substrate is doped with an N-type doping element. By configuring the doped semiconductor layer as an emitter, the emitter's doping concentration can be reduced during the subsequent printing of a metal paste and formation of a metal conductive layer, thereby reducing the recombination rate between the high concentration and the substrate, thereby improving cell efficiency. For emitters in non-metallic regions, recombination losses caused by high concentrations can be reduced, and the short-wavelength effect of light can be enhanced, thereby improving photoelectric conversion efficiency.

[0051] In some embodiments, the original substrate may be subjected to a diffusion process to convert a portion of the thickness of the original substrate into a doped semiconductor layer, and the remaining original substrate serves as a substrate.

[0052] In some embodiments, a thin doped semiconductor layer is formed on the front surface of the substrate by a deposition process and serves as an emitter.

[0053] refer to Figure 4The preparation method includes forming a metal paste on the surface of the doped semiconductor layer corresponding to the metal region. This metal paste is subsequently used as a metal contact layer. By improving the contact performance between the first electrode and the metal contact layer, the contact performance between the first electrode and the doped semiconductor layer is improved, thereby reducing electrical losses and improving the photoelectric conversion efficiency of the solar cell.

[0054] In some embodiments, the metal paste includes: 0.3 wt% to 1 wt% of a glass component, 90 wt% to 98 wt% of metal particles, 0.5 wt% to 3 wt% of a binder, 0.5 wt% to 3 wt% of an additive, and 0.5 wt% to 3 wt% of a solvent. The formula of the metal paste can ensure that the metal paste and the doped semiconductor layer not only have contact at the contact interface, but also that the metal particles in the metal paste can form metal crystals, and the metal crystals are located in the doped semiconductor layer, thereby improving the contact performance between the metal conductive layer subsequently formed by the metal paste and the doped semiconductor layer, and forming new conductive channels between the metal crystals, so that carriers preferentially diffuse from the region with lower resistance, that is, the region of the conductive channel, to the first electrode, thereby reducing the path electrical loss, thereby improving the photoelectric conversion efficiency of the battery.

[0055] In some embodiments, the metal particles are aluminum, copper, or silver. When aluminum is used as the metal material, it not only serves as the metal material but also acts as an aluminum back surface field (when a P-type dopant element is doped within the doped semiconductor layer). In other words, the metal conductive layer also serves as part of the electrode, reducing the carrier recombination rate. When copper or silver is used as the metal particle, the metal particles themselves have excellent electrical conductivity and low electrical losses.

[0056] It should be noted that the metal slurry does not completely coat the metal area 11, that is, there is a certain distance between the edge of the metal slurry and the edge of the metal area 11 to prevent the metal elements in the metal slurry from diffusing into the non-metallic area 12. Those skilled in the art can design the distance between the edge of the metal slurry and the edge of the metal area according to actual conditions.

[0057] Continue to refer Figure 4 The preparation method includes: performing a first sintering process, the first sintering process is used to convert the metal paste into the metal conductive layer 121, and in the first sintering process, the metal elements in the metal paste diffuse into a partial thickness of the doped semiconductor layer 102.

[0058] Among them, reference Figure 5 , a part of the thickness of the doped semiconductor layer is used as a mixed doped film layer 122, that is, the mixed doped film layer 122 contains two doping elements, one is a metal element and the other is a P-type doping element, and the two doping elements constitute a mixed doped film layer.

[0059] It should be noted that the hybrid doped film layer 122 does not form a discrete film layer, but rather a partially doped conductive layer containing both a P-type dopant element and a metal element. In some embodiments, the hybrid doped film layer 122 more generally refers to a doped semiconductor layer containing a metal element. The relationship between the metal element and the elements in the doped semiconductor layer can be simply a mixed distribution, or a connection between some elements through interaction.

[0060] In some embodiments, the process parameters of the first sintering process include a sintering temperature of 750°C to 900°C and a sintering time of 20s to 40s. The first sintering process is primarily used to ensure good contact between the metal paste and the doped semiconductor layer without causing excessive thermal damage to the substrate. The first sintering process is also used to ensure that the metal elements are only or mostly in the doped semiconductor layer, thereby effectively avoiding PN junction leakage and excessive contact resistance.

[0061] refer to Figure 6 The preparation method includes: forming a first passivation layer 105 , the first passivation layer 105 is located on the surface of the metal conductive layer 121 and on the doped semiconductor layer 102 corresponding to the non-metallic area 12 .

[0062] In some embodiments, the first passivation layer 105 is formed by a deposition process, which may be LPCVD.

[0063] In some embodiments, the first passivation layer 105 may be a single-layer structure or a stacked-layer structure, and the material of the first passivation layer 105 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, titanium oxide, hafnium oxide, or aluminum oxide.

[0064] refer to Figure 7 The preparation method includes: forming an electrode slurry, and the electrode slurry is located on the surface of the first passivation layer 105 corresponding to the metal area 11.

[0065] In some embodiments, the electrode paste is printed on the surface of the first passivation layer using a screen printing process.

[0066] In some embodiments, the electrode slurry comprises: 0.3 wt% to 2 wt% glass, 85 wt% to 90 wt% metal particles, 1 wt% to 5 wt% binder, 1 wt% to 5 wt% additive, and 1 wt% to 5 wt% solvent. The components of the electrode slurry can migrate into the first passivation layer and connect with the metal conductive layer without excessively damaging the first passivation layer, thereby ensuring the integrity of the first passivation layer and improving the passivation performance of the first passivation layer. Furthermore, the electrode slurry contains less glass and silver than conventional slurries, reducing the production cost of the first electrode.

[0067] In some embodiments, the electrode slurry may be sintered from LECO (Laser-enhanced contact optimization) slurry, and part of the LECO slurry corrodes and penetrates the first passivation layer 105 and forms an electrical connection with the metal conductive layer 121 or with the metal conductive layer 121 through crystals.

[0068] It should be noted that the printing area of ​​the electrode paste is larger than the printing area of ​​the metal paste, or the printing line width of the electrode paste is larger than the line width of the metal paste.

[0069] Compared with the printing height of the electrode paste of conventional solar cells (7μm~12μm), in the solution provided in the embodiment of the present application, the printing height of the electrode paste can be reduced to 4μm~8μm, which can reduce the amount of electrode paste used and thus reduce the preparation cost.

[0070] refer to Figure 7 The preparation method includes: performing a second sintering treatment, the second sintering treatment is used to convert the electrode slurry into a first electrode 106, the first electrode 106 is electrically connected to the metal conductive layer 121; the ratio of the thickness of the metal conductive layer 121 to the thickness of the first electrode 106 is 1:4 to 1:5.

[0071] In some embodiments, process parameters of the second sintering process include: a sintering temperature of 750° C. to 900° C., and a sintering time of 20 seconds to 60 seconds.

[0072] In some embodiments, the ratio of the thickness of the metal conductive layer 121 to the thickness of the first electrode 106 is 1:4 to 1:4.3, 1:4.3 to 1:4.6, 1:4.6 to 1:4.8, or 1:4.8 to 1:5. The ratio of the thickness of the metal conductive layer 121 to the thickness of the first electrode 106 can be 1:4.1, 1:4.4, 1:4.6, or 1:4.9.

[0073] Some embodiments of the present application also provide a method for preparing a solar cell, which is similar to the above embodiment ( Figures 2 to 7 ) is that, Figure 7 The doped semiconductor layer in the solar cell shown is located on the first side, and the first side is the front side; Figure 8 The doped semiconductor layer shown is located on the first surface, and the first surface is the back surface, and there is a first tunnel dielectric layer between the doped semiconductor layer and the substrate. The same parts as the above embodiment will not be described in detail here. Figure 8 Mainly talk about different parts.

[0074] refer to Figure 8The preparation method includes providing a substrate 200, wherein the substrate 200 includes a first surface 23 and a second surface 24 opposite to each other, and the substrate 200 includes alternating metal regions 21 and non-metal regions 22. The front surface of the substrate 200 has a suede structure 211, which can increase the internal reflectivity of incident light, thereby improving the photoelectric conversion efficiency. The suede structure 211 can include a plurality of protrusions 201.

[0075] refer to Figure 8 The preparation method includes: forming a first tunnel dielectric layer 203 on the first surface 23 of the substrate 200. The preparation method includes: forming a doped semiconductor layer 202; doping the doped semiconductor layer 202 with a first doping element; and positioning the doped semiconductor layer 202 on the first tunnel dielectric layer 203.

[0076] The doped semiconductor layer 202 is a doped polysilicon layer, a doped amorphous silicon layer or a doped microcrystalline silicon layer. The first doping element has the same conductivity type as the doping element of the substrate.

[0077] The first tunneling dielectric layer 203 and the doped semiconductor layer 202 form a passivation contact structure. Due to the special energy band structure of the passivation contact structure, the doped semiconductor layer 202 is in electrical contact with the substrate 200, causing the energy band of the substrate 100 to bend downward, thereby reducing the electron transmission barrier. Therefore, the ultra-thin first tunneling dielectric layer 203 can allow majority carriers to tunnel while blocking minority carriers from penetrating, thereby separating electrons and holes, reducing recombination, and lowering the recombination rate.

[0078] Specifically, the ultrathin first tunneling dielectric layer 203 causes an asymmetric shift in the energy bands on the surface of the substrate 100, resulting in a lower barrier to majority carriers than to minority carriers. Consequently, majority carriers can more easily undergo quantum tunneling through the first tunneling dielectric layer 203, while minority carriers have difficulty passing through the first tunneling dielectric layer 203, thereby achieving selective carrier transport. Secondly, the first tunneling dielectric layer 203 acts as a chemical passivation agent. Due to the presence of interface state defects at the interface between the substrate 200 and the first tunneling dielectric layer 203, the interface state density on the surface of the substrate 100 is relatively high. This increased interface state density promotes the recombination of photogenerated carriers, increasing the fill factor, short-circuit current, and open-circuit voltage of the solar cell, thereby improving the solar cell's photoelectric conversion efficiency. In other words, the first tunneling dielectric layer 203 reduces the carrier recombination rate by saturating the dangling bonds of the substrate 200, reducing the defect state density in the substrate 200, and reducing the number of recombination centers in the substrate 200.

[0079] In some embodiments, the thickness of the first tunneling dielectric layer 203 is 0.5 nm to 10 nm. The thickness of the first tunneling dielectric layer 203 ranges from 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 10 nm. When the thickness of the first tunneling dielectric layer 203 is within any of the above ranges, the first tunneling dielectric layer 203 is thinner, and majority carriers can more easily quantum tunnel through the first tunneling dielectric layer 203, while minority carriers have difficulty passing through the first tunneling dielectric layer 203, thereby achieving selective carrier transmission.

[0080] In some embodiments, the material of the first tunnel dielectric layer 203 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0081] The doped semiconductor layer 202 has a field passivation effect. Specifically, an electrostatic field directed toward the interior of the substrate 100 is formed on the surface of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and the carrier recombination rate at the interface of the substrate 100. This increases the open circuit voltage, short circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0082] In some embodiments, the doping concentration of the first doping element is 2×e 20 cm -3 ~3×e 20 cm -3 The thickness of the doped semiconductor layer is 100nm to 130nm. The conventional doping concentration of the first doping element (without metal paste) is 3×e 20 cm -3 ~5×e 20 cm -3 The thickness of the doped semiconductor layer is 130 nm to 150 nm. The solar cell provided by the embodiment of the present application can set the thickness of the doped semiconductor layer 202 to be thinner, thereby avoiding optical absorption caused by the doped semiconductor layer 202.

[0083] Continue to refer Figure 8The preparation method includes: forming a metal paste on the surface of the doped semiconductor layer 202 corresponding to the metal region 21. The preparation method includes: performing a first sintering process, the first sintering process is used to convert the metal paste into a metal conductive layer 221, and in the first sintering process, the metal elements in the metal paste diffuse into a portion of the thickness of the doped semiconductor layer 202. The preparation method includes: forming a first passivation layer 205, the first passivation layer 205 is located on the surface of the metal conductive layer 221 and the doped semiconductor layer 202 corresponding to the non-metallic region 22. The preparation method includes: forming an electrode paste, the electrode paste is located on the surface of the first passivation layer 205 corresponding to the metal region 21. The preparation method includes: performing a second sintering process, the second sintering process is used to convert the electrode paste into a first electrode 206, the first electrode 206 is electrically connected to the metal conductive layer 221; the ratio of the thickness of the metal conductive layer 221 to the thickness of the first electrode 206 is 1:4 to 1:5.

[0084] Among them, the formation of metal paste, the first sintering treatment, the formation of the first passivation layer, the formation of electrode paste and the second sintering treatment can refer to the description of the formation of metal paste, the first sintering treatment, the formation of the first passivation layer, the formation of electrode paste and the second sintering treatment in the previous embodiment, and will not be described in detail here.

[0085] It should be noted that the above-mentioned film layers can be located on the front or back of the substrate. Figure 7 The film layers are located on the front side. Figure 8 The layers in FIG are located on the back side, for example only. In other words, Figure 7 The layers shown can be on the back side. Figure 8 The film layers in the embodiment may be located on the front side, and in one embodiment may include Figure 7 and Figure 8 Or just one.

[0086] Accordingly, the present invention also provides a method for preparing a solar cell, comprising the above-mentioned embodiment. Figure 7 and Figure 8 The method shown below will be combined with Figures 9 to 14 The same parts as the above embodiments will not be described in detail.

[0087] refer to Figure 9 The preparation method includes providing a substrate 300, wherein the substrate 300 includes a first surface 33 and a second surface 34 opposite to each other, and the substrate 300 includes metal regions 31 and non-metal regions 33 arranged alternately. The front surface of the substrate 300 has a suede structure 311, which can increase the internal reflectivity of incident light, thereby improving the photoelectric conversion efficiency. The suede structure 311 can include a plurality of protrusions 301.

[0088] refer to Figure 10 The preparation method includes: forming a first tunnel dielectric layer 303 on the first surface 33 of the substrate 300. The preparation method includes: forming a doped semiconductor layer 302 doped with a first doping element; and forming the doped semiconductor layer 302 on the first tunnel dielectric layer 303.

[0089] Continue to refer Figure 10 The preparation method includes: forming a second tunneling dielectric layer 331 on the second surface 34 of the substrate 300; forming a doped conductive layer 332, wherein the doped conductive layer 332 is located on the surface of the second tunneling dielectric layer 331, the first doping element is one of an N-type doping element or a P-type doping element, and the doped conductive layer 332 is doped with the other of the N-type doping element or the P-type doping element.

[0090] It should be noted that the first tunnel dielectric layer 303 and the second tunnel dielectric layer 331 may refer to the description of the first tunnel dielectric layer 203 in the previous embodiment. The doped conductive layer 332 may refer to the description of the doped semiconductor layer 202 in the previous embodiment.

[0091] In some embodiments, a first tunnel dielectric layer 303 is formed on the first side of the substrate, and a second tunnel dielectric layer 331 is formed on the second side of the substrate in the same fabrication process. In this way, a TOPCon structure can be formed on both sides of the substrate, thereby improving the passivation effect and thereby increasing the photoelectric conversion efficiency of the cell.

[0092] refer to Figure 11 In the same preparation process, a metal paste is formed on the surface of the doped semiconductor layer corresponding to the metal area, and a metal paste is formed on the surface of the doped conductive layer corresponding to the metal area. The first sintering treatment is also used to diffuse the metal elements in the metal paste into the doped conductive layer of partial thickness.

[0093] refer to Figure 12 The preparation method includes: forming a first passivation layer 305 , the first passivation layer 305 is located on the surface of the metal conductive layer 321 and on the doped semiconductor layer 302 corresponding to the non-metallic area 32 .

[0094] Continue to refer Figure 12 , forming a second passivation layer 315 , the second passivation layer 315 is located on the surface of the metal conductive layer 321 and on the doped conductive layer 332 corresponding to the non-metallic area 32 .

[0095] refer to Figure 13The preparation method includes forming an electrode paste, the electrode paste being disposed on a surface of the first passivation layer 305 corresponding to the metal region 31. The preparation method includes performing a second sintering process, the second sintering process being used to transform the electrode paste into a first electrode 306, the first electrode 306 being electrically connected to the metal conductive layer 321; the ratio of the thickness of the metal conductive layer 321 to the thickness of the first electrode 306 being 1:4 to 1:5.

[0096] Continue to refer Figure 13 The preparation method includes: forming a second electrode 316, the second electrode 316 is located on the second passivation layer 315, and the second electrode 316 is electrically connected to the metal conductive layer.

[0097] Among them, the formation of metal paste, the first sintering treatment, the formation of the first passivation layer, the formation of electrode paste and the second sintering treatment can refer to the description of the formation of metal paste, the first sintering treatment, the formation of the first passivation layer, the formation of electrode paste and the second sintering treatment in the previous embodiment, and will not be described in detail here.

[0098] In other embodiments, metal paste is formed only on the doped semiconductor layer, but not on the doped conductive layer; the preparation method includes: forming a second passivation layer and a second electrode, the second passivation layer is located on the doped conductive layer, the second electrode is located on the second passivation layer, and the second electrode is electrically connected to the doped conductive layer.

[0099] In some embodiments, reference Figure 14 Before forming the first tunnel dielectric layer, the method further includes: forming a diffusion layer 310 on the first surface of the substrate, and the first tunnel dielectric layer 303 is located on the diffusion layer 310 .

[0100] In the technical solution provided in the embodiment of the present application, in the process of preparing a solar cell, a doped semiconductor layer is first formed on the surface of the substrate, and then a metal paste is formed on the surface of the doped semiconductor layer. In this way, the metal paste can serve as a contact layer, which can reduce the thickness and concentration of the doped semiconductor layer, thereby avoiding optical absorption and composite defects caused by the high doping concentration caused by the doped semiconductor layer. Secondly, the first electrode is designed to contact the metal conductive layer, and the ratio of the thickness of the finally formed metal conductive layer to the thickness of the first electrode is 1:4 to 1:5, which reduces the amount of electrode paste used, improves the degree of damage to the first passivation layer caused by the electrode paste, and the first passivation layer can play a better passivation effect. The amount of electrode paste used is reduced, which can reduce the preparation cost.

[0101] The beneficial effects of the embodiments of the present application will be further illustrated below in combination with examples and comparative examples.

[0102] Blank example: A solar cell prepared using conventional methods. The substrate includes, from top to bottom, a first electrode, a first passivation layer, a doped semiconductor layer, a first tunnel dielectric layer, a substrate, a second tunnel dielectric layer, a doped conductive layer, a second passivation layer, and a second electrode. The first electrode is electrically connected to the doped semiconductor layer, and the second electrode is electrically connected to the doped conductive layer. The thickness of the first electrode is 7 μm, the thickness of the doped semiconductor layer is 130 nm, and the doping concentration of the doped semiconductor layer is 3.5×e 20 cm -3 The thickness of the doped conductive layer is 145 nm, and the doping concentration of the doped semiconductor layer is 4×e 20 cm -3 , the thickness of the second electrode is 10 μm.

[0103] Example 1: A metal conductive layer is prepared using a metal slurry method. The substrate comprises, from top to bottom, a first electrode, a first passivation layer, a metal conductive layer, a doped semiconductor layer, a first tunnel dielectric layer, a substrate, a second tunnel dielectric layer, a doped conductive layer, a second passivation layer, and a second electrode, wherein the first electrode is electrically connected to the metal conductive layer, and the second electrode is electrically connected to the doped conductive layer. The thickness of the first electrode is 5 μm, the thickness of the metal conductive layer is 1.5 μm, the thickness of the doped semiconductor layer is 105 nm, and the doping concentration of the doped semiconductor layer is 2.5×e 20 cm -3 The thickness of the doped conductive layer is 145 nm, and the doping concentration of the doped semiconductor layer is 4×e 20 cm -3 , the thickness of the second electrode is 10 μm.

[0104] Example 2: A metal conductive layer is prepared using a metal slurry method. The substrate comprises, from top to bottom, a first electrode, a first passivation layer, a doped semiconductor layer, a first tunnel dielectric layer, a substrate, a second tunnel dielectric layer, a doped conductive layer, a metal conductive layer, a second passivation layer, and a second electrode. The first electrode is electrically connected to the doped semiconductor layer, and the second electrode is electrically connected to the metal conductive layer. The thickness of the first electrode is 5 μm, the thickness of the metal conductive layer is 1.5 μm, the thickness of the doped semiconductor layer is 105 nm, and the doping concentration of the doped semiconductor layer is 2.5×e 20 cm -3 The thickness of the doped conductive layer is 145 nm, and the doping concentration of the doped semiconductor layer is 4×e 20 cm -3 , the thickness of the second electrode is 10 μm.

[0105] Example 3: A metal conductive layer is prepared using a metal slurry method. The substrate includes, from top to bottom, a first electrode, a first passivation layer, a metal conductive layer, a doped semiconductor layer, a first tunnel dielectric layer, a substrate, a second tunnel dielectric layer, a doped conductive layer, a metal conductive layer, a second passivation layer, and a second electrode, wherein the first electrode is electrically connected to the metal conductive layer, and the second electrode is electrically connected to the metal conductive layer. The thickness of the first electrode is 5 μm, the thickness of the metal conductive layer is 1.5 μm, the thickness of the doped semiconductor layer is 105 nm, and the doping concentration of the doped semiconductor layer is 2.5×e 20 cm -3 The thickness of the doped conductive layer is 105 nm, and the doping concentration of the doped semiconductor layer is 2.5×e 20 cm -3 , the thickness of the second electrode is 5 μm.

[0106] Comparative Example 1: The difference from Example 3 is that a metal conductive layer is directly formed on the surface of the doped semiconductor layer using a metal thin film deposition process instead of a metal slurry method.

[0107] Comparative Example 2: The difference from Example 3 is that: the metal slurry is only dried and the first sintering process is not performed; only one sintering process is provided, namely the second sintering process.

[0108] The photoelectric conversion efficiency and preparation cost of the above examples and comparative examples were summarized and calculated in turn, and the test results were summarized and recorded in Table 1. In Table 1, the increase ratio of photoelectric conversion efficiency / blank example is the ratio of the increase of the examples and comparative examples compared with the blank example to the blank example, and the reduction ratio of preparation cost is the ratio of the reduction of the examples and comparative examples compared with the blank example to the blank example.

[0109] Table 1

[0110] project Photoelectric conversion efficiency / increase ratio of blank case Reduction ratio of preparation cost Example 1 0.09％ 5％ Example 2 0.08％ 5％ Example 3 0.13％ 7％ Comparative Example 1 -0.05％ 5％ Comparative Example 2 -0.01％ 8％

[0111] From the comparison between the above embodiment and comparative examples 1-2, it can be seen that the design of the metal paste and the sintering process of this solution can improve the photoelectric conversion efficiency of the solar cell and reduce the preparation cost.

[0112] Accordingly, according to some embodiments of the present application, the embodiments of the present application also provide a solar cell, which can be prepared using the solar cell preparation method disclosed in the above embodiments. The technical features that are the same or corresponding to the above embodiments will not be described in detail here.

[0113] refer to Figure 7The solar cell includes: a substrate 100, the substrate 100 includes a first surface 13 and a second surface 14 opposite to each other, the substrate 100 includes alternating metal regions 11 and non-metal regions 12; a doped semiconductor layer 102, the doped semiconductor layer 102 is located on the first surface 13 of the substrate 100, and the doped semiconductor layer 102 is doped with a first doping element; a metal conductive layer 121, the metal conductive layer 121 is located on the surface of the doped semiconductor layer 102 corresponding to the metal region 11, and a portion of the thickness of the doped semiconductor layer 102 contains the metal element of the metal conductive layer 121; a first passivation layer 105, the first passivation layer 105 is located on the doped semiconductor layer 102 in the non-metal region 12 and on the surface of the metal conductive layer 121; a first electrode 106, the first electrode 106 is located on the surface of the first passivation layer 105 corresponding to the metal region 11, and the first electrode 106 is electrically connected to the metal conductive layer 121; wherein the ratio of the thickness of the metal conductive layer 121 to the thickness of the first electrode 106 is 1:4 to 1:5.

[0114] refer to Figure 8 The solar cell includes a substrate 200, which includes a first surface 23 and a second surface 24 opposite to each other and includes alternating metal regions 21 and non-metal regions 22; a doped semiconductor layer 202, which is located on the first surface 23 of the substrate 200 and is doped with a first doping element; and a first tunneling dielectric layer 203, which is located between the first surface 23 and the doped semiconductor layer 202. The solar cell includes: a metal conductive layer 221, the metal conductive layer 221 is located on the surface of the doped semiconductor layer 202 corresponding to the metal area 21, and the metal elements of the metal conductive layer 221 are contained in a partial thickness of the doped semiconductor layer 202; a first passivation layer 205, the first passivation layer 205 is located on the doped semiconductor layer 202 in the non-metallic area 22 and on the surface of the metal conductive layer 221; a first electrode 206, the first electrode 206 is located on the surface of the first passivation layer 205 corresponding to the metal area 21, and the first electrode 206 is electrically connected to the metal conductive layer 221; wherein the ratio of the thickness of the metal conductive layer 221 to the thickness of the first electrode 206 is 1:4 to 1:5.

[0115] In some embodiments, the solar cell further includes: a second tunneling dielectric layer, the second tunneling dielectric layer is located on the second surface; a doped conductive layer, the doped conductive layer is located on the surface of the second tunneling dielectric layer; a second passivation layer, the second passivation layer is located on the doped conductive layer; and a second electrode, the second electrode is located on the second passivation layer, and the second electrode is electrically connected to the doped conductive layer.

[0116] refer to Figure 13The solar cell includes a substrate 300, which includes a first surface 33 and a second surface 34 opposite to each other and includes alternating metal regions 31 and non-metal regions 32; a doped semiconductor layer 302, which is located on the first surface 33 of the substrate 300 and is doped with a first doping element; and a first tunneling dielectric layer 303, which is located between the first surface 23 and the doped semiconductor layer 302. The solar cell includes: a metal conductive layer 321, which is located on the surface of the doped semiconductor layer 302 corresponding to the metal area 31, and the metal elements of the metal conductive layer 321 are contained in a partial thickness of the doped semiconductor layer 302; a first passivation layer 305, which is located on the doped semiconductor layer 302 in the non-metallic area 32 and on the surface of the metal conductive layer 321; a first electrode 306, which is located on the surface of the first passivation layer 305 corresponding to the metal area 31, and is electrically connected to the metal conductive layer 321; wherein the ratio of the thickness of the metal conductive layer 321 to the thickness of the first electrode 306 is 1:4 to 1:5.

[0117] Continue to refer Figure 13 The solar cell includes: a second tunneling dielectric layer 331, which is located on the second surface 34; a doped conductive layer 332, which is located on the surface of the second tunneling dielectric layer 331; a metal conductive layer 321 is also located between the doped conductive layer 332 and the second passivation layer 315, and a second alloy layer is provided between the metal conductive layer 321 and the doped conductive layer 332; a second passivation layer 315, which is located on the doped conductive layer 332; and a second electrode 316, which is located on the second passivation layer 315 and is electrically connected to the metal conductive layer 321.

[0118] In some embodiments, reference Figure 14 The solar cell further includes a diffusion layer 310 , which is located between the first surface 33 and the first tunneling dielectric layer 303 .

[0119] In some embodiments, the thickness of the metal conductive layer 321 is 1 μm to 5 μm; the thickness of the first electrode 306 is 4 μm to 8 μm.

[0120] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a laminated battery.

[0121] Figure 15 A cross-sectional view of a laminated battery provided in another embodiment of the present application. Figure 13 A solar cell is shown as an example.

[0122] refer to Figure 15The stacked battery includes: a bottom battery 150, which is a solar cell prepared by the preparation method of any one of the above embodiments or a solar cell of any one of the above embodiments; a top battery, which is located on the side of the substrate 300 in the bottom battery 150 away from the first electrode 306.

[0123] In some embodiments, the stacked battery has a first gridline 186 of a first polarity and a second gridline of a second polarity, wherein the first gridline 186 is in electrical contact with the top battery 180 and the second gridline is in electrical contact with the bottom battery 150. The second gridline is the first electrode 306 of the bottom battery.

[0124] In some embodiments, an interface layer 181 is provided between the top cell and the bottom cell. The interface layer 181 also covers the passivation contact structure on the back side, that is, covers the doped conductive layer 332 .

[0125] It is worth noting that the stacked cells in the embodiments of the present application only illustrate two layers of solar cells. Those skilled in the art can set three layers of solar cells or multi-layer stacked solar cells with more than three layers according to actual needs.

[0126] In some embodiments, the top cell 180 may be a perovskite solar cell, which includes a stacked first transmission layer 182, a perovskite substrate 183, a second transmission layer 184, a transparent conductive layer 185, and an anti-reflection layer (not shown). The first transmission layer is directly opposite to the bottom cell.

[0127] In some embodiments, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0128] Accordingly, according to some embodiments of the present application, the embodiments of the present application further provide a photovoltaic component, including the solar cell provided by the above embodiments, and the technical features that are the same as or corresponding to the above embodiments are not described in detail here.

[0129] Figure 16 A schematic structural diagram of a photovoltaic module provided in yet another embodiment of the present application; Figure 17 for Figure 16 A cross-section along the M1-M2 section.

[0130] refer to Figure 16 and Figure 17 The photovoltaic module includes: a cell string, which is formed by connecting multiple solar cells 40 prepared by the preparation method of any one of the above embodiments, the solar cells 40 of any one of the above embodiments, or the stacked cells of the above embodiments; an encapsulation film 41, which is used to cover the surface of the cell string; and a cover plate 42, which is used to cover the surface of the encapsulation film 41 facing away from the cell string.

[0131] Specifically, in some embodiments, multiple cells can be electrically connected via a connecting member 418, which is welded to a busbar on the cell. The busbar includes a main electrode electrically connected to the first electrode 306 and a main electrode electrically connected to the second electrode 316.

[0132] In some embodiments, no space is provided between the battery cells, ie, the battery cells overlap with each other.

[0133] In some embodiments, the connecting component 418 is welded to the secondary grid 408 on the solar cell, and the secondary grid 408 includes the first electrode 306 and the second electrode 316 .

[0134] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front or back sides of the solar cell, and the second encapsulation layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastomer (POE) film or polyethylene terephthalate (PET) film.

[0135] It is worth noting that there is a dividing line between the first encapsulation layer and the second encapsulation layer before the lamination process. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0136] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other light-transmitting cover plate. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 can be a concave-convex surface to increase the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, with the first cover plate facing the first encapsulation layer and the second cover plate facing the second encapsulation layer; alternatively, the first cover plate faces one side of the solar cell and the second cover plate faces the other side of the solar cell.

[0137] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising metal areas and non-metal areas arranged alternately; forming a doped semiconductor layer on the first surface of the substrate; the doped semiconductor layer is doped with a first doping element; forming a metal paste on a surface of the doped semiconductor layer corresponding to the metal region; Performing a first sintering process, wherein the first sintering process is used to convert the metal paste into a metal conductive layer, and in the first sintering process, the metal elements in the metal paste diffuse into a partial thickness of the doped semiconductor layer; forming a first passivation layer, wherein the first passivation layer is located on a surface of the metal conductive layer and on the doped semiconductor layer corresponding to the non-metallic region; forming an electrode paste, wherein the electrode paste is located on a surface of the first passivation layer corresponding to the metal region; A second sintering process is performed, wherein the second sintering process is used to convert the electrode slurry into a first electrode, and the first electrode is electrically connected to the metal conductive layer; wherein the ratio of the thickness of the metal conductive layer to the thickness of the first electrode is 1:4~1:

5.

2. The preparation method according to claim 1, characterized in that Before forming the doped semiconductor layer, the method further includes: forming a first tunnel dielectric layer on the first surface of the substrate, wherein the doped semiconductor layer is located on the first tunnel dielectric layer; and before forming the metal paste, the method further includes: forming a second tunneling dielectric layer on the second surface of the substrate; forming a doped conductive layer, the doped conductive layer being located on a surface of the second tunneling dielectric layer, the first doping element being one of an N-type doping element and a P-type doping element, and the doped conductive layer being doped with the other of the N-type doping element and the P-type doping element; A second passivation layer and a second electrode are formed, wherein the second passivation layer is located on the doped conductive layer, the second electrode is located on the second passivation layer, and the second electrode is electrically connected to the doped conductive layer.

3. The preparation method according to claim 2, characterized in that In the same preparation process, a metal paste is formed on the surface of the doped semiconductor layer corresponding to the metal area, and the metal paste is formed on the surface of the doped conductive layer corresponding to the metal area. The first sintering treatment is used to convert the metal paste located on the doped conductive layer into a metal conductive layer, and is also used to diffuse the metal elements in the metal paste into a partial thickness of the doped conductive layer; the second passivation layer is also located on the metal conductive layer, and the second electrode is electrically connected to the metal conductive layer located on the doped conductive layer.

4. The preparation method according to claim 2, characterized in that The doping concentration of the first doping element is 2×e 20 cm -3 ~3×e 20 cm -3 , the thickness of the doped semiconductor layer is 100nm~130nm.

5. The preparation method according to claim 1, characterized in that The metal paste includes: 0.3wt% to 1wt% of glass component, 90wt% to 98wt% of metal particles, 0.5wt% to 3wt% of adhesive, 0.5wt% to 3wt% of auxiliary agent and 0.5wt% to 3wt% of solvent.

6. The preparation method according to claim 5, characterized in that The metal particles are aluminum, copper or silver.

7. The preparation method according to claim 1 or 5, characterized in that The process parameters of the first sintering treatment include: sintering temperature of 750°C to 900°C, and sintering time of 20s to 40s; the process parameters of the second sintering treatment include: sintering temperature of 750°C to 900°C, and sintering time of 20s to 60s.

8. A solar cell prepared by the preparation method according to any one of claims 1 to 7, characterized in that: include: A substrate, comprising a first surface and a second surface opposite to each other, and comprising metal areas and non-metal areas arranged alternately; a doped semiconductor layer, the doped semiconductor layer being located on the first surface of the substrate and being doped with a first doping element; a metal conductive layer, the metal conductive layer being located on a surface of the doped semiconductor layer corresponding to the metal region; a portion of the doped semiconductor layer having a metal element of the metal conductive layer; a first passivation layer, the first passivation layer being located on the doped semiconductor layer in the non-metallic region and on a surface of the metal conductive layer; A first electrode is located on a surface of the first passivation layer corresponding to the metal area, and the first electrode is electrically connected to the metal conductive layer; wherein a ratio of a thickness of the metal conductive layer to a thickness of the first electrode is 1:4 to 1:

5.

9. The solar cell according to claim 8, characterized in that Also includes: a first tunneling dielectric layer, wherein the first tunneling dielectric layer is located between the first surface and the doped semiconductor layer; a second tunneling dielectric layer, wherein the second tunneling dielectric layer is located on the second surface; a doped conductive layer, wherein the doped conductive layer is located on a surface of the second tunneling dielectric layer; a second passivation layer, the second passivation layer being located on the doped conductive layer; A second electrode is located on the second passivation layer, and the second electrode is electrically connected to the doped conductive layer.

10. The solar cell according to claim 8, wherein The thickness of the metal conductive layer is 1 μm to 5 μm; the thickness of the first electrode is 4 μm to 8 μm.

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