An asymmetric trench gate display sensing module and a manufacturing method thereof

Abstract

The present application relates to the technical field of display manufacturing, and particularly relates to an asymmetric trench gate type display sensing module and a manufacturing method thereof. The asymmetric trench gate type display sensing module comprises: a plurality of pixels, each pixel comprising a light emitting area and an image sensing area, the light emitting area comprising three light emitting diodes, and the image sensing area comprising three image sensing units; a driving back plate, the driving back plate being provided with a plurality of regularly arranged through holes, the light emitting diodes and the image sensing units covering at least one through hole, the driving back plate bearing the plurality of pixels and driving the light emitting diodes to emit light, and the light emitting diodes emitting light according to the configuration of the image sensing units. The asymmetric trench gate type display sensing module is prepared by using a semiconductor process, which can not only realize the display function of high resolution, high brightness, high contrast and low response time, but also can receive real-time external full-color images, thereby providing a feasible solution for single-chip integration of interactive display.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display manufacturing technology, and particularly relates to an asymmetric trench gate type display sensing module and a manufacturing method thereof. BACKGROUND

[0002] With the pursuit of visual experience by consumers, high-definition display products are increasingly popular, which promotes the development of display technology in the direction of higher resolution, higher brightness, higher contrast and low response time. However, if the display sensing module of the prior art needs to receive real-time external full-color images, it needs to be processed synchronously through specific software.

[0003] If the asymmetric trench gate type display sensing module is mounted, the display and image sensing are integrated on one device, which provides a feasible solution for single-chip integration of interactive display. SUMMARY

[0004] The present application solves the technical problem of the prior art in the background art, and provides an asymmetric trench gate type display sensing module and a manufacturing method thereof.

[0005] The technical solution adopted by the present application to solve the technical problem is: an asymmetric trench gate type display sensing module, comprising:

[0006] a plurality of pixels, each pixel comprising a light-emitting area and an image sensing area, the light-emitting area comprising three light-emitting diodes, namely a red light-emitting diode, a green light-emitting diode and a blue light-emitting diode, and the image sensing area comprising three image sensing units, namely a red image sensing unit, a green image sensing unit and a blue image sensing unit;

[0007] a driving backplate, the driving backplate being provided with a plurality of regularly arranged through holes, the light-emitting diodes and the image sensing units covering at least one through hole, the driving backplate carrying a plurality of pixels and driving the light-emitting diodes to emit light, and the light-emitting diodes emitting light according to the configuration of the image sensing units;

[0008] The light-emitting diodes and the image sensing units each comprise an anode, a semiconductor device and an ITO thin film layer, the anode being located on the driving backplate and covering at least one through hole, the semiconductor device being located on the side of the anode away from the driving backplate,

[0009] The semiconductor device has an N-type high-doped region and an N-type epitaxial layer, the N-type high-doped region is located on the side of the anode far from the driving backboard, the N-type epitaxial layer is formed on the N-type high-doped region, an asymmetric P+ region is formed by ion implantation on the N-type epitaxial layer or a symmetric P+ region is formed by ion implantation on the N-type epitaxial layer and etching to form an asymmetric groove, a gate oxide layer is arranged on the surface of the groove, and a polysilicon gate is deposited in the groove with the gate oxide layer.

[0010] Further, the asymmetric P+ region includes a first P+ region located in the middle of the left half of the N-type epitaxial layer and a second P+ region located on the upper part of the right half, a P-well region is formed on the upper part of the first P+ region, an N+ region is formed on the P-well region, and the upper surface of the N+ region is flush with the upper surface of the second P+ region.

[0011] Further, a groove is arranged between the middle section of the plane where the upper surface of the N+ region is located and the plane where the upper surface of the first P+ region is located, a gate oxide layer is arranged on the surface of the groove, a metal layer is arranged above the plane where the upper surface of the N+ region is located, and an ITO thin film layer is arranged on the metal layer.

[0012] Further, the N-type epitaxial layer is formed with a left P+ region, a middle P+ region and a right P+ region, a groove is etched on the right side of the left P+ region and the middle P+ region, a polysilicon gate is deposited in the groove and a gate oxide layer is arranged on the surface of the groove.

[0013] Further, a P- region is formed between the outside of the groove and the adjacent P+ region, an N+ region is formed on the upper part of the P- region, a metal layer is arranged above the plane where the upper surface of the P+ region is located, and an ITO thin film layer is arranged on the metal layer.

[0014] Further, the red light emitting diode includes a P-pad layer, a P-GaAs layer, an MQW layer, an n-GaAs layer and an N-pad layer arranged in sequence on the ITO thin film layer, and the green light emitting diode and the blue light emitting diode each include a P-pad layer, a P-GaN layer, an MQW layer, an n-GaN layer and an N-pad layer arranged in sequence on the ITO thin film layer.

[0015] Further, the semiconductor device further includes an interlayer dielectric layer, a common cathode and a thin film encapsulation layer, the interlayer dielectric layer encapsulates and covers the semiconductor device, the ITO thin film layer, the light emitting diode and the upper surface of the driving backboard, and an electrode groove is formed in the interlayer dielectric layer corresponding to the light emitting diode and the image sensing unit;

[0016] The common cathode is arranged on a layer of the interlayer dielectric layer far from the driving backboard and covers the electrode groove, the common cathode is in contact with the upper surface of the image sensing unit through the electrode groove and is in contact with the upper surface of the light emitting diode through the electrode groove.

[0017] The thin film encapsulation layer is arranged on the side of the common cathode away from the driving backplane and covers the common cathode.

[0018] Further, the RGB filter layer, the microlens and the glass encapsulation layer are further included, the RGB filter layer is arranged on the side of the thin film encapsulation layer in the image sensing area away from the driving backplane, the RGB filter layer comprises a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, the red filter unit R, the green filter unit G and the blue filter unit B are arranged on the upper surface of the thin film encapsulation layer in sequence and at intervals, the red filter unit R, the green filter unit G and the blue filter unit B are respectively overlapped with the projection of the semiconductor device on the driving backplane in the three image sensing units; the black matrix is arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the microlens is arranged on the side of the red filter unit R, the green filter unit G and the blue filter unit B away from the driving backplane; the glass encapsulation layer is arranged above the microlens and is adhered to the side of the thin film encapsulation layer away from the driving backplane by UV glue.

[0019] Further, a manufacturing method of the asymmetric trench gate type display sensing module is provided, comprising the following steps:

[0020] S1, forming a plurality of regularly arranged through holes on the driving backplane, filling the through holes with conductive material, and then forming a plurality of anodes on the upper surface of the driving backplane, and each anode covers at least one through hole;

[0021] S2, growing an N-type high-doped region and an N-type epitaxial layer on the driving backplane and the anodes in sequence to form a semiconductor layer;

[0022] S3, patterning the semiconductor layer, so that the N-type high-doped region and the N-type epitaxial layer are divided into a plurality of blocks, and each block is consistent with the width of the anode;

[0023] S4, ion implantation is performed on the middle of the left half and the upper part of the right half of the N-type epitaxial layer to obtain a first P+ region and a second P+ region, respectively;

[0024] S5, ion implantation is performed above the first P+ region to form a P-well layer, and ion implantation is performed above the P-well region to obtain an N+ region;

[0025] S6, etching a trench between the middle segment of the plane where the upper surface of the N+ region is located and the plane where the upper surface of the first P+ region is located, and plating a layer of gate oxide layer on the surface of the trench;

[0026] S7, depositing polysilicon gate in the trench plated with gate oxide layer and depositing thick gate oxide layer, then plating metal layer and ITO thin film layer, growing filling interlayer dielectric layer, and polishing the interlayer dielectric layer to make the upper surface of the interlayer dielectric layer flush with the upper surface of the ITO thin film layer by using chemical mechanical polishing process;

[0027] S8, connecting the RGB LED chip integrated with red light emitting diode, green light emitting diode and blue light emitting diode with the driving back plate by using mass transfer and vacuum bonding technology;

[0028] S9, setting common cathode, growing and patterning thin film packaging layer;

[0029] S10, preparing RGB filter layer in the image sensing area by using yellow light process, making microlens on the red filter unit R, green filter unit G and blue filter unit B of the RGB filter layer, and finally bonding glass packaging layer above the thin film packaging layer by using UV glue.

[0030] Another method for manufacturing asymmetric trench gate type display sensing module is also mentioned, comprising the following steps:

[0031] Sa, forming a plurality of regularly arranged through holes on the driving back plate, filling the through holes with conductive material, then forming a plurality of anodes on the upper surface of the driving back plate, and each anode covers at least one through hole;

[0032] Sb, growing N-type high-doped region and N-type epitaxial layer on the driving back plate and anode in sequence to form semiconductor layer;

[0033] Sc, patterning the semiconductor layer to divide the N-type high-doped region and N-type epitaxial layer into a plurality of blocks, and each block is consistent with the width of the anode;

[0034] Sd, ion implantation on the left, middle and right positions of the N-type epitaxial layer to obtain left P+ region, middle P+ region and right P+ region respectively;

[0035] Se, etching to form a trench on the right side of the left P+ region and the middle P+ region, and plating a layer of gate oxide layer on the surface of the trench;

[0036] Sf, depositing polysilicon gate in the trench plated with gate oxide layer and plating a layer of gate oxide layer for encapsulation;

[0037] Sg, ion implantation between the P+ region and the adjacent P+ region outside the trench to form P- region, and ion implantation on the upper part of the P- region to form N+ region;

[0038] Sh, PVD production on the plane where the upper surface of the P+ region is located to form metal layer, plating ITO thin film layer on the metal layer, growing filling interlayer dielectric layer, and polishing the interlayer dielectric layer to make the upper surface of the interlayer dielectric layer flush with the upper surface of the ITO thin film layer by using chemical mechanical polishing process;

[0039] Si, adopt mass transfer and vacuum bonding technology to connect RGB LED chip integrated with red light emitting diode, green light emitting diode and blue light emitting diode with driving back plate;

[0040] Sj, set common cathode, grow and pattern film packaging layer;

[0041] Sk, prepare RGB filter layer by yellow light process in image sensing area, and make microlens on red filter unit R, green filter unit G and blue filter unit B of the RGB filter layer, finally, adopt UV glue to bond glass packaging layer above the film packaging layer.

[0042] The present application has the beneficial effects: the present application uses semiconductor process to prepare the asymmetric trench gate type display sensing module, which can not only realize the display function of high resolution, high brightness, high contrast and low response time, but also can receive real-time external full-color image, and provides a feasible solution for single-chip integration of interactive display. BRIEF DESCRIPTION OF DRAWINGS

[0043] The present application will be further described below in combination with the drawings and examples.

[0044] Figure 1 is a structural schematic diagram of the embodiment one of the present application.

[0045] Figure 2 is a schematic diagram of step 1 of the embodiment one of the present application.

[0046] Figure 3 is a schematic diagram of step 2 of the embodiment one of the present application.

[0047] Figure 4 is a schematic diagram of step 3 of the embodiment one of the present application.

[0048] Figure 5 is a schematic diagram of step 4 of the embodiment one of the present application.

[0049] Figure 6 is a schematic diagram of step 5 of the embodiment one of the present application.

[0050] Figure 7 is a schematic diagram of step 6 of the embodiment one of the present application.

[0051] Figure 8 is a schematic diagram of step 7 of the embodiment one of the present application.

[0052] Figure 9 is a schematic diagram of step 8 of the embodiment one of the present application.

[0053] Figure 10 is a schematic diagram of step 9 of the embodiment one of the present application.

[0054] Figure 11 is a schematic diagram of step 10 of embodiment 1 of the present application.

[0055] Figure 12 is a schematic diagram of step a of embodiment 2 of the present application.

[0056] Figure 13 is a schematic diagram of step b of embodiment 2 of the present application.

[0057] Figure 14 is a schematic diagram of step c of embodiment 2 of the present application.

[0058] Figure 15 is a schematic diagram of step d of embodiment 2 of the present application.

[0059] Figure 16 is a schematic diagram of step e of embodiment 2 of the present application.

[0060] Figure 17 is a schematic diagram of step f of embodiment 2 of the present application.

[0061] Figure 18 is a schematic diagram of step g of embodiment 2 of the present application.

[0062] Figure 19 is a schematic diagram of step h of embodiment 2 of the present application.

[0063] Figure 20 is a schematic diagram of step i of embodiment 2 of the present application.

[0064] Figure 21 is a schematic diagram of step j of embodiment 2 of the present application.

[0065] Figure 22 is a schematic diagram of step k of embodiment 2 of the present application.

[0066] Figure 23 is a schematic diagram of step 1 of embodiment 2 of the present application.

[0067] Figure 24 is a schematic diagram of the driving circuit of embodiment 1 and embodiment 2 of the present application.

[0068] in the figure:

[0069] 1, driving back plate; 2, via hole; 3, anode;

[0070] 4, semiconductor device; 41, N-type high-doped region; 42, N-type epitaxial layer; 43, P+ region; 431, first P+ region; 432, second P+ region; 431', left P+ region; 432', middle P+ region; 433', right P+ region; 44, P-well region; 45, N+ region; 46, metal layer; 47, P- region; 48, gate oxide layer; 49, polysilicon gate;

[0071] 5. ITO thin film layer; 6. Interlayer dielectric layer; 7. Common cathode; 8. Thin film encapsulation layer; 9. RGB filter layer; 10. Microlens; 11. Glass encapsulation layer; 12. Light-emitting diode; 121. P-pad layer; 122. P-GaAs layer; 123. MQW layer; 124. n-GaAs layer; 125. N-pad layer; 126. P-GaN layer; 127. n-GaN layer; 13. Image sensing unit. Detailed Implementation

[0072] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0073] Example 1

[0074] like Figure 1 As shown, an asymmetric trench grid display sensing module includes:

[0075] The device comprises multiple pixels, each including a light-emitting area and an image sensing area. The light-emitting area includes three light-emitting diodes 12, namely a red light-emitting diode, a green light-emitting diode, and a blue light-emitting diode. The image sensing area includes three image sensing units 13, namely a red image sensing unit, a green image sensing unit, and a blue image sensing unit. A driving backplate 1 is provided with a plurality of regularly arranged vias 2. The light-emitting diodes and the image sensing units 13 cover at least one via 2. The driving backplate 1 carries multiple pixels and drives the light-emitting diodes 12 to emit light. The light-emitting diodes 12 emit light according to the configuration of the image sensing units 13. Both the light-emitting diodes 12 and the image sensing units 13 include an anode 3, a semiconductor device 4, and an ITO thin film layer 5. The anode 3 is located on the driving backplate 1 and covers at least one via 2. The semiconductor device 4 is located on the side of the anode 3 away from the driving backplate 1.

[0076] It also includes: an interlayer dielectric layer 6, a common cathode 7, and a thin-film encapsulation layer 8. The interlayer dielectric layer 6 encapsulates and covers the semiconductor device 4, the ITO thin film layer 5, the light-emitting diode 12, and the upper surface of the driving backplate 1. An electrode groove is formed on the interlayer dielectric layer 6 corresponding to the light-emitting diode 12 and the image sensing unit 13. The common cathode 7 is disposed on the layer of the interlayer dielectric layer 6 away from the driving backplate 1 and covers the electrode groove. The common cathode 7 contacts the upper surface of the image sensing unit 13 through the electrode groove and contacts the upper surface of the light-emitting diode 12 through the electrode groove. The thin-film encapsulation layer 8 is disposed on the side of the common cathode 7 away from the driving backplate 1 and covers the common cathode 7.

[0077] Further comprising: an RGB filter layer 9, a microlens 10 and a glass packaging layer 11, the RGB filter layer 9 is arranged on the side of the thin film packaging layer 8 away from the driving backboard 1 in the image sensing area, the RGB filter layer 9 comprises a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, the red filter unit R, the green filter unit G and the blue filter unit B are arranged on the upper surface of the thin film packaging layer 8 in sequence and at intervals, the red filter unit R, the green filter unit G and the blue filter unit B are overlapped with the projections of the three image sensing units 13 and the semiconductor device 4 on the driving backboard 1 respectively; the black matrix is arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the microlens 10 is arranged on the side of the red filter unit R, the green filter unit G and the blue filter unit B away from the driving backboard 1; the glass packaging layer 11 is arranged above the microlens 10 and is adhered to the side of the thin film packaging layer 8 away from the driving backboard 1 by UV glue.

[0078] Wherein, the semiconductor device 4 has an N-type high-doped area 41 and an N-type epitaxial layer 42, the N-type high-doped area 41 is located on the side of the anode 3 away from the driving backboard 1, the N-type epitaxial layer 42 is formed on the N-type high-doped area 41, the N-type epitaxial layer 42 is ion implanted to form an asymmetric P+ area 43, specifically, the asymmetric P+ area 43 comprises a first P+ area 431 located in the middle of the left half of the N-type epitaxial layer 42 and a second P+ area 432 located on the upper part of the right half, a P-well area 44 is formed on the upper part of the first P+ area 431, an N+ area 45 is formed on the P-well area 44, and the upper surface of the N+ area 45 is flush with the upper surface of the second P+ area 432. A groove is arranged between the middle section of the plane where the upper surface of the N+ area 45 is located and the plane where the upper surface of the first P+ area 431 is located, a gate oxide layer 48 is arranged on the surface of the groove, a metal layer 46 is arranged above the plane where the upper surface of the N+ area 45 is located, and an ITO thin film layer 5 is arranged on the metal layer 46.

[0079] The red light emitting diode comprises a P-pad layer 121, a P-GaAs layer 122, an MQW layer 123, an n-GaAs layer 124 and an N-pad layer 125 arranged in sequence from the ITO thin film layer 5, the green light emitting diode and the blue light emitting diode each comprise a P-pad layer 121, a P-GaN layer 126, an MQW layer 123, an n-GaN layer 127 and an N-pad layer 125 arranged in sequence from the ITO thin film layer 5.

[0080] The manufacturing method of the asymmetric trench gate type display sensing module of the first embodiment is specifically as follows:

[0081] Step 1: as shown in Figure 2As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias 2. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0082] Step 2: As Figure 3 As shown, an N-type highly doped region 41 and an N-type epitaxial layer 42 are sequentially grown on the driving backplate 1 and the anode to form a semiconductor layer;

[0083] Step 3: As Figure 4 As shown, the patterned semiconductor layer divides the N-type highly doped region 41 and the N-type epitaxial layer 42 into several blocks, and each block has the same width as the anode 3.

[0084] Step 4: As Figure 5 As shown, the first P+ region 431 and the second P+ region 432 are obtained by ion implantation in the middle of the left half and the upper part of the right half of the N-type epitaxial layer 42, respectively.

[0085] Step 5: As Figure 6 As shown, a P-well layer 44 is formed by ion implantation above the first P+ region 431, and an N+ region 45 is obtained by ion implantation above the P-well region 44.

[0086] Step 6: As Figure 7 As shown, a trench is etched between the middle section of the plane where the upper surface of the N+ region 45 is located and the plane where the upper surface of the first P+ region 431 is located, and a gate oxide layer 48 is deposited on the surface of the trench.

[0087] Step 7: As Figure 8 As shown, polysilicon 49 is deposited in a trench with gate oxide 48 and a thick gate oxide 48 is deposited. Then, metal layer 46 and ITO thin film layer 5 are deposited, interlayer dielectric layer 6 is grown and filled, and interlayer dielectric layer 6 is ground flat by chemical mechanical grinding process so that the upper surface of interlayer dielectric layer 6 is flush with the upper surface of ITO thin film layer 5.

[0088] Step 8: As Figure 9 As shown, a mass transfer and vacuum bonding technology is used to connect an RGB LED chip integrating red, green and blue light-emitting diodes to a driver backplane 1.

[0089] Step 9: As Figure 10 As shown, a common cathode 7 is provided, and a thin film encapsulation layer 8 is grown and patterned.

[0090] Step 10: As Figure 11As shown, an RGB filter layer 9 is fabricated in the image sensing area using a photoluminescence process, and microlenses 10 are fabricated on the red filter unit R, green filter unit G, and blue filter unit B of the filter layer 9. Finally, a glass encapsulation layer 11 is bonded to the thin film encapsulation layer 8 using UV adhesive, and the current flow is shown by the orange arrow.

[0091] Example 2

[0092] like Figures 12 to 23 As shown, the difference from Embodiment 1 is that: in the semiconductor device 4, a left P+ region 431', a middle P+ region 432', and a right P+ region 433' are formed on the N-type epitaxial layer 42. Trenches are etched to form the right sides of the left P+ region 431' and the middle P+ region 432'. A polysilicon gate 49 is deposited in the trench and a gate oxide layer 48 is provided on its surface. A P- region 47 is formed between the outside of the trench and the adjacent P+ region 43. An N+ region 45 is formed on the upper part of the P- region 47. A metal layer 46 is provided above the plane where the upper surface of the P+ region 43 is located, and an ITO thin film layer 5 is provided on the metal layer 46.

[0093] The fabrication method of the asymmetric trench grid display sensor module in Example 2 is as follows:

[0094] Step a: As Figure 13 As shown, a number of regularly arranged vias 2 are formed on the drive backplate 1, and conductive material is filled in the vias. Subsequently, a number of anodes 3 are formed on the upper surface of the drive backplate 1, and each anode 3 covers at least one via 2.

[0095] Step b: As Figure 14 As shown, an N-type highly doped region 41 and an N-type epitaxial layer 42 are sequentially grown on the driving backplate 1 and the anode 3 to form a semiconductor layer;

[0096] Step c: As Figure 15 As shown, the patterned semiconductor layer divides the N-type highly doped region 41 and the N-type epitaxial layer 42 into several blocks, and each block has the same width as the anode 3.

[0097] Step d: As Figure 16 As shown, ion implantation was performed at the left, middle, and right positions of the N-type epitaxial layer 41 to obtain the left P+ region 431′, the middle P+ region 432′, and the right P+ region 433′, respectively.

[0098] Step e: as Figure 17 As shown, trenches are etched to form on the right side of the left P+ region 431′ and the middle P+ region 432′, and a gate oxide layer 48 is deposited on the surface of the trenches.

[0099] Step f: as Figure 18 As shown, a polysilicon gate 49 is deposited in a trench with a gate oxide layer 48 and then plated with a gate oxide layer 48 for encapsulation.

[0100] Step g: as Figure 19 As shown, ion implantation forms a P-region 47 between the outer side of the trench and the adjacent P+ region 43, and ion implantation forms an N+ region 45 above the P-region 47.

[0101] Step h: as Figure 20 As shown, a metal layer 46 is formed by PVD (physical vapor deposition) on the plane where the upper surface of P+ region 43 is located, and an ITO thin film layer 5 is deposited on the metal layer 46. An interlayer dielectric layer 6 is grown and filled, and the interlayer dielectric layer 6 is ground by chemical mechanical grinding so that the upper surface of the interlayer dielectric layer 6 is flush with the upper surface of the ITO thin film layer 5.

[0102] Step i: As Figure 21 As shown, a mass transfer and vacuum bonding technology is used to connect an RGB LED chip integrating red, green and blue light-emitting diodes to a driver backplane 1.

[0103] Step j: as Figure 22 As shown, a common cathode 7 is provided, and a thin film encapsulation layer 8 is grown and patterned.

[0104] Step k: as follows Figure 23 As shown, an RGB filter layer 9 is fabricated in the image sensing area using a photoluminescence process, and microlenses 10 are fabricated on the red filter unit R, green filter unit G, and blue filter unit B of the RGB filter layer 9. Finally, a glass encapsulation layer 11 is bonded to the thin film encapsulation layer 8 using UV adhesive, and the current flow is shown by the orange arrow.

[0105] Example 1 and Example 2 are combined as follows Figure 24 The driving circuit shown can improve the performance and reliability of the display, and has the advantages of high integration, low power consumption, high speed and good stability, making it widely applicable.

[0106] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An asymmetric trench grid-type display sensing module, characterized in that, The application relates to a pixel array and a pixel thereof. The pixel array comprises a plurality of pixels, each of which comprises a light-emitting area and an image sensing area, the light-emitting area comprises three light-emitting diodes (12), which are respectively a red light-emitting diode, a green light-emitting diode and a blue light-emitting diode, and the image sensing area comprises three image sensing units (13), which are respectively a red image sensing unit, a green image sensing unit and a blue image sensing unit. A driving backboard (1) is provided with a plurality of regularly arranged through holes (2), the light-emitting diode (12) and the image sensing unit (13) cover at least one through hole (2), the driving backboard (1) carries a plurality of pixels, drives the light-emitting diode (12) to emit light, and the light-emitting diode (12) emits light according to the configuration of the image sensing unit (13). The light-emitting diode (12) and the image sensing unit (13) each comprise an anode (3), a semiconductor device (4) and an ITO film layer (5), the anode (3) is located on the driving backboard (1) and covers at least one through hole (2), the semiconductor device (4) is located on a side of the anode (3) away from the driving backboard (1), The semiconductor device (4) has an N-type high-doped area (41) and an N-type epitaxial layer (42), the N-type high-doped area (41) is located on a side of the anode (3) away from the driving backboard (1), the N-type high-doped area (41) is formed with the N-type epitaxial layer (42), the N-type epitaxial layer (42) is ion implanted to form an asymmetric P+ area (43) or the N-type epitaxial layer (42) is ion implanted to form a symmetric P+ area (43) and etched to form an asymmetric groove, a gate oxide layer (48) is arranged on the surface of the groove, and a polysilicon gate (49) is deposited in the groove with the gate oxide layer (48). 2.The asymmetric trench gate display and sensing module of claim 1, wherein: The asymmetric P+ area (43) comprises a first P+ area (431) located in the middle of the left half of the N-type epitaxial layer (42) and a second P+ area (432) located on the upper part of the right half, a P-well area (44) is formed on the upper part of the first P+ area (431), an N+ area (45) is formed on the P-well area (44), and the upper surface of the N+ area (45) is flush with the upper surface of the second P+ area (432). 3.The asymmetric trench gate display and sensing module of claim 2, wherein: A groove is arranged between the middle section of the plane where the upper surface of the N+ area (45) is located and the plane where the upper surface of the first P+ area (431) is located, the surface of the groove is provided with a gate oxide layer (48), a metal layer (46) is arranged above the plane where the upper surface of the N+ area (45) is located, and an ITO film layer (5) is arranged on the metal layer (46).

4. The asymmetric trench gate display and sensing module of claim 1, wherein: The N-type epitaxial layer (42) is formed with a left P+ area (431'), a middle P+ area (432') and a right P+ area (433'), a groove is etched on the right side of the left P+ area (431') and the middle P+ area (432'), a polysilicon gate (49) is deposited in the groove and a gate oxide layer (48) is arranged on the surface of the groove.

5. The asymmetric trench-gate display and sensing module of claim 4, wherein: A P- region (47) is formed between the trench outer side and the adjacent P+ region (43), an N+ region (45) is formed on the upper portion of the P- region (47), a metal layer (46) is arranged above the plane where the upper surface of the P+ region (43) is located, and an ITO thin film layer (5) is arranged on the metal layer (46).

6. The asymmetric trench-gate display and sensing module according to claim 3 or 5, wherein: The red light emitting diode comprises a P-pad layer (121), a P-GaAs layer (122), an MQW layer (123), an n-GaAs layer (124) and an N-pad layer (125) arranged on the ITO thin film layer (5) in sequence, and the green light emitting diode and the blue light emitting diode each comprise a P-pad layer (121), a P-GaN layer (126), an MQW layer (123), an n-GaN layer (127) and an N-pad layer (125) arranged on the ITO thin film layer (5) in sequence.

7. The asymmetric trench-gate display and sensing module of claim 6, wherein: It also comprises an interlayer dielectric layer (6), a common cathode (7) and a thin film encapsulation layer (8), the interlayer dielectric layer (6) encapsulates and covers the semiconductor device (4), the ITO thin film layer (5), the light emitting diode (12) and the upper surface of the driving backboard (1), and an electrode groove is formed on the corresponding interlayer dielectric layer (6) in the light emitting diode (12) and the image sensing unit (13); The common cathode (7) is arranged on a layer of the interlayer dielectric layer (6) far away from the driving backboard (1) and covers the electrode groove, and the common cathode (7) is in contact with the upper surface of the image sensing unit (13) and the upper surface of the light emitting diode (12) through the electrode groove; The thin film encapsulation layer (8) is arranged on the side of the common cathode (7) far away from the driving backboard (1) and covers the common cathode (7).

8. The asymmetric trench-gate display and sensing module of claim 6, wherein: It also comprises an RGB filter layer (9), a microlens (10) and a glass encapsulation layer (11), the RGB filter layer (9) is arranged on the side of the thin film encapsulation layer (8) far away from the driving backboard (1) in the image sensing area, the RGB filter layer (9) comprises a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, the red filter unit R, the green filter unit G and the blue filter unit B are arranged on the upper surface of the thin film encapsulation layer (8) in sequence and at intervals, the red filter unit R, the green filter unit G and the blue filter unit B are respectively overlapped with the projections of the semiconductor devices (4) on the driving backboard (1) in the three image sensing units (13); the black matrix is arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, the side of the red filter unit R, the green filter unit G and the blue filter unit B far away from the driving backboard (1) is provided with the microlens (10); and the glass encapsulation layer (11) is arranged above the microlens (10) and is adhered to the side of the thin film encapsulation layer (8) far away from the driving backboard (1) by UV glue.

9. The method for manufacturing the asymmetric trench-gate display and sensor module as claimed in claim 3, wherein, The method comprises the following steps: S1, forming a plurality of regularly arranged via holes (2) on the driving backplane (1), filling the via holes (2) with conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving backplane (1), wherein each anode (3) covers at least one via hole (2); S2, growing an N-type high-doped region (41) and an N-type epitaxial layer (42) on the driving backplane (1) and the anodes (3) in sequence to form a semiconductor layer; S3, patterning the semiconductor layer, so that the N-type high-doped region (41) and the N-type epitaxial layer (42) are divided into a plurality of blocks, and each block is consistent with the width of the anode (3); S4, ion implantation is performed on the middle of the left half and the upper part of the right half of the N-type epitaxial layer (42) to obtain a first P+ region (431) and a second P+ region (432), respectively; S5, ion implantation is performed above the first P+ region (431) to form a P-well region (44), and ion implantation is performed above the P-well region (44) to obtain an N+ region (45); S6, etching a groove between the middle section of the plane on which the N+ region (45) is located and the plane on which the upper surface of the first P+ region (431) is located, and plating a layer of gate oxide layer (48) on the surface of the groove; S7, depositing a polysilicon gate (49) in the groove plated with the gate oxide layer (48) and depositing a thick gate oxide layer (48), then plating a metal layer (46) and an ITO thin film layer (5), growing an interlayer dielectric layer (6), and using a chemical mechanical polishing process to polish the interlayer dielectric layer (6) to make the upper surface of the interlayer dielectric layer (6) flush with the upper surface of the ITO thin film layer (5); S8, using mass transfer and vacuum bonding technology to connect the RGB LED chip integrated with red light-emitting diodes, green light-emitting diodes and blue light-emitting diodes with the driving backplane (1); S9, setting a common cathode (7), growing and patterning a thin film packaging layer (8); S10, preparing an RGB filter layer (9) in the image sensing area using a yellow light process, and manufacturing a microlens (10) on the red filter unit R, the green filter unit G and the blue filter unit B of the RGB filter layer (9), and finally bonding a glass packaging layer (11) above the thin film packaging layer (8) using UV glue.

10. The method for manufacturing the asymmetric trench-gate display and sensor module as claimed in claim 5, wherein, The method comprises the following steps: Sa, forming a plurality of regularly arranged via holes (2) on the driving backplane (1), filling the via holes (2) with conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving backplane (1), wherein each anode (3) covers at least one via hole (2); Sb, growing an N-type high-doped region (41) and an N-type epitaxial layer (42) on the driving backplane (1) and the anodes in sequence to form a semiconductor layer; Sc, patterning the semiconductor layer, so that the N-type high-doped region (41) and the N-type epitaxial layer (42) are divided into a plurality of blocks, and each block is consistent with the width of the anode (3); Sd, ion implantation is performed on the left, middle and right positions of the N-type epitaxial layer (42) to obtain a left P+ region (431'), a middle P+ region (432') and a right P+ region (433'), respectively; Se, etching a groove in the left P+ region (431') and the right part of the middle P+ region (432'), and plating a gate oxide layer (48) on the surface of the groove; Sf, depositing a polysilicon gate (49) in the groove plated with the gate oxide layer (48) and plating a gate oxide layer (48) to encapsulate; Sg, ion implantation between the outside of the groove and the adjacent P+ region (43) to form a P- region (47), and ion implantation on the upper part of the P- region (47) to form an N+ region (45); Sh, PVD production of a metal layer (46) on the surface of the P+ region (43), plating an ITO thin film layer (5) on the metal layer (46), growing a filling interlayer (6), and using a chemical mechanical polishing process to polish the interlayer (6) to make the upper surface of the interlayer (6) flush with the upper surface of the ITO thin film layer (5); Si, using mass transfer and vacuum bonding technology to connect the RGB LED chip integrated with red, green and blue light emitting diodes to the driving backboard (1); Sj, setting a common cathode (7), growing and patterning a thin film packaging layer (8); Sk, using yellow light technology to prepare an RGB filter layer (9) in the image sensing area, making a microlens (10) on the red filter unit R, green filter unit G and blue filter unit B of the RGB filter layer (9), and finally using UV glue to bond a glass packaging layer (11) above the thin film packaging layer (8).

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