Transition metal sulfide-based memristor and preparation method thereof

Abstract

The invention discloses a memristor based on transition metal sulfide and a preparation method thereof, relates to the technical field of memristors, and aims to solve the problems of low response speed (ms level), small conductivity dynamic range and easy breakdown of devices. The preparation method comprises the following steps: S1, accurately preparing a single-layer MoS2 silicon wafer; s2, carrying out mild and controllable defect regulation and control on the single-layer MoS2 silicon wafer prepared in the step S1; and S3, constructing the MoS2 memristor with a horizontal structure by adopting the single-layer MoS2 silicon wafer.

Description

Technical Field

[0001] The present invention relates to the technical field of memristors, and in particular to a memristor based on transition metal sulfides and a preparation method thereof. Background Art

[0002] Memristor is the fourth basic circuit element proposed by Leon O. Chua. In 2008, Strukov et al. of Hewlett-Packard (HP) Labs first experimentally verified the realization of memristor function. Memristor has the advantages of simple structure, good scalability, high density, and compatibility with CMOS process.

[0003] Compared with vertical structure, horizontal structure memristor has advantages such as mature manufacturing process and easy integration. However, currently horizontal structure two-dimensional material memristors are mostly active metal electrodes with conductive filament-type mechanisms, which have problems such as slow response speed (ms level), small conductivity dynamic range, and easy device breakdown. Summary of the invention

[0004] The present invention proposes a transition metal sulfide-based memristor and a preparation method thereof, which comprises the following steps: S1: Precise preparation of single-layer MoS 2 Silicon wafer; S2: The single-layer MoS prepared in step S1 2 Gentle and controllable defect regulation of silicon wafers; S3: Using the single-layer MoS 2 MoS2 with silicon wafers to build horizontal structures 2 Memristor.

[0005] The present invention is further configured as follows: step S1 includes the following steps: S1-1: introduce 140-190 sccm of Ar into the tube furnace, place a porcelain boat filled with sulfur powder in the second temperature zone, and control the temperature of the second temperature zone to 140-180°C; S1-2: Raise the temperature of the tubular furnace to 500°C, and then place 4-12 mg of MoO 3 The quartz boat containing the powder and two inverted silicon wafers is pushed into the center of the tube furnace, and then the tube furnace is heated to 780-880° C. for 30-50 min; S1-3: After the temperature rise is completed, the constant temperature stage is reached, and 0.6-1.4 sccm of O is introduced into the constant temperature stage. 2 , keep constant temperature for 30-55min, turn off O after the constant temperature stage 2 After the tube furnace is cooled to 500°C, it is taken out to obtain a deposited single-layer MoS 2 Silicon wafer.

[0006] The present invention is further configured as follows: step S2 includes the following steps: S2-1: Ultra-high vacuum high temperature annealing: The single layer MoS 2 The silicon wafer is pushed into a vacuum annealing furnace, the vacuum degree of which is 10 -6 Pa, and then the temperature in the vacuum annealing furnace is raised from room temperature to 400-800°C over 60-120 minutes, and then kept at a constant temperature for 0.5-2 hours, and then naturally cooled to room temperature before being taken out.

[0007] The present invention is further configured as follows: step S2 includes the following steps: S2-1: Weak oxidation regulation: The single-layer MoS 2 The silicon wafer is immersed in 10-30% H 2 O 2 The solution was soaked for 1-3 minutes, then taken out and rinsed in deionized water for 1-3 minutes. 2 Blow dry with air gun.

[0008] The present invention is further configured as follows: step S3 includes the following steps: S3-1: Use a coating machine to spin-coat PMMA positive photoresist twice on a blank silicon wafer, heat it on a hot plate at 150-200°C for 1-4 minutes, and use electron beam exposure (EBL) technology to expose electrodes with a distance of 0.1-30μm. The distance between the electrodes is the thickness of the resistive layer. Then use AR600-56 and isopropyl alcohol for development and fixing respectively, and then perform vapor deposition, and at the same time evaporate 5-10nmCr to stabilize Au. S3-2: Using a sizing machine to coat the single layer MoS 2 The silicon wafer was coated with a layer of PPC, and then heated on a 120°C hot plate for 1 min. Then a layer of PMMA was spin-coated, and then heated on a 120°C hot plate for 1 min. After the spin coating was completed, it was cut into 2×2 mm sizes. The cut single layer of MoS 2 Place in etching solution for etching. S3-3: After the etching solution is etched, the PMMA film is separated from the silicon wafer. The PMMA film is picked up with a cover glass and repeatedly washed in deionized water for 3-6 times. Then, it is placed on the transfer platform for precise transfer. 2 The silicon wafer is transferred between two horizontal electrodes, and the electrodes are connected to the single-layer MoS 2 The silicon wafer is kept at the same level, and then heated on a hot plate at 80-130°C for 15-60 minutes, then debonded with acetone and cleaned with isopropyl alcohol; S3-4: Use a vacuum annealing furnace to anneal at 100-200°C for 1-3 hours, and take it out after cooling to room temperature to obtain MoS2 Memristor.

[0009] The present invention is further configured as follows: the etching solution is prepared by mixing HF and deionized water in a ratio of 1:3.

[0010] The present invention is further configured as follows: the etching process of step S3-2 is: on the cut single layer MoS 2 Spin-coat two layers of PMMA on the silicon wafer and heat it on a hot plate at 150-200°C for 1-4 minutes. Combine the EBL technology with the etcher to form a triangular MoS 2 The material is cut into strips and etched using O 2 , gas flow rate is 30-80sccm, power is 30-90W, and time is 20-100s.

[0011] The present invention also provides a transition metal sulfide-based memristor, which is manufactured using the above-mentioned preparation method.

[0012] The beneficial effects of the present invention are:

[0013] 1. The vacancy-defect-rich horizontal structure memristor designed by the present invention has a wider dynamic range of conductance change, which means that the device can respond to input signals more sensitively and accurately, store more states and information, and improve storage density. At the same time, the maximum operating voltage is >40V, and it will not be broken down after 100 cycles, which is helpful for working under extreme conditions and improving system integration, greatly broadening the application scenarios of memristors.

[0014] 2. The horizontal structure memristor with vacancy-rich defect resistive switching layer designed by the present invention has a resistive switching mechanism in which electrons migrate in vacancies to form conductive filaments. Compared with the currently mainstream active metal conductive filament-type memristors, electrons have a faster migration speed than metal ions. Therefore, the memristor designed in this invention has a faster response speed.

[0015] 3. The vacancy defect control and device construction method designed in the present invention is simple to operate and has high repeatability, which is conducive to industrial production and commercial application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 shows a schematic diagram of the fabricated memristor structure.

[0017] Figure 2 A light microscope image of a memristor is shown.

[0018] Figure 3 The IV cycle characteristic curve of the memristor at 10V-40V is shown.

[0019] Figure 4 The IV characteristic curve under 100 cycles of 40V voltage is shown.

[0020] Figure 5 Conductance dynamics are shown.

[0021] Figure 6 A single pulse diagram is shown.

[0022] Figure 7 The IV cycle characteristic curve at 40V voltage at a distance of 1 μm is shown.

[0023] Figure 8 The IV cycle characteristic curve at 40V voltage at a distance of 3 μm is shown.

[0024] Fig. 9 The IV cycle characteristic curve at 40V voltage at a distance of 5 μm is shown.

[0025] Fig.10 The IV cycle characteristic curve at a voltage of 40 V at a distance of 10 μm is shown.

[0026] Fig.11 The IV cycle characteristic curve at 40V voltage at a distance of 15 μm is shown.

[0027] Fig.12 It shows that the annealing temperature at 400℃ is similar to that of the original MoS 2 Raman diagram.

[0028] Fig.13 The XPS spectra of S2P at different annealing temperatures are shown. DETAILED DESCRIPTION

[0029] Those skilled in the art can refer to the content of this article and appropriately improve the process parameters. It is particularly important to point out that all similar replacements and modifications are obvious to those skilled in the art, and they are all considered to be included in the present invention. The methods and applications of the present invention have been described through preferred embodiments, and relevant personnel can modify or appropriately change and combine the methods and applications described herein without departing from the content, spirit and scope of the present invention to implement and apply the technology of the present invention.

[0030] Example 1

[0031] This embodiment proposes a method for preparing a memristor based on transition sulfide, comprising the following steps:

[0032] S1: Precise preparation of single-layer MoS 2 Silicon wafer;

[0033] S2: The single-layer MoS prepared in step S1 2 Gentle and controllable defect regulation of silicon wafers;

[0034] S3: Using the single-layer MoS 2 MoS2 with silicon wafers to build horizontal structures 2 Memristor.

[0035] Wherein step 1 includes the following steps:

[0036] S1-1: 140-190 sccm of Ar is introduced into the tube furnace, a porcelain boat filled with sulfur powder is placed in the second temperature zone, and the temperature of the second temperature zone is controlled to be 140-180°C.

[0037] S1-2: Raise the temperature of the tubular furnace to 500°C, and then place 4-12 mg of MoO 3 The quartz boat containing the powder and two inverted silicon wafers is pushed into the center of the tube furnace, and then the tube furnace is heated to 780-880° C. for 30-50 min;

[0038] S1-3: After the temperature rise is completed, the constant temperature stage is reached, and 0.6-1.4 sccm of O is introduced into the constant temperature stage. 2 , keep constant temperature for 30-55min, turn off O after the constant temperature stage 2 After the tube furnace is cooled to 500°C, it is taken out to obtain a deposited single-layer MoS 2 Silicon wafer.

[0039] Wherein step 2 comprises the following steps:

[0040] S2-1: Ultra-high vacuum high temperature annealing: The single layer MoS 2 The silicon wafer is pushed into a vacuum annealing furnace, the vacuum degree of which is 10 -6 Pa, and then the temperature in the vacuum annealing furnace is raised from room temperature to 400-800°C over 60-120 minutes, and then kept at a constant temperature for 0.5-2 hours, and then naturally cooled to room temperature before being taken out.

[0041] Wherein step S3 comprises the following steps: S3-1: Use a coating machine to spin-coat PMMA positive photoresist twice on the blank silicon wafer, heat it on a hot plate at 150-200℃ for 1-4min, and use electron beam exposure (EBL) technology to expose electrodes with a distance of 0.1-30μm. The distance between the electrodes is the thickness of the resistive layer. Then use AR600-56 and isopropyl alcohol for development and fixing respectively, and then perform vapor deposition to deposit 20-40nmAu, and at the same time evaporate 5-10nmCr to stabilize Au. S3-2: Using a sizing machine to coat the single layer MoS 2The silicon wafer was coated with a layer of PPC, and then heated on a 120°C hot plate for 1 min. Then a layer of PMMA was coated and heated on a 120°C hot plate for 1 min. After the coating was completed, it was cut into 2×2 mm sizes. The cut single layer of MoS 2 Place in etching solution for etching. S3-3: After the etching solution is etched, the PMMA film is separated from the silicon wafer. The PMMA film is picked up with a cover glass and repeatedly washed in deionized water for 3-6 times. Then, it is placed on the transfer platform for precise transfer. 2 The silicon wafer is transferred between two horizontal electrodes, and the electrodes are connected to the single-layer MoS 2 The silicon wafer is kept at the same level, and then heated on a hot plate at 80-130°C for 15-60 minutes, then debonded with acetone and cleaned with isopropyl alcohol;

[0042] S3-4: Use a vacuum annealing furnace to anneal at 100-200°C for 1-3 hours, and take it out after cooling to room temperature to obtain MoS 2 Memristor.

[0043] In step S3-2, the etching solution is prepared by mixing HF and deionized water in a ratio of 1:3. The etching process is as follows: 2 Spin-coat two layers of PMMA on the silicon wafer and heat it on a hot plate at 150-200°C for 1-4 minutes. Combine the EBL technology with the etcher to form a triangular MoS 2 The material is cut into strips and etched using O 2 , gas flow rate is 30-80sccm, power is 30-90W, and time is 20-100s.

[0044] Example 2

[0045] The difference between this embodiment and embodiment 1 is that step 2 includes the following steps:

[0046] S2-1: Weak oxidation regulation: The single-layer MoS 2 The silicon wafer is immersed in 10-30% H 2 O 2 The solution was soaked for 1-3 minutes, then taken out and rinsed in deionized water for 1-3 minutes. 2 Blow dry with air gun.

[0047] Example 3

[0048] This embodiment proposes a transition sulfide-based memristor, which is manufactured using the manufacturing method disclosed in Embodiment 1 or Embodiment 2.

[0049] Example 4

[0050] This embodiment adopts the preparation method of embodiment 1 to manufacture a memristor, and the specific steps are as follows:

[0051] S1: Precise preparation of single-layer MoS 2 Silicon wafer;

[0052] S2: The single-layer MoS prepared in step S1 2 Gentle and controllable defect regulation of silicon wafers;

[0053] S3: Using single-layer MoS 2 MoS2 with silicon wafers to build horizontal structures 2 Memristor.

[0054] Wherein step S1 comprises the following steps:

[0055] S1-1: 160 sccm of Ar is introduced into the tube furnace, a porcelain boat filled with sulfur powder is placed in the second temperature zone, and the temperature of the second temperature zone is controlled to be 160°C;

[0056] S1-2: Raise the temperature of the tube furnace to 500°C and place 8 mg of MoO 3 The powder and the quartz boat with two inverted silicon wafers were pushed into the furnace to the center of the tube furnace, and then the tube furnace was heated to 820°C for 40 min;

[0057] S1-3: After the temperature rise is completed, the constant temperature stage is reached. During the constant temperature stage, 1.0 sccm of O is introduced. 2 , keep the temperature constant for 40 minutes, and turn off the O 2 After the tube furnace is cooled to 500°C, it is taken out to obtain a deposited single-layer MoS 2 Silicon wafer.

[0058] The single-layer MoS prepared in step S1 is 2 The silicon wafer is subjected to gentle and controllable defect control treatment. The specific steps are as follows:

[0059] S2-1: Using ultra-high vacuum high temperature annealing: a single layer of MoS 2 The silicon wafer is pushed into the vacuum annealing furnace, and the vacuum degree in the vacuum annealing furnace is 10 -6 Pa, then raise the temperature in the vacuum annealing furnace from room temperature 25°C to 500°C over 60 minutes, keep the temperature constant for 1 hour, then naturally cool to room temperature and take out.

[0060] Wherein step 3 comprises the following steps:

[0061] S3-1 uses a coating machine to spin-coat PMMA positive resist twice on an empty silicon wafer, then heats it on a hot plate at 180°C for 2 minutes, and uses electron beam exposure (EBL) technology to expose electrodes with a distance of 7μm. The distance between the electrodes is the thickness of the resistive layer. AR600-56 and isopropyl alcohol are then used for development and fixing, and then vapor deposition is performed to ensure that the bottom electrode is in close contact with the substrate, 30nm Au is evaporated, and 10nm Cr is evaporated at the same time.

[0062] S3-2: Using a sizing machine to sizing a single layer of MoS 2 The silicon wafer was coated with a layer of PPC to reduce the damage to the material caused by the wrinkles of the PMMA film during the transfer. It was heated on a 120℃ hot plate for 1min, and then another layer of PMMA was spin-coated. It was heated on a 120℃ hot plate for 1min. After the spin coating was completed, it was cut into 2×2mm sizes and the cut single layer of MoS 2 The silicon wafer is placed in an etching solution for etching.

[0063] The etching solution is prepared by mixing HF and deionized water in a ratio of 1:3. The etching process is as follows:

[0064] In the cut single layer MoS 2 Two layers of PMMA were spin-coated on the silicon wafer and heated on a hot plate at 180°C for 2 minutes. The triangular MoS 2 The material is cut into strips and etched using O 2 , the gas flow rate is 50sccm, the power is 60W, and the time is 60s.

[0065] S3-3: After the etching solution is etched, the PMMA film is separated from the silicon wafer. The PMMA film is picked up with a cover glass and repeatedly washed in deionized water for 3-6 times. Then, it is placed on the transfer platform for precise transfer. 2 The silicon wafer is transferred between two horizontal electrodes, and the electrodes are connected to the single-layer MoS 2 The silicon wafer is kept at the same level, which ensures that the single-layer MoS 2 The silicon wafer had excellent contact with the target substrate and was then heated on a 100°C hot plate for 30 min, followed by degumming with acetone and cleaning with isopropanol;

[0066] S3-4: Use a vacuum annealing furnace to anneal at 150°C for 2 hours, and then take it out after cooling to room temperature to obtain MoS 2 Memristor. Annealing in a vacuum annealing furnace can improve the contact between the electrode and the resistive layer.

[0067] Example 5

[0068] The only difference between this embodiment and embodiment 4 is that the distance between horizontal electrodes is 1 μm, and the other steps are the same as those in embodiment 4.

[0069] Example 6

[0070] The only difference between this embodiment and embodiment 4 is that the distance between horizontal electrodes is 3 μm, and the other steps are the same as those in embodiment 4.

[0071] Example 7

[0072] The only difference between this embodiment and embodiment 4 is that the distance between horizontal electrodes is 5 μm, and the other steps are the same as those in embodiment 4.

[0073] Example 8

[0074] The only difference between this embodiment and embodiment 4 is that the distance between horizontal electrodes is 10 μm, and the other steps are the same as those in embodiment 4.

[0075] Example 9

[0076] The only difference between this embodiment and embodiment 4 is that the distance between horizontal electrodes is 15 μm, and the other steps are the same as those in embodiment 4.

[0077] Performance Test:

[0078] The structural schematic diagrams and optical microscope images in this application refer to Figure 1 , 2 As shown, Figure 3 The IV cycle characteristic curve of the device at 10V-40V is shown. As the voltage increases, the switching ratio gradually increases, and the current is always in the μA level without breakdown. Figure 4 This is the IV characteristic curve under 100 cycles of 40V voltage. It can still work normally after 100 cycles, proving that it has good cycle stability under high voltage; Figure 5 The device showed a PPF of up to 121.9% and a PTP of 231.9, demonstrating its large conductance dynamic range. Figure 6 This is a single pulse diagram with a duration of 50μs, which is 3 orders of magnitude lower than the ms level of the conductive filament type. Figure 7 , 8 When the distances between 9, 10, and 11 are 1, 3, 5, 10, and 15 μm, the IV cycle characteristic curves at 40 V voltage, the forward conductance changes are 138.9%, 160.6%, 187.6%, 166.9%, and 121.0%, respectively, and the reverse conductance changes are 24.8%, 13.8%, 66.6%, 64.4%, and 12.4%, respectively, together with the above-mentioned 7 μm embodiment, are summarized in the following Table 1. Table 1 Summary of I-V cycle characteristic curves

[0079] It is demonstrated to have excellent stability at high voltage and a large conductivity range. Fig.12 The results show that the annealing temperature is 400℃ and the original MoS 2 Raman map, it is found that after annealing The characteristic peak and the characteristic peak of A1g both show a 2 cm -1 The red shift of the two characteristic peaks is related to the in-plane vibration and out-of-plane vibration. Fig.13 Figure 2 shows the XPS spectra of S2p at different annealing temperatures. After high-temperature annealing, the S2p orbital peaks above 400°C all red-shifted, but the magnitude of the red-shift was not the same. In the 400°C-500°C range, they gradually moved toward the low binding energy direction. After 500°C, they began to gradually blue-shift, and none of them were higher than the binding energy without annealing.

[0080] In summary, the vacancy defect-rich horizontal structure memristor designed by the present invention has a wider dynamic range of conductivity change, which means that the device can respond to the input signal more sensitively and accurately, store more states and information, and improve the storage density. At the same time, the maximum operating voltage is >40V, and it will not be broken down after 100 cycles, which is helpful for working under extreme conditions and improving system integration, greatly broadening the application scenarios of memristors. The horizontal structure memristor with a vacancy defect-rich resistive switching layer designed by the present invention has a resistive switching mechanism in which electrons migrate in vacancies to form conductive filaments. Compared with the current mainstream active metal conductive filament-type memristor, electrons have a faster migration speed than metal ions. Therefore, the memristor of this design has a faster response speed. The vacancy defect regulation and device construction method designed by the present invention is simple to operate, has high repeatability, and is conducive to industrial production and commercial application.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be within the scope of protection of the present invention.

Claims

1. A method for preparing a memristor based on transition metal sulfide, characterized in that: The steps include: S1: Precise preparation of single-layer MoS2 silicon wafers; S2: performing gentle and controllable defect regulation on the single-layer MoS2 silicon wafer prepared in step S1; S3: Use the single-layer MoS2 silicon wafer to construct a horizontally structured MoS2 memristor.

2. The method for preparing a transition metal sulfide memristor according to claim 1, characterized in that: The step S1 includes the following steps: S1-1: introduce 140-190 sccm of Ar into the tube furnace, place a porcelain boat filled with sulfur powder in the second temperature zone, and control the temperature of the second temperature zone to 140-180°C; S1-2: Raise the temperature of the tube furnace to 500°C, then push a quartz boat carrying 4-12 mg of MoO3 powder and two inverted silicon wafers into the center of the tube furnace, and then raise the temperature of the tube furnace to 780-880°C for 30-50 minutes; S1-3: After the temperature rise is completed, the constant temperature stage is reached. 0.6-1.4sccm of O2 is introduced during the constant temperature stage, and the temperature is kept constant for 30-55 minutes. After the constant temperature stage ends, the introduction of O2 is turned off, and the tube furnace is taken out after cooling to 500°C, thereby obtaining a deposited single-layer MoS2 silicon wafer.

3. The method for preparing a transition metal sulfide memristor according to claim 1 or 2, characterized in that: The step S2 includes the following steps: S2-1: Ultra-high vacuum high temperature annealing: Push the single-layer MoS2 silicon wafer into a vacuum annealing furnace with a vacuum degree of 10 -6 Pa, and then the temperature in the vacuum annealing furnace is raised from room temperature to 400-800°C over 60-120 minutes, and then kept at a constant temperature for 0.5-2 hours, and then naturally cooled to room temperature before being taken out.

4. The method for preparing a transition metal sulfide memristor according to claim 1 or 2, characterized in that: The step S2 includes the following steps: S2-1: Weak oxidation regulation: immerse the single-layer MoS2 silicon wafer in a H2O2 solution with a mass concentration of 10-30%, take it out after soaking for 1-3 minutes, then place it in deionized water for cleaning for 1-3 minutes, and then blow it dry with a N2 air gun.

5. The method for preparing a transition metal sulfide memristor according to claim 1, characterized in that: The step S3 includes the following steps: S3-1: Use a coating machine to spin-coat PMMA positive photoresist twice on the blank silicon wafer, heat it on a hot plate at 150-200℃ for 1-4min, and use electron beam exposure (EBL) technology to expose electrodes with a distance of 0.1-30μm. The distance between the electrodes is the thickness of the resistive layer. Then use AR600-56 and isopropyl alcohol for development and fixing respectively, and then perform vapor deposition to deposit 20-40nmAu, and at the same time evaporate 5-10nmCr to stabilize Au. S3-2: Use a coating machine to coat the single-layer MoS2 silicon wafer. First, spin-coat a layer of PPC, heat it on a 120°C hot plate for 1 minute, then spin-coat a layer of PMMA, and heat it on a 120°C hot plate for 1 minute. After spin coating, cut it into 2×2mm size, and place the cut single-layer MoS2 in an etching solution for etching. S3-3: After the etching solution is etched, the PMMA film is separated from the silicon wafer. The PMMA film is picked up with a cover glass and repeatedly washed in deionized water for 3-6 times. Then, it is placed on the transfer platform for precise transfer. The single-layer MoS2 silicon wafer is transferred between two horizontal electrodes. The electrodes and the single-layer MoS2 silicon wafer are basically kept at the same level. Then, a hot plate at 80-130°C is used for heating for 15-60 minutes. Then, acetone is used for degumming and isopropanol is used for cleaning. S3-4: Use a vacuum annealing furnace to anneal at a constant temperature of 100-200°C for 1-3 hours, and take it out after cooling to room temperature to obtain a MoS2 memristor.

6. The method for preparing a transition metal sulfide memristor according to claim 5, characterized in that: The etching solution is prepared by mixing HF and deionized water in a ratio of 1:

3.

7. The method for preparing a transition metal sulfide memristor according to claim 5, characterized in that: The etching process of step S3-2 is as follows: two layers of PMMA are spin-coated on the cut single-layer MoS2 silicon wafer, and heated on a hot plate at 150-200°C for 1-4 minutes, and the triangular MoS2 material is etched into strips by combining EBL technology with an etcher, and O2 is used for etching, with a gas flow rate of 30-80sccm, a power of 30-90W, and a time of 20-100s.

8. A memristor based on transition metal sulfide, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 7.

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