Method for controlling an active matrix display, associated control device and computer program product

Abstract

The invention relates to a method for controlling an active matrix display (4), by means of which the active matrix display can be controlled inexpensively, in particular with a very flexible color change, and comprising a step of executing a program stored in a program memory (5) of a microcontroller (3), which program controls a DMA controller (6), a DMA controller (6) is made to read image data deeper per pixel 1 from a data memory (2), an RGB image data set generated by a program is transmitted to a hardware SPI (7) connected with the DMA controller (6) through the DMA controller (6), and the hardware SPI sends the RGB image data set to an active matrix display (4) in series through a data output (MOSI) of the hardware SPI, in order to synchronize the data transmission to the active matrix display (4), a pixel clock input (PCLK) of the active matrix display (4) is controlled by an SPI clock output (SCK). The invention also relates to an associated control device (1) and to a computer program product.

Description

Technical Field

[0001] The invention relates to a method for operating an active-matrix display and a control device having a program memory in which a program is stored, which is designed and configured to carry out the method. The invention also relates to a computer program product having a machine-readable carrier on which a program code of the program is stored for carrying out the method on the control device. Background Art

[0002] Patent document EP1560190A2 describes a host computer that provides image data for each image sequence via a serial bus. The image data is extracted from the data received by the serial bus to an electronic subassembly connected between the host computer and the display device. The extracted image data is stored in an image memory of the electronic subassembly for display under the control of the electronic subassembly. A device is also described for operating a display device by generating a continuously updated display based on sequentially received image data frames, wherein the image data frames define one or more pixels.

[0003] Patent document EP1691272A2 describes a method and system for processing video data that needs to be displayed on a first video display, which is connected to a single mobile multimedia processor that supports multiple display formats. The single multimedia mobile processor can be integrated into a mobile device. The video data transferred from the memory to the first video display by the DMA controller can be limited based on a specific first video format associated with the video data to be displayed on the first video display. Only a limited amount of video data that needs to be displayed by the first video display can be transferred from the memory to the first video display by the DMA controller. Summary of the invention

[0004] The object of the present invention is to provide a method for operating an active-matrix display, by means of which the active-matrix display can be operated cost-effectively and in particular with a very flexible color change.

[0005] The object of the present invention is achieved by a method for operating an active matrix display, the method comprising the following steps:

[0006] - loading a data memory with image data of a 1 bit color depth per pixel of an image to be displayed on the active matrix display,

[0007] - executing a program stored in the program memory of the microcontroller, which program controls the DMA controller,

[0008] causing the DMA controller to read image data with a color depth of 1 bit per pixel from the data memory, wherein the read image data with a color depth of 1 bit per pixel is extended by the program with additional blank data corresponding to the parallel RGB interface specification, thereby generating an RGB image data set readable by an active matrix display, and

[0009] -The RGB image data set generated by the program is transferred to the hardware SPI connected to the DMA controller through the DMA controller, and the SPI sends the RGB image data set serially (seriell) to the active matrix display through its data output. Here, in order to synchronize the data transmission with the active matrix display, the pixel clock input of the active matrix display is controlled by the SPI clock output.

[0010] Active matrix displays (AMD), in particular liquid crystal display devices, have active control of a plurality of point-shaped image display elements (pixels) arranged in rows and columns. The plurality of point-shaped image display elements arranged in rows and columns form a matrix of image display elements, which can be controlled, for example, by thin-film transistors on the matrix. Active matrix displays can, for example, be active matrix liquid crystal displays, which are also abbreviated to AMLCD (English: active matrix liquid crystal display). Alternatively, active matrix displays can also be based on other display technologies, such as organic LEDs (OLED or AMOLED).

[0011] Active matrix displays (AMD) can generally be equipped with an internal image memory or without it. Image memory is also generally referred to as frame buffer. The method according to the invention is particularly advantageously suitable for operating active matrix displays that are not equipped with an internal image memory.

[0012] The image memory usually has essentially any data memory, which however must be suitable for storing the image data therein. Preferably, the data memory is at least one electronic storage module with free selection, i.e. direct access. This type of memory is also referred to as RAM. For example, it can be a static RAM (SRAM) or a dynamic RAM (DRAM).

[0013] Since large data memories or image memories are relatively expensive above a certain resolution, active-matrix displays are preferably manufactured and provided without internal image memory, so that the price of the active-matrix displays can be kept as low as possible. However, it is necessary for users of such active-matrix displays without image memory to provide the required data memory or image memory in order to be able to display images with the desired color depth on the active-matrix display used.

[0014] The method for operating an active matrix display according to the invention aims to find a technical solution so that images with reduced color depth, in particular images with a color depth greater than 1 bit per pixel, can be displayed on an active matrix display being operated without having to have a data memory or image memory with a storage size corresponding to the desired or displayed color depth. With the method according to the invention, in particular only one data memory or one image memory with a color depth of 1 bit per pixel is required. Therefore, in the simplest case, only information is stored in the data memory or in the image memory as to whether a certain point-shaped image display element (i.e. a certain pixel) should be lit or remain dark. Therefore, according to the invention, the color information that may be desired for each pixel, each row and / or each column of the matrix of the active matrix display does not have to be stored in the data memory or the image memory, but can be provided individually according to each pixel, each row and / or each column of the matrix of the active matrix display by a program stored in a program memory. Since the full color depth that the correspondingly selected active matrix display may provide due to the design type is not required in many application scenarios, a significantly smaller data memory or image memory can be used when using the method according to the invention. This enables the operation of the active matrix display to be realized very cost-effectively.

[0015] Active matrix displays (e.g. AM-LCD or AM-OLED) can provide, for example, high resolutions of up to 4096 x 2180 dots (pixels) or even higher, depending on their size and construction, and usually have a color depth of 24 bits per pixel. That is, these active matrix displays can display about 16.8 million different colors per pixel. Such high resolution and color depth active matrix displays have significantly higher storage requirements for image content than passive matrix displays. Such large image content can no longer be stored in "chip on glass" (COG) memories or "chip on board" (COB) memories with display sizes of about 3.5 inches or resolutions of about 320 x 240 pixels or more, so such displays do not have internal image memory. Since the display matrix must be constantly updated like a passive matrix display to maintain a flicker-free image, the required image data must be continuously provided by a microcontroller or application processor. The microcontroller or processor either fetches these image data from its internal memory (e.g., SRAM) or usually fetches the image data from an external SD-RAM or DDR-RAM, because only in this way can there be enough storage space available.

[0016] Due to the required update frequencies of the displays (e.g. ≥50 Hz) and the high image storage requirements, the data rates required to operate active-matrix displays quickly reach 100 Mbit / s up to over 10 Gbit / s. This data rate must be transmitted continuously, both between the microcontroller or processor and the display and between the microcontroller or processor and the external image data memory, even for static images. Such high bandwidths can only be transmitted to the display via special interfaces, such as parallel RGB (DPI) or LVDS. In addition, the microcontroller must contain high-performance peripheral components in order to be able to process and provide such data rates, which usually results in significantly higher costs for operating active-matrix displays than for passive-matrix displays.

[0017] Active matrix displays usually have huge color depth, so the signal sources used to operate such displays, such as microcontrollers and processors, must have suitable interfaces (such as parallel RGB interfaces), complex peripheral modules (such as hardware accelerators), DRAM controllers, and a large number of inputs and outputs (I / O). These peripheral modules require additional chip area. In addition, due to the large number of inputs and outputs, the chip housing also becomes larger, so the microcontroller not only becomes more expensive, but also the complexity of the layout is significantly increased. Therefore, microcontrollers can be divided into two categories according to resolution for being suitable or unsuitable for operating active matrix displays without image memory. Although many microcontrollers with required peripheral modules and display interfaces can reduce the color depth, for example, to 8 bits or 256 colors per pixel, and thus save pins and memory, users still have to use a complete microcontroller with special peripheral modules and a pre-given display interface. The microcontroller is mainly discussed under the framework of the present invention. However, for example, a processor or a microcontroller and a processor implemented in an FPGA can also be used in the same way to replace the microcontroller.

[0018] This situation causes dissatisfaction for all users who do not need color display or only need a very limited number of colors but still want to use the other advantages of active matrix displays (such as high contrast, high resolution, high brightness, a good choice of many standard sizes and / or a more attractive visual appearance than passive matrix displays are generally.

[0019] The advantage of the method according to the invention is that it allows the user to use a cheap, simple, relatively primitive microcontroller or processor and simulate the parallel RGB interface of the active matrix display without the help of an external display controller with an image memory (such as SSD2119, FT800) or a timing generator (such as CPLD, FPGA), thereby directly and low-costly controlling the active matrix display.

[0020] Preferably, a microcontroller that can be used to perform the method includes a data memory for image data and a program memory storing a program. The program includes a program code readable by the microcontroller, which configures and / or designs the microcontroller to perform the method according to the present invention when the microcontroller executes the program code.

[0021] Preferably, the microcontroller further comprises a DMA controller (DMAC) and a hardware SPI peripheral device (hereinafter referred to as hardware SPI), the hardware SPI having a serial data output (MOSI) and a clock output (SCK).

[0022] After the DMA controller controlled by the program reads the image data with a color depth of 1 bit per pixel from the data memory, according to the method, the program expands the image data with additional blanking data corresponding to the specification of the parallel RGB interface of the active matrix display to be controlled. The blanking data supplements the matrix of image data pixels to be visually displayed with additional data pixels, which expand the image data pixels into an enlarged matrix, which in addition to the internal image data pixels also includes a vertical leading blanking period (vertical front porch), a vertical trailing blanking period (vertical trailing porch) and a vertical synchronization, and includes a horizontal leading blanking period (horizontal front porch), a horizontal trailing blanking period (horizontal trailing porch) and a horizontal synchronization.

[0023] Therefore, the program automatically extends the image data with additional blank data, thereby generating an RGB image data set (frame) readable by an active matrix display. Then, according to the method of the present invention, the automatically generated RGB image data set is transmitted by the program in a special way, that is, transmitted to the hardware SPI (English: serial peripheral interface) connected to the DMA controller through a DMA controller (DMAC). Therefore, the program automatically extends the image data with the additional blank data, in particular, generates an RGB image data set (frame) readable by an active matrix display, which meets the requirements of a display with a parallel RGB interface. In most cases, a display with a parallel RGB interface is a color display with a parallel RGB interface accordingly. However, the method according to the present invention can also be applied to a pure monochrome active matrix display, in which the data lines for transmitting the color information of the parallel RGB interface are usually called D0, D1, D2, ... Dn, instead of R0, R1, R2, ... Rn, G0, G1, G2, ... Gn, B0, B1, B2, ... Bn in a color display.

[0024] The hardware SPI sends the RGB image data set automatically merged by the program serially to the display through its data output (MOSI; English: master out, slave in).

[0025] In order to synchronize the data transmission with the active matrix display, the pixel clock input (PCLK) of the active matrix display is controlled by the SPI clock output (SCK). In order to be able to achieve this, in a hardware construction including a microcontroller required for carrying out the method and a required active matrix display, the SPI clock output (SCK) of the microcontroller is connected to the pixel clock input (PCLK) of the active matrix display.

[0026] Other signals, such as the horizontal synchronization pulse (HSYNC), the vertical synchronization pulse (VSYNC) and the data enable signal (DE), are also generated, i.e. provided, by the program, so that no specific pins are required for this purpose, but only simple GPIOs of the microcontroller can be used. For this purpose, the program tracks the position in the data stream in the horizontal and vertical direction and controls the signals HS, VS and DE accordingly. As a receiving pulse for reading the color information into the display, the pixel clock input (PCLK), the method described here directly uses the SPI clock line (SCK) of the hardware SPI peripheral of the microcontroller, which is connected to the pixel clock input (PCLK), as already mentioned.

[0027] The color information is provided directly by the data output of the hardware SPI peripheral (MOSI). In the simplest case, all color inputs of the display are connected to each other and to the MOSI pin of the microcontroller for this purpose. The display will then operate in pure monochrome as a black and white display. However, the display can also be displayed in monochrome instead of black and white by correspondingly connecting the color inputs of the display, for example black and red or black and yellow, in particular in any color from the color depth palette of the display. In the further description of preferred embodiment variants of the invention, alternative configurations for the connection and / or manipulation of the color inputs of the display will also be revealed later, so that the monochrome display can also be replaced by an arbitrary color display.

[0028] In an extension of the method, the program stored in the program memory can automatically add the additional blanking data required according to a predetermined specification to the image data during its execution in order to simulate a parallel RGB interface.

[0029] Such an addition can be carried out in particular by inserting the blank data piecewise in the form of a row-by-row or column-by-column grid into the serial data stream of the image data.

[0030] In order to insert blank data segments into the serial data stream, it can be particularly provided that: the program automatically inserts a number of dummy bytes (Dummy-Bytes) corresponding to the parallel RGB interface specification into the data stream of the image data. The dummy bytes can be provided in the following manner: the program is designed to read a fixed byte from a fixed preset storage position based on a fixed preset storage position in the data memory, and automatically copy the read byte to the corresponding position in the data stream of the image data to generate the required blank data. According to the known display specifications of the parallel RGB interface, the length of the image row (i.e., the number of pixels per row of the image to be displayed) and the length of the image column (i.e., the number of pixels per column of the image to be displayed) are known. Therefore, blank data or dummy bytes can be inserted in segments into the correct position in the serial data stream of the image data.

[0031] The program stored in the program memory can automatically and synchronously generate the synchronization signals (HSYNC, VSYNC, Data-Enable) required to synchronously read the data stream of image data into the active matrix display during its execution, and send it to the active matrix display (AMD) through the GPIO of the microcontroller.

[0032] Therefore, the program provides the required synchronization signal at the required time point according to the specification of the parallel RGB interface. The horizontal synchronization signal can be provided, for example, at the first GPIO of the microcontroller. The vertical synchronization signal can be provided, for example, at the second GPIO of the microcontroller. The data enable signal can be provided, for example, at the third GPIO of the microcontroller. Each GPIO is a general input / output pin at a microcontroller port known to those skilled in the art. For example, a GPIO can be used as a digital input or output.

[0033] As mentioned above, in a first embodiment variant of the method, one or more RGB inputs of the active matrix display can be connected to each other and together to a data output (MOSI) of a hardware SPI peripheral of the microcontroller. In this case, the data output (MOSI) of the hardware SPI peripheral controls the connected RGB inputs of the active matrix display individually, or the data output (MOSI) of the hardware SPI peripheral controls together a corresponding plurality of connected RGB inputs of the active matrix display. For example, if a single pin of an 8-bit color channel (i.e. any one of the red channel, the green channel or the blue channel) is connected to the data output (MOSI) of the hardware SPI peripheral, the image read from the data memory is displayed on the connected active matrix display in the corresponding hue, i.e., for example, in a specific red, a specific green or a specific blue. Accordingly, this connection can be hardwired so that the color setting is non-programmable, i.e., cannot be changed without physical intervention.

[0034] Depending on the type and number of RGB color channel pins connected to the data output (MOSI) of the hardware SPI peripheral, any color can be selected from the palette corresponding to the parallel RGB interface specification of the display.

[0035] In a second embodiment of the method, in order to set a specific color tone, the data stream provided by the data output (MOSI) can alternatively or additionally be guided through an inverter (complement gate) before being fed to one or more RGB inputs of an active matrix display (AMD). Alternatively or additionally, different pins of the corresponding 8-bit color channel can be selectively set to "0" instead of "1" to be able to set specific color values.

[0036] In a third embodiment of the method, alternatively or additionally, the data stream provided via the data output (MOSI) can be fed to the respective first input of one or more AND gates, and the program can provide control data via at least one additional GPIO of the microcontroller, which is connected to the respective second input of the respective AND gate, for feeding the masked data stream to one or more RGB inputs of the active matrix display (AMD) after the masked data stream, so that the desired RGB values ​​are automatically set by the control of the at least one AND gate by the program stored in the program memory. For example, one or more pins of each 8-bit color channel can be selectively programmed to "1" or "0". Thus, the pins of the color channels controlled by the data output (MOSI) of the hardware SPI peripheral can be switched at any time as desired by the program in order to select, i.e. activate, different colors for display on the active matrix display. This program-controlled switching can not only be targeted at each frame to be displayed, but also the color to be displayed can be switched arbitrarily within a frame, such as switching after each row or multiple rows of a frame, switching alternately within a row, for example, making one or more columns displayed in specific colors respectively, or even displaying pixel by pixel, so that images of almost any color can be displayed on the active matrix display.

[0037] In order to implement this special expansion solution, the program stored in the program memory can, during its execution, automatically switch at least one AND gate synchronously with the data flow, in particular based on a signal of the SPI clock output (SCK), in order to change the color displayed on the active matrix display (AMD), in particular column by column, row by row or pixel by pixel.

[0038] In another possible embodiment, the RGB image data set may be sent not directly to an active matrix display, but to an interface converter, which converts the data stream of the RGB image data set into a changed data stream of another display interface, in particular, into a changed data stream of a non-parallel RGB interface, such as an LVDS interface, and then provides the converted data stream as an image data set to an active matrix display, in particular, to an active matrix display having an interface different from a parallel RGB interface.

[0039] The object of the present invention is also achieved by a control device, which has:

[0040] - a data memory for storing image data with a color depth of 1 bit per pixel of an image to be displayed on an active matrix display,

[0041] - a microcontroller having a program memory, in which a program is stored, the program being configured and designed to execute the method according to one or more of the embodiments, wherein the microcontroller controls a DMA controller controlled by the program and a hardware SPI connected to the DMA controller, so that:

[0042] -The RGB image data set generated by the program can be transferred to the hardware SPI connected to the DMA controller through the DMA controller, so that the hardware SPI can transmit the RGB image data set to the hardware SPI through its data output.

[0043] The image data set is sent serially to the active matrix display,

[0044] - wherein, in order to synchronize the data transfer with the active matrix display, the SPI clock output of the microcontroller is connected to the pixel clock input of the active matrix display.

[0045] Any standard microcontroller can be used as the microcontroller, for example an Arm Cortex-Mx IP-Core with a RISC architecture. Alternatively, for example an Arm Cortex-Ax IP-Core which is already widely used in smartphones, mobile computers and digital TV devices can also be used. A dedicated display controller such as SSD 2119 or FT 800 is not required. A dedicated timing generator such as CPLD or FPGA is also not required.

[0046] The DMA controller may be part of a microcontroller, in whose program memory a program is stored, which is configured and designed to perform the method. The hardware SPI connected to the DMA controller may also be part of a microcontroller, in whose program memory a program is stored, which is configured and designed to perform the method.

[0047] The control device comprising the microcontroller, the DMA controller and the connected hardware SPI can form a display assembly connected to a selected active matrix display. In the display assembly, in particular the SPI clock output of the hardware SPI peripheral device can be connected to the pixel clock input of the active matrix display.

[0048] In the display assembly, a first GPIO port of a microcontroller can be connected to an HSYNC port of an active matrix display to transmit a horizontal synchronization signal. A second GPIO port of the microcontroller can be connected to a VSYNC port of an active matrix display to transmit a vertical synchronization signal. A third GPIO port of the microcontroller can be connected to a Data-Enable port of an active matrix display to transmit a data enable signal. Each GPIO is a general purpose input / output pin at a microcontroller port known to those skilled in the art. For example, a GPIO can be used as a digital input or output.

[0049] In this display assembly, one or more RGB inputs of the active matrix display (AMD) can be connected to each other and together to the data output (MOSI) of the hardware SPI peripheral of the microcontroller.

[0050] In this display assembly, the data output (MOSI) of the microcontroller can be connected to an inverter (compensation gate) if necessary, and the inverter output is then connected to one or more RGB inputs of the active matrix display.

[0051] In the display component, a data output (MOSI) of the microcontroller can, if necessary, be connected to a corresponding first input of one or more AND gates so that the program can provide control data via at least one additional GPIO of the microcontroller (which is connected to a corresponding second input of a corresponding AND gate) for feeding the masked data stream to one or more RGB inputs of an active matrix display (AMD) after the masked data stream so as to automatically set the desired RGB value by manipulating at least one AND gate by a program stored in a program memory.

[0052] In this display assembly, the microcontroller can be connected to the input side of the interface converter instead of being directly connected to the active matrix display, so as to convert the data stream of the RGB image data set into a changed data stream of another display interface, in particular into a changed data stream of a non-parallel RGB interface, and then provide the converted data stream as an image data set to the active matrix display, in particular to an active matrix display having an interface different from a parallel RGB interface. In this regard, in this display assembly variant, the interface converter is connected to the actual active matrix display on the output side.

[0053] The present invention also relates to a computer program product having a machine-readable carrier on which a program code of a program is stored, the program code being readable by a control device as described above and constructing and / or designing the control device so that, when the program code is executed by the control device, the control device executes a method according to one or more of the described embodiments.

[0054] The machine-readable carrier may, for example, comprise a storage module, such as a ROM or EPROM, a USB stick or a CD-ROM or a DVD. The machine-readable carrier may also be a data storage on a server, which is configured and designed to read a program from the data storage of the server upon request to create a copy of the data and then send the copy to the requesting client for storage on the data storage of the client computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The specific features of these exemplary embodiments can be considered individually or in combination to form the general features of the present invention when necessary, regardless of where they are specifically mentioned in this article. Among them:

[0056] Figure 1 A schematic diagram shows an exemplary first embodiment of a control device or display assembly for carrying out the method according to the invention, wherein the hard-wired RGB inputs of an active-matrix display are connected to an SPI data output (MOSI) of a microcontroller, wherein the data memory is an internal RAM,

[0057] Figure 2 A schematic diagram shows an exemplary first embodiment of a control device or display assembly for carrying out the method according to the invention, wherein the hardwired RGB inputs of an active-matrix display are connected to an SPI data output (MOSI) of a microcontroller, wherein the data memory is an external RAM,

[0058] Figure 3 A schematic diagram of an exemplary second embodiment of a control device or display assembly for carrying out the method according to the invention is shown, wherein a representative RGB input for green of an active matrix display is connected via an inverter to a data output of a microcontroller and a representative RGB input for red of an active matrix display is set to a "0" level,

[0059] Figure 4 A schematic diagram shows an exemplary third embodiment of a control device or display assembly for carrying out the method according to the invention, wherein representative RGB inputs for green and red of an active matrix display are connected to data outputs of a microcontroller via inverters, respectively,

[0060] Figure 5A schematic diagram of an exemplary fourth embodiment of a control device or display assembly for carrying out the method according to the invention is shown, wherein representative RGB inputs for blue, green and red of an active matrix display are connected to data outputs of a microcontroller via AND gates, respectively, and the AND gates are driven by separate GPIOs,

[0061] Figure 6 A schematic diagram shows an exemplary fifth embodiment of a control device or display assembly for carrying out the method according to the invention, wherein a microcontroller is connected to an input of an interface converter, an output of the interface converter is connected to an active matrix display,

[0062] Figure 7 A schematic diagram showing the structure of image data and blank data corresponding to the parallel RGB interface specification is shown.

[0063] Figure 8 A schematic diagram showing the horizontal timing of the parallel RGB interface,

[0064] Fig. 9 A schematic diagram showing the vertical timing of the parallel RGB interface,

[0065] Fig.10 A flow chart showing the basic steps of the method according to the invention,

[0066] Fig.11 A schematic diagram showing 8-bit color channels of an RGB input to an exemplary active matrix display,

[0067] Fig.12 FIG. 4 is a schematic diagram showing a state machine H_STATE for generating a horizontal synchronization signal and transmitting image data,

[0068] Fig.13 Schematic diagram of a state machine V_STATE for generating a vertical synchronization signal,

[0069] Fig.14 shows a schematic flow chart for generating a horizontal synchronization signal HSYNC,

[0070] Fig.15 A schematic flow chart for generating a vertical synchronization signal VSYNC is shown, and

[0071] Fig.16 A schematic flow chart for generating the synchronization signal DATA-ENABLE is shown. DETAILED DESCRIPTION

[0072] exist Figures 1 to 6 The figures of FIG. 4 show different exemplary embodiments of a control device 1 according to the invention which are able to carry out the method according to the invention.

[0073] The respective control device 1 has a data memory 2 (RAM) for storing image data with a 1-bit color depth per pixel. The respective control device 1 comprises a microcontroller 3 which is connected to an active-matrix display 4 in the manner according to the invention.

[0074] The microcontroller 3 also includes a program memory 5 (PRG), in which a program is stored, which is configured and designed to execute the method according to the present invention, wherein the microcontroller 3 controls a DMA controller 6 controlled by the program and a hardware SPI 7 connected to the DMA controller 6, so that the RGB image data set generated by the program can be transmitted to the hardware SPI 7 connected to the DMA controller 6 through the DMA controller 6, so that the RGB image data set can be sent serially to the active matrix display 4 through the SPI data input MOSI of the microcontroller. Here, in order to synchronize the data transmission with the active matrix display 4, the SPI clock output SCK of the microcontroller 3 is connected to the pixel clock input PCLK of the active matrix display 4.

[0075] The DMA controller 6 can be part of the microcontroller 3 as shown, in whose program memory 5 a program is stored, which is configured and designed to execute the method. The hardware SPI peripheral device 7 connected to the DMA controller 6 can also be part of the microcontroller 3, in whose program memory a program is stored, which is configured and designed to execute the method.

[0076] The control device 1 comprises a microcontroller 3, a DMA controller 6 and a connected hardware SPI 7, which can form a display component connected to a selected active matrix display 4. In the display component, the SPI clock output SCK of the hardware SPI 7 can be connected to the pixel clock input PCLK of the active matrix display 4.

[0077] In the display assembly, the first GPIO port GPIO_1 of the microcontroller 3 can be connected to the HSYNC port of the active matrix display 4 to transmit the horizontal synchronization signal. The second GPIO port GPIO_2 of the microcontroller 3 can be connected to the VSYNC port of the active matrix display 4 to transmit the vertical synchronization signal. The third GPIO port GPIO_3 of the microcontroller 3 can be connected to the DATA_ENABLE port of the active matrix display 4 to transmit the data enable signal. Each GPIO is a general input / output pin at a port of the microcontroller 3 known to those skilled in the art. For example, the GPIO can be used as a digital input or output.

[0078] In the display assembly, one or more RGB inputs of the active matrix display 4 can be connected to each other via connection 8 and together to line 9 which is directed to the data output MOSI of the hardware SPI peripheral 7 of the microcontroller 3, which is in particular Figure 1 and Figure 2 shown.

[0079] Here, the pixel clock input PCLK of the active matrix display 4 is controlled by the SPI clock output SCK in order to synchronize the data transmission with the active matrix display 4. In order to be able to achieve this, in a hardware construction including the microcontroller 3 required for carrying out the method and the required active matrix display 4, the SPI clock output SCK of the microcontroller 3 is connected to the pixel clock input PCLK of the active matrix display 4 via a fixed line 17.

[0080] In the display module, the SPI data output MOSI of the microcontroller 3 can also be connected via line 10 to an inverter 11 (complementary gate) if necessary, wherein the output of the inverter 11 is then connected via line 12 to one or more RGB inputs of the active matrix display 4. Figure 3 In the embodiment, for example, the inverter 11 is connected only to the color input of green (G0, G1, G2, etc.) via one or more lines 12. In this case, the color input of red (R0, R1, R2, etc.) is always set to "0" via line 13.

[0081] On the contrary, Figure 4 For example, there are two inverters 11.1 and 11.2, wherein the first inverter 11.1 is connected to the red (R0, R1, R2, etc.) color input via one or more first lines 12.1, and the second inverter 11.2 is connected to the green (G0, G1, G2, etc.) color input via one or more second lines 12.2.

[0082] Figure 5 A variant embodiment is shown, in which, as in the display component, the SPI data output MOSI of the microcontroller 3 can be connected to the corresponding first input 14.1 of one or more AND gates 15 when necessary, so that the program can provide control data through, for example, three additional GPIOs (GPIO_4, GPIO_5, GPIO_6) of the microcontroller 3, which are connected to the corresponding second input 14.2 of the corresponding AND gate 15 for feeding the masked data stream to one or more RGB inputs (R0, R1, R2, etc. or G0, G1, G2, etc. or B0, B1, B2, etc.) of the active matrix display 4 after the masked data stream, so that the required RGB value can be automatically set by the program stored in the program memory 5 to manipulate at least one AND gate.

[0083] In a display assembly, the microcontroller 3 may be connected to the input side of the interface converter 16 rather than directly to the active matrix display 4, such as Figure 6 As shown, the data stream of the RGB image data set is converted into a changed data stream of another display interface, in particular, into a changed data stream of a non-parallel RGB interface, and then the converted data stream is provided as an image data set to the active matrix display 4, in particular, to the active matrix display 4 having an interface different from the parallel RGB interface. In this regard, in this display component variant, the interface converter 16 is connected to the active matrix display 4 on the output side.

[0084] Figure 7 The structure of image data (pixels Pxl (0, 0) to Pxl (x-1, y-1)) and blank data corresponding to the parallel RGB interface specification is schematically shown. The method uses the peripheral modules of the hardware SPI peripheral device 7 and the DMA controller 6 contained in the microcontroller 3 to simulate the parallel RGB interface for operating the active matrix display 4. The microcontroller 3 only needs to have enough RAM or ROM memory (internal or external) to store the display image or part thereof with a color depth of 1 bit per pixel. The data memory 2 is also referred to as the frame buffer in the following text. In this way, an active matrix display 4 with a resolution of, for example, 320x 240 pixels only needs a frame buffer of 9.6 kilobytes (kByte). The DMA controller 6 is used here to transfer the frame buffer directly to the module of the hardware SPI peripheral device 7. The transmission is controlled here by an interrupt (Interrupt) configured by a software algorithm or a microcontroller program, so that the hardware SPI peripheral device 7 transmits the required blank data (also called black shoulder or edge) in addition to the valid data, which must be provided to the parallel RGB interface for synchronizing the active matrix display 4. Here, blank data is transmitted both before and after each visible row (horizontal leading and trailing edges) and before and after each visible column (vertical leading and trailing edges). Therefore, according to the specification of the parallel RGB interface, the visible image is surrounded by an invisible frame. During this period, the color value "black" is transmitted. The data enable signal (DE for short) of the parallel RGB interface indicates whether it is currently in the visible part or the invisible part of the transmission. In addition, the interface requires a horizontal synchronization pulse (HSYNC line, HS for short) before each row and a vertical synchronization pulse (VSYNC line, VS for short) before each image, such as Figure 8 and Fig. 9 This results in four regions in each case in the horizontal and vertical direction, the duration of which, ie the number of transmitted pixels, depends on the active matrix display 4 to be actuated.

[0085] exist Fig.10A flow chart of a method for operating an active-matrix display 4 is shown in FIG.

[0086] In a first step S1 , the data memory 2 is loaded with image data of a 1 bit color depth per pixel of an image to be displayed on the active matrix display 4 .

[0087] In the second step S2, a program stored in the program memory 5 of the microcontroller 3 is executed, which controls the DMA controller 6 to read image data with a color depth of 1 bit per pixel from the data memory 2, wherein the read image data with a color depth of 1 bit per pixel is expanded by the program with additional blank data corresponding to the specification of the parallel RGB interface, thereby generating an RGB image data set (frame) readable by the active matrix display 4.

[0088] In the third step S3, the RGB image data set generated by the program is transmitted to the hardware SPI 7 connected to the DMA controller 6 through the DMA controller 6, and the hardware SPI sends the RGB image data set serially to the active matrix display 4 through its data output MOSI. Here, in order to synchronize the data transmission with the active matrix display 4, the pixel clock input PCLK of the active matrix display 4 is controlled by the SPI clock output SCK.

[0089] The first step S1, the second step S2 and the third step S3 of the method do not have to be performed sequentially and separately from each other. Instead, these steps S1, S2 and / or S3 or in the form of sub-steps can be performed simultaneously, staggered and / or in a different order, in particular, blank data can be inserted in real time, for example, when horizontal synchronization, horizontal back porch and horizontal front porch are added to the visible image data during the transmission of the image line.

[0090] Fig.11 A schematic diagram of an 8-bit color channel at the RGB input of an exemplary active matrix display 4 is shown. Figures 1 to 6 In the figure, for the sake of clarity, only one line (R0, R1, R2 ..., G0, G1, G2 ..., B0, B1, B2 ...) is shown for each color channel (red, green, blue). Of course, depending on the color depth of the selected active matrix display 4, there may also be a certain number of multiple lines for each color channel (red, green, blue), wherein each line may be connected according to one of the disclosed embodiments, i.e., for example, as Figure 1 and Figure 2 The fixed wiring shown, such as Figure 3 and Figure 4 As shown, the inverter 11 is connected, and / or Figure 5 The connection is shown via an AND gate 15 . Fig.11The input of the RGB color channel with 8-bit color depth per pixel is shown as a representative example. This means that for each primary color red, green and blue, there can be 8 input lines (R0, R1, R2, R3, R4, R5, R6, R7, G0, G1, G2, G3, G4, G5, G6, G7, B0, B1, B2, B3, B4, B5, B6, B7), respectively. Those lines in each of the 8 input lines can be selectively connected in the same type or different types.

[0091] exist Fig.12 In FIG. 1 , an exemplary state machine H_STATE for generating a horizontal synchronization signal and transmitting image data is shown.

[0092] The following tasks are performed in the state machine H_STATE for generating horizontal synchronization signals and transmitting image data:

[0093] If the required number of transmitted image points (THS, THB, THD or THF) is reached according to the current state (H_SYNC, H_BACK, H_DATA or H_FRONT), switch to the next state. The DMA controller 6 is responsible for counting the transmitted image points. Before each H_STATE state transition, one or more completed DMA transfer processes occur. The state machine H_STATE is controlled by the progress (Fortschritt) of the DMA controller 6. The horizontal timing of the simulated parallel RGB interface is predetermined by the parameters THS, THB, THD and THF. These values ​​must match the display to be used. If the state machine H_STATE is in the H_DATA state and V_STATE is in the V_DATA state, the DMA controller 6 transfers the visible image data from the frame buffer to the hardware SPI peripheral device 7. In any other case, blank data is transmitted according to H_STATE and V_STATE. To this end, the DMA controller 6 sends the required number of dummy data (0x00) to the hardware SPI peripheral device 7. Each time the H_FRONT state is left, a line has been completely transferred. Subsequently, the row counter is incremented, which in turn controls the state machine V_STATE.

[0094] exist Fig.13 An exemplary state machine V_STATE for generating a vertical synchronization signal is shown in FIG.

[0095] The following tasks are performed in the state machine V_STATE for generating the vertical synchronization signal:

[0096] If the number of corresponding rows (TVS, TVB, TVD or TVF) of the row counter is reached according to the current state (V_SYNC, V_BACK, V_DATA or V_FRONT), switch to the next state. Before each V_STATE state transition, the row counter is reset. The state machine V_STATE is controlled by the row counter and can only reset it. The row counter is incremented by the state machine H_STATE. The vertical timing of the analog parallel RGB interface is predetermined by the parameters TVS, TVB, TVD and TVF. These values ​​must match the display to be used. Each time the state V_FRONT is left, an image has been completely transmitted. Therefore, the data pointer of the frame buffer can then be reset or set to a new image source.

[0097] exist Fig.14 An exemplary flow chart H_SYNC for generating a horizontal synchronization signal H_SYNC is shown in FIG.

[0098] The logic level of the signal H_SYNC is usually “active low”.

[0099] exist Fig.15 An exemplary flowchart V_SYNC for generating a vertical synchronization signal V_SYNC is shown in FIG.

[0100] The logic level of the signal V_SYNC is usually “active low”.

[0101] exist Fig.16 An exemplary flow chart for generating the synchronization signal DATA_ENABLE is shown in FIG.

[0102] The logic level of the signal DATA_ENABLE is usually "high active".

Claims

1. A method for operating an active matrix display (4), comprising the following steps: - loading the data memory (2) with image data having a color depth of 1 bit per pixel of an image to be displayed on the active matrix display (4), - executing a program stored in a program memory (5) of a microcontroller (3), said program controlling a DMA controller (6) so that said DMA controller (6) reads image data with a color depth of 1 bit per pixel from said data memory (2), wherein said read image data with a color depth of 1 bit per pixel is extended by said program with additional blank data corresponding to the parallel RGB interface specification, thereby generating an RGB image data set (frame) that can be read by said active matrix display (4), and - The RGB image data set generated by the program is transferred to a hardware SPI (7) connected to the DMA controller (6) through the DMA controller (6), and the hardware SPI sends the RGB image data set serially to the active matrix display (4) through its data output (MOSI), wherein, in order to synchronize the data transmission with the active matrix display (4), the pixel clock input (PCLK) of the active matrix display (4) is controlled by the SPI clock output (SCK).

2. The method according to claim 1, characterized in that The program stored in the program memory (5) automatically adds additional blank data required according to a predetermined specification to the image data during its execution to simulate a parallel RGB interface, in particular by inserting the blank data into the serial data stream of the image data in a grid-like manner row by row or column by column, in particular by automatically inserting a number of virtual bytes corresponding to the parallel RGB interface specification into the data stream of the image data by the program.

3. The method according to claim 1 or 2, characterized in that: During its execution, the program stored in the program memory (5) automatically and synchronously generates synchronization signals (HSYNC, VSYNC, Data-Enable) required for synchronously reading the data stream of the image data into the active matrix display (4), and sends them to the active matrix display (4) through the GPIO of the microcontroller (3).

4. The method according to any one of claims 1 to 3, characterized in that One or more RGB inputs of the active matrix display (4) are connected to each other and together to a data output (MOSI) of a hardware SPI peripheral device (7).

5. The method according to any one of claims 1 to 4, characterized in that The data stream provided via the data output (MOSI) is directed through an inverter (11) before being fed to one or more RGB inputs of the active matrix display (4).

6. The method according to any one of claims 1 to 5, characterized in that The data stream provided via the data output (MOSI) is fed to respective first inputs of one or more AND gates (15), and the program provides control data via at least one additional GPIO of the microcontroller (3), the GPIO being connected to respective second inputs of respective AND gates (15) for feeding the masked data stream to one or more RGB inputs of the active matrix display (4) after masking the data stream, so as to automatically set the desired RGB value by manipulation of the at least one AND gate (15) by the program stored in the program memory (5).

7. The method according to claim 6, characterized in that During its execution, the program stored in the program memory (5) automatically switches the at least one AND gate (15) synchronously with the data stream, in particular based on a signal of the SPI clock output (SCK), so as to change the color to be displayed on the active matrix display (4), in particular column by column, row by row or pixel by pixel.

8. The method according to any one of claims 1 to 7, characterized in that The RGB image data set is not sent directly to the active matrix display (4), but is sent to an interface converter (16), which converts the data stream of the RGB image data set into a changed data stream of another display interface, in particular into a changed data stream of a non-parallel RGB interface, and provides the converted data stream as an image data set to the active matrix display (4), in particular to an active matrix display (4) having an interface different from the parallel RGB interface.

9. A control device comprising: - a data memory (2) for storing image data with a color depth of 1 bit per pixel of an image to be displayed on an active matrix display (4), - a microcontroller (3) having a program memory (5) in which a program is stored, the program being configured and designed to execute the method according to any one of claims 1 to 8, wherein the microcontroller (3) controls a DMA controller (6) controlled by the program and a hardware SPI (7) connected to the DMA controller (6), so that an RGB image data set generated by the program can be transferred to the hardware SPI (7) connected to the DMA controller (6) via the DMA controller (6), so that the hardware SPI (7) can send the RGB image data set serially to the active matrix display (4) via its data output, wherein In order to synchronize data transmission with the active matrix display (4), the SPI clock output (SCK) of the microcontroller (3) is connected to the pixel clock input (PCLK) of the active matrix display (4).

10. A computer program product having a machine-readable carrier on which a program code of a program is stored, the program code being readable by a control device according to claim 9, and the control device being constructed and / or designed so that, when the program code is executed by the control device, the control device executes the method according to any one of claims 1 to 8.

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