Chip sorting equipment and chip sorting method
By designing chip sorting equipment and using test results to transfer the chips of the wafer to be selected to the corresponding carrier wafer, the problem of low chip sorting efficiency in the existing technology is solved, and efficient chip sorting and output optimization are achieved. .
Patent Information
- Application Number
- CN202411465156.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-01-24
AI Technical Summary
The existing chip sorting technology is difficult to quickly divide multiple chips on the wafer to be selected into different levels and integrate them into a carrier wafer, resulting in low wafer output per unit time and no subsequent process steps are optimized.
By designing a chip sorting device, including testing device, disk device, and load components, the different levels of chips that are selected to the chip to be selected are used to the corresponding carrier wafers to achieve one -to -many or more pairs of one -to -one. Chip spanning.
It realizes rapid sorting of chips of different grades, improves the machine's wafer output per unit time, and optimizes subsequent process steps, such as chip-wafer hybrid bonding.
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Figure CN119346470A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and relates to but is not limited to a chip sorting device and a chip sorting method. Background Art
[0002] Die sorting is a key step in the chip packaging process. It is necessary to sort the chips and quickly separate the chips of different grades to improve the wafer output per hour (WPH) of the machine, and to obtain packaged chips of approximately the same grade for subsequent processes such as die to wafer hybrid bonding. Summary of the invention
[0003] In view of this, an embodiment of the present application provides a chip sorting device and a chip sorting method.
[0004] In a first aspect, an embodiment of the present application provides a chip sorting device, which includes: a testing device, used to test multiple chips to be selected on a wafer to be selected and obtain test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into chips of multiple different grades; a tray taking device, used to transfer chips of different grades of a wafer to be selected to multiple carrier wafers corresponding to different grades according to different grades according to the test results; a carrier assembly, used to receive multiple chips of different grades of a wafer to be selected transferred by the tray taking device; the carrier assembly is used to place multiple carrier wafers; a carrier wafer is used to place chips of the same grade; a discharge port, used to place a first wafer box; the first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly; a carrier wafer is placed with chips of the same grade.
[0005] In some embodiments, the carrier assembly includes a planetary carrier assembly; the planetary carrier assembly includes: a first supporting structure, including a plurality of ends arranged circumferentially and spaced apart; the end includes a carrier table; the carrier table is provided with an adsorption structure; the adsorption structure is used to adsorb carrier wafers; a first rotating structure, used to circumferentially rotate at least one carrier wafer adsorbed by the carrier table to a transfer area of a disc retrieval device; wherein a carrier wafer in the transfer area is used to receive chips of the same level transferred by the disc retrieval device.
[0006] In some embodiments, the carrier assembly includes a vertical carrier assembly; the vertical carrier assembly includes: a second supporting structure, including a plurality of ends arranged in a vertically stacked manner; the end includes a carrier surface; the carrier surface is provided with an adsorption structure; the adsorption structure is used to adsorb carrier wafers; a lifting structure, used to vertically lift and lower each carrier wafer adsorbed by the carrier surface to the carrier position of a disc retrieval device; a second rotating structure, used to circumferentially rotate each carrier wafer adsorbed by the carrier surface to the transfer area of the disc retrieval device; wherein each carrier wafer in the transfer area and located at the carrier position is used to receive chips of the same level transferred by the disc retrieval device.
[0007] In some embodiments, the chip sorting equipment also includes: a feed port for placing a second wafer box; the second wafer box is used to carry the wafers to be selected; a wafer to be selected includes multiple chips to be selected; a first turntable device is used to take out the wafers to be selected from the feed port and place the wafers to be selected into the testing device, and place the tested wafers to be selected into the transfer area of the tray retrieval device; a second turntable device is used to take out each carrier wafer with chips of the same grade from the carrier assembly and place each carrier wafer into the first wafer box.
[0008] In some embodiments, the first turntable device includes a clamping assembly; the clamping assembly includes clamping frames of different sizes, which are used to take out different sizes of selected wafers from the feed port and place the selected wafers into the testing device, and to place the tested selected wafers of different sizes into the transfer area of the turntable device.
[0009] In some embodiments, the test result includes at least one of coordinate data of the chip to be selected on the wafer to be selected, electrical characteristics of the chip to be selected, or appearance characteristics of the chip to be selected.
[0010] In the second aspect, an embodiment of the present application provides a chip sorting device, which includes: a testing device, used to test multiple chips to be selected on a wafer to be selected and obtain test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into chips of multiple different levels; a carrier assembly, used to place multiple tested wafers to be selected; a tray removal device, used to transfer chips of the same level of the multiple wafers to be selected to at least one carrier wafer according to the test results; a feed and discharge port, used to place a first wafer box and a second wafer box; the first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly in a first time period; a carrier wafer is placed with chips of the same level; the feed and discharge port is also used to place a second wafer box; the second wafer box is used to carry the wafer to be selected in the second time period; a wafer to be selected includes multiple chips to be selected; the second time period and the first time period are different time periods.
[0011] In some embodiments, the carrier assembly includes a planetary carrier assembly; the planetary carrier assembly includes: a support structure, including a plurality of ends arranged circumferentially and spaced apart; the end includes a carrier table; the carrier table is provided with an adsorption structure; the adsorption structure is used to adsorb carrier wafers; a rotation structure, used to circumferentially rotate at least one carrier wafer adsorbed by the carrier table to a transfer area of a disc retrieval device; wherein a carrier wafer in the transfer area is used to receive chips of the same level transferred by the disc retrieval device.
[0012] In some embodiments, the chip sorting equipment also includes: a first turntable device, used to take out the wafers to be selected from the feed and discharge ports and place the wafers to be selected into the testing device, and to place the tested wafers to be selected into the carrier assembly; the first turntable device is also used to take out each carrier wafer with chips of the same grade from the carrier assembly and place each carrier wafer into the first wafer box.
[0013] In a third aspect, an embodiment of the present application provides a chip sorting method, which includes: testing multiple chips to be selected on a wafer to be selected and obtaining test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into chips of multiple different levels; according to the test results, chips of different levels of a wafer to be selected are transferred to multiple carrier wafers corresponding to different levels according to different levels; testing a wafer to be selected in turn and transferring the chips of a wafer to be selected; or, testing multiple wafers to be selected in turn; and according to multiple test results, chips of the same level of multiple wafers to be selected are transferred to at least one carrier wafer.
[0014] In some embodiments, obtaining test results of multiple chips to be selected includes: obtaining at least one of the electrical characteristics of the chips to be selected or the appearance characteristics of the chips to be selected; obtaining a comprehensive yield based on at least one of the electrical characteristics of the chips to be selected or the appearance characteristics of the chips to be selected; obtaining a comparison result by comparing the comprehensive yield with a preset value; wherein the difference in comparison results is used to characterize that the multiple chips to be selected are classified into chips of multiple different levels.
[0015] In some embodiments, obtaining test results of multiple chips to be selected also includes: obtaining coordinate data of the chips to be selected on the wafer to be selected.
[0016] In each embodiment of the present application, by transferring multiple chips of different grades of a wafer to be selected to multiple carrier wafers corresponding to different grades according to different grades; or, by transferring multiple chips of the same grade of wafers to be selected to at least one carrier wafer; the chips can be sorted and the chips of different grades can be quickly separated, thereby improving the wafer output per unit time of the machine and optimizing the subsequent process steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1A schematic block diagram of a chip sorting device provided in an embodiment of the present application;
[0018] Figure 2 A schematic diagram of a wafer to be selected provided in an embodiment of the present application;
[0019] Figure 3 One of the schematic diagrams of a carrier wafer provided in an embodiment of the present application;
[0020] Figure 4 A second schematic diagram of a carrier wafer provided in an embodiment of the present application;
[0021] Figure 5A One of the schematic diagrams of a planetary carrier assembly provided in an embodiment of the present application;
[0022] Figure 5B A second schematic diagram of a planetary carrier assembly provided in an embodiment of the present application;
[0023] Figure 5C A third schematic diagram of a planetary carrier assembly provided in an embodiment of the present application;
[0024] Fig. 6A One of the schematic diagrams of a vertical carrier assembly provided in an embodiment of the present application;
[0025] Figure 6B A second schematic diagram of a vertical carrier assembly provided in an embodiment of the present application;
[0026] Figure 6C A third schematic diagram of a vertical carrier assembly provided in an embodiment of the present application;
[0027] Fig.6D A fourth schematic diagram of a vertical carrier assembly provided in an embodiment of the present application;
[0028] Figure 7 A schematic block diagram of another chip sorting device provided in an embodiment of the present application;
[0029] Figure 8 A schematic diagram of a first chip sorting device provided in an embodiment of the present application;
[0030] Fig. 9 A schematic diagram of a second chip sorting device provided in an embodiment of the present application;
[0031] Fig.10 A schematic diagram of a third chip sorting device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0032] The following will combine the implementation methods and drawings of this application to clearly and completely describe the technical solutions in the implementation methods of this application. The described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0033] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.
[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0035] Chip sorting is a key step in the chip packaging process. After being separated into individual chips and imported into the semiconductor manufacturing plant's process conditions and electrical test data, the chip sorting equipment uses a mechanical device to remove the target chip from the framewafer, inspect it, and then classify it and place it on the carrier wafer.
[0036] The existing chip sorting technology is to place each wafer with multiple independent chips on the chip sorting equipment, sort the multiple chips into different grades and integrate them on a carrier wafer. When the number of wafers to be sorted increases and each output wafer has only one grade, it is impossible to quickly sort the multiple chips on each wafer into different grades and quickly integrate them on a carrier wafer. The only way to quickly sort the multiple chips into different grades is to repeatedly extract each wafer.
[0037] In order to quickly classify the multiple chips on the selected wafer into different grades, a one-to-many method or a many-to-one method can be used to quickly place the multiple chips on the selected wafer on different carrier wafers. The chips can be sorted and quickly sorted into chips of different grades, which improves the wafer output per unit time of the machine and optimizes the subsequent process steps. For example, the optimization is conducive to the smooth progress of subsequent chip-wafer hybrid bonding processes. Among them, the one-to-many method can be understood as transferring chips of different grades of a selected wafer to multiple carrier wafers corresponding to different grades according to different grades; the many-to-one method can be understood as transferring chips of the same grade of multiple selected wafers to at least one carrier wafer; the specific details of the one-to-many method or the many-to-one method are described below.
[0038] In a first aspect, the present application provides a chip sorting device, referring to Figure 1 The chip sorting equipment includes: a testing device 106, which is used to test multiple chips to be selected on a wafer to be selected and obtain test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into multiple chips of different grades; a tray-taking device 108, which is used to transfer chips of different grades of a wafer to be selected to multiple carrier wafers corresponding to different grades according to different grades according to the test results; a carrier assembly 110, which is used to receive multiple chips of different grades of a wafer to be selected transferred by the tray-taking device; the carrier assembly is used to place multiple carrier wafers; a carrier wafer is used to place chips of the same grade; a discharge port 114, which is used to place a first wafer box; the first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly; a carrier wafer is placed with chips of the same grade.
[0039] refer to Figure 2 , each wafer to be tested includes multiple chips to be selected, and the multiple chips to be selected need to be tested and the test results of each chip to be selected are obtained; the test results are used to characterize the level of the corresponding chip to be selected. Exemplarily, a wafer to be selected 200 includes three different levels of chips, namely, a first-level chip 201, a second-level chip 202, and a third-level chip 203. The first-level chip 201 and the second-level chip 202 can be understood as two different levels of known good chips (Known Good Die, KGD). For example, the qualified level of the first-level chip 201 can be higher than the qualified level of the second-level chip 202; the third-level chip 203 can be understood as a known unqualified chip. In other exemplary embodiments, a wafer to be selected 200 may include more than three or less than three different levels of chips.
[0040] refer to Figure 3 and Figure 4 , each carrier wafer is placed with chips of the same level. Figure 3, a carrier wafer 300 includes chips of the same level, namely, first-level chips 301; the first-level chips 301 can be understood as known qualified chips. Figure 4 , a carrier wafer 310 includes chips of the same grade, namely, second grade chips 311. Among them, the qualified grade of the first grade chips 301 may be higher than the qualified grade of the second grade chips 311. Sorting out the first grade chips 301 of a carrier wafer 300 and the second grade chips 311 of a carrier wafer 310 of different qualified grades can be used to optimize subsequent process steps, for example, optimizing the bonding process to proceed smoothly.
[0041] refer to Figure 1 In some embodiments, the chip sorting equipment also includes: a feed port 102 for placing a second wafer box; the second wafer box is used to carry the wafer to be selected; a wafer to be selected includes multiple chips to be selected; a first turntable device 104 is used to take out the wafer to be selected from the feed port and place the wafer to be selected into the testing device, and to place the tested wafer to be selected into the transfer area of the tray retrieval device; a second turntable device 112 is used to take out each carrier wafer with chips of the same grade from the carrier assembly and place each carrier wafer into the first wafer box.
[0042] In some embodiments, a batch of wafers to be tested may be sorted sequentially through the chip sorting equipment's feed port 102, first turntable device 104, test device 106, tray retrieval device 108, tray loading assembly 110, second turntable device 112, and discharge port 114. A batch of wafers to be tested may be understood as the number of wafers to be tested loaded in a unit wafer box, for example, the number of wafers to be tested in a batch may be 13 pcs, or any number greater than 13 pcs or less than 13 pcs.
[0043] refer to Figure 1 ,refer to Figure 5A In some embodiments, the carrier assembly 110 includes a planetary carrier assembly 1102; the planetary carrier assembly 1102 includes: a first support structure 1104, including a plurality of ends 1106 arranged circumferentially and spaced apart; the end includes a carrier surface; the carrier surface is provided with an adsorption structure ( Figure 5A The adsorption structure is used to adsorb the carrier wafer; the first rotating structure ( Figure 5A (not shown), for circumferentially rotating at least one carrier wafer adsorbed on the stage to the transfer area A1 of the disc retrieval device; wherein a carrier wafer in the transfer area A1 is used to receive chips of the same grade transferred by the disc retrieval device.
[0044] refer to Figure 5BFor example, when a carrier wafer 300a is full (or has been completely filled) with first-level chips 301, or when additional chips need to be placed, another carrier wafer 300b adsorbed by the circumferentially rotating stage is moved to the transfer area A1 of the disc retrieval device, for example, to place additional first-level chips 301.
[0045] refer to Figure 5C For example, when a carrier wafer 300a is full (or has been completely filled) with first-level chips 301, or when some other chips need to be placed, another carrier wafer 310 adsorbed on the rotating stage is moved to the transfer area A1 of the tray removal device, for example, to place second-level chips 311. The transfer paths of all chips of different levels in a tested wafer to be selected are the same. The tray removal device only needs to transfer the marked chips from the same starting area to the same destination area, which can transfer chips more stably and quickly, and can complete chip sorting by cooperating with the rotation of the carrier assembly. Reference Figure 5A , the planetary carrier assembly 1102 rotates a carrier wafer 300a to the transfer area A1 of the disk-taking device, and the disk-taking device can transfer all the first-level chips 301 in a tested wafer to be selected to a carrier wafer 300a in sequence along the same transfer path; refer to Figure 5B After all the first-level chips 301 are transferred, the planetary carrier assembly 1102 rotates another carrier wafer 300b to the transfer area A1 of the disk-taking device, and the disk-taking device can transfer all the second-level chips in a tested wafer to be selected to a carrier wafer 300b in sequence along the same transfer path; refer to Figure 5C , and so on, all chips of different grades in a tested wafer to be selected can be transferred to the carrier of the planetary carrier assembly 1102 more stably and quickly.
[0046] refer to Figure 1 and Fig. 6A In some embodiments, the carrier assembly 110 includes a vertical carrier assembly 1103; the vertical carrier assembly 1103 includes: a second support structure 1105, including a plurality of ends 1107 arranged in a vertical stacked manner; the end includes a carrier surface; the carrier surface is provided with an adsorption structure 1109; the adsorption structure 1109 is used to adsorb the carrier wafer; a lifting structure ( Fig. 6A (not shown) for vertically lifting the carrier wafer adsorbed on each stage to the stage position of the disk-taking device; the second rotating structure ( Fig. 6A Not shown), used for circumferentially rotating the carrier wafer adsorbed on each carrier surface to the transfer area of the disc removal device; wherein each carrier wafer in the transfer area and located at the carrier position is used to receive chips of the same level transferred by the disc removal device.
[0047] refer to Figure 6C and Fig.6D , the vertical carrier assembly 1103 can utilize a lifting structure ( Figure 6C and Fig.6D The carrier wafer adsorbed on each stage surface is lifted and lowered along a vertical direction (Z direction in the example in the figure) to a stage position of a disc taking device.
[0048] refer to Fig.6D , the vertical carrier assembly 1103 lifting structure is in an initial state, and is used to obtain a batch of carrier wafers from the discharge port, for example, directly taking a whole batch of carrier wafers, and a carrier wafer is placed with chips of the same grade. For example, the number of a batch of carrier wafers can be 13 pcs, or any number greater than 13 pcs or less than 13 pcs.
[0049] refer to Figure 6C , and then extend to the corresponding platform position in turn through the lifting structure.
[0050] refer to Figure 6B , and then placed on the carrier, and vacuum adsorbed on the carrier by the adsorption structure 1109 under the carrier.
[0051] refer to Fig. 6A , rotating with the vertical direction (the example in the figure is the Z direction) as the axis, for example, rotating 90 degrees clockwise, is used to circumferentially rotate the carrier wafer adsorbed on each carrier surface to the transfer area of the disc removal device; wherein each carrier wafer in the transfer area and located at the carrier position is used to receive the same level of chips transferred by the disc removal device.
[0052] In some embodiments, reference Fig. 6A , the whole batch of carrier wafers are filled (or placed) with corresponding chips of the same level. For example, a carrier wafer 300 is filled with first-level chips 301, a carrier wafer 310 is filled with second-level chips 311, and other carrier wafers are filled (or placed) with corresponding chips of the same level ( Fig. 6A Not shown); Reference Figure 6B , rotating with the vertical direction (Z direction in the example of the attached figure) as the axis, for example, rotating 90 degrees counterclockwise, for circumferentially rotating the carrier wafer adsorbed on each stage surface to move out of the transfer area of the disc removal device; wherein each carrier wafer in the transfer area and located at the stage position is used to receive the same level of chips transferred by the disc removal device; refer to FIG. 6C to FIG. 6D , and then the lifting structure is lowered from the corresponding platform position to the initial position in sequence; refer to Fig.6D , the lifting structure of the vertical carrier assembly 1103 is in an initial state, and the entire batch of carrier wafers that have been filled (or placed completely) are placed into the discharge port.
[0053] The transfer paths of the chips of the same grade in a tested wafer to be selected are the same. It is only necessary to transfer the marked chips of the same grade from the same starting area to the same destination area, which can transfer the chips more stably and quickly. The chip sorting can be completed in cooperation with the carrier assembly; wherein the carrier assembly has a plurality of carrier wafers staggered in the vertical direction (Z direction in the example in the attached figure) and fixed in the transfer area. Fig.6D , the vertical carrier assembly 1103 lifting structure is in the initial state, and a batch of carrier wafers are obtained from the discharge port; Figure 6C , and then extend to the corresponding platform position in turn through the lifting structure; refer to Figure 6B , and then placed on the stage, and vacuum adsorbed on the stage by the adsorption structure 1109 under the stage; Fig. 6A , rotating with the vertical direction (Z direction in the example in the figure) as the axis, rotating the carrier wafer adsorbed on each stage surface to the transfer area of the plate removal device. After staggering and fixing multiple carrier wafers in the vertical direction (Z direction in the example in the figure) to the transfer area of the plate removal device, refer to Fig. 6A The tray-taking device can transfer all first-level chips 301 in a tested wafer to be selected along the same transfer path to a carrier wafer 300 in sequence; after the transfer of all first-level chips 301 is completed, the tray-taking device can transfer all second-level chips 311 in a tested wafer to be selected along the same transfer path to another carrier wafer 310 in sequence; and so on, all chips of different levels in a tested wafer to be selected can be transferred to different carriers of the vertical carrier assembly 1103 more stably and quickly.
[0054] In some embodiments, the first turntable device includes a clamping assembly; the clamping assembly includes clamping frames of different sizes, which are used to take out different sizes of selected wafers from the feed port and place the selected wafers into the testing device, and to place the tested selected wafers of different sizes into the transfer area of the turntable device.
[0055] In some embodiments, the test result includes at least one of coordinate data of the chip to be selected on the wafer to be selected, electrical characteristics of the chip to be selected, or appearance characteristics of the chip to be selected.
[0056] In a second aspect, the present application embodiment provides a chip sorting device, referring to Figure 7The chip sorting equipment includes: a testing device 406, which is used to test multiple chips to be selected on the wafer to be selected and obtain the test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into multiple chips of different grades; a carrier assembly, which is used to place the tested multiple wafers to be selected; a plate-taking device 408, which is used to transfer the chips of the same grade of the multiple wafers to be selected to at least one carrier wafer according to the test results; a feed and discharge port 402, which is used to place a first wafer box and a second wafer box; the first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly in a first time period; a carrier wafer is placed with chips of the same grade; the feed and discharge port 402 is also used to place a second wafer box; the second wafer box is used to carry the wafer to be selected in the second time period; a wafer to be selected includes multiple chips to be selected; the second time period and the first time period are different time periods.
[0057] Here, the testing device 406, the tray taking device 408, and the feeding and discharging port 402 can be understood by referring to the testing device 106, the tray taking device 108, and the feeding port 102 shown in 1. Figure 1 The feed port 102 is shown, and here the feed and discharge port 402 is used to place the first wafer box and the second wafer box.
[0058] refer to Figure 7 In some embodiments, the chip sorting equipment also includes: a first turntable device 404, used to take out the wafer to be selected from the feed and discharge port and place the wafer to be selected into the testing device, and to place the tested wafer to be selected into the carrier assembly; the first turntable device 404 is also used to take out each carrier wafer with chips of the same grade from the carrier assembly and place each carrier wafer into the first wafer box.
[0059] In some embodiments, a batch of wafers to be tested may be sorted sequentially through the feed and discharge port 402 of the chip sorting device, the first turntable device 404, the testing device 406, the tray assembly 410, the tray removal device 408, and the feed and discharge port 402. A batch of wafers to be tested may be understood as the number of wafers to be tested loaded in a unit wafer box. For example, the number of wafers to be tested in a batch may be 13 pcs, or any number greater than 13 pcs or less than 13 pcs.
[0060] refer to Figure 7 In some embodiments, the carrier assembly 410 includes a planetary carrier assembly; the planetary carrier assembly includes: a support structure, including a plurality of ends arranged circumferentially and spaced apart; the end includes a carrier table; the carrier table is provided with an adsorption structure; the adsorption structure is used to adsorb the wafer to be selected; a rotating structure, used to circumferentially rotate at least one wafer to be selected adsorbed by the carrier table to a transfer area of a disc removal device; wherein a carrier wafer in the transfer area is used to receive chips of the same level transferred by the disc removal device.
[0061] Planetary carrier assembly can refer to the above Figure 5A The satellite disk assembly 1102 shown in FIG. Figure 5A The planetary carrier assembly 1102 is shown, where the planetary carrier assembly is used to absorb the candidate wafers to be tested and the tested candidate wafers. In the subsequent process, the plate removal device 408 is used to transfer the chips of the same grade of the multiple candidate wafers to at least one carrier wafer according to the test results.
[0062] In a third aspect, an embodiment of the present application provides a chip sorting method, which includes: testing multiple chips to be selected on a wafer to be selected and obtaining test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into chips of multiple different grades; according to the test results, chips of different grades of a wafer to be selected are transferred to multiple carrier wafers corresponding to different grades according to different grades; testing a wafer to be selected in turn and transferring the chips of a wafer to be selected.
[0063] For example, reference Figure 1 and Figure 8 , or, refer to Figure 1 and Fig. 9 The chip sorting equipment includes: a feed port 102 for placing a second wafer box; the second wafer box is used to carry a wafer to be selected; a wafer to be selected includes multiple chips to be selected; a first turntable device 104 is used to take out the wafer to be selected from the feed port and put the wafer to be selected into the testing device, and put the tested wafer to be selected into the transfer area of the disk taking device; a testing device 106 is used to test multiple chips to be selected of the wafer to be selected and obtain the test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into multiple chips of different grades; a disk taking device 108 is used to take a wafer to be selected according to the test results. The chips of different grades are transferred to multiple carrier wafers corresponding to different grades according to different grades; the carrier assembly 110 is used to receive chips of different grades from a wafer to be selected transferred by the tray removal device; the carrier assembly is used to place multiple carrier wafers; a carrier wafer is used to place chips of the same grade; the second turntable device 112 is used to take out each carrier wafer with chips of the same grade from the carrier assembly and put each carrier wafer into the first wafer box; the discharge port 114 is used to place the first wafer box; the first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly; a carrier wafer is placed with chips of the same grade.
[0064] refer to Figure 1 and Figure 8 The chip sorting method includes but is not limited to the following steps:
[0065] Step S101, the second turntable device 112 transfers the blank first wafer box without chips placed at the discharge port 114 to the planetary carrier assembly 1102;
[0066] Step S102, the first turntable device 104 transfers the second wafer box with chips placed on the feed port 102 to the testing device 106 in sequence for testing;
[0067] Step S103, the first turntable device 104 puts the tested wafer to be selected into the transfer area of the disk taking device;
[0068] Step S104, rotating the planetary carrier assembly 1102, and rotating a carrier wafer 300a to the transfer area of the disk removal device;
[0069] Step S105, the disk taking device 108 can transfer all the first-level chips 301 in a tested wafer to be selected to a carrier wafer 300a in sequence along the same transfer path;
[0070] The disc taking device and the carrier assembly rotate in cooperation, referring to step S104 and step S105, and so on, the disc taking device 108 transfers all other chips of different grades remaining in a wafer to be selected that has been tested to the corresponding blank first wafer box of the planetary carrier assembly 1102, and obtains a plurality of sorted carrier wafers loaded with (or full of) chips;
[0071] Step S106, transfer the plurality of carrier wafers loaded with (or full of) chips on the planetary carrier assembly 1102 to the discharge port 114 in sequence for placement in the following process; wherein the transfer action not specifically described can be performed by a transfer robot ( Figure 8 not shown) implementation.
[0072] refer to Figure 1 and Fig. 9 The chip sorting method may also include but is not limited to the following steps:
[0073] Step S201: Transfer the blank first wafer box without chips placed at the discharge port 114 to the vertical carrier assembly 1103 in the initial state (refer to Fig.6D );
[0074] Step S202: The vertical carrier assembly 1103 is lifted and rotated from the initial state (reference Fig.6D ) into the final state (reference Fig. 6A );For the specific process, please refer to FIG. 6D to FIG. 6C , FIG. 6C to FIG. 6B , FIG. 6B to FIG. 6A The detailed description will not be repeated here;
[0075] Step S203, the first turntable device 104 transfers the second wafer box with chips placed on the feed port 102 to the testing device 106 in sequence and performs testing;
[0076] Step S204, the first turntable device 104 places the tested wafer to be selected into the transfer area of the disk taking device;
[0077] Step S205, combined with reference Fig. 6A , the tray-taking device 108 can transfer all first-level chips 301 in a tested wafer to be selected to a carrier wafer 300 along the same transfer path in sequence; after all first-level chips 301 are transferred, the tray-taking device can transfer all second-level chips 311 in a tested wafer to be selected to another carrier wafer 310 along the same transfer path in sequence; and so on, all chips of different levels in a tested wafer to be selected can be transferred to the blank first wafer box of the vertical tray assembly 1103 more stably and quickly to obtain a first wafer box loaded with (or full of) chips;
[0078] Step S206: After all the tested wafers to be selected are sorted in sequence, the rotation and lifting of the vertical carrier assembly 1103 are changed from the final state (reference Fig. 6A ) changes to the initial state (reference Fig.6D );For the specific process, please refer to FIG. 6A to FIG. 6B , FIG. 6B to FIG. 6C , FIG. 6C to FIG. 6D The detailed description will not be repeated here;
[0079] Step S206: The vertical loading plate assembly 1103 (reference Fig.6D ) is transferred to the discharge port 114 for placement in the next process; wherein the transfer action not specifically described may be performed by a transfer robot ( Fig. 9 not shown) implementation.
[0080] In each embodiment of the present application, by transferring multiple chips of different grades of a wafer to be selected to multiple carrier wafers corresponding to different grades according to different grades, the chips can be sorted and chips of different grades can be quickly separated, thereby improving the wafer output per unit time of the machine and optimizing subsequent process steps.
[0081] A chip sorting method comprises: testing a plurality of chips to be selected of a wafer to be selected and obtaining test results of the plurality of chips to be selected; the test results are used to characterize that the plurality of chips to be selected are classified into chips of a plurality of different grades; testing the plurality of wafers to be selected in sequence; and transferring the chips of the same grade of the plurality of wafers to at least one carrier wafer according to the plurality of test results.
[0082] For example, reference Figure 7 and Fig.10 The chip sorting equipment includes: a feed and discharge port 402 for placing a first wafer box and a second wafer box; the first wafer box is used to receive a plurality of carrier wafers transferred by a carrier assembly in a first period; a carrier wafer is placed with chips of the same grade; the feed and discharge port 402 is also used to place a second wafer box; the second wafer box is used to carry a wafer to be selected in a second period; a wafer to be selected includes a plurality of chips to be selected; the second period is different from the first period; a first turntable device 404 is used to take out the wafer to be selected from the feed and discharge port and put the wafer to be selected into a test device, and to put the tested wafer to be selected into a test device; The selected wafer is placed in the carrier assembly; the first turntable device 404 is also used to take out each carrier wafer with chips of the same level from the carrier assembly and place each carrier wafer into the first wafer box; the testing device 406 is used to test multiple chips to be selected of the selected wafer and obtain the test results of the multiple chips to be selected; the test results are used to characterize that the multiple chips to be selected are classified into multiple chips of different levels; the carrier assembly 410 is used to place the tested multiple wafers to be selected; the disk removal device 408 is used to transfer the chips of the same level of the multiple wafers to be selected to at least one carrier wafer according to the test results. Compared with the chip sorting equipment including the feed port and the discharge port, the two ports of the feed port and the discharge port are combined into one feed and discharge port 402, which is conducive to the miniaturization of the equipment.
[0083] Here, the testing device 406, the tray taking device 408, and the feeding and discharging port 402 can be understood by referring to the testing device 106, the tray taking device 108, and the feeding port 102 shown in Figure 1. Figure 1 The feed port 102 is shown, and here the feed and discharge port 402 is used to place the first wafer box and the second wafer box.
[0084] For example, reference Figure 7 and Fig.10 The chip sorting method may include but is not limited to the following steps:
[0085] Step S301, transferring the chips to be selected placed in the second wafer box of the inlet and outlet port to the planetary carrier assembly in sequence;
[0086] Step S302, rotating the planetary carrier assembly to the test area of the test device 406 and testing the chips to be selected; completing the test of all the chips to be selected in sequence;
[0087] Step S303, rotating the planetary carrier assembly to rotate a carrier wafer to the transfer area of the disk removal device;
[0088] Step S304, the disk taking device 108 can transfer all first-level chips in a tested wafer to be selected to a carrier wafer in sequence along the same transfer path;
[0089] Step S305, the disc taking device 108 rotates with the planetary disc assembly, referring to step S303 and step S304, and by analogy, the disc taking device 108 rotates another or more wafers to be selected that have been tested to the transfer area of the disc taking device in sequence, and transfers all first-level chips in the corresponding wafer to be selected to the same carrier wafer in sequence along the same transfer path, until a first wafer box full of chips is obtained; it should be noted that the first wafer box full of chips here can also be understood as a wafer box that cannot or does not need to place chips later, and can be transferred to the inlet and outlet ports for placement;
[0090] Step S306: transfer the first wafer box loaded with chips to the loading and unloading port for placement in the next process; wherein the transfer action not specifically described can be performed by a transfer robot ( Fig.10 (not shown) implementation;
[0091] The disc taking device rotates with the planetary disc carrier assembly, and the transfer robot ( Fig.10 The first chip (not shown) cooperates with the disk taking device, referring to step S304, step S305 and step S306, and so on, to complete the sorting of all the tested chips to be selected in sequence.
[0092] In some embodiments, obtaining test results of multiple chips to be selected includes: obtaining at least one of the electrical characteristics of the chips to be selected or the appearance characteristics of the chips to be selected; obtaining a comprehensive yield based on at least one of the electrical characteristics of the chips to be selected or the appearance characteristics of the chips to be selected; obtaining a comparison result by comparing the comprehensive yield with a preset value; wherein the difference in comparison results is used to characterize that the multiple chips to be selected are classified into chips of multiple different levels.
[0093] In some embodiments, obtaining test results of multiple chips to be selected also includes: obtaining coordinate data of the chips to be selected on the wafer to be selected.
[0094] The chip sorting equipment used in the chip sorting method provided in the embodiments of the present application is similar to the chip sorting equipment in the embodiments of the first aspect or the second aspect mentioned above. For the technical features not fully disclosed in the embodiments of the present application, please refer to the above embodiments for understanding, and no further details will be given here.
[0095] In each embodiment of the present application, by transferring chips of the same grade of multiple wafers to be selected to at least one carrier wafer, the chips can be sorted and chips of different grades can be quickly separated, thereby improving the wafer output per unit time of the machine and optimizing subsequent process steps.
[0096] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the protection scope of the present application.
Claims
1. A chip sorting device, characterized in that: include: A testing device, used for testing a plurality of chips to be selected of a wafer to be selected and obtaining test results of the plurality of chips to be selected; The test result is used to characterize that the plurality of chips to be selected are classified into chips of a plurality of different grades; A disk taking device, used for transferring the chips of the plurality of different grades of a wafer to be selected to a plurality of carrier wafers corresponding to the different grades according to the test result; A tray assembly, used for receiving the plurality of chips of different grades of the wafer to be selected transferred by the tray taking device; The carrier plate assembly is used to place the multiple carrier wafers; The carrier wafer is used to place chips of the same level; A discharge port, used for placing the first wafer box; The first wafer box is used to receive the plurality of carrier wafers transferred by the carrier assembly; one of the carrier wafers is provided with chips of the same grade.
2. The chip sorting device according to claim 1, characterized in that: The carrier assembly includes a planetary carrier assembly; the planetary carrier assembly includes: The first support structure comprises a plurality of ends arranged circumferentially and spaced apart from each other; the end comprises a loading platform; the loading platform is provided with an adsorption structure; the adsorption structure is used to adsorb the carrier wafer; A first rotating structure is used for circumferentially rotating at least one of the carrier wafers adsorbed by the stage to a transfer area of the disk-taking device; Among them, a carrier wafer in the transfer area is used to receive chips of the same level transferred by the disk-taking device.
3. The chip sorting device according to claim 1, characterized in that: The carrier assembly includes a vertical carrier assembly; the vertical carrier assembly includes: The second supporting structure comprises a plurality of ends arranged in a vertically stacked manner; the end comprises a loading platform; the loading platform is provided with an adsorption structure; the adsorption structure is used to adsorb the carrier wafer; A lifting structure, used for vertically lifting the carrier wafer adsorbed on each of the loading platforms to the loading platform position of the disk taking device; A second rotating structure is used for circumferentially rotating the carrier wafer adsorbed on each of the loading platforms to a transfer area of the disk taking device; Wherein, each of the carrier wafers in the transfer area and located at the stage position is used to receive chips of the same level transferred by the disc removal device.
4. The chip sorting device according to claim 1, characterized in that: The chip sorting equipment also includes: A feed port is used to place a second wafer box; the second wafer box is used to carry the wafer to be selected; the wafer to be selected includes the plurality of chips to be selected; A first turntable device is used to take out the wafer to be selected from the feed port and put the wafer to be selected into the testing device, and put the tested wafer to be selected into the transfer area of the turntable device; The second turntable device is used to take out each of the carrier wafers with chips of the same level placed thereon from the carrier assembly and put each of the carrier wafers into the first wafer box.
5. The chip sorting device according to claim 4, characterized in that: The first turntable device includes a clamping assembly; the clamping assembly includes clamping frames of different sizes, which are used to take out the selected wafers of different sizes from the feed port and place the selected wafers into the testing device, and to place the tested selected wafers of different sizes into the transfer area of the turntable device.
6. The chip sorting device according to any one of claims 1 to 5, characterized in that: The test result includes at least one of coordinate data of the chip to be selected on the wafer to be selected, electrical characteristics of the chip to be selected, or appearance characteristics of the chip to be selected.
7. A chip sorting device, characterized in that: include: A testing device, used for testing a plurality of chips to be selected of a wafer to be selected and obtaining test results of the plurality of chips to be selected; The test result is used to characterize that the plurality of chips to be selected are classified into chips of a plurality of different grades; A tray assembly, used for placing the plurality of tested wafers to be selected; A disk taking device, used for transferring chips belonging to the same level of the plurality of wafers to be selected to at least one carrier wafer according to the test result; A material feeding and discharging port, used for placing the first wafer box and the second wafer box; The first wafer box is used to receive multiple carrier wafers transferred by the carrier assembly in the first time period; one of the carrier wafers is placed with chips of the same level; the feed and discharge port is also used to place the second wafer box; the second wafer box is used to carry the wafer to be selected in the second time period; one of the wafers to be selected includes the multiple chips to be selected; the second time period and the first time period are different time periods.
8. The chip sorting device according to claim 7, characterized in that: The carrier assembly includes a planetary carrier assembly; the planetary carrier assembly includes: The support structure comprises a plurality of ends arranged at intervals around the circumference; the end comprises a loading platform; the loading platform is provided with an adsorption structure; the adsorption structure is used to adsorb the carrier wafer; A rotating structure, used for circumferentially rotating at least one of the carrier wafers adsorbed by the stage surface to a transfer area of the disk-taking device; Among them, a carrier wafer in the transfer area is used to receive chips of the same level transferred by the disk-taking device.
9. The chip sorting device according to claim 7, characterized in that: The chip sorting equipment also includes: A first turntable device is used to take out the wafer to be selected from the feeding and discharging port and put the wafer to be selected into the testing device, and put the tested wafer to be selected into the carrier assembly; The first turntable device is further used for taking out each of the carrier wafers with chips of the same level placed thereon from the carrier assembly and placing each of the carrier wafers into the first wafer box.
10. A chip sorting method, characterized in that: include: Testing a plurality of chips to be selected of a wafer to be selected and obtaining test results of the plurality of chips to be selected; The test result is used to characterize that the plurality of chips to be selected are classified into chips of a plurality of different grades; Transferring the chips of the plurality of different grades of the wafer to be selected to a plurality of carrier wafers corresponding to the different grades according to the different grades according to the test results; testing the wafers to be selected in sequence and transferring the chips of the wafers to be selected; or, Testing the plurality of wafers to be selected in sequence; and transferring chips belonging to the same level of the plurality of wafers to be selected to at least one carrier wafer according to the plurality of test results.
11. The chip sorting method according to claim 10, characterized in that: Obtaining test results of the plurality of chips to be selected, including: Acquire at least one of the electrical characteristics of the chip to be selected or the appearance characteristics of the chip to be selected; Obtaining a comprehensive yield rate according to at least one of an electrical characteristic of the chip to be selected or an appearance characteristic of the chip to be selected; Obtaining a comparison result by comparing the comprehensive yield with a preset value; The difference in the comparison results is used to indicate that the multiple chips to be selected are classified into chips of multiple different levels.
12. The chip sorting method according to claim 11, characterized in that: Acquiring the test results of the plurality of chips to be selected also includes: Obtain coordinate data of the chip to be selected on the wafer to be selected.