Test circuit

Abstract

A test circuit comprises: a module to be isolated; the scanning register module comprises a scanning chain formed by cascading N scanning registers; the data selection module comprises a first input end and a second input end, and the N scanning registers select input signals or scanning signals of the input end of the module to be isolated to the first input end of the data selection module under the control of scanning enable signals; the second input end of the data selection module is connected with the output end of the to-be-isolated module, and the data selection module selects one path of input data to be output under the control of the test mode signal; and the peripheral circuit is connected with the input end of the to-be-isolated module and / or the output end of the data selection module. The to-be-isolated module is isolated through the scanning register module, the output circuit can directly receive the input signal instead of the X-state output signal output by the to-be-isolated module, and the accuracy of circuit testing is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of chip testing, and in particular relates to a testing circuit. Background Art

[0002] With the development of the integrated circuit industry, the chip integration is getting higher and higher, the logic scale is getting larger and larger, and the working mode is becoming more and more complex. There are problems such as long testing time and low test coverage. Therefore, DFT (Design for Testability) testing is needed.

[0003] In existing DFT testing solutions, chip designs usually have some outsourced IPs, such as various PHY (Physical Layer) chips. When performing DFT digital logic testing, because these IPs are black box structures, the input and output signals will be in the X state, and the propagation of the X state will affect the coverage of the peripheral circuit test.

[0004] like Figure 1 As shown, the values ​​of the input signals in0 / in1 / in2 of the PHY chip cannot be observed, so the input circuits AND0 / XOR / OR of the PHY chip cannot be observed, and the previous stage driver of AND0 / XOR / OR cannot be observed either; in addition, since the outputs out0 / out1 / out2 of the PHY are in the X state, the outputs of the next stage logic circuits Gating0 / BUF0 / AND1 driven by them may also be in the X state, and the next stage circuit driven by Gating0 / BUF0 / AND1 cannot be measured due to the influence of the X state; this will lead to a large number of unmeasured risks in the logic around the PHY chip, which greatly affects the test quality.

[0005] In the prior art, a single trigger or multiple separate triggers are mostly used to cache signals to address the above problems. However, a single trigger cannot cache and output multiple input signals at the same time, and multiple separate triggers cannot be compressed, which requires a large circuit design area, and a single trigger or multiple separate triggers cannot avoid being mixed and chained with registers of other modules in the circuit. In addition, neither a single trigger nor multiple separate triggers can output the cached input signal completely and independently. If the complete input signal cannot be observed separately, defects in the circuit design process cannot be discovered and repaired in time, which greatly increases the uncontrollability and unobservability of the circuit design. Summary of the invention

[0006] The present application isolates the module to be isolated through a scan register module. The scan chain formed by cascading N scan registers selects the input signal of the input end of the module to be isolated to the data selection module under the control of the scan enable signal, and directly outputs it to the output circuit through the data selection module. The output circuit can directly receive the input signal of the input end of the module to be isolated instead of the X-state output signal output by the module to be isolated, thereby improving the accuracy of circuit testing.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one, part, or all of the above purposes or other purposes, the present invention provides a test circuit.

[0009] A test circuit comprising: Module to be isolated; A scan register module, comprising a scan chain formed by cascading N scan registers; A data selection module, comprising a first input end and a second input end, wherein N scan registers select an input signal or a scan signal of an input end of a module to be isolated to the first input end of the data selection module under the control of a scan enable signal; the second input end of the data selection module is connected to an output end of the module to be isolated, and the data selection module selects one of the input data for output under the control of a test mode signal; and a peripheral circuit connected to the input end of the module to be isolated and / or the output end of the data selection module; Wherein, N is a positive integer not less than 1.

[0010] The multiple input signals of the module to be isolated are sequentially connected to the data input end of each scanning register; The data output end of each of the scanning registers is output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scanning register.

[0011] The input signal of the input end of the module to be isolated is processed by combinational logic and then sequentially input into the data input ends of the N scanning registers.

[0012] The scanning and registering module also includes: A scan signal input terminal is electrically connected to a scan input terminal of a first-stage scan register to provide a scan signal; A scan enable signal input terminal, electrically connected to the scan enable terminals of the N scan registers, and controlling the scan registers to select the input signal of the module to be isolated or the scan signal for input; A scan clock signal input terminal is electrically connected to the scan clock terminals of the N scan registers to provide a scan clock signal; The scan output terminal is electrically connected to the data output terminal of the last-stage scan register, and shifts and outputs the captured input signal of the module to be isolated.

[0013] The scan register includes a multiplexer controlled by the scan enable signal, and a D flip-flop connected to an output end of the multiplexer; The scan clock signal is connected to the clock signal interface of the D flip-flop.

[0014] The working process of the scanning and registering module includes: In the shift input stage, the scan enable signal controls the multiplexer to select the scan signal and shift it into the N scan registers of the scan register module one by one; In the capture phase, the multiplexers in the N scan registers select the input signal of the module to be isolated under the control of the scan enable signal for input and output to the corresponding D flip-flop; In the shift output stage, under the control of the scan clock signal, the input signal of the module to be isolated cached in the D flip-flops in the N scan registers is output to the data selection module through the data output end, and is output to the scan output end bit by bit.

[0015] The scanning signal is a signal sequence corresponding to the scanning clock signal.

[0016] The working process of the scanning and registering module also includes: The shift-in phase of the next scan cycle is performed simultaneously with the shift-out phase of the previous scan cycle.

[0017] The data selection module includes N data selection units, and the data selection unit is a multiplexer; The test mode signal controls the multiplexer to select data of the first input terminal or the second input terminal for output.

[0018] The peripheral circuit includes: an input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module; The input circuit is electrically connected to the input signal interface of the module to be isolated, inputs different input signals to the module to be isolated, and the different input signals are transmitted to the data selection module through the scanning and registering module; The output end of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, the data of the first input end or the second input end is selected and output to the output circuit.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. In the present application, N of the scan registers select the input signal or scan signal at the input end of the module to be isolated to the first input end of the data selection module under the control of the scan enable signal; the data selection module selects one of the input data for output under the control of the test mode signal. In this way, the scan chain formed by the cascade of N scan registers in the present application selects the input signal at the input end of the module to be isolated to the data selection module under the control of the scan enable signal. The input signal at the input end of the module to be isolated can be directly output to the output circuit through the data selection module, and the output circuit can directly receive the input signal at the input end of the module to be isolated, thereby isolating the module to be isolated through the scan register module, shielding the influence of the X-state output signal, and improving the accuracy of the circuit test.

[0020] Since the output end of the module to be isolated is connected to the second input end of the data selection module, the data selection module can directly transmit the output of the module to be isolated to the peripheral circuit under the control of the test mode signal without affecting the realization of the original logic function of the circuit.

[0021] 2. The present application adds a scanning function to the input signal of the module to be isolated by designing a scan chain formed by cascading N scan registers, which can realize the separate observation of the input signal. The designer can quickly and effectively detect and repair the defects in the circuit design process through the observed input signal, reduce the dependence on external test equipment, reduce the circuit design cost, and avoid the problem that the input signal X state cannot be observed, shorten the test time, and improve the observability of the circuit; on the basis of observation, the scan chain can realize the control input of the input signal under the control of the scan enable signal, which not only realizes the isolation of the module to be isolated, but also realizes the controllability of the design, greatly improving the flexibility and effectiveness of the test; in addition, the scan register module also supports the automatic test mode. Since all scan registers can be accessed through the scan chain, it is convenient to apply the test vector, and the coverage of the peripheral circuit test is improved on the basis of isolating the X-state signal.

[0022] 3. The present application connects N scan registers in series into a scan chain, which is isolated from other modules of the circuit. The user can add or delete scan registers in the scan chain according to the actual situation of the input signal. The circuit design is more flexible and there is no need to consider the impact on other modules of the circuit design. Compression or no compression can be selected according to actual design requirements. The integration method is very flexible, which greatly reduces the circuit design area and avoids mixed chaining with registers of other modules, reducing the impact of other modules in the circuit design.

[0023] 4. The scanning register module of the present application outputs a scanning signal into the data selection module, and the data selection module outputs the scanning signal to the peripheral circuit. The test vector of the scanning signal will be used as a test stimulus for the register in the peripheral circuit, ensuring that the register in the peripheral circuit and its related circuits can be effectively tested, thereby improving the testability of the register in the peripheral circuit of the data selection module output port and further increasing the test coverage.

[0024] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 This is a schematic diagram of the input and output circuit of the PHY chip.

[0027] Figure 2 A test circuit diagram provided in an embodiment of the present application Figure 1 .

[0028] Figure 3 A test circuit diagram provided in an embodiment of the present application Figure 2 .

[0029] Figure 4 A timing diagram of a test circuit provided in an embodiment of the present application.

[0030] Among them, D is the data input terminal of SDFF, SI is the scan input terminal of SDFF, SE is the scan enable terminal of SDFF, CP is the scan clock terminal of SDFF, and Q is the data output terminal of SDFF. DETAILED DESCRIPTION

[0031] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0032] The present application isolates the module to be isolated through a scan register module. The scan chain formed by cascading N scan registers selects the input signal of the input end of the module to be isolated to the data selection module under the control of the scan enable signal, and directly outputs it to the output circuit through the data selection module. The output circuit can directly receive the input signal of the input end of the module to be isolated instead of the X-state output signal output by the module to be isolated, thereby improving the accuracy of circuit testing.

[0033] However, it is understood by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0034] Example: like Figure 2 As shown, a test circuit includes: a module to be isolated, a scan register module connected to the module to be isolated, a data selection module and a peripheral circuit.

[0035] Specifically, Figure 3 As shown, the peripheral circuit includes an input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module.

[0036] In this embodiment, the module to be isolated is a black box module in the circuit, and its input and output signals are in the X state (unknown state) (e.g. Figure 3 The PHY chip in the peripheral circuit), the input circuit AND0 / XOR / OR in the peripheral circuit is the previous level driver of the module to be isolated and cannot be observed; the output circuit Gating0 / BUF0 / AND1 in the peripheral circuit is the next level logic circuit driven by the module to be isolated, which may be affected by the output signal Out0 / Out1 / Out2 of the module to be isolated, which may be in the X state and cannot be observed either; therefore, there are a lot of unmeasurable risks in the upper and lower logic circuits of the module to be isolated, and the module to be isolated needs to be isolated.

[0037] In this embodiment, the input end of the module to be isolated is connected to the input circuit AND0 / XOR / OR and the scan register module in the peripheral circuit, and the output end is connected to the data selection module. The output end of the data selection module is connected to the output circuit Gating0 / BUF0 / AND1 in the peripheral circuit.

[0038] Specifically, the input circuit AND0 / XOR / OR in the peripheral circuit is electrically connected to the input signal interface of the module to be isolated, and different input signals In0 / In1 / In2 are input to the module to be isolated, and the different input signals In0 / In1 / In2 are transmitted to the first input end of the data selection module through the scanning register module; The output end of the module to be isolated is connected to the second input end of the data selection module, and the different output signals Out0 / Out1 / Out2 are transmitted to the second input end of the data selection module; The output end of the data selection module is electrically connected to the output circuit Gating0 / BUF0 / AND1 in the peripheral circuit, and selects the data of the first input end or the second input end to be output to the output circuit Gating0 / BUF0 / AND1 under the control of the test mode signal.

[0039] The scan register module includes a scan chain formed by cascading N scan registers. The data input end of each scan register is sequentially connected to multiple input signals of the module to be isolated, and the output end is connected to the first input end of the data selection module. By transmitting the input circuit to the input signal In0 / In1 / In2 of the module to be isolated through the scan register module to the data selection module, and then transmitting it to the output circuit through the data selection module, the problem of being unable to observe due to the signal X state is avoided.

[0040] The cascade relationship of the N scan registers in the scan chain is series connection, and N is a positive integer not less than 1.

[0041] The scan register module also includes: a scan signal input terminal, a scan enable signal input terminal, a scan clock signal input terminal and a scan output terminal.

[0042] The scan signal input terminal is electrically connected to the scan input terminal of the first-level scan register in the scan chain to provide a scan signal for the scan chain; the scan enable signal input terminal is electrically connected to the scan enable terminals of the N scan registers in the scan chain to control the scan registers in the scan chain to select the input signal or scan signal of the module to be isolated for input; the scan clock signal input terminal is electrically connected to the scan clock terminals of the N scan registers to provide a scan clock signal for the scan chain; the scan output terminal is electrically connected to the data output terminal of the last-level scan register in the scan chain to shift and output the captured input signal of the module to be isolated.

[0043] The present application adds a scanning function for the input signal of the module to be isolated by designing a scan chain formed by cascading N scan registers, which can realize the separate observation of the input signal. The designer can quickly and effectively detect and repair the defects in the circuit design process through the observed input signal, reduce the dependence on external test equipment, reduce the circuit design cost, and avoid the problem that the input signal X state cannot be observed, shorten the test time, and improve the observability of the circuit; on the basis of observation, the scan chain can realize the control input of the input signal under the control of the scan enable signal, which not only realizes the isolation of the module to be isolated, but also realizes the controllability of the design, greatly improving the flexibility and effectiveness of the test; in addition, the scan register module also supports the automatic test mode. Since all scan registers can be accessed through the scan chain, it is convenient to apply the test vector, and the coverage of the peripheral circuit test is improved on the basis of isolating the X-state signal.

[0044] The present application connects N scan registers in series into a scan chain, which is isolated from other modules of the circuit. The user can add or delete scan registers in the scan chain according to the actual situation of the input signal. The circuit design is more flexible and there is no need to consider the impact on other modules of the circuit design. Compression or no compression can be selected according to actual design requirements. The integration method is very flexible, which greatly reduces the circuit design area and avoids mixed chaining with registers of other modules, reducing the impact of other modules in the circuit design.

[0045] The data selection module comprises a first input terminal and a second input terminal. N scanning registers select the input signal or the scanning signal of the input terminal of the module to be isolated to the first input terminal of the data selection module under the control of the scanning enable signal. The second input terminal of the data selection module is connected to the output terminal of the module to be isolated. The data selection module selects one of the input data for output under the control of the test mode signal.

[0046] Specifically, Figure 3 As shown, the input circuit is electrically connected to the input signal interface of the module to be isolated, and different input signals are input to the module to be isolated. The different input signals are transmitted to the data selection module through the scanning register module; the output end of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, the data of the first input end or the second input end is selected to be output to the output circuit.

[0047] The data selection module includes N data selection units, which are 2-to-1 multiplexers (2:1 MUX for short), including two input lines, one selection line and one output line; the two input lines correspond to two input ends respectively, and according to the state of the selection line, the output line selects the data of one of the input ends for output.

[0048] It should be noted that in other embodiments, the data selection module can be determined according to actual conditions. In other embodiments, the data selection module can also be implemented by a switch matrix, a programmable logic device or a logic circuit, which is not limited in this application.

[0049] Specifically, Figure 3 As shown, the test mode signal is connected to the selection line of the multiplexer to control the output line of the multiplexer to output the data of the first input terminal or the second input terminal; When the level of the test mode signal is a first level, the multiplexer selects the data transmitted by the scan register module for output; when the level of the test mode signal is a second level, the multiplexer selects the output signal of the module to be isolated for output.

[0050] like Figure 3 As shown, multiple input signals of the module to be isolated are sequentially connected to the data input end of each scanning register; the data output end of each scanning register is output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scanning register.

[0051] Specifically, the input signals In0 / In1 / In2 of the module to be isolated are respectively connected to the data input terminals of the scan registers SDFF1 / SDFF2 / SDFF3. After the scan registers capture the input signals In0 / In1 / In2, they are simultaneously output to the first input terminals of the corresponding multiplexers MUX1 / MUX2 / MUX3 through the Q terminals. Since the Q terminal of SDFF1 is respectively connected to the first input terminal of MUX1 and the SI terminal of SDFF2, the Q terminal of SDFF2 is respectively connected to the first input terminal of MUX2 and the SI terminal of SDFF3, and the Q terminal of SDFF3 is respectively connected to the first input terminal of MUX3 and the scan output terminal. Therefore, the transmission path corresponding to the In0 signal is isolated from the transmission paths corresponding to the In1 signal and the In2 signal. The user can add or delete the scan registers in the scan chain according to the actual conditions of the input signals, without affecting each other while taking into account the design flexibility.

[0052] It should be noted that the input signal at the input end of the module to be isolated can be first processed by a combinational logic circuit, and then sequentially input into the data input ends of the N scan registers. Whether it is a common gate circuit (basic logic gates such as AND, OR, NOT, NAND, NOR, XOR...) or an adder for performing binary addition operations or a decoder, encoder, and multiplexer, the output of the combinational logic circuit depends only on the current input and is not affected by the previous input; therefore, the output of a stable input signal after being processed by the combinational logic circuit is also stable, and the design of adding a combinational logic circuit can better pre-process the input signal according to actual needs (such as compression or no compression), and the circuit design is more flexible.

[0053] As a preferred embodiment of the present invention, the output of the combinational logic circuit in this embodiment immediately responds to changes in the input, and there is no storage unit. The output only depends on the current input. When the input is stable, the output is also stable.

[0054] As a preferred embodiment of the present invention, the scanning register in this embodiment is a scanning D flip-flop (Scan DFlip-Flop, abbreviated as SDFF). The scanning D flip-flop is a special D flip-flop that adds a scanning function on the basis of the register, including a multiplexer controlled by a scan enable signal, and a D flip-flop that uses the output signal of the multiplexer as a signal input; the scanning clock signal is connected to the clock signal interface of the D flip-flop.

[0055] like Figure 3 As shown in the figure, the input signals In0 / In1 / In2 are connected to the D terminals of SDFF1 / SDFF2 / SDFF3 respectively, and are captured through the D terminals of SDFF, so that the In0 / In1 / In2 signals can be observed; the 1 terminals of MUX1 / MUX2 / MUX3 of the data selection module are connected to the Q terminals of SDFF1 / SDFF2 / SDFF3 respectively through net1 / net2 / net3, and the 0 terminals of MUX1 / MUX2 / MUX3 are connected to the output signals Out0 / Out1 / Out2 of the modules to be isolated. When the test mode signal test_mode is 0, MUX1 / MUX2 / MUX3 goes to the 0 end and outputs the output signal Out0 / Out1 / Out2 of the module to be isolated to the output circuit; when the test mode signal test_mode is 1, MUX1 / MUX2 / MUX3 goes to the 1 end and outputs the output signal of the Q end of sdff1 / sdff2 / sdff3 to the output circuit, and no longer outputs the signal Out0 / Out1 / Out2 to the output circuit, thereby isolating the X-state output signal.

[0056] like Figure 4As shown, when the level of the scan enable signal is a first level, the scan register selects the scan signal as an input signal; when the level of the scan enable signal is a second level, the scan register selects the input signal of the module to be isolated for input.

[0057] The specific work process includes: Shift input stage: the scan enable signal controls the multiplexer to select the scan signal and shift it bit by bit into the scan chain composed of N serial scan registers; specifically, under the first clock pulse, the first bit of the scan signal enters the first scan register SDFF1, under the second clock pulse, the first bit of the scan signal enters the second scan register SDFF2, and at the same time, the second bit of the scan signal enters the first scan register SDFF1, until all the scan signals are shifted into the scan chain, and the shifted scan signals serve as the input or initial state of the N scan registers; Capture phase: under the control of the scan enable signal, the multiplexer inputs the input signal In0 / In1 / In2 of the module to be isolated into the scan register SDFF1 / SDFF2 / SDFF3 accordingly, the D flip-flop in the scan register SDFF1 captures the input signal In0, the D flip-flop in the scan register SDFF2 captures the input signal In1, and the D flip-flop in the scan register SDFF3 captures the input signal In2; and because the input signals In0 / In1 / In2 are simultaneously input into the scan register SDFF1 / SDFF2 / SDFF3, when the D flip-flop in the scan register SDFF1 captures the input signal In0, the D flip-flop in the scan register SDFF2 / SDFF3 will simultaneously capture the input signal In1 / In2; Shift output stage: under the control of the scan clock signal, the signal In0 of the D flip-flop cache in the scan register SDFF1, the signal In1 of the D flip-flop cache in the scan register SDFF2, and the signal In2 of the D flip-flop cache in the scan register SDFF3 are simultaneously output to MUX1 / MUX2 / MUX3 in the data selection module, that is, when the signal In0 is output from the Q end of the scan register SDFF1 to the 1 end of MUX1 through net1, the signal In1 / In2 is simultaneously output from the Q end of the scan register SDFF2 / SDFF3 to the 1 end of MUX2 / MUX3 through net2 / net3 respectively. At this time, the input signal In0 / In1 / In2 of the module to be isolated is output to the data selection module accordingly, so that the data selection module directly outputs the input signal In0 / In1 / In2 of the module to be isolated to the peripheral circuit, thereby realizing the isolation of the module to be isolated.

[0058] At the same time, under the control of the scan enable signal, the multiplexer in the scan register will again shift the scan signal into the scan chain one by one, and shift the data cached in the scan chain out of the scan chain one by one; since the scan register in the scan chain is not mixed in series with the registers of other modules in the circuit design, it is not only possible to observe the signal individually, but also to promptly discover and repair defects in the circuit design and improve circuit performance; the scan chain of the present application also has a control function, which can realize the controlled input of the input signal under the control of the scan enable signal, thereby improving the controllability of the circuit.

[0059] As a preferred embodiment of the present invention, the shift input phase of the next cycle is performed simultaneously with the shift output phase of the previous cycle.

[0060] In this embodiment, multiple input signals of the module to be isolated are connected to the data input end of each scanning register in sequence; the data output end of each scanning register is output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scanning register.

[0061] Since the input and output of the module to be isolated are in the X state, it becomes a black box module. In the Shift input stage, the N scan registers select the scan signal to the first input end of the data selection module under the control of the scan enable signal, and the scan signal can enter the output circuit through the data selection module. Thus, in the Shift input stage, a signal sequence of 0 / 1 values ​​is provided as a test vector for the register in the output circuit. When the Capture stage begins after the Shift input stage, the test vector of the scan signal will be used as a test stimulus for the register in the output circuit, solving the problem that the output of the module to be isolated is unobservable, ensuring that the registers connected to the module to be isolated and the multiplexer can be effectively tested, improving the testability of the registers, and further improving the coverage of the peripheral circuit test.

[0062] As a preferred embodiment of the present invention, in this embodiment, the first level is a high level, the second level is a low level, and the scanning signal (01010101010) corresponds to the signal sequence of the scanning clock signal.

[0063] In the present application, a scan chain formed by cascading N scan registers selects the input signal of the input end of the module to be isolated to the data selection module under the control of the scan enable signal. The input signal of the input end of the module to be isolated can be directly output to the output circuit through the data selection module, and the output circuit can directly receive the input signal of the input end of the module to be isolated, thereby isolating the module to be isolated through the scan register module, shielding the influence of the X-state output signal, and improving the accuracy of the circuit test.

[0064] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0065] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A test circuit, characterized in that: include: Module to be isolated; A scan register module, comprising a scan chain formed by cascading N scan registers; A data selection module, comprising a first input end and a second input end, wherein the N scan registers select an input signal or a scan signal from an input end of a module to be isolated to the first input end of the data selection module under the control of a scan enable signal; the second input end of the data selection module is connected to an output end of the module to be isolated, and the data selection module selects one of the input data for output under the control of a test mode signal; and a peripheral circuit connected to the input end of the module to be isolated and / or the output end of the data selection module; Wherein, N is a positive integer not less than 1.

2. A test circuit according to claim 1, characterized in that: The multiple input signals of the module to be isolated are sequentially connected to the data input end of each scanning register; The data output end of each of the scanning registers is output to the first input end of the data selection module according to the input signal of the module to be isolated received by the scanning register.

3. A test circuit according to claim 2, characterized in that: The input signal of the input end of the module to be isolated is processed by combinational logic and then sequentially input into the data input ends of the N scanning registers.

4. A test circuit according to claim 1, characterized in that: The scanning and registering module also includes: A scan signal input terminal is electrically connected to a scan input terminal of a first-stage scan register to provide a scan signal; A scan enable signal input terminal, electrically connected to the scan enable terminals of the N scan registers, and controlling the scan registers to select the input signal of the module to be isolated or the scan signal for input; A scan clock signal input terminal is electrically connected to the scan clock terminals of the N scan registers to provide a scan clock signal; The scan output terminal is electrically connected to the data output terminal of the last-stage scan register, and shifts and outputs the captured input signal of the module to be isolated.

5. A test circuit according to claim 4, characterized in that: The scan register includes a multiplexer controlled by the scan enable signal, and a D flip-flop connected to an output end of the multiplexer; The scan clock signal is connected to the clock signal interface of the D flip-flop.

6. A test circuit according to claim 5, characterized in that: The working process of the scanning and registering module includes: In the shift input stage, the scan enable signal controls the multiplexer to select the scan signal and shift it into the N scan registers of the scan register module one by one; In the capture phase, the multiplexers in the N scan registers select the input signal of the module to be isolated under the control of the scan enable signal for input and output to the corresponding D flip-flop; In the shift output stage, under the control of the scan clock signal, the input signal of the module to be isolated cached in the D flip-flops in the N scan registers is output to the data selection module through the data output end, and is output to the scan output end bit by bit.

7. A test circuit according to claim 6, characterized in that: The scanning signal is a signal sequence corresponding to the scanning clock signal.

8. A test circuit according to claim 6, characterized in that: The working process of the scanning and registering module also includes: The shift-in phase of the next scan cycle is performed simultaneously with the shift-out phase of the previous scan cycle.

9. A test circuit according to claim 1, characterized in that: The data selection module includes N data selection units, and the data selection unit is a multiplexer; The test mode signal controls the multiplexer to select data of the first input terminal or the second input terminal for output.

10. A test circuit according to claim 1, characterized in that: The peripheral circuit includes an input circuit connected to the input end of the module to be isolated, and / or an output circuit connected to the output end of the data selection module; The input circuit is electrically connected to the input signal interface of the module to be isolated, inputs different input signals to the module to be isolated, and the different input signals are transmitted to the data selection module through the scanning and registering module; The output end of the data selection module is electrically connected to the output circuit, and under the control of the test mode signal, the data of the first input end or the second input end is selected and output to the output circuit.

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